1 /* 2 * Copyright (c) 2014 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #ifndef BRCMF_CHIP_H 17 #define BRCMF_CHIP_H 18 19 #include <linux/types.h> 20 21 #define CORE_CC_REG(base, field) \ 22 (base + offsetof(struct chipcregs, field)) 23 24 /** 25 * struct brcmf_chip - chip level information. 26 * 27 * @chip: chip identifier. 28 * @chiprev: chip revision. 29 * @cc_caps: chipcommon core capabilities. 30 * @pmucaps: PMU capabilities. 31 * @pmurev: PMU revision. 32 * @rambase: RAM base address (only applicable for ARM CR4 chips). 33 * @ramsize: amount of RAM on chip including retention. 34 * @srsize: amount of retention RAM on chip. 35 * @name: string representation of the chip identifier. 36 */ 37 struct brcmf_chip { 38 u32 chip; 39 u32 chiprev; 40 u32 cc_caps; 41 u32 pmucaps; 42 u32 pmurev; 43 u32 rambase; 44 u32 ramsize; 45 u32 srsize; 46 char name[8]; 47 }; 48 49 /** 50 * struct brcmf_core - core related information. 51 * 52 * @id: core identifier. 53 * @rev: core revision. 54 * @base: base address of core register space. 55 */ 56 struct brcmf_core { 57 u16 id; 58 u16 rev; 59 u32 base; 60 }; 61 62 /** 63 * struct brcmf_buscore_ops - buscore specific callbacks. 64 * 65 * @read32: read 32-bit value over bus. 66 * @write32: write 32-bit value over bus. 67 * @prepare: prepare bus for core configuration. 68 * @setup: bus-specific core setup. 69 * @active: chip becomes active. 70 * The callback should use the provided @rstvec when non-zero. 71 */ 72 struct brcmf_buscore_ops { 73 u32 (*read32)(void *ctx, u32 addr); 74 void (*write32)(void *ctx, u32 addr, u32 value); 75 int (*prepare)(void *ctx); 76 int (*reset)(void *ctx, struct brcmf_chip *chip); 77 int (*setup)(void *ctx, struct brcmf_chip *chip); 78 void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec); 79 }; 80 81 struct brcmf_chip *brcmf_chip_attach(void *ctx, 82 const struct brcmf_buscore_ops *ops); 83 void brcmf_chip_detach(struct brcmf_chip *chip); 84 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid); 85 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip); 86 bool brcmf_chip_iscoreup(struct brcmf_core *core); 87 void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset); 88 void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset, 89 u32 postreset); 90 void brcmf_chip_set_passive(struct brcmf_chip *ci); 91 bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec); 92 bool brcmf_chip_sr_capable(struct brcmf_chip *pub); 93 94 #endif /* BRCMF_AXIDMP_H */ 95