1 /* 2 * Copyright (c) 2014 Broadcom Corporation 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 #include <linux/kernel.h> 17 #include <linux/delay.h> 18 #include <linux/list.h> 19 #include <linux/ssb/ssb_regs.h> 20 #include <linux/bcma/bcma.h> 21 #include <linux/bcma/bcma_regs.h> 22 23 #include <defs.h> 24 #include <soc.h> 25 #include <brcm_hw_ids.h> 26 #include <brcmu_utils.h> 27 #include <chipcommon.h> 28 #include "debug.h" 29 #include "chip.h" 30 31 /* SOC Interconnect types (aka chip types) */ 32 #define SOCI_SB 0 33 #define SOCI_AI 1 34 35 /* PL-368 DMP definitions */ 36 #define DMP_DESC_TYPE_MSK 0x0000000F 37 #define DMP_DESC_EMPTY 0x00000000 38 #define DMP_DESC_VALID 0x00000001 39 #define DMP_DESC_COMPONENT 0x00000001 40 #define DMP_DESC_MASTER_PORT 0x00000003 41 #define DMP_DESC_ADDRESS 0x00000005 42 #define DMP_DESC_ADDRSIZE_GT32 0x00000008 43 #define DMP_DESC_EOT 0x0000000F 44 45 #define DMP_COMP_DESIGNER 0xFFF00000 46 #define DMP_COMP_DESIGNER_S 20 47 #define DMP_COMP_PARTNUM 0x000FFF00 48 #define DMP_COMP_PARTNUM_S 8 49 #define DMP_COMP_CLASS 0x000000F0 50 #define DMP_COMP_CLASS_S 4 51 #define DMP_COMP_REVISION 0xFF000000 52 #define DMP_COMP_REVISION_S 24 53 #define DMP_COMP_NUM_SWRAP 0x00F80000 54 #define DMP_COMP_NUM_SWRAP_S 19 55 #define DMP_COMP_NUM_MWRAP 0x0007C000 56 #define DMP_COMP_NUM_MWRAP_S 14 57 #define DMP_COMP_NUM_SPORT 0x00003E00 58 #define DMP_COMP_NUM_SPORT_S 9 59 #define DMP_COMP_NUM_MPORT 0x000001F0 60 #define DMP_COMP_NUM_MPORT_S 4 61 62 #define DMP_MASTER_PORT_UID 0x0000FF00 63 #define DMP_MASTER_PORT_UID_S 8 64 #define DMP_MASTER_PORT_NUM 0x000000F0 65 #define DMP_MASTER_PORT_NUM_S 4 66 67 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000 68 #define DMP_SLAVE_ADDR_BASE_S 12 69 #define DMP_SLAVE_PORT_NUM 0x00000F00 70 #define DMP_SLAVE_PORT_NUM_S 8 71 #define DMP_SLAVE_TYPE 0x000000C0 72 #define DMP_SLAVE_TYPE_S 6 73 #define DMP_SLAVE_TYPE_SLAVE 0 74 #define DMP_SLAVE_TYPE_BRIDGE 1 75 #define DMP_SLAVE_TYPE_SWRAP 2 76 #define DMP_SLAVE_TYPE_MWRAP 3 77 #define DMP_SLAVE_SIZE_TYPE 0x00000030 78 #define DMP_SLAVE_SIZE_TYPE_S 4 79 #define DMP_SLAVE_SIZE_4K 0 80 #define DMP_SLAVE_SIZE_8K 1 81 #define DMP_SLAVE_SIZE_16K 2 82 #define DMP_SLAVE_SIZE_DESC 3 83 84 /* EROM CompIdentB */ 85 #define CIB_REV_MASK 0xff000000 86 #define CIB_REV_SHIFT 24 87 88 /* ARM CR4 core specific control flag bits */ 89 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020 90 91 /* D11 core specific control flag bits */ 92 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004 93 #define D11_BCMA_IOCTL_PHYRESET 0x0008 94 95 /* chip core base & ramsize */ 96 /* bcm4329 */ 97 /* SDIO device core, ID 0x829 */ 98 #define BCM4329_CORE_BUS_BASE 0x18011000 99 /* internal memory core, ID 0x80e */ 100 #define BCM4329_CORE_SOCRAM_BASE 0x18003000 101 /* ARM Cortex M3 core, ID 0x82a */ 102 #define BCM4329_CORE_ARM_BASE 0x18002000 103 104 /* Max possibly supported memory size (limited by IO mapped memory) */ 105 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024) 106 107 #define CORE_SB(base, field) \ 108 (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) 109 #define SBCOREREV(sbidh) \ 110 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \ 111 ((sbidh) & SSB_IDHIGH_RCLO)) 112 113 struct sbconfig { 114 u32 PAD[2]; 115 u32 sbipsflag; /* initiator port ocp slave flag */ 116 u32 PAD[3]; 117 u32 sbtpsflag; /* target port ocp slave flag */ 118 u32 PAD[11]; 119 u32 sbtmerrloga; /* (sonics >= 2.3) */ 120 u32 PAD; 121 u32 sbtmerrlog; /* (sonics >= 2.3) */ 122 u32 PAD[3]; 123 u32 sbadmatch3; /* address match3 */ 124 u32 PAD; 125 u32 sbadmatch2; /* address match2 */ 126 u32 PAD; 127 u32 sbadmatch1; /* address match1 */ 128 u32 PAD[7]; 129 u32 sbimstate; /* initiator agent state */ 130 u32 sbintvec; /* interrupt mask */ 131 u32 sbtmstatelow; /* target state */ 132 u32 sbtmstatehigh; /* target state */ 133 u32 sbbwa0; /* bandwidth allocation table0 */ 134 u32 PAD; 135 u32 sbimconfiglow; /* initiator configuration */ 136 u32 sbimconfighigh; /* initiator configuration */ 137 u32 sbadmatch0; /* address match0 */ 138 u32 PAD; 139 u32 sbtmconfiglow; /* target configuration */ 140 u32 sbtmconfighigh; /* target configuration */ 141 u32 sbbconfig; /* broadcast configuration */ 142 u32 PAD; 143 u32 sbbstate; /* broadcast state */ 144 u32 PAD[3]; 145 u32 sbactcnfg; /* activate configuration */ 146 u32 PAD[3]; 147 u32 sbflagst; /* current sbflags */ 148 u32 PAD[3]; 149 u32 sbidlow; /* identification */ 150 u32 sbidhigh; /* identification */ 151 }; 152 153 /* bankidx and bankinfo reg defines corerev >= 8 */ 154 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 155 #define SOCRAM_BANKINFO_SZMASK 0x0000007f 156 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100 157 158 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 159 /* socram bankinfo memtype */ 160 #define SOCRAM_MEMTYPE_RAM 0 161 #define SOCRAM_MEMTYPE_R0M 1 162 #define SOCRAM_MEMTYPE_DEVRAM 2 163 164 #define SOCRAM_BANKINFO_SZBASE 8192 165 #define SRCI_LSS_MASK 0x00f00000 166 #define SRCI_LSS_SHIFT 20 167 #define SRCI_SRNB_MASK 0xf0 168 #define SRCI_SRNB_MASK_EXT 0x100 169 #define SRCI_SRNB_SHIFT 4 170 #define SRCI_SRBSZ_MASK 0xf 171 #define SRCI_SRBSZ_SHIFT 0 172 #define SR_BSZ_BASE 14 173 174 struct sbsocramregs { 175 u32 coreinfo; 176 u32 bwalloc; 177 u32 extracoreinfo; 178 u32 biststat; 179 u32 bankidx; 180 u32 standbyctrl; 181 182 u32 errlogstatus; /* rev 6 */ 183 u32 errlogaddr; /* rev 6 */ 184 /* used for patching rev 3 & 5 */ 185 u32 cambankidx; 186 u32 cambankstandbyctrl; 187 u32 cambankpatchctrl; 188 u32 cambankpatchtblbaseaddr; 189 u32 cambankcmdreg; 190 u32 cambankdatareg; 191 u32 cambankmaskreg; 192 u32 PAD[1]; 193 u32 bankinfo; /* corev 8 */ 194 u32 bankpda; 195 u32 PAD[14]; 196 u32 extmemconfig; 197 u32 extmemparitycsr; 198 u32 extmemparityerrdata; 199 u32 extmemparityerrcnt; 200 u32 extmemwrctrlandsize; 201 u32 PAD[84]; 202 u32 workaround; 203 u32 pwrctl; /* corerev >= 2 */ 204 u32 PAD[133]; 205 u32 sr_control; /* corerev >= 15 */ 206 u32 sr_status; /* corerev >= 15 */ 207 u32 sr_address; /* corerev >= 15 */ 208 u32 sr_data; /* corerev >= 15 */ 209 }; 210 211 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f) 212 #define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f) 213 214 #define ARMCR4_CAP (0x04) 215 #define ARMCR4_BANKIDX (0x40) 216 #define ARMCR4_BANKINFO (0x44) 217 #define ARMCR4_BANKPDA (0x4C) 218 219 #define ARMCR4_TCBBNB_MASK 0xf0 220 #define ARMCR4_TCBBNB_SHIFT 4 221 #define ARMCR4_TCBANB_MASK 0xf 222 #define ARMCR4_TCBANB_SHIFT 0 223 224 #define ARMCR4_BSZ_MASK 0x3f 225 #define ARMCR4_BSZ_MULT 8192 226 227 struct brcmf_core_priv { 228 struct brcmf_core pub; 229 u32 wrapbase; 230 struct list_head list; 231 struct brcmf_chip_priv *chip; 232 }; 233 234 struct brcmf_chip_priv { 235 struct brcmf_chip pub; 236 const struct brcmf_buscore_ops *ops; 237 void *ctx; 238 /* assured first core is chipcommon, second core is buscore */ 239 struct list_head cores; 240 u16 num_cores; 241 242 bool (*iscoreup)(struct brcmf_core_priv *core); 243 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset, 244 u32 reset); 245 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset, 246 u32 postreset); 247 }; 248 249 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci, 250 struct brcmf_core *core) 251 { 252 u32 regdata; 253 254 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); 255 core->rev = SBCOREREV(regdata); 256 } 257 258 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core) 259 { 260 struct brcmf_chip_priv *ci; 261 u32 regdata; 262 u32 address; 263 264 ci = core->chip; 265 address = CORE_SB(core->pub.base, sbtmstatelow); 266 regdata = ci->ops->read32(ci->ctx, address); 267 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT | 268 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK); 269 return SSB_TMSLOW_CLOCK == regdata; 270 } 271 272 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core) 273 { 274 struct brcmf_chip_priv *ci; 275 u32 regdata; 276 bool ret; 277 278 ci = core->chip; 279 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 280 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK; 281 282 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); 283 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); 284 285 return ret; 286 } 287 288 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core, 289 u32 prereset, u32 reset) 290 { 291 struct brcmf_chip_priv *ci; 292 u32 val, base; 293 294 ci = core->chip; 295 base = core->pub.base; 296 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 297 if (val & SSB_TMSLOW_RESET) 298 return; 299 300 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 301 if ((val & SSB_TMSLOW_CLOCK) != 0) { 302 /* 303 * set target reject and spin until busy is clear 304 * (preserve core-specific bits) 305 */ 306 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 307 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 308 val | SSB_TMSLOW_REJECT); 309 310 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 311 udelay(1); 312 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)) 313 & SSB_TMSHIGH_BUSY), 100000); 314 315 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); 316 if (val & SSB_TMSHIGH_BUSY) 317 brcmf_err("core state still busy\n"); 318 319 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); 320 if (val & SSB_IDLOW_INITIATOR) { 321 val = ci->ops->read32(ci->ctx, 322 CORE_SB(base, sbimstate)); 323 val |= SSB_IMSTATE_REJECT; 324 ci->ops->write32(ci->ctx, 325 CORE_SB(base, sbimstate), val); 326 val = ci->ops->read32(ci->ctx, 327 CORE_SB(base, sbimstate)); 328 udelay(1); 329 SPINWAIT((ci->ops->read32(ci->ctx, 330 CORE_SB(base, sbimstate)) & 331 SSB_IMSTATE_BUSY), 100000); 332 } 333 334 /* set reset and reject while enabling the clocks */ 335 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 336 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET; 337 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); 338 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 339 udelay(10); 340 341 /* clear the initiator reject bit */ 342 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); 343 if (val & SSB_IDLOW_INITIATOR) { 344 val = ci->ops->read32(ci->ctx, 345 CORE_SB(base, sbimstate)); 346 val &= ~SSB_IMSTATE_REJECT; 347 ci->ops->write32(ci->ctx, 348 CORE_SB(base, sbimstate), val); 349 } 350 } 351 352 /* leave reset and reject asserted */ 353 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 354 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET)); 355 udelay(1); 356 } 357 358 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core, 359 u32 prereset, u32 reset) 360 { 361 struct brcmf_chip_priv *ci; 362 u32 regdata; 363 364 ci = core->chip; 365 366 /* if core is already in reset, skip reset */ 367 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); 368 if ((regdata & BCMA_RESET_CTL_RESET) != 0) 369 goto in_reset_configure; 370 371 /* configure reset */ 372 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 373 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); 374 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 375 376 /* put in reset */ 377 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 378 BCMA_RESET_CTL_RESET); 379 usleep_range(10, 20); 380 381 /* wait till reset is 1 */ 382 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) != 383 BCMA_RESET_CTL_RESET, 300); 384 385 in_reset_configure: 386 /* in-reset configure */ 387 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 388 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); 389 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 390 } 391 392 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset, 393 u32 reset, u32 postreset) 394 { 395 struct brcmf_chip_priv *ci; 396 u32 regdata; 397 u32 base; 398 399 ci = core->chip; 400 base = core->pub.base; 401 /* 402 * Must do the disable sequence first to work for 403 * arbitrary current core state. 404 */ 405 brcmf_chip_sb_coredisable(core, 0, 0); 406 407 /* 408 * Now do the initialization sequence. 409 * set reset while enabling the clock and 410 * forcing them on throughout the core 411 */ 412 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 413 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 414 SSB_TMSLOW_RESET); 415 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 416 udelay(1); 417 418 /* clear any serror */ 419 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); 420 if (regdata & SSB_TMSHIGH_SERR) 421 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); 422 423 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate)); 424 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 425 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 426 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata); 427 } 428 429 /* clear reset and allow it to propagate throughout the core */ 430 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 431 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK); 432 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 433 udelay(1); 434 435 /* leave clock enabled */ 436 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 437 SSB_TMSLOW_CLOCK); 438 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 439 udelay(1); 440 } 441 442 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset, 443 u32 reset, u32 postreset) 444 { 445 struct brcmf_chip_priv *ci; 446 int count; 447 448 ci = core->chip; 449 450 /* must disable first to work for arbitrary current core state */ 451 brcmf_chip_ai_coredisable(core, prereset, reset); 452 453 count = 0; 454 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) & 455 BCMA_RESET_CTL_RESET) { 456 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0); 457 count++; 458 if (count > 50) 459 break; 460 usleep_range(40, 60); 461 } 462 463 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 464 postreset | BCMA_IOCTL_CLK); 465 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 466 } 467 468 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len) 469 { 470 const char *fmt; 471 472 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u"; 473 snprintf(buf, len, fmt, id, rev); 474 return buf; 475 } 476 477 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci, 478 u16 coreid, u32 base, 479 u32 wrapbase) 480 { 481 struct brcmf_core_priv *core; 482 483 core = kzalloc(sizeof(*core), GFP_KERNEL); 484 if (!core) 485 return ERR_PTR(-ENOMEM); 486 487 core->pub.id = coreid; 488 core->pub.base = base; 489 core->chip = ci; 490 core->wrapbase = wrapbase; 491 492 list_add_tail(&core->list, &ci->cores); 493 return &core->pub; 494 } 495 496 /* safety check for chipinfo */ 497 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci) 498 { 499 struct brcmf_core_priv *core; 500 bool need_socram = false; 501 bool has_socram = false; 502 bool cpu_found = false; 503 int idx = 1; 504 505 list_for_each_entry(core, &ci->cores, list) { 506 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n", 507 idx++, core->pub.id, core->pub.rev, core->pub.base, 508 core->wrapbase); 509 510 switch (core->pub.id) { 511 case BCMA_CORE_ARM_CM3: 512 cpu_found = true; 513 need_socram = true; 514 break; 515 case BCMA_CORE_INTERNAL_MEM: 516 has_socram = true; 517 break; 518 case BCMA_CORE_ARM_CR4: 519 cpu_found = true; 520 break; 521 case BCMA_CORE_ARM_CA7: 522 cpu_found = true; 523 break; 524 default: 525 break; 526 } 527 } 528 529 if (!cpu_found) { 530 brcmf_err("CPU core not detected\n"); 531 return -ENXIO; 532 } 533 /* check RAM core presence for ARM CM3 core */ 534 if (need_socram && !has_socram) { 535 brcmf_err("RAM core not provided with ARM CM3 core\n"); 536 return -ENODEV; 537 } 538 return 0; 539 } 540 541 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg) 542 { 543 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); 544 } 545 546 static void brcmf_chip_core_write32(struct brcmf_core_priv *core, 547 u16 reg, u32 val) 548 { 549 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); 550 } 551 552 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx, 553 u32 *banksize) 554 { 555 u32 bankinfo; 556 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT); 557 558 bankidx |= idx; 559 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx); 560 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo)); 561 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1; 562 *banksize *= SOCRAM_BANKINFO_SZBASE; 563 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK); 564 } 565 566 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize, 567 u32 *srsize) 568 { 569 u32 coreinfo; 570 uint nb, banksize, lss; 571 bool retent; 572 int i; 573 574 *ramsize = 0; 575 *srsize = 0; 576 577 if (WARN_ON(sr->pub.rev < 4)) 578 return; 579 580 if (!brcmf_chip_iscoreup(&sr->pub)) 581 brcmf_chip_resetcore(&sr->pub, 0, 0, 0); 582 583 /* Get info for determining size */ 584 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo)); 585 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 586 587 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) { 588 banksize = (coreinfo & SRCI_SRBSZ_MASK); 589 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; 590 if (lss != 0) 591 nb--; 592 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE)); 593 if (lss != 0) 594 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE)); 595 } else { 596 /* length of SRAM Banks increased for corerev greater than 23 */ 597 if (sr->pub.rev >= 23) { 598 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT)) 599 >> SRCI_SRNB_SHIFT; 600 } else { 601 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 602 } 603 for (i = 0; i < nb; i++) { 604 retent = brcmf_chip_socram_banksize(sr, i, &banksize); 605 *ramsize += banksize; 606 if (retent) 607 *srsize += banksize; 608 } 609 } 610 611 /* hardcoded save&restore memory sizes */ 612 switch (sr->chip->pub.chip) { 613 case BRCM_CC_4334_CHIP_ID: 614 if (sr->chip->pub.chiprev < 2) 615 *srsize = (32 * 1024); 616 break; 617 case BRCM_CC_43430_CHIP_ID: 618 /* assume sr for now as we can not check 619 * firmware sr capability at this point. 620 */ 621 *srsize = (64 * 1024); 622 break; 623 default: 624 break; 625 } 626 } 627 628 /** Return the SYS MEM size */ 629 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem) 630 { 631 u32 memsize = 0; 632 u32 coreinfo; 633 u32 idx; 634 u32 nb; 635 u32 banksize; 636 637 if (!brcmf_chip_iscoreup(&sysmem->pub)) 638 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0); 639 640 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo)); 641 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 642 643 for (idx = 0; idx < nb; idx++) { 644 brcmf_chip_socram_banksize(sysmem, idx, &banksize); 645 memsize += banksize; 646 } 647 648 return memsize; 649 } 650 651 /** Return the TCM-RAM size of the ARMCR4 core. */ 652 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4) 653 { 654 u32 corecap; 655 u32 memsize = 0; 656 u32 nab; 657 u32 nbb; 658 u32 totb; 659 u32 bxinfo; 660 u32 idx; 661 662 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP); 663 664 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT; 665 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT; 666 totb = nab + nbb; 667 668 for (idx = 0; idx < totb; idx++) { 669 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx); 670 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO); 671 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT; 672 } 673 674 return memsize; 675 } 676 677 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci) 678 { 679 switch (ci->pub.chip) { 680 case BRCM_CC_4345_CHIP_ID: 681 return 0x198000; 682 case BRCM_CC_4335_CHIP_ID: 683 case BRCM_CC_4339_CHIP_ID: 684 case BRCM_CC_4350_CHIP_ID: 685 case BRCM_CC_4354_CHIP_ID: 686 case BRCM_CC_4356_CHIP_ID: 687 case BRCM_CC_43567_CHIP_ID: 688 case BRCM_CC_43569_CHIP_ID: 689 case BRCM_CC_43570_CHIP_ID: 690 case BRCM_CC_4358_CHIP_ID: 691 case BRCM_CC_4359_CHIP_ID: 692 case BRCM_CC_43602_CHIP_ID: 693 case BRCM_CC_4371_CHIP_ID: 694 return 0x180000; 695 case BRCM_CC_43465_CHIP_ID: 696 case BRCM_CC_43525_CHIP_ID: 697 case BRCM_CC_4365_CHIP_ID: 698 case BRCM_CC_4366_CHIP_ID: 699 case BRCM_CC_43664_CHIP_ID: 700 return 0x200000; 701 case CY_CC_4373_CHIP_ID: 702 return 0x160000; 703 default: 704 brcmf_err("unknown chip: %s\n", ci->pub.name); 705 break; 706 } 707 return 0; 708 } 709 710 static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci) 711 { 712 struct brcmf_core_priv *mem_core; 713 struct brcmf_core *mem; 714 715 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4); 716 if (mem) { 717 mem_core = container_of(mem, struct brcmf_core_priv, pub); 718 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core); 719 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); 720 if (!ci->pub.rambase) { 721 brcmf_err("RAM base not provided with ARM CR4 core\n"); 722 return -EINVAL; 723 } 724 } else { 725 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM); 726 if (mem) { 727 mem_core = container_of(mem, struct brcmf_core_priv, 728 pub); 729 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core); 730 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); 731 if (!ci->pub.rambase) { 732 brcmf_err("RAM base not provided with ARM CA7 core\n"); 733 return -EINVAL; 734 } 735 } else { 736 mem = brcmf_chip_get_core(&ci->pub, 737 BCMA_CORE_INTERNAL_MEM); 738 if (!mem) { 739 brcmf_err("No memory cores found\n"); 740 return -ENOMEM; 741 } 742 mem_core = container_of(mem, struct brcmf_core_priv, 743 pub); 744 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize, 745 &ci->pub.srsize); 746 } 747 } 748 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n", 749 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize, 750 ci->pub.srsize, ci->pub.srsize); 751 752 if (!ci->pub.ramsize) { 753 brcmf_err("RAM size is undetermined\n"); 754 return -ENOMEM; 755 } 756 757 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) { 758 brcmf_err("RAM size is incorrect\n"); 759 return -ENOMEM; 760 } 761 762 return 0; 763 } 764 765 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr, 766 u8 *type) 767 { 768 u32 val; 769 770 /* read next descriptor */ 771 val = ci->ops->read32(ci->ctx, *eromaddr); 772 *eromaddr += 4; 773 774 if (!type) 775 return val; 776 777 /* determine descriptor type */ 778 *type = (val & DMP_DESC_TYPE_MSK); 779 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS) 780 *type = DMP_DESC_ADDRESS; 781 782 return val; 783 } 784 785 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr, 786 u32 *regbase, u32 *wrapbase) 787 { 788 u8 desc; 789 u32 val, szdesc; 790 u8 mpnum = 0; 791 u8 stype, sztype, wraptype; 792 793 *regbase = 0; 794 *wrapbase = 0; 795 796 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); 797 if (desc == DMP_DESC_MASTER_PORT) { 798 mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S; 799 wraptype = DMP_SLAVE_TYPE_MWRAP; 800 } else if (desc == DMP_DESC_ADDRESS) { 801 /* revert erom address */ 802 *eromaddr -= 4; 803 wraptype = DMP_SLAVE_TYPE_SWRAP; 804 } else { 805 *eromaddr -= 4; 806 return -EILSEQ; 807 } 808 809 do { 810 /* locate address descriptor */ 811 do { 812 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); 813 /* unexpected table end */ 814 if (desc == DMP_DESC_EOT) { 815 *eromaddr -= 4; 816 return -EFAULT; 817 } 818 } while (desc != DMP_DESC_ADDRESS && 819 desc != DMP_DESC_COMPONENT); 820 821 /* stop if we crossed current component border */ 822 if (desc == DMP_DESC_COMPONENT) { 823 *eromaddr -= 4; 824 return 0; 825 } 826 827 /* skip upper 32-bit address descriptor */ 828 if (val & DMP_DESC_ADDRSIZE_GT32) 829 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 830 831 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S; 832 833 /* next size descriptor can be skipped */ 834 if (sztype == DMP_SLAVE_SIZE_DESC) { 835 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 836 /* skip upper size descriptor if present */ 837 if (szdesc & DMP_DESC_ADDRSIZE_GT32) 838 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 839 } 840 841 /* look for 4K or 8K register regions */ 842 if (sztype != DMP_SLAVE_SIZE_4K && 843 sztype != DMP_SLAVE_SIZE_8K) 844 continue; 845 846 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S; 847 848 /* only regular slave and wrapper */ 849 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE) 850 *regbase = val & DMP_SLAVE_ADDR_BASE; 851 if (*wrapbase == 0 && stype == wraptype) 852 *wrapbase = val & DMP_SLAVE_ADDR_BASE; 853 } while (*regbase == 0 || *wrapbase == 0); 854 855 return 0; 856 } 857 858 static 859 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci) 860 { 861 struct brcmf_core *core; 862 u32 eromaddr; 863 u8 desc_type = 0; 864 u32 val; 865 u16 id; 866 u8 nmp, nsp, nmw, nsw, rev; 867 u32 base, wrap; 868 int err; 869 870 eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr)); 871 872 while (desc_type != DMP_DESC_EOT) { 873 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); 874 if (!(val & DMP_DESC_VALID)) 875 continue; 876 877 if (desc_type == DMP_DESC_EMPTY) 878 continue; 879 880 /* need a component descriptor */ 881 if (desc_type != DMP_DESC_COMPONENT) 882 continue; 883 884 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S; 885 886 /* next descriptor must be component as well */ 887 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); 888 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT)) 889 return -EFAULT; 890 891 /* only look at cores with master port(s) */ 892 nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S; 893 nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S; 894 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S; 895 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S; 896 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S; 897 898 /* need core with ports */ 899 if (nmw + nsw == 0 && 900 id != BCMA_CORE_PMU && 901 id != BCMA_CORE_GCI) 902 continue; 903 904 /* try to obtain register address info */ 905 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap); 906 if (err) 907 continue; 908 909 /* finally a core to be added */ 910 core = brcmf_chip_add_core(ci, id, base, wrap); 911 if (IS_ERR(core)) 912 return PTR_ERR(core); 913 914 core->rev = rev; 915 } 916 917 return 0; 918 } 919 920 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci) 921 { 922 struct brcmf_core *core; 923 u32 regdata; 924 u32 socitype; 925 int ret; 926 927 /* Get CC core rev 928 * Chipid is assume to be at offset 0 from SI_ENUM_BASE 929 * For different chiptypes or old sdio hosts w/o chipcommon, 930 * other ways of recognition should be added here. 931 */ 932 regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid)); 933 ci->pub.chip = regdata & CID_ID_MASK; 934 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; 935 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; 936 937 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev, 938 ci->pub.name, sizeof(ci->pub.name)); 939 brcmf_dbg(INFO, "found %s chip: %s\n", 940 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name); 941 942 if (socitype == SOCI_SB) { 943 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) { 944 brcmf_err("SB chip is not supported\n"); 945 return -ENODEV; 946 } 947 ci->iscoreup = brcmf_chip_sb_iscoreup; 948 ci->coredisable = brcmf_chip_sb_coredisable; 949 ci->resetcore = brcmf_chip_sb_resetcore; 950 951 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON, 952 SI_ENUM_BASE, 0); 953 brcmf_chip_sb_corerev(ci, core); 954 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV, 955 BCM4329_CORE_BUS_BASE, 0); 956 brcmf_chip_sb_corerev(ci, core); 957 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM, 958 BCM4329_CORE_SOCRAM_BASE, 0); 959 brcmf_chip_sb_corerev(ci, core); 960 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3, 961 BCM4329_CORE_ARM_BASE, 0); 962 brcmf_chip_sb_corerev(ci, core); 963 964 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0); 965 brcmf_chip_sb_corerev(ci, core); 966 } else if (socitype == SOCI_AI) { 967 ci->iscoreup = brcmf_chip_ai_iscoreup; 968 ci->coredisable = brcmf_chip_ai_coredisable; 969 ci->resetcore = brcmf_chip_ai_resetcore; 970 971 brcmf_chip_dmp_erom_scan(ci); 972 } else { 973 brcmf_err("chip backplane type %u is not supported\n", 974 socitype); 975 return -ENODEV; 976 } 977 978 ret = brcmf_chip_cores_check(ci); 979 if (ret) 980 return ret; 981 982 /* assure chip is passive for core access */ 983 brcmf_chip_set_passive(&ci->pub); 984 985 /* Call bus specific reset function now. Cores have been determined 986 * but further access may require a chip specific reset at this point. 987 */ 988 if (ci->ops->reset) { 989 ci->ops->reset(ci->ctx, &ci->pub); 990 brcmf_chip_set_passive(&ci->pub); 991 } 992 993 return brcmf_chip_get_raminfo(ci); 994 } 995 996 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id) 997 { 998 struct brcmf_core *core; 999 struct brcmf_core_priv *cpu; 1000 u32 val; 1001 1002 1003 core = brcmf_chip_get_core(&chip->pub, id); 1004 if (!core) 1005 return; 1006 1007 switch (id) { 1008 case BCMA_CORE_ARM_CM3: 1009 brcmf_chip_coredisable(core, 0, 0); 1010 break; 1011 case BCMA_CORE_ARM_CR4: 1012 case BCMA_CORE_ARM_CA7: 1013 cpu = container_of(core, struct brcmf_core_priv, pub); 1014 1015 /* clear all IOCTL bits except HALT bit */ 1016 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL); 1017 val &= ARMCR4_BCMA_IOCTL_CPUHALT; 1018 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT, 1019 ARMCR4_BCMA_IOCTL_CPUHALT); 1020 break; 1021 default: 1022 brcmf_err("unknown id: %u\n", id); 1023 break; 1024 } 1025 } 1026 1027 static int brcmf_chip_setup(struct brcmf_chip_priv *chip) 1028 { 1029 struct brcmf_chip *pub; 1030 struct brcmf_core_priv *cc; 1031 struct brcmf_core *pmu; 1032 u32 base; 1033 u32 val; 1034 int ret = 0; 1035 1036 pub = &chip->pub; 1037 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); 1038 base = cc->pub.base; 1039 1040 /* get chipcommon capabilites */ 1041 pub->cc_caps = chip->ops->read32(chip->ctx, 1042 CORE_CC_REG(base, capabilities)); 1043 pub->cc_caps_ext = chip->ops->read32(chip->ctx, 1044 CORE_CC_REG(base, 1045 capabilities_ext)); 1046 1047 /* get pmu caps & rev */ 1048 pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */ 1049 if (pub->cc_caps & CC_CAP_PMU) { 1050 val = chip->ops->read32(chip->ctx, 1051 CORE_CC_REG(pmu->base, pmucapabilities)); 1052 pub->pmurev = val & PCAP_REV_MASK; 1053 pub->pmucaps = val; 1054 } 1055 1056 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n", 1057 cc->pub.rev, pub->pmurev, pub->pmucaps); 1058 1059 /* execute bus core specific setup */ 1060 if (chip->ops->setup) 1061 ret = chip->ops->setup(chip->ctx, pub); 1062 1063 return ret; 1064 } 1065 1066 struct brcmf_chip *brcmf_chip_attach(void *ctx, 1067 const struct brcmf_buscore_ops *ops) 1068 { 1069 struct brcmf_chip_priv *chip; 1070 int err = 0; 1071 1072 if (WARN_ON(!ops->read32)) 1073 err = -EINVAL; 1074 if (WARN_ON(!ops->write32)) 1075 err = -EINVAL; 1076 if (WARN_ON(!ops->prepare)) 1077 err = -EINVAL; 1078 if (WARN_ON(!ops->activate)) 1079 err = -EINVAL; 1080 if (err < 0) 1081 return ERR_PTR(-EINVAL); 1082 1083 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1084 if (!chip) 1085 return ERR_PTR(-ENOMEM); 1086 1087 INIT_LIST_HEAD(&chip->cores); 1088 chip->num_cores = 0; 1089 chip->ops = ops; 1090 chip->ctx = ctx; 1091 1092 err = ops->prepare(ctx); 1093 if (err < 0) 1094 goto fail; 1095 1096 err = brcmf_chip_recognition(chip); 1097 if (err < 0) 1098 goto fail; 1099 1100 err = brcmf_chip_setup(chip); 1101 if (err < 0) 1102 goto fail; 1103 1104 return &chip->pub; 1105 1106 fail: 1107 brcmf_chip_detach(&chip->pub); 1108 return ERR_PTR(err); 1109 } 1110 1111 void brcmf_chip_detach(struct brcmf_chip *pub) 1112 { 1113 struct brcmf_chip_priv *chip; 1114 struct brcmf_core_priv *core; 1115 struct brcmf_core_priv *tmp; 1116 1117 chip = container_of(pub, struct brcmf_chip_priv, pub); 1118 list_for_each_entry_safe(core, tmp, &chip->cores, list) { 1119 list_del(&core->list); 1120 kfree(core); 1121 } 1122 kfree(chip); 1123 } 1124 1125 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid) 1126 { 1127 struct brcmf_chip_priv *chip; 1128 struct brcmf_core_priv *core; 1129 1130 chip = container_of(pub, struct brcmf_chip_priv, pub); 1131 list_for_each_entry(core, &chip->cores, list) 1132 if (core->pub.id == coreid) 1133 return &core->pub; 1134 1135 return NULL; 1136 } 1137 1138 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub) 1139 { 1140 struct brcmf_chip_priv *chip; 1141 struct brcmf_core_priv *cc; 1142 1143 chip = container_of(pub, struct brcmf_chip_priv, pub); 1144 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); 1145 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON)) 1146 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON); 1147 return &cc->pub; 1148 } 1149 1150 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub) 1151 { 1152 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub); 1153 struct brcmf_core *pmu; 1154 1155 /* See if there is separated PMU core available */ 1156 if (cc->rev >= 35 && 1157 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) { 1158 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU); 1159 if (pmu) 1160 return pmu; 1161 } 1162 1163 /* Fallback to ChipCommon core for older hardware */ 1164 return cc; 1165 } 1166 1167 bool brcmf_chip_iscoreup(struct brcmf_core *pub) 1168 { 1169 struct brcmf_core_priv *core; 1170 1171 core = container_of(pub, struct brcmf_core_priv, pub); 1172 return core->chip->iscoreup(core); 1173 } 1174 1175 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset) 1176 { 1177 struct brcmf_core_priv *core; 1178 1179 core = container_of(pub, struct brcmf_core_priv, pub); 1180 core->chip->coredisable(core, prereset, reset); 1181 } 1182 1183 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset, 1184 u32 postreset) 1185 { 1186 struct brcmf_core_priv *core; 1187 1188 core = container_of(pub, struct brcmf_core_priv, pub); 1189 core->chip->resetcore(core, prereset, reset, postreset); 1190 } 1191 1192 static void 1193 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip) 1194 { 1195 struct brcmf_core *core; 1196 struct brcmf_core_priv *sr; 1197 1198 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3); 1199 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1200 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1201 D11_BCMA_IOCTL_PHYCLOCKEN, 1202 D11_BCMA_IOCTL_PHYCLOCKEN, 1203 D11_BCMA_IOCTL_PHYCLOCKEN); 1204 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); 1205 brcmf_chip_resetcore(core, 0, 0, 0); 1206 1207 /* disable bank #3 remap for this device */ 1208 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) { 1209 sr = container_of(core, struct brcmf_core_priv, pub); 1210 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3); 1211 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0); 1212 } 1213 } 1214 1215 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip) 1216 { 1217 struct brcmf_core *core; 1218 1219 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); 1220 if (!brcmf_chip_iscoreup(core)) { 1221 brcmf_err("SOCRAM core is down after reset?\n"); 1222 return false; 1223 } 1224 1225 chip->ops->activate(chip->ctx, &chip->pub, 0); 1226 1227 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3); 1228 brcmf_chip_resetcore(core, 0, 0, 0); 1229 1230 return true; 1231 } 1232 1233 static inline void 1234 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip) 1235 { 1236 struct brcmf_core *core; 1237 1238 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4); 1239 1240 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1241 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1242 D11_BCMA_IOCTL_PHYCLOCKEN, 1243 D11_BCMA_IOCTL_PHYCLOCKEN, 1244 D11_BCMA_IOCTL_PHYCLOCKEN); 1245 } 1246 1247 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec) 1248 { 1249 struct brcmf_core *core; 1250 1251 chip->ops->activate(chip->ctx, &chip->pub, rstvec); 1252 1253 /* restore ARM */ 1254 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4); 1255 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); 1256 1257 return true; 1258 } 1259 1260 static inline void 1261 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip) 1262 { 1263 struct brcmf_core *core; 1264 1265 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7); 1266 1267 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1268 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1269 D11_BCMA_IOCTL_PHYCLOCKEN, 1270 D11_BCMA_IOCTL_PHYCLOCKEN, 1271 D11_BCMA_IOCTL_PHYCLOCKEN); 1272 } 1273 1274 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec) 1275 { 1276 struct brcmf_core *core; 1277 1278 chip->ops->activate(chip->ctx, &chip->pub, rstvec); 1279 1280 /* restore ARM */ 1281 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7); 1282 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); 1283 1284 return true; 1285 } 1286 1287 void brcmf_chip_set_passive(struct brcmf_chip *pub) 1288 { 1289 struct brcmf_chip_priv *chip; 1290 struct brcmf_core *arm; 1291 1292 brcmf_dbg(TRACE, "Enter\n"); 1293 1294 chip = container_of(pub, struct brcmf_chip_priv, pub); 1295 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4); 1296 if (arm) { 1297 brcmf_chip_cr4_set_passive(chip); 1298 return; 1299 } 1300 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7); 1301 if (arm) { 1302 brcmf_chip_ca7_set_passive(chip); 1303 return; 1304 } 1305 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3); 1306 if (arm) { 1307 brcmf_chip_cm3_set_passive(chip); 1308 return; 1309 } 1310 } 1311 1312 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec) 1313 { 1314 struct brcmf_chip_priv *chip; 1315 struct brcmf_core *arm; 1316 1317 brcmf_dbg(TRACE, "Enter\n"); 1318 1319 chip = container_of(pub, struct brcmf_chip_priv, pub); 1320 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4); 1321 if (arm) 1322 return brcmf_chip_cr4_set_active(chip, rstvec); 1323 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7); 1324 if (arm) 1325 return brcmf_chip_ca7_set_active(chip, rstvec); 1326 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3); 1327 if (arm) 1328 return brcmf_chip_cm3_set_active(chip); 1329 1330 return false; 1331 } 1332 1333 bool brcmf_chip_sr_capable(struct brcmf_chip *pub) 1334 { 1335 u32 base, addr, reg, pmu_cc3_mask = ~0; 1336 struct brcmf_chip_priv *chip; 1337 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub); 1338 1339 brcmf_dbg(TRACE, "Enter\n"); 1340 1341 /* old chips with PMU version less than 17 don't support save restore */ 1342 if (pub->pmurev < 17) 1343 return false; 1344 1345 base = brcmf_chip_get_chipcommon(pub)->base; 1346 chip = container_of(pub, struct brcmf_chip_priv, pub); 1347 1348 switch (pub->chip) { 1349 case BRCM_CC_4354_CHIP_ID: 1350 case BRCM_CC_4356_CHIP_ID: 1351 case BRCM_CC_4345_CHIP_ID: 1352 /* explicitly check SR engine enable bit */ 1353 pmu_cc3_mask = BIT(2); 1354 /* fall-through */ 1355 case BRCM_CC_43241_CHIP_ID: 1356 case BRCM_CC_4335_CHIP_ID: 1357 case BRCM_CC_4339_CHIP_ID: 1358 /* read PMU chipcontrol register 3 */ 1359 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 1360 chip->ops->write32(chip->ctx, addr, 3); 1361 addr = CORE_CC_REG(pmu->base, chipcontrol_data); 1362 reg = chip->ops->read32(chip->ctx, addr); 1363 return (reg & pmu_cc3_mask) != 0; 1364 case BRCM_CC_43430_CHIP_ID: 1365 addr = CORE_CC_REG(base, sr_control1); 1366 reg = chip->ops->read32(chip->ctx, addr); 1367 return reg != 0; 1368 case CY_CC_4373_CHIP_ID: 1369 /* explicitly check SR engine enable bit */ 1370 addr = CORE_CC_REG(base, sr_control0); 1371 reg = chip->ops->read32(chip->ctx, addr); 1372 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0; 1373 case CY_CC_43012_CHIP_ID: 1374 addr = CORE_CC_REG(pmu->base, retention_ctl); 1375 reg = chip->ops->read32(chip->ctx, addr); 1376 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | 1377 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; 1378 default: 1379 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext); 1380 reg = chip->ops->read32(chip->ctx, addr); 1381 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0) 1382 return false; 1383 1384 addr = CORE_CC_REG(pmu->base, retention_ctl); 1385 reg = chip->ops->read32(chip->ctx, addr); 1386 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | 1387 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; 1388 } 1389 } 1390