1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (c) 2014 Broadcom Corporation 4 */ 5 #include <linux/kernel.h> 6 #include <linux/delay.h> 7 #include <linux/list.h> 8 #include <linux/ssb/ssb_regs.h> 9 #include <linux/bcma/bcma.h> 10 #include <linux/bcma/bcma_regs.h> 11 12 #include <defs.h> 13 #include <soc.h> 14 #include <brcm_hw_ids.h> 15 #include <brcmu_utils.h> 16 #include <chipcommon.h> 17 #include "debug.h" 18 #include "chip.h" 19 20 /* SOC Interconnect types (aka chip types) */ 21 #define SOCI_SB 0 22 #define SOCI_AI 1 23 24 /* PL-368 DMP definitions */ 25 #define DMP_DESC_TYPE_MSK 0x0000000F 26 #define DMP_DESC_EMPTY 0x00000000 27 #define DMP_DESC_VALID 0x00000001 28 #define DMP_DESC_COMPONENT 0x00000001 29 #define DMP_DESC_MASTER_PORT 0x00000003 30 #define DMP_DESC_ADDRESS 0x00000005 31 #define DMP_DESC_ADDRSIZE_GT32 0x00000008 32 #define DMP_DESC_EOT 0x0000000F 33 34 #define DMP_COMP_DESIGNER 0xFFF00000 35 #define DMP_COMP_DESIGNER_S 20 36 #define DMP_COMP_PARTNUM 0x000FFF00 37 #define DMP_COMP_PARTNUM_S 8 38 #define DMP_COMP_CLASS 0x000000F0 39 #define DMP_COMP_CLASS_S 4 40 #define DMP_COMP_REVISION 0xFF000000 41 #define DMP_COMP_REVISION_S 24 42 #define DMP_COMP_NUM_SWRAP 0x00F80000 43 #define DMP_COMP_NUM_SWRAP_S 19 44 #define DMP_COMP_NUM_MWRAP 0x0007C000 45 #define DMP_COMP_NUM_MWRAP_S 14 46 #define DMP_COMP_NUM_SPORT 0x00003E00 47 #define DMP_COMP_NUM_SPORT_S 9 48 #define DMP_COMP_NUM_MPORT 0x000001F0 49 #define DMP_COMP_NUM_MPORT_S 4 50 51 #define DMP_MASTER_PORT_UID 0x0000FF00 52 #define DMP_MASTER_PORT_UID_S 8 53 #define DMP_MASTER_PORT_NUM 0x000000F0 54 #define DMP_MASTER_PORT_NUM_S 4 55 56 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000 57 #define DMP_SLAVE_ADDR_BASE_S 12 58 #define DMP_SLAVE_PORT_NUM 0x00000F00 59 #define DMP_SLAVE_PORT_NUM_S 8 60 #define DMP_SLAVE_TYPE 0x000000C0 61 #define DMP_SLAVE_TYPE_S 6 62 #define DMP_SLAVE_TYPE_SLAVE 0 63 #define DMP_SLAVE_TYPE_BRIDGE 1 64 #define DMP_SLAVE_TYPE_SWRAP 2 65 #define DMP_SLAVE_TYPE_MWRAP 3 66 #define DMP_SLAVE_SIZE_TYPE 0x00000030 67 #define DMP_SLAVE_SIZE_TYPE_S 4 68 #define DMP_SLAVE_SIZE_4K 0 69 #define DMP_SLAVE_SIZE_8K 1 70 #define DMP_SLAVE_SIZE_16K 2 71 #define DMP_SLAVE_SIZE_DESC 3 72 73 /* EROM CompIdentB */ 74 #define CIB_REV_MASK 0xff000000 75 #define CIB_REV_SHIFT 24 76 77 /* ARM CR4 core specific control flag bits */ 78 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020 79 80 /* D11 core specific control flag bits */ 81 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004 82 #define D11_BCMA_IOCTL_PHYRESET 0x0008 83 84 /* chip core base & ramsize */ 85 /* bcm4329 */ 86 /* SDIO device core, ID 0x829 */ 87 #define BCM4329_CORE_BUS_BASE 0x18011000 88 /* internal memory core, ID 0x80e */ 89 #define BCM4329_CORE_SOCRAM_BASE 0x18003000 90 /* ARM Cortex M3 core, ID 0x82a */ 91 #define BCM4329_CORE_ARM_BASE 0x18002000 92 93 /* Max possibly supported memory size (limited by IO mapped memory) */ 94 #define BRCMF_CHIP_MAX_MEMSIZE (4 * 1024 * 1024) 95 96 #define CORE_SB(base, field) \ 97 (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) 98 #define SBCOREREV(sbidh) \ 99 ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \ 100 ((sbidh) & SSB_IDHIGH_RCLO)) 101 102 struct sbconfig { 103 u32 PAD[2]; 104 u32 sbipsflag; /* initiator port ocp slave flag */ 105 u32 PAD[3]; 106 u32 sbtpsflag; /* target port ocp slave flag */ 107 u32 PAD[11]; 108 u32 sbtmerrloga; /* (sonics >= 2.3) */ 109 u32 PAD; 110 u32 sbtmerrlog; /* (sonics >= 2.3) */ 111 u32 PAD[3]; 112 u32 sbadmatch3; /* address match3 */ 113 u32 PAD; 114 u32 sbadmatch2; /* address match2 */ 115 u32 PAD; 116 u32 sbadmatch1; /* address match1 */ 117 u32 PAD[7]; 118 u32 sbimstate; /* initiator agent state */ 119 u32 sbintvec; /* interrupt mask */ 120 u32 sbtmstatelow; /* target state */ 121 u32 sbtmstatehigh; /* target state */ 122 u32 sbbwa0; /* bandwidth allocation table0 */ 123 u32 PAD; 124 u32 sbimconfiglow; /* initiator configuration */ 125 u32 sbimconfighigh; /* initiator configuration */ 126 u32 sbadmatch0; /* address match0 */ 127 u32 PAD; 128 u32 sbtmconfiglow; /* target configuration */ 129 u32 sbtmconfighigh; /* target configuration */ 130 u32 sbbconfig; /* broadcast configuration */ 131 u32 PAD; 132 u32 sbbstate; /* broadcast state */ 133 u32 PAD[3]; 134 u32 sbactcnfg; /* activate configuration */ 135 u32 PAD[3]; 136 u32 sbflagst; /* current sbflags */ 137 u32 PAD[3]; 138 u32 sbidlow; /* identification */ 139 u32 sbidhigh; /* identification */ 140 }; 141 142 #define INVALID_RAMBASE ((u32)(~0)) 143 144 /* bankidx and bankinfo reg defines corerev >= 8 */ 145 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 146 #define SOCRAM_BANKINFO_SZMASK 0x0000007f 147 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100 148 149 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 150 /* socram bankinfo memtype */ 151 #define SOCRAM_MEMTYPE_RAM 0 152 #define SOCRAM_MEMTYPE_R0M 1 153 #define SOCRAM_MEMTYPE_DEVRAM 2 154 155 #define SOCRAM_BANKINFO_SZBASE 8192 156 #define SRCI_LSS_MASK 0x00f00000 157 #define SRCI_LSS_SHIFT 20 158 #define SRCI_SRNB_MASK 0xf0 159 #define SRCI_SRNB_MASK_EXT 0x100 160 #define SRCI_SRNB_SHIFT 4 161 #define SRCI_SRBSZ_MASK 0xf 162 #define SRCI_SRBSZ_SHIFT 0 163 #define SR_BSZ_BASE 14 164 165 struct sbsocramregs { 166 u32 coreinfo; 167 u32 bwalloc; 168 u32 extracoreinfo; 169 u32 biststat; 170 u32 bankidx; 171 u32 standbyctrl; 172 173 u32 errlogstatus; /* rev 6 */ 174 u32 errlogaddr; /* rev 6 */ 175 /* used for patching rev 3 & 5 */ 176 u32 cambankidx; 177 u32 cambankstandbyctrl; 178 u32 cambankpatchctrl; 179 u32 cambankpatchtblbaseaddr; 180 u32 cambankcmdreg; 181 u32 cambankdatareg; 182 u32 cambankmaskreg; 183 u32 PAD[1]; 184 u32 bankinfo; /* corev 8 */ 185 u32 bankpda; 186 u32 PAD[14]; 187 u32 extmemconfig; 188 u32 extmemparitycsr; 189 u32 extmemparityerrdata; 190 u32 extmemparityerrcnt; 191 u32 extmemwrctrlandsize; 192 u32 PAD[84]; 193 u32 workaround; 194 u32 pwrctl; /* corerev >= 2 */ 195 u32 PAD[133]; 196 u32 sr_control; /* corerev >= 15 */ 197 u32 sr_status; /* corerev >= 15 */ 198 u32 sr_address; /* corerev >= 15 */ 199 u32 sr_data; /* corerev >= 15 */ 200 }; 201 202 #define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f) 203 #define SYSMEMREGOFFS(_f) offsetof(struct sbsocramregs, _f) 204 205 #define ARMCR4_CAP (0x04) 206 #define ARMCR4_BANKIDX (0x40) 207 #define ARMCR4_BANKINFO (0x44) 208 #define ARMCR4_BANKPDA (0x4C) 209 210 #define ARMCR4_TCBBNB_MASK 0xf0 211 #define ARMCR4_TCBBNB_SHIFT 4 212 #define ARMCR4_TCBANB_MASK 0xf 213 #define ARMCR4_TCBANB_SHIFT 0 214 215 #define ARMCR4_BSZ_MASK 0x3f 216 #define ARMCR4_BSZ_MULT 8192 217 218 struct brcmf_core_priv { 219 struct brcmf_core pub; 220 u32 wrapbase; 221 struct list_head list; 222 struct brcmf_chip_priv *chip; 223 }; 224 225 struct brcmf_chip_priv { 226 struct brcmf_chip pub; 227 const struct brcmf_buscore_ops *ops; 228 void *ctx; 229 /* assured first core is chipcommon, second core is buscore */ 230 struct list_head cores; 231 u16 num_cores; 232 233 bool (*iscoreup)(struct brcmf_core_priv *core); 234 void (*coredisable)(struct brcmf_core_priv *core, u32 prereset, 235 u32 reset); 236 void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset, 237 u32 postreset); 238 }; 239 240 static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci, 241 struct brcmf_core *core) 242 { 243 u32 regdata; 244 245 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); 246 core->rev = SBCOREREV(regdata); 247 } 248 249 static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core) 250 { 251 struct brcmf_chip_priv *ci; 252 u32 regdata; 253 u32 address; 254 255 ci = core->chip; 256 address = CORE_SB(core->pub.base, sbtmstatelow); 257 regdata = ci->ops->read32(ci->ctx, address); 258 regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT | 259 SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK); 260 return SSB_TMSLOW_CLOCK == regdata; 261 } 262 263 static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core) 264 { 265 struct brcmf_chip_priv *ci; 266 u32 regdata; 267 bool ret; 268 269 ci = core->chip; 270 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 271 ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK; 272 273 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); 274 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); 275 276 return ret; 277 } 278 279 static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core, 280 u32 prereset, u32 reset) 281 { 282 struct brcmf_chip_priv *ci; 283 u32 val, base; 284 285 ci = core->chip; 286 base = core->pub.base; 287 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 288 if (val & SSB_TMSLOW_RESET) 289 return; 290 291 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 292 if ((val & SSB_TMSLOW_CLOCK) != 0) { 293 /* 294 * set target reject and spin until busy is clear 295 * (preserve core-specific bits) 296 */ 297 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 298 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 299 val | SSB_TMSLOW_REJECT); 300 301 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 302 udelay(1); 303 SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)) 304 & SSB_TMSHIGH_BUSY), 100000); 305 306 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); 307 if (val & SSB_TMSHIGH_BUSY) 308 brcmf_err("core state still busy\n"); 309 310 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); 311 if (val & SSB_IDLOW_INITIATOR) { 312 val = ci->ops->read32(ci->ctx, 313 CORE_SB(base, sbimstate)); 314 val |= SSB_IMSTATE_REJECT; 315 ci->ops->write32(ci->ctx, 316 CORE_SB(base, sbimstate), val); 317 val = ci->ops->read32(ci->ctx, 318 CORE_SB(base, sbimstate)); 319 udelay(1); 320 SPINWAIT((ci->ops->read32(ci->ctx, 321 CORE_SB(base, sbimstate)) & 322 SSB_IMSTATE_BUSY), 100000); 323 } 324 325 /* set reset and reject while enabling the clocks */ 326 val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 327 SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET; 328 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val); 329 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 330 udelay(10); 331 332 /* clear the initiator reject bit */ 333 val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow)); 334 if (val & SSB_IDLOW_INITIATOR) { 335 val = ci->ops->read32(ci->ctx, 336 CORE_SB(base, sbimstate)); 337 val &= ~SSB_IMSTATE_REJECT; 338 ci->ops->write32(ci->ctx, 339 CORE_SB(base, sbimstate), val); 340 } 341 } 342 343 /* leave reset and reject asserted */ 344 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 345 (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET)); 346 udelay(1); 347 } 348 349 static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core, 350 u32 prereset, u32 reset) 351 { 352 struct brcmf_chip_priv *ci; 353 u32 regdata; 354 355 ci = core->chip; 356 357 /* if core is already in reset, skip reset */ 358 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); 359 if ((regdata & BCMA_RESET_CTL_RESET) != 0) 360 goto in_reset_configure; 361 362 /* configure reset */ 363 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 364 prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); 365 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 366 367 /* put in reset */ 368 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 369 BCMA_RESET_CTL_RESET); 370 usleep_range(10, 20); 371 372 /* wait till reset is 1 */ 373 SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) != 374 BCMA_RESET_CTL_RESET, 300); 375 376 in_reset_configure: 377 /* in-reset configure */ 378 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 379 reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK); 380 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 381 } 382 383 static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset, 384 u32 reset, u32 postreset) 385 { 386 struct brcmf_chip_priv *ci; 387 u32 regdata; 388 u32 base; 389 390 ci = core->chip; 391 base = core->pub.base; 392 /* 393 * Must do the disable sequence first to work for 394 * arbitrary current core state. 395 */ 396 brcmf_chip_sb_coredisable(core, 0, 0); 397 398 /* 399 * Now do the initialization sequence. 400 * set reset while enabling the clock and 401 * forcing them on throughout the core 402 */ 403 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 404 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | 405 SSB_TMSLOW_RESET); 406 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 407 udelay(1); 408 409 /* clear any serror */ 410 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh)); 411 if (regdata & SSB_TMSHIGH_SERR) 412 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); 413 414 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate)); 415 if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { 416 regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); 417 ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata); 418 } 419 420 /* clear reset and allow it to propagate throughout the core */ 421 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 422 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK); 423 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 424 udelay(1); 425 426 /* leave clock enabled */ 427 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), 428 SSB_TMSLOW_CLOCK); 429 regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow)); 430 udelay(1); 431 } 432 433 static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset, 434 u32 reset, u32 postreset) 435 { 436 struct brcmf_chip_priv *ci; 437 int count; 438 struct brcmf_core *d11core2 = NULL; 439 struct brcmf_core_priv *d11priv2 = NULL; 440 441 ci = core->chip; 442 443 /* special handle two D11 cores reset */ 444 if (core->pub.id == BCMA_CORE_80211) { 445 d11core2 = brcmf_chip_get_d11core(&ci->pub, 1); 446 if (d11core2) { 447 brcmf_dbg(INFO, "found two d11 cores, reset both\n"); 448 d11priv2 = container_of(d11core2, 449 struct brcmf_core_priv, pub); 450 } 451 } 452 453 /* must disable first to work for arbitrary current core state */ 454 brcmf_chip_ai_coredisable(core, prereset, reset); 455 if (d11priv2) 456 brcmf_chip_ai_coredisable(d11priv2, prereset, reset); 457 458 count = 0; 459 while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) & 460 BCMA_RESET_CTL_RESET) { 461 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0); 462 count++; 463 if (count > 50) 464 break; 465 usleep_range(40, 60); 466 } 467 468 if (d11priv2) { 469 count = 0; 470 while (ci->ops->read32(ci->ctx, 471 d11priv2->wrapbase + BCMA_RESET_CTL) & 472 BCMA_RESET_CTL_RESET) { 473 ci->ops->write32(ci->ctx, 474 d11priv2->wrapbase + BCMA_RESET_CTL, 475 0); 476 count++; 477 if (count > 50) 478 break; 479 usleep_range(40, 60); 480 } 481 } 482 483 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL, 484 postreset | BCMA_IOCTL_CLK); 485 ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); 486 487 if (d11priv2) { 488 ci->ops->write32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL, 489 postreset | BCMA_IOCTL_CLK); 490 ci->ops->read32(ci->ctx, d11priv2->wrapbase + BCMA_IOCTL); 491 } 492 } 493 494 char *brcmf_chip_name(u32 id, u32 rev, char *buf, uint len) 495 { 496 const char *fmt; 497 498 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u"; 499 snprintf(buf, len, fmt, id, rev); 500 return buf; 501 } 502 503 static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci, 504 u16 coreid, u32 base, 505 u32 wrapbase) 506 { 507 struct brcmf_core_priv *core; 508 509 core = kzalloc(sizeof(*core), GFP_KERNEL); 510 if (!core) 511 return ERR_PTR(-ENOMEM); 512 513 core->pub.id = coreid; 514 core->pub.base = base; 515 core->chip = ci; 516 core->wrapbase = wrapbase; 517 518 list_add_tail(&core->list, &ci->cores); 519 return &core->pub; 520 } 521 522 /* safety check for chipinfo */ 523 static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci) 524 { 525 struct brcmf_core_priv *core; 526 bool need_socram = false; 527 bool has_socram = false; 528 bool cpu_found = false; 529 int idx = 1; 530 531 list_for_each_entry(core, &ci->cores, list) { 532 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n", 533 idx++, core->pub.id, core->pub.rev, core->pub.base, 534 core->wrapbase); 535 536 switch (core->pub.id) { 537 case BCMA_CORE_ARM_CM3: 538 cpu_found = true; 539 need_socram = true; 540 break; 541 case BCMA_CORE_INTERNAL_MEM: 542 has_socram = true; 543 break; 544 case BCMA_CORE_ARM_CR4: 545 cpu_found = true; 546 break; 547 case BCMA_CORE_ARM_CA7: 548 cpu_found = true; 549 break; 550 default: 551 break; 552 } 553 } 554 555 if (!cpu_found) { 556 brcmf_err("CPU core not detected\n"); 557 return -ENXIO; 558 } 559 /* check RAM core presence for ARM CM3 core */ 560 if (need_socram && !has_socram) { 561 brcmf_err("RAM core not provided with ARM CM3 core\n"); 562 return -ENODEV; 563 } 564 return 0; 565 } 566 567 static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg) 568 { 569 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); 570 } 571 572 static void brcmf_chip_core_write32(struct brcmf_core_priv *core, 573 u16 reg, u32 val) 574 { 575 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); 576 } 577 578 static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx, 579 u32 *banksize) 580 { 581 u32 bankinfo; 582 u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT); 583 584 bankidx |= idx; 585 brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx); 586 bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo)); 587 *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1; 588 *banksize *= SOCRAM_BANKINFO_SZBASE; 589 return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK); 590 } 591 592 static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize, 593 u32 *srsize) 594 { 595 u32 coreinfo; 596 uint nb, banksize, lss; 597 bool retent; 598 int i; 599 600 *ramsize = 0; 601 *srsize = 0; 602 603 if (WARN_ON(sr->pub.rev < 4)) 604 return; 605 606 if (!brcmf_chip_iscoreup(&sr->pub)) 607 brcmf_chip_resetcore(&sr->pub, 0, 0, 0); 608 609 /* Get info for determining size */ 610 coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo)); 611 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 612 613 if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) { 614 banksize = (coreinfo & SRCI_SRBSZ_MASK); 615 lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT; 616 if (lss != 0) 617 nb--; 618 *ramsize = nb * (1 << (banksize + SR_BSZ_BASE)); 619 if (lss != 0) 620 *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE)); 621 } else { 622 /* length of SRAM Banks increased for corerev greater than 23 */ 623 if (sr->pub.rev >= 23) { 624 nb = (coreinfo & (SRCI_SRNB_MASK | SRCI_SRNB_MASK_EXT)) 625 >> SRCI_SRNB_SHIFT; 626 } else { 627 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 628 } 629 for (i = 0; i < nb; i++) { 630 retent = brcmf_chip_socram_banksize(sr, i, &banksize); 631 *ramsize += banksize; 632 if (retent) 633 *srsize += banksize; 634 } 635 } 636 637 /* hardcoded save&restore memory sizes */ 638 switch (sr->chip->pub.chip) { 639 case BRCM_CC_4334_CHIP_ID: 640 if (sr->chip->pub.chiprev < 2) 641 *srsize = (32 * 1024); 642 break; 643 case BRCM_CC_43430_CHIP_ID: 644 case CY_CC_43439_CHIP_ID: 645 /* assume sr for now as we can not check 646 * firmware sr capability at this point. 647 */ 648 *srsize = (64 * 1024); 649 break; 650 default: 651 break; 652 } 653 } 654 655 /** Return the SYS MEM size */ 656 static u32 brcmf_chip_sysmem_ramsize(struct brcmf_core_priv *sysmem) 657 { 658 u32 memsize = 0; 659 u32 coreinfo; 660 u32 idx; 661 u32 nb; 662 u32 banksize; 663 664 if (!brcmf_chip_iscoreup(&sysmem->pub)) 665 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0); 666 667 coreinfo = brcmf_chip_core_read32(sysmem, SYSMEMREGOFFS(coreinfo)); 668 nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT; 669 670 for (idx = 0; idx < nb; idx++) { 671 brcmf_chip_socram_banksize(sysmem, idx, &banksize); 672 memsize += banksize; 673 } 674 675 return memsize; 676 } 677 678 /** Return the TCM-RAM size of the ARMCR4 core. */ 679 static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4) 680 { 681 u32 corecap; 682 u32 memsize = 0; 683 u32 nab; 684 u32 nbb; 685 u32 totb; 686 u32 bxinfo; 687 u32 idx; 688 689 corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP); 690 691 nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT; 692 nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT; 693 totb = nab + nbb; 694 695 for (idx = 0; idx < totb; idx++) { 696 brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx); 697 bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO); 698 memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT; 699 } 700 701 return memsize; 702 } 703 704 static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci) 705 { 706 switch (ci->pub.chip) { 707 case BRCM_CC_4345_CHIP_ID: 708 case BRCM_CC_43454_CHIP_ID: 709 return 0x198000; 710 case BRCM_CC_4335_CHIP_ID: 711 case BRCM_CC_4339_CHIP_ID: 712 case BRCM_CC_4350_CHIP_ID: 713 case BRCM_CC_4354_CHIP_ID: 714 case BRCM_CC_4356_CHIP_ID: 715 case BRCM_CC_43567_CHIP_ID: 716 case BRCM_CC_43569_CHIP_ID: 717 case BRCM_CC_43570_CHIP_ID: 718 case BRCM_CC_4358_CHIP_ID: 719 case BRCM_CC_43602_CHIP_ID: 720 case BRCM_CC_4371_CHIP_ID: 721 return 0x180000; 722 case BRCM_CC_43465_CHIP_ID: 723 case BRCM_CC_43525_CHIP_ID: 724 case BRCM_CC_4365_CHIP_ID: 725 case BRCM_CC_4366_CHIP_ID: 726 case BRCM_CC_43664_CHIP_ID: 727 case BRCM_CC_43666_CHIP_ID: 728 return 0x200000; 729 case BRCM_CC_4359_CHIP_ID: 730 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000; 731 case BRCM_CC_4364_CHIP_ID: 732 case CY_CC_4373_CHIP_ID: 733 return 0x160000; 734 case CY_CC_43752_CHIP_ID: 735 return 0x170000; 736 case BRCM_CC_4378_CHIP_ID: 737 return 0x352000; 738 case CY_CC_89459_CHIP_ID: 739 return ((ci->pub.chiprev < 9) ? 0x180000 : 0x160000); 740 default: 741 brcmf_err("unknown chip: %s\n", ci->pub.name); 742 break; 743 } 744 return INVALID_RAMBASE; 745 } 746 747 int brcmf_chip_get_raminfo(struct brcmf_chip *pub) 748 { 749 struct brcmf_chip_priv *ci = container_of(pub, struct brcmf_chip_priv, 750 pub); 751 struct brcmf_core_priv *mem_core; 752 struct brcmf_core *mem; 753 754 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4); 755 if (mem) { 756 mem_core = container_of(mem, struct brcmf_core_priv, pub); 757 ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core); 758 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); 759 if (ci->pub.rambase == INVALID_RAMBASE) { 760 brcmf_err("RAM base not provided with ARM CR4 core\n"); 761 return -EINVAL; 762 } 763 } else { 764 mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_SYS_MEM); 765 if (mem) { 766 mem_core = container_of(mem, struct brcmf_core_priv, 767 pub); 768 ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core); 769 ci->pub.rambase = brcmf_chip_tcm_rambase(ci); 770 if (ci->pub.rambase == INVALID_RAMBASE) { 771 brcmf_err("RAM base not provided with ARM CA7 core\n"); 772 return -EINVAL; 773 } 774 } else { 775 mem = brcmf_chip_get_core(&ci->pub, 776 BCMA_CORE_INTERNAL_MEM); 777 if (!mem) { 778 brcmf_err("No memory cores found\n"); 779 return -ENOMEM; 780 } 781 mem_core = container_of(mem, struct brcmf_core_priv, 782 pub); 783 brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize, 784 &ci->pub.srsize); 785 } 786 } 787 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n", 788 ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize, 789 ci->pub.srsize, ci->pub.srsize); 790 791 if (!ci->pub.ramsize) { 792 brcmf_err("RAM size is undetermined\n"); 793 return -ENOMEM; 794 } 795 796 if (ci->pub.ramsize > BRCMF_CHIP_MAX_MEMSIZE) { 797 brcmf_err("RAM size is incorrect\n"); 798 return -ENOMEM; 799 } 800 801 return 0; 802 } 803 804 static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr, 805 u8 *type) 806 { 807 u32 val; 808 809 /* read next descriptor */ 810 val = ci->ops->read32(ci->ctx, *eromaddr); 811 *eromaddr += 4; 812 813 if (!type) 814 return val; 815 816 /* determine descriptor type */ 817 *type = (val & DMP_DESC_TYPE_MSK); 818 if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS) 819 *type = DMP_DESC_ADDRESS; 820 821 return val; 822 } 823 824 static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr, 825 u32 *regbase, u32 *wrapbase) 826 { 827 u8 desc; 828 u32 val, szdesc; 829 u8 stype, sztype, wraptype; 830 831 *regbase = 0; 832 *wrapbase = 0; 833 834 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); 835 if (desc == DMP_DESC_MASTER_PORT) { 836 wraptype = DMP_SLAVE_TYPE_MWRAP; 837 } else if (desc == DMP_DESC_ADDRESS) { 838 /* revert erom address */ 839 *eromaddr -= 4; 840 wraptype = DMP_SLAVE_TYPE_SWRAP; 841 } else { 842 *eromaddr -= 4; 843 return -EILSEQ; 844 } 845 846 do { 847 /* locate address descriptor */ 848 do { 849 val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc); 850 /* unexpected table end */ 851 if (desc == DMP_DESC_EOT) { 852 *eromaddr -= 4; 853 return -EFAULT; 854 } 855 } while (desc != DMP_DESC_ADDRESS && 856 desc != DMP_DESC_COMPONENT); 857 858 /* stop if we crossed current component border */ 859 if (desc == DMP_DESC_COMPONENT) { 860 *eromaddr -= 4; 861 return 0; 862 } 863 864 /* skip upper 32-bit address descriptor */ 865 if (val & DMP_DESC_ADDRSIZE_GT32) 866 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 867 868 sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S; 869 870 /* next size descriptor can be skipped */ 871 if (sztype == DMP_SLAVE_SIZE_DESC) { 872 szdesc = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 873 /* skip upper size descriptor if present */ 874 if (szdesc & DMP_DESC_ADDRSIZE_GT32) 875 brcmf_chip_dmp_get_desc(ci, eromaddr, NULL); 876 } 877 878 /* look for 4K or 8K register regions */ 879 if (sztype != DMP_SLAVE_SIZE_4K && 880 sztype != DMP_SLAVE_SIZE_8K) 881 continue; 882 883 stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S; 884 885 /* only regular slave and wrapper */ 886 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE) 887 *regbase = val & DMP_SLAVE_ADDR_BASE; 888 if (*wrapbase == 0 && stype == wraptype) 889 *wrapbase = val & DMP_SLAVE_ADDR_BASE; 890 } while (*regbase == 0 || *wrapbase == 0); 891 892 return 0; 893 } 894 895 static 896 int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci) 897 { 898 struct brcmf_core *core; 899 u32 eromaddr; 900 u8 desc_type = 0; 901 u32 val; 902 u16 id; 903 u8 nmw, nsw, rev; 904 u32 base, wrap; 905 int err; 906 907 eromaddr = ci->ops->read32(ci->ctx, 908 CORE_CC_REG(ci->pub.enum_base, eromptr)); 909 910 while (desc_type != DMP_DESC_EOT) { 911 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); 912 if (!(val & DMP_DESC_VALID)) 913 continue; 914 915 if (desc_type == DMP_DESC_EMPTY) 916 continue; 917 918 /* need a component descriptor */ 919 if (desc_type != DMP_DESC_COMPONENT) 920 continue; 921 922 id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S; 923 924 /* next descriptor must be component as well */ 925 val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type); 926 if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT)) 927 return -EFAULT; 928 929 /* only look at cores with master port(s) */ 930 nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S; 931 nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S; 932 rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S; 933 934 /* need core with ports */ 935 if (nmw + nsw == 0 && 936 id != BCMA_CORE_PMU && 937 id != BCMA_CORE_GCI) 938 continue; 939 940 /* try to obtain register address info */ 941 err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap); 942 if (err) 943 continue; 944 945 /* finally a core to be added */ 946 core = brcmf_chip_add_core(ci, id, base, wrap); 947 if (IS_ERR(core)) 948 return PTR_ERR(core); 949 950 core->rev = rev; 951 } 952 953 return 0; 954 } 955 956 u32 brcmf_chip_enum_base(u16 devid) 957 { 958 return SI_ENUM_BASE_DEFAULT; 959 } 960 961 static int brcmf_chip_recognition(struct brcmf_chip_priv *ci) 962 { 963 struct brcmf_core *core; 964 u32 regdata; 965 u32 socitype; 966 int ret; 967 968 /* Get CC core rev 969 * Chipid is assume to be at offset 0 from SI_ENUM_BASE 970 * For different chiptypes or old sdio hosts w/o chipcommon, 971 * other ways of recognition should be added here. 972 */ 973 regdata = ci->ops->read32(ci->ctx, 974 CORE_CC_REG(ci->pub.enum_base, chipid)); 975 ci->pub.chip = regdata & CID_ID_MASK; 976 ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT; 977 socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT; 978 979 brcmf_chip_name(ci->pub.chip, ci->pub.chiprev, 980 ci->pub.name, sizeof(ci->pub.name)); 981 brcmf_dbg(INFO, "found %s chip: %s\n", 982 socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name); 983 984 if (socitype == SOCI_SB) { 985 if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) { 986 brcmf_err("SB chip is not supported\n"); 987 return -ENODEV; 988 } 989 ci->iscoreup = brcmf_chip_sb_iscoreup; 990 ci->coredisable = brcmf_chip_sb_coredisable; 991 ci->resetcore = brcmf_chip_sb_resetcore; 992 993 core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON, 994 SI_ENUM_BASE_DEFAULT, 0); 995 brcmf_chip_sb_corerev(ci, core); 996 core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV, 997 BCM4329_CORE_BUS_BASE, 0); 998 brcmf_chip_sb_corerev(ci, core); 999 core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM, 1000 BCM4329_CORE_SOCRAM_BASE, 0); 1001 brcmf_chip_sb_corerev(ci, core); 1002 core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3, 1003 BCM4329_CORE_ARM_BASE, 0); 1004 brcmf_chip_sb_corerev(ci, core); 1005 1006 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0); 1007 brcmf_chip_sb_corerev(ci, core); 1008 } else if (socitype == SOCI_AI) { 1009 ci->iscoreup = brcmf_chip_ai_iscoreup; 1010 ci->coredisable = brcmf_chip_ai_coredisable; 1011 ci->resetcore = brcmf_chip_ai_resetcore; 1012 1013 brcmf_chip_dmp_erom_scan(ci); 1014 } else { 1015 brcmf_err("chip backplane type %u is not supported\n", 1016 socitype); 1017 return -ENODEV; 1018 } 1019 1020 ret = brcmf_chip_cores_check(ci); 1021 if (ret) 1022 return ret; 1023 1024 /* assure chip is passive for core access */ 1025 brcmf_chip_set_passive(&ci->pub); 1026 1027 /* Call bus specific reset function now. Cores have been determined 1028 * but further access may require a chip specific reset at this point. 1029 */ 1030 if (ci->ops->reset) { 1031 ci->ops->reset(ci->ctx, &ci->pub); 1032 brcmf_chip_set_passive(&ci->pub); 1033 } 1034 1035 return brcmf_chip_get_raminfo(&ci->pub); 1036 } 1037 1038 static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id) 1039 { 1040 struct brcmf_core *core; 1041 struct brcmf_core_priv *cpu; 1042 u32 val; 1043 1044 1045 core = brcmf_chip_get_core(&chip->pub, id); 1046 if (!core) 1047 return; 1048 1049 switch (id) { 1050 case BCMA_CORE_ARM_CM3: 1051 brcmf_chip_coredisable(core, 0, 0); 1052 break; 1053 case BCMA_CORE_ARM_CR4: 1054 case BCMA_CORE_ARM_CA7: 1055 cpu = container_of(core, struct brcmf_core_priv, pub); 1056 1057 /* clear all IOCTL bits except HALT bit */ 1058 val = chip->ops->read32(chip->ctx, cpu->wrapbase + BCMA_IOCTL); 1059 val &= ARMCR4_BCMA_IOCTL_CPUHALT; 1060 brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT, 1061 ARMCR4_BCMA_IOCTL_CPUHALT); 1062 break; 1063 default: 1064 brcmf_err("unknown id: %u\n", id); 1065 break; 1066 } 1067 } 1068 1069 static int brcmf_chip_setup(struct brcmf_chip_priv *chip) 1070 { 1071 struct brcmf_chip *pub; 1072 struct brcmf_core_priv *cc; 1073 struct brcmf_core *pmu; 1074 u32 base; 1075 u32 val; 1076 int ret = 0; 1077 1078 pub = &chip->pub; 1079 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); 1080 base = cc->pub.base; 1081 1082 /* get chipcommon capabilites */ 1083 pub->cc_caps = chip->ops->read32(chip->ctx, 1084 CORE_CC_REG(base, capabilities)); 1085 pub->cc_caps_ext = chip->ops->read32(chip->ctx, 1086 CORE_CC_REG(base, 1087 capabilities_ext)); 1088 1089 /* get pmu caps & rev */ 1090 pmu = brcmf_chip_get_pmu(pub); /* after reading cc_caps_ext */ 1091 if (pub->cc_caps & CC_CAP_PMU) { 1092 val = chip->ops->read32(chip->ctx, 1093 CORE_CC_REG(pmu->base, pmucapabilities)); 1094 pub->pmurev = val & PCAP_REV_MASK; 1095 pub->pmucaps = val; 1096 } 1097 1098 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n", 1099 cc->pub.rev, pub->pmurev, pub->pmucaps); 1100 1101 /* execute bus core specific setup */ 1102 if (chip->ops->setup) 1103 ret = chip->ops->setup(chip->ctx, pub); 1104 1105 return ret; 1106 } 1107 1108 struct brcmf_chip *brcmf_chip_attach(void *ctx, u16 devid, 1109 const struct brcmf_buscore_ops *ops) 1110 { 1111 struct brcmf_chip_priv *chip; 1112 int err = 0; 1113 1114 if (WARN_ON(!ops->read32)) 1115 err = -EINVAL; 1116 if (WARN_ON(!ops->write32)) 1117 err = -EINVAL; 1118 if (WARN_ON(!ops->prepare)) 1119 err = -EINVAL; 1120 if (WARN_ON(!ops->activate)) 1121 err = -EINVAL; 1122 if (err < 0) 1123 return ERR_PTR(-EINVAL); 1124 1125 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1126 if (!chip) 1127 return ERR_PTR(-ENOMEM); 1128 1129 INIT_LIST_HEAD(&chip->cores); 1130 chip->num_cores = 0; 1131 chip->ops = ops; 1132 chip->ctx = ctx; 1133 chip->pub.enum_base = brcmf_chip_enum_base(devid); 1134 1135 err = ops->prepare(ctx); 1136 if (err < 0) 1137 goto fail; 1138 1139 err = brcmf_chip_recognition(chip); 1140 if (err < 0) 1141 goto fail; 1142 1143 err = brcmf_chip_setup(chip); 1144 if (err < 0) 1145 goto fail; 1146 1147 return &chip->pub; 1148 1149 fail: 1150 brcmf_chip_detach(&chip->pub); 1151 return ERR_PTR(err); 1152 } 1153 1154 void brcmf_chip_detach(struct brcmf_chip *pub) 1155 { 1156 struct brcmf_chip_priv *chip; 1157 struct brcmf_core_priv *core; 1158 struct brcmf_core_priv *tmp; 1159 1160 chip = container_of(pub, struct brcmf_chip_priv, pub); 1161 list_for_each_entry_safe(core, tmp, &chip->cores, list) { 1162 list_del(&core->list); 1163 kfree(core); 1164 } 1165 kfree(chip); 1166 } 1167 1168 struct brcmf_core *brcmf_chip_get_d11core(struct brcmf_chip *pub, u8 unit) 1169 { 1170 struct brcmf_chip_priv *chip; 1171 struct brcmf_core_priv *core; 1172 1173 chip = container_of(pub, struct brcmf_chip_priv, pub); 1174 list_for_each_entry(core, &chip->cores, list) { 1175 if (core->pub.id == BCMA_CORE_80211) { 1176 if (unit-- == 0) 1177 return &core->pub; 1178 } 1179 } 1180 return NULL; 1181 } 1182 1183 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid) 1184 { 1185 struct brcmf_chip_priv *chip; 1186 struct brcmf_core_priv *core; 1187 1188 chip = container_of(pub, struct brcmf_chip_priv, pub); 1189 list_for_each_entry(core, &chip->cores, list) 1190 if (core->pub.id == coreid) 1191 return &core->pub; 1192 1193 return NULL; 1194 } 1195 1196 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub) 1197 { 1198 struct brcmf_chip_priv *chip; 1199 struct brcmf_core_priv *cc; 1200 1201 chip = container_of(pub, struct brcmf_chip_priv, pub); 1202 cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list); 1203 if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON)) 1204 return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON); 1205 return &cc->pub; 1206 } 1207 1208 struct brcmf_core *brcmf_chip_get_pmu(struct brcmf_chip *pub) 1209 { 1210 struct brcmf_core *cc = brcmf_chip_get_chipcommon(pub); 1211 struct brcmf_core *pmu; 1212 1213 /* See if there is separated PMU core available */ 1214 if (cc->rev >= 35 && 1215 pub->cc_caps_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) { 1216 pmu = brcmf_chip_get_core(pub, BCMA_CORE_PMU); 1217 if (pmu) 1218 return pmu; 1219 } 1220 1221 /* Fallback to ChipCommon core for older hardware */ 1222 return cc; 1223 } 1224 1225 bool brcmf_chip_iscoreup(struct brcmf_core *pub) 1226 { 1227 struct brcmf_core_priv *core; 1228 1229 core = container_of(pub, struct brcmf_core_priv, pub); 1230 return core->chip->iscoreup(core); 1231 } 1232 1233 void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset) 1234 { 1235 struct brcmf_core_priv *core; 1236 1237 core = container_of(pub, struct brcmf_core_priv, pub); 1238 core->chip->coredisable(core, prereset, reset); 1239 } 1240 1241 void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset, 1242 u32 postreset) 1243 { 1244 struct brcmf_core_priv *core; 1245 1246 core = container_of(pub, struct brcmf_core_priv, pub); 1247 core->chip->resetcore(core, prereset, reset, postreset); 1248 } 1249 1250 static void 1251 brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip) 1252 { 1253 struct brcmf_core *core; 1254 struct brcmf_core_priv *sr; 1255 1256 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3); 1257 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1258 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1259 D11_BCMA_IOCTL_PHYCLOCKEN, 1260 D11_BCMA_IOCTL_PHYCLOCKEN, 1261 D11_BCMA_IOCTL_PHYCLOCKEN); 1262 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); 1263 brcmf_chip_resetcore(core, 0, 0, 0); 1264 1265 /* disable bank #3 remap for this device */ 1266 if (chip->pub.chip == BRCM_CC_43430_CHIP_ID || 1267 chip->pub.chip == CY_CC_43439_CHIP_ID) { 1268 sr = container_of(core, struct brcmf_core_priv, pub); 1269 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3); 1270 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0); 1271 } 1272 } 1273 1274 static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip) 1275 { 1276 struct brcmf_core *core; 1277 1278 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM); 1279 if (!brcmf_chip_iscoreup(core)) { 1280 brcmf_err("SOCRAM core is down after reset?\n"); 1281 return false; 1282 } 1283 1284 chip->ops->activate(chip->ctx, &chip->pub, 0); 1285 1286 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3); 1287 brcmf_chip_resetcore(core, 0, 0, 0); 1288 1289 return true; 1290 } 1291 1292 static inline void 1293 brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip) 1294 { 1295 struct brcmf_core *core; 1296 1297 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4); 1298 1299 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1300 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1301 D11_BCMA_IOCTL_PHYCLOCKEN, 1302 D11_BCMA_IOCTL_PHYCLOCKEN, 1303 D11_BCMA_IOCTL_PHYCLOCKEN); 1304 } 1305 1306 static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec) 1307 { 1308 struct brcmf_core *core; 1309 1310 chip->ops->activate(chip->ctx, &chip->pub, rstvec); 1311 1312 /* restore ARM */ 1313 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4); 1314 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); 1315 1316 return true; 1317 } 1318 1319 static inline void 1320 brcmf_chip_ca7_set_passive(struct brcmf_chip_priv *chip) 1321 { 1322 struct brcmf_core *core; 1323 1324 brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CA7); 1325 1326 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211); 1327 brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET | 1328 D11_BCMA_IOCTL_PHYCLOCKEN, 1329 D11_BCMA_IOCTL_PHYCLOCKEN, 1330 D11_BCMA_IOCTL_PHYCLOCKEN); 1331 } 1332 1333 static bool brcmf_chip_ca7_set_active(struct brcmf_chip_priv *chip, u32 rstvec) 1334 { 1335 struct brcmf_core *core; 1336 1337 chip->ops->activate(chip->ctx, &chip->pub, rstvec); 1338 1339 /* restore ARM */ 1340 core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CA7); 1341 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); 1342 1343 return true; 1344 } 1345 1346 void brcmf_chip_set_passive(struct brcmf_chip *pub) 1347 { 1348 struct brcmf_chip_priv *chip; 1349 struct brcmf_core *arm; 1350 1351 brcmf_dbg(TRACE, "Enter\n"); 1352 1353 chip = container_of(pub, struct brcmf_chip_priv, pub); 1354 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4); 1355 if (arm) { 1356 brcmf_chip_cr4_set_passive(chip); 1357 return; 1358 } 1359 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7); 1360 if (arm) { 1361 brcmf_chip_ca7_set_passive(chip); 1362 return; 1363 } 1364 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3); 1365 if (arm) { 1366 brcmf_chip_cm3_set_passive(chip); 1367 return; 1368 } 1369 } 1370 1371 bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec) 1372 { 1373 struct brcmf_chip_priv *chip; 1374 struct brcmf_core *arm; 1375 1376 brcmf_dbg(TRACE, "Enter\n"); 1377 1378 chip = container_of(pub, struct brcmf_chip_priv, pub); 1379 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4); 1380 if (arm) 1381 return brcmf_chip_cr4_set_active(chip, rstvec); 1382 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CA7); 1383 if (arm) 1384 return brcmf_chip_ca7_set_active(chip, rstvec); 1385 arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CM3); 1386 if (arm) 1387 return brcmf_chip_cm3_set_active(chip); 1388 1389 return false; 1390 } 1391 1392 bool brcmf_chip_sr_capable(struct brcmf_chip *pub) 1393 { 1394 u32 base, addr, reg, pmu_cc3_mask = ~0; 1395 struct brcmf_chip_priv *chip; 1396 struct brcmf_core *pmu = brcmf_chip_get_pmu(pub); 1397 1398 brcmf_dbg(TRACE, "Enter\n"); 1399 1400 /* old chips with PMU version less than 17 don't support save restore */ 1401 if (pub->pmurev < 17) 1402 return false; 1403 1404 base = brcmf_chip_get_chipcommon(pub)->base; 1405 chip = container_of(pub, struct brcmf_chip_priv, pub); 1406 1407 switch (pub->chip) { 1408 case BRCM_CC_4354_CHIP_ID: 1409 case BRCM_CC_4356_CHIP_ID: 1410 case BRCM_CC_4345_CHIP_ID: 1411 case BRCM_CC_43454_CHIP_ID: 1412 /* explicitly check SR engine enable bit */ 1413 pmu_cc3_mask = BIT(2); 1414 fallthrough; 1415 case BRCM_CC_43241_CHIP_ID: 1416 case BRCM_CC_4335_CHIP_ID: 1417 case BRCM_CC_4339_CHIP_ID: 1418 /* read PMU chipcontrol register 3 */ 1419 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 1420 chip->ops->write32(chip->ctx, addr, 3); 1421 addr = CORE_CC_REG(pmu->base, chipcontrol_data); 1422 reg = chip->ops->read32(chip->ctx, addr); 1423 return (reg & pmu_cc3_mask) != 0; 1424 case BRCM_CC_43430_CHIP_ID: 1425 case CY_CC_43439_CHIP_ID: 1426 addr = CORE_CC_REG(base, sr_control1); 1427 reg = chip->ops->read32(chip->ctx, addr); 1428 return reg != 0; 1429 case CY_CC_4373_CHIP_ID: 1430 case CY_CC_89459_CHIP_ID: 1431 /* explicitly check SR engine enable bit */ 1432 addr = CORE_CC_REG(base, sr_control0); 1433 reg = chip->ops->read32(chip->ctx, addr); 1434 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0; 1435 case BRCM_CC_4359_CHIP_ID: 1436 case CY_CC_43752_CHIP_ID: 1437 case CY_CC_43012_CHIP_ID: 1438 addr = CORE_CC_REG(pmu->base, retention_ctl); 1439 reg = chip->ops->read32(chip->ctx, addr); 1440 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | 1441 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; 1442 default: 1443 addr = CORE_CC_REG(pmu->base, pmucapabilities_ext); 1444 reg = chip->ops->read32(chip->ctx, addr); 1445 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0) 1446 return false; 1447 1448 addr = CORE_CC_REG(pmu->base, retention_ctl); 1449 reg = chip->ops->read32(chip->ctx, addr); 1450 return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK | 1451 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; 1452 } 1453 } 1454