1 /* 2 3 Broadcom B43legacy wireless driver 4 5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, 6 Stefano Brivio <stefano.brivio@polimi.it> 7 Michael Buesch <m@bues.ch> 8 Danny van Dyk <kugelfang@gentoo.org> 9 Andreas Jaggi <andreas.jaggi@waterwave.ch> 10 Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net> 11 12 Some parts of the code in this file are derived from the ipw2200 13 driver Copyright(c) 2003 - 2004 Intel Corporation. 14 15 This program is free software; you can redistribute it and/or modify 16 it under the terms of the GNU General Public License as published by 17 the Free Software Foundation; either version 2 of the License, or 18 (at your option) any later version. 19 20 This program is distributed in the hope that it will be useful, 21 but WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 GNU General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with this program; see the file COPYING. If not, write to 27 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 28 Boston, MA 02110-1301, USA. 29 30 */ 31 32 #include <linux/delay.h> 33 #include <linux/pci.h> 34 #include <linux/sched.h> 35 #include <linux/slab.h> 36 #include <linux/types.h> 37 38 #include "b43legacy.h" 39 #include "phy.h" 40 #include "main.h" 41 #include "radio.h" 42 #include "ilt.h" 43 44 45 static const s8 b43legacy_tssi2dbm_b_table[] = { 46 0x4D, 0x4C, 0x4B, 0x4A, 47 0x4A, 0x49, 0x48, 0x47, 48 0x47, 0x46, 0x45, 0x45, 49 0x44, 0x43, 0x42, 0x42, 50 0x41, 0x40, 0x3F, 0x3E, 51 0x3D, 0x3C, 0x3B, 0x3A, 52 0x39, 0x38, 0x37, 0x36, 53 0x35, 0x34, 0x32, 0x31, 54 0x30, 0x2F, 0x2D, 0x2C, 55 0x2B, 0x29, 0x28, 0x26, 56 0x25, 0x23, 0x21, 0x1F, 57 0x1D, 0x1A, 0x17, 0x14, 58 0x10, 0x0C, 0x06, 0x00, 59 -7, -7, -7, -7, 60 -7, -7, -7, -7, 61 -7, -7, -7, -7, 62 }; 63 64 static const s8 b43legacy_tssi2dbm_g_table[] = { 65 77, 77, 77, 76, 66 76, 76, 75, 75, 67 74, 74, 73, 73, 68 73, 72, 72, 71, 69 71, 70, 70, 69, 70 68, 68, 67, 67, 71 66, 65, 65, 64, 72 63, 63, 62, 61, 73 60, 59, 58, 57, 74 56, 55, 54, 53, 75 52, 50, 49, 47, 76 45, 43, 40, 37, 77 33, 28, 22, 14, 78 5, -7, -20, -20, 79 -20, -20, -20, -20, 80 -20, -20, -20, -20, 81 }; 82 83 static void b43legacy_phy_initg(struct b43legacy_wldev *dev); 84 85 86 static inline 87 void b43legacy_voluntary_preempt(void) 88 { 89 B43legacy_BUG_ON(!(!in_atomic() && !in_irq() && 90 !in_interrupt() && !irqs_disabled())); 91 #ifndef CONFIG_PREEMPT 92 cond_resched(); 93 #endif /* CONFIG_PREEMPT */ 94 } 95 96 /* Lock the PHY registers against concurrent access from the microcode. 97 * This lock is nonrecursive. */ 98 void b43legacy_phy_lock(struct b43legacy_wldev *dev) 99 { 100 #if B43legacy_DEBUG 101 B43legacy_WARN_ON(dev->phy.phy_locked); 102 dev->phy.phy_locked = 1; 103 #endif 104 105 if (dev->dev->id.revision < 3) { 106 b43legacy_mac_suspend(dev); 107 } else { 108 if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) 109 b43legacy_power_saving_ctl_bits(dev, -1, 1); 110 } 111 } 112 113 void b43legacy_phy_unlock(struct b43legacy_wldev *dev) 114 { 115 #if B43legacy_DEBUG 116 B43legacy_WARN_ON(!dev->phy.phy_locked); 117 dev->phy.phy_locked = 0; 118 #endif 119 120 if (dev->dev->id.revision < 3) { 121 b43legacy_mac_enable(dev); 122 } else { 123 if (!b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) 124 b43legacy_power_saving_ctl_bits(dev, -1, -1); 125 } 126 } 127 128 u16 b43legacy_phy_read(struct b43legacy_wldev *dev, u16 offset) 129 { 130 b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset); 131 return b43legacy_read16(dev, B43legacy_MMIO_PHY_DATA); 132 } 133 134 void b43legacy_phy_write(struct b43legacy_wldev *dev, u16 offset, u16 val) 135 { 136 b43legacy_write16(dev, B43legacy_MMIO_PHY_CONTROL, offset); 137 b43legacy_write16(dev, B43legacy_MMIO_PHY_DATA, val); 138 } 139 140 void b43legacy_phy_calibrate(struct b43legacy_wldev *dev) 141 { 142 struct b43legacy_phy *phy = &dev->phy; 143 144 b43legacy_read32(dev, B43legacy_MMIO_MACCTL); /* Dummy read. */ 145 if (phy->calibrated) 146 return; 147 if (phy->type == B43legacy_PHYTYPE_G && phy->rev == 1) { 148 b43legacy_wireless_core_reset(dev, 0); 149 b43legacy_phy_initg(dev); 150 b43legacy_wireless_core_reset(dev, B43legacy_TMSLOW_GMODE); 151 } 152 phy->calibrated = 1; 153 } 154 155 /* initialize B PHY power control 156 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl 157 */ 158 static void b43legacy_phy_init_pctl(struct b43legacy_wldev *dev) 159 { 160 struct b43legacy_phy *phy = &dev->phy; 161 u16 saved_batt = 0; 162 u16 saved_ratt = 0; 163 u16 saved_txctl1 = 0; 164 int must_reset_txpower = 0; 165 166 B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B || 167 phy->type == B43legacy_PHYTYPE_G)); 168 if (is_bcm_board_vendor(dev) && 169 (dev->dev->bus->boardinfo.type == 0x0416)) 170 return; 171 172 b43legacy_phy_write(dev, 0x0028, 0x8018); 173 b43legacy_write16(dev, 0x03E6, b43legacy_read16(dev, 0x03E6) & 0xFFDF); 174 175 if (phy->type == B43legacy_PHYTYPE_G) { 176 if (!phy->gmode) 177 return; 178 b43legacy_phy_write(dev, 0x047A, 0xC111); 179 } 180 if (phy->savedpctlreg != 0xFFFF) 181 return; 182 #ifdef CONFIG_B43LEGACY_DEBUG 183 if (phy->manual_txpower_control) 184 return; 185 #endif 186 187 if (phy->type == B43legacy_PHYTYPE_B && 188 phy->rev >= 2 && 189 phy->radio_ver == 0x2050) 190 b43legacy_radio_write16(dev, 0x0076, 191 b43legacy_radio_read16(dev, 0x0076) 192 | 0x0084); 193 else { 194 saved_batt = phy->bbatt; 195 saved_ratt = phy->rfatt; 196 saved_txctl1 = phy->txctl1; 197 if ((phy->radio_rev >= 6) && (phy->radio_rev <= 8) 198 && /*FIXME: incomplete specs for 5 < revision < 9 */ 0) 199 b43legacy_radio_set_txpower_bg(dev, 0xB, 0x1F, 0); 200 else 201 b43legacy_radio_set_txpower_bg(dev, 0xB, 9, 0); 202 must_reset_txpower = 1; 203 } 204 b43legacy_dummy_transmission(dev); 205 206 phy->savedpctlreg = b43legacy_phy_read(dev, B43legacy_PHY_G_PCTL); 207 208 if (must_reset_txpower) 209 b43legacy_radio_set_txpower_bg(dev, saved_batt, saved_ratt, 210 saved_txctl1); 211 else 212 b43legacy_radio_write16(dev, 0x0076, b43legacy_radio_read16(dev, 213 0x0076) & 0xFF7B); 214 b43legacy_radio_clear_tssi(dev); 215 } 216 217 static void b43legacy_phy_agcsetup(struct b43legacy_wldev *dev) 218 { 219 struct b43legacy_phy *phy = &dev->phy; 220 u16 offset = 0x0000; 221 222 if (phy->rev == 1) 223 offset = 0x4C00; 224 225 b43legacy_ilt_write(dev, offset, 0x00FE); 226 b43legacy_ilt_write(dev, offset + 1, 0x000D); 227 b43legacy_ilt_write(dev, offset + 2, 0x0013); 228 b43legacy_ilt_write(dev, offset + 3, 0x0019); 229 230 if (phy->rev == 1) { 231 b43legacy_ilt_write(dev, 0x1800, 0x2710); 232 b43legacy_ilt_write(dev, 0x1801, 0x9B83); 233 b43legacy_ilt_write(dev, 0x1802, 0x9B83); 234 b43legacy_ilt_write(dev, 0x1803, 0x0F8D); 235 b43legacy_phy_write(dev, 0x0455, 0x0004); 236 } 237 238 b43legacy_phy_write(dev, 0x04A5, (b43legacy_phy_read(dev, 0x04A5) 239 & 0x00FF) | 0x5700); 240 b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A) 241 & 0xFF80) | 0x000F); 242 b43legacy_phy_write(dev, 0x041A, (b43legacy_phy_read(dev, 0x041A) 243 & 0xC07F) | 0x2B80); 244 b43legacy_phy_write(dev, 0x048C, (b43legacy_phy_read(dev, 0x048C) 245 & 0xF0FF) | 0x0300); 246 247 b43legacy_radio_write16(dev, 0x007A, 248 b43legacy_radio_read16(dev, 0x007A) 249 | 0x0008); 250 251 b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0) 252 & 0xFFF0) | 0x0008); 253 b43legacy_phy_write(dev, 0x04A1, (b43legacy_phy_read(dev, 0x04A1) 254 & 0xF0FF) | 0x0600); 255 b43legacy_phy_write(dev, 0x04A2, (b43legacy_phy_read(dev, 0x04A2) 256 & 0xF0FF) | 0x0700); 257 b43legacy_phy_write(dev, 0x04A0, (b43legacy_phy_read(dev, 0x04A0) 258 & 0xF0FF) | 0x0100); 259 260 if (phy->rev == 1) 261 b43legacy_phy_write(dev, 0x04A2, 262 (b43legacy_phy_read(dev, 0x04A2) 263 & 0xFFF0) | 0x0007); 264 265 b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488) 266 & 0xFF00) | 0x001C); 267 b43legacy_phy_write(dev, 0x0488, (b43legacy_phy_read(dev, 0x0488) 268 & 0xC0FF) | 0x0200); 269 b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496) 270 & 0xFF00) | 0x001C); 271 b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489) 272 & 0xFF00) | 0x0020); 273 b43legacy_phy_write(dev, 0x0489, (b43legacy_phy_read(dev, 0x0489) 274 & 0xC0FF) | 0x0200); 275 b43legacy_phy_write(dev, 0x0482, (b43legacy_phy_read(dev, 0x0482) 276 & 0xFF00) | 0x002E); 277 b43legacy_phy_write(dev, 0x0496, (b43legacy_phy_read(dev, 0x0496) 278 & 0x00FF) | 0x1A00); 279 b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481) 280 & 0xFF00) | 0x0028); 281 b43legacy_phy_write(dev, 0x0481, (b43legacy_phy_read(dev, 0x0481) 282 & 0x00FF) | 0x2C00); 283 284 if (phy->rev == 1) { 285 b43legacy_phy_write(dev, 0x0430, 0x092B); 286 b43legacy_phy_write(dev, 0x041B, 287 (b43legacy_phy_read(dev, 0x041B) 288 & 0xFFE1) | 0x0002); 289 } else { 290 b43legacy_phy_write(dev, 0x041B, 291 b43legacy_phy_read(dev, 0x041B) & 0xFFE1); 292 b43legacy_phy_write(dev, 0x041F, 0x287A); 293 b43legacy_phy_write(dev, 0x0420, 294 (b43legacy_phy_read(dev, 0x0420) 295 & 0xFFF0) | 0x0004); 296 } 297 298 if (phy->rev > 2) { 299 b43legacy_phy_write(dev, 0x0422, 0x287A); 300 b43legacy_phy_write(dev, 0x0420, 301 (b43legacy_phy_read(dev, 0x0420) 302 & 0x0FFF) | 0x3000); 303 } 304 305 b43legacy_phy_write(dev, 0x04A8, (b43legacy_phy_read(dev, 0x04A8) 306 & 0x8080) | 0x7874); 307 b43legacy_phy_write(dev, 0x048E, 0x1C00); 308 309 if (phy->rev == 1) { 310 b43legacy_phy_write(dev, 0x04AB, 311 (b43legacy_phy_read(dev, 0x04AB) 312 & 0xF0FF) | 0x0600); 313 b43legacy_phy_write(dev, 0x048B, 0x005E); 314 b43legacy_phy_write(dev, 0x048C, 315 (b43legacy_phy_read(dev, 0x048C) & 0xFF00) 316 | 0x001E); 317 b43legacy_phy_write(dev, 0x048D, 0x0002); 318 } 319 320 b43legacy_ilt_write(dev, offset + 0x0800, 0); 321 b43legacy_ilt_write(dev, offset + 0x0801, 7); 322 b43legacy_ilt_write(dev, offset + 0x0802, 16); 323 b43legacy_ilt_write(dev, offset + 0x0803, 28); 324 325 if (phy->rev >= 6) { 326 b43legacy_phy_write(dev, 0x0426, 327 (b43legacy_phy_read(dev, 0x0426) & 0xFFFC)); 328 b43legacy_phy_write(dev, 0x0426, 329 (b43legacy_phy_read(dev, 0x0426) & 0xEFFF)); 330 } 331 } 332 333 static void b43legacy_phy_setupg(struct b43legacy_wldev *dev) 334 { 335 struct b43legacy_phy *phy = &dev->phy; 336 u16 i; 337 338 B43legacy_BUG_ON(phy->type != B43legacy_PHYTYPE_G); 339 if (phy->rev == 1) { 340 b43legacy_phy_write(dev, 0x0406, 0x4F19); 341 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, 342 (b43legacy_phy_read(dev, 343 B43legacy_PHY_G_CRS) & 0xFC3F) | 0x0340); 344 b43legacy_phy_write(dev, 0x042C, 0x005A); 345 b43legacy_phy_write(dev, 0x0427, 0x001A); 346 347 for (i = 0; i < B43legacy_ILT_FINEFREQG_SIZE; i++) 348 b43legacy_ilt_write(dev, 0x5800 + i, 349 b43legacy_ilt_finefreqg[i]); 350 for (i = 0; i < B43legacy_ILT_NOISEG1_SIZE; i++) 351 b43legacy_ilt_write(dev, 0x1800 + i, 352 b43legacy_ilt_noiseg1[i]); 353 for (i = 0; i < B43legacy_ILT_ROTOR_SIZE; i++) 354 b43legacy_ilt_write32(dev, 0x2000 + i, 355 b43legacy_ilt_rotor[i]); 356 } else { 357 /* nrssi values are signed 6-bit values. Why 0x7654 here? */ 358 b43legacy_nrssi_hw_write(dev, 0xBA98, (s16)0x7654); 359 360 if (phy->rev == 2) { 361 b43legacy_phy_write(dev, 0x04C0, 0x1861); 362 b43legacy_phy_write(dev, 0x04C1, 0x0271); 363 } else if (phy->rev > 2) { 364 b43legacy_phy_write(dev, 0x04C0, 0x0098); 365 b43legacy_phy_write(dev, 0x04C1, 0x0070); 366 b43legacy_phy_write(dev, 0x04C9, 0x0080); 367 } 368 b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev, 369 0x042B) | 0x800); 370 371 for (i = 0; i < 64; i++) 372 b43legacy_ilt_write(dev, 0x4000 + i, i); 373 for (i = 0; i < B43legacy_ILT_NOISEG2_SIZE; i++) 374 b43legacy_ilt_write(dev, 0x1800 + i, 375 b43legacy_ilt_noiseg2[i]); 376 } 377 378 if (phy->rev <= 2) 379 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++) 380 b43legacy_ilt_write(dev, 0x1400 + i, 381 b43legacy_ilt_noisescaleg1[i]); 382 else if ((phy->rev >= 7) && (b43legacy_phy_read(dev, 0x0449) & 0x0200)) 383 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++) 384 b43legacy_ilt_write(dev, 0x1400 + i, 385 b43legacy_ilt_noisescaleg3[i]); 386 else 387 for (i = 0; i < B43legacy_ILT_NOISESCALEG_SIZE; i++) 388 b43legacy_ilt_write(dev, 0x1400 + i, 389 b43legacy_ilt_noisescaleg2[i]); 390 391 if (phy->rev == 2) 392 for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++) 393 b43legacy_ilt_write(dev, 0x5000 + i, 394 b43legacy_ilt_sigmasqr1[i]); 395 else if ((phy->rev > 2) && (phy->rev <= 8)) 396 for (i = 0; i < B43legacy_ILT_SIGMASQR_SIZE; i++) 397 b43legacy_ilt_write(dev, 0x5000 + i, 398 b43legacy_ilt_sigmasqr2[i]); 399 400 if (phy->rev == 1) { 401 for (i = 0; i < B43legacy_ILT_RETARD_SIZE; i++) 402 b43legacy_ilt_write32(dev, 0x2400 + i, 403 b43legacy_ilt_retard[i]); 404 for (i = 4; i < 20; i++) 405 b43legacy_ilt_write(dev, 0x5400 + i, 0x0020); 406 b43legacy_phy_agcsetup(dev); 407 408 if (is_bcm_board_vendor(dev) && 409 (dev->dev->bus->boardinfo.type == 0x0416) && 410 (dev->dev->bus->sprom.board_rev == 0x0017)) 411 return; 412 413 b43legacy_ilt_write(dev, 0x5001, 0x0002); 414 b43legacy_ilt_write(dev, 0x5002, 0x0001); 415 } else { 416 for (i = 0; i <= 0x20; i++) 417 b43legacy_ilt_write(dev, 0x1000 + i, 0x0820); 418 b43legacy_phy_agcsetup(dev); 419 b43legacy_phy_read(dev, 0x0400); /* dummy read */ 420 b43legacy_phy_write(dev, 0x0403, 0x1000); 421 b43legacy_ilt_write(dev, 0x3C02, 0x000F); 422 b43legacy_ilt_write(dev, 0x3C03, 0x0014); 423 424 if (is_bcm_board_vendor(dev) && 425 (dev->dev->bus->boardinfo.type == 0x0416) && 426 (dev->dev->bus->sprom.board_rev == 0x0017)) 427 return; 428 429 b43legacy_ilt_write(dev, 0x0401, 0x0002); 430 b43legacy_ilt_write(dev, 0x0402, 0x0001); 431 } 432 } 433 434 /* Initialize the APHY portion of a GPHY. */ 435 static void b43legacy_phy_inita(struct b43legacy_wldev *dev) 436 { 437 438 might_sleep(); 439 440 b43legacy_phy_setupg(dev); 441 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) 442 b43legacy_phy_write(dev, 0x046E, 0x03CF); 443 } 444 445 static void b43legacy_phy_initb2(struct b43legacy_wldev *dev) 446 { 447 struct b43legacy_phy *phy = &dev->phy; 448 u16 offset; 449 int val; 450 451 b43legacy_write16(dev, 0x03EC, 0x3F22); 452 b43legacy_phy_write(dev, 0x0020, 0x301C); 453 b43legacy_phy_write(dev, 0x0026, 0x0000); 454 b43legacy_phy_write(dev, 0x0030, 0x00C6); 455 b43legacy_phy_write(dev, 0x0088, 0x3E00); 456 val = 0x3C3D; 457 for (offset = 0x0089; offset < 0x00A7; offset++) { 458 b43legacy_phy_write(dev, offset, val); 459 val -= 0x0202; 460 } 461 b43legacy_phy_write(dev, 0x03E4, 0x3000); 462 b43legacy_radio_selectchannel(dev, phy->channel, 0); 463 if (phy->radio_ver != 0x2050) { 464 b43legacy_radio_write16(dev, 0x0075, 0x0080); 465 b43legacy_radio_write16(dev, 0x0079, 0x0081); 466 } 467 b43legacy_radio_write16(dev, 0x0050, 0x0020); 468 b43legacy_radio_write16(dev, 0x0050, 0x0023); 469 if (phy->radio_ver == 0x2050) { 470 b43legacy_radio_write16(dev, 0x0050, 0x0020); 471 b43legacy_radio_write16(dev, 0x005A, 0x0070); 472 b43legacy_radio_write16(dev, 0x005B, 0x007B); 473 b43legacy_radio_write16(dev, 0x005C, 0x00B0); 474 b43legacy_radio_write16(dev, 0x007A, 0x000F); 475 b43legacy_phy_write(dev, 0x0038, 0x0677); 476 b43legacy_radio_init2050(dev); 477 } 478 b43legacy_phy_write(dev, 0x0014, 0x0080); 479 b43legacy_phy_write(dev, 0x0032, 0x00CA); 480 b43legacy_phy_write(dev, 0x0032, 0x00CC); 481 b43legacy_phy_write(dev, 0x0035, 0x07C2); 482 b43legacy_phy_lo_b_measure(dev); 483 b43legacy_phy_write(dev, 0x0026, 0xCC00); 484 if (phy->radio_ver != 0x2050) 485 b43legacy_phy_write(dev, 0x0026, 0xCE00); 486 b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1000); 487 b43legacy_phy_write(dev, 0x002A, 0x88A3); 488 if (phy->radio_ver != 0x2050) 489 b43legacy_phy_write(dev, 0x002A, 0x88C2); 490 b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF); 491 b43legacy_phy_init_pctl(dev); 492 } 493 494 static void b43legacy_phy_initb4(struct b43legacy_wldev *dev) 495 { 496 struct b43legacy_phy *phy = &dev->phy; 497 u16 offset; 498 u16 val; 499 500 b43legacy_write16(dev, 0x03EC, 0x3F22); 501 b43legacy_phy_write(dev, 0x0020, 0x301C); 502 b43legacy_phy_write(dev, 0x0026, 0x0000); 503 b43legacy_phy_write(dev, 0x0030, 0x00C6); 504 b43legacy_phy_write(dev, 0x0088, 0x3E00); 505 val = 0x3C3D; 506 for (offset = 0x0089; offset < 0x00A7; offset++) { 507 b43legacy_phy_write(dev, offset, val); 508 val -= 0x0202; 509 } 510 b43legacy_phy_write(dev, 0x03E4, 0x3000); 511 b43legacy_radio_selectchannel(dev, phy->channel, 0); 512 if (phy->radio_ver != 0x2050) { 513 b43legacy_radio_write16(dev, 0x0075, 0x0080); 514 b43legacy_radio_write16(dev, 0x0079, 0x0081); 515 } 516 b43legacy_radio_write16(dev, 0x0050, 0x0020); 517 b43legacy_radio_write16(dev, 0x0050, 0x0023); 518 if (phy->radio_ver == 0x2050) { 519 b43legacy_radio_write16(dev, 0x0050, 0x0020); 520 b43legacy_radio_write16(dev, 0x005A, 0x0070); 521 b43legacy_radio_write16(dev, 0x005B, 0x007B); 522 b43legacy_radio_write16(dev, 0x005C, 0x00B0); 523 b43legacy_radio_write16(dev, 0x007A, 0x000F); 524 b43legacy_phy_write(dev, 0x0038, 0x0677); 525 b43legacy_radio_init2050(dev); 526 } 527 b43legacy_phy_write(dev, 0x0014, 0x0080); 528 b43legacy_phy_write(dev, 0x0032, 0x00CA); 529 if (phy->radio_ver == 0x2050) 530 b43legacy_phy_write(dev, 0x0032, 0x00E0); 531 b43legacy_phy_write(dev, 0x0035, 0x07C2); 532 533 b43legacy_phy_lo_b_measure(dev); 534 535 b43legacy_phy_write(dev, 0x0026, 0xCC00); 536 if (phy->radio_ver == 0x2050) 537 b43legacy_phy_write(dev, 0x0026, 0xCE00); 538 b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x1100); 539 b43legacy_phy_write(dev, 0x002A, 0x88A3); 540 if (phy->radio_ver == 0x2050) 541 b43legacy_phy_write(dev, 0x002A, 0x88C2); 542 b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF); 543 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) { 544 b43legacy_calc_nrssi_slope(dev); 545 b43legacy_calc_nrssi_threshold(dev); 546 } 547 b43legacy_phy_init_pctl(dev); 548 } 549 550 static void b43legacy_phy_initb5(struct b43legacy_wldev *dev) 551 { 552 struct b43legacy_phy *phy = &dev->phy; 553 u16 offset; 554 u16 value; 555 u8 old_channel; 556 557 if (phy->analog == 1) 558 b43legacy_radio_write16(dev, 0x007A, 559 b43legacy_radio_read16(dev, 0x007A) 560 | 0x0050); 561 if (!is_bcm_board_vendor(dev) && 562 (dev->dev->bus->boardinfo.type != 0x0416)) { 563 value = 0x2120; 564 for (offset = 0x00A8 ; offset < 0x00C7; offset++) { 565 b43legacy_phy_write(dev, offset, value); 566 value += 0x0202; 567 } 568 } 569 b43legacy_phy_write(dev, 0x0035, 570 (b43legacy_phy_read(dev, 0x0035) & 0xF0FF) 571 | 0x0700); 572 if (phy->radio_ver == 0x2050) 573 b43legacy_phy_write(dev, 0x0038, 0x0667); 574 575 if (phy->gmode) { 576 if (phy->radio_ver == 0x2050) { 577 b43legacy_radio_write16(dev, 0x007A, 578 b43legacy_radio_read16(dev, 0x007A) 579 | 0x0020); 580 b43legacy_radio_write16(dev, 0x0051, 581 b43legacy_radio_read16(dev, 0x0051) 582 | 0x0004); 583 } 584 b43legacy_write16(dev, B43legacy_MMIO_PHY_RADIO, 0x0000); 585 586 b43legacy_phy_write(dev, 0x0802, b43legacy_phy_read(dev, 0x0802) 587 | 0x0100); 588 b43legacy_phy_write(dev, 0x042B, b43legacy_phy_read(dev, 0x042B) 589 | 0x2000); 590 591 b43legacy_phy_write(dev, 0x001C, 0x186A); 592 593 b43legacy_phy_write(dev, 0x0013, (b43legacy_phy_read(dev, 594 0x0013) & 0x00FF) | 0x1900); 595 b43legacy_phy_write(dev, 0x0035, (b43legacy_phy_read(dev, 596 0x0035) & 0xFFC0) | 0x0064); 597 b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev, 598 0x005D) & 0xFF80) | 0x000A); 599 b43legacy_phy_write(dev, 0x5B, 0x0000); 600 b43legacy_phy_write(dev, 0x5C, 0x0000); 601 } 602 603 if (dev->bad_frames_preempt) 604 b43legacy_phy_write(dev, B43legacy_PHY_RADIO_BITFIELD, 605 b43legacy_phy_read(dev, 606 B43legacy_PHY_RADIO_BITFIELD) | (1 << 12)); 607 608 if (phy->analog == 1) { 609 b43legacy_phy_write(dev, 0x0026, 0xCE00); 610 b43legacy_phy_write(dev, 0x0021, 0x3763); 611 b43legacy_phy_write(dev, 0x0022, 0x1BC3); 612 b43legacy_phy_write(dev, 0x0023, 0x06F9); 613 b43legacy_phy_write(dev, 0x0024, 0x037E); 614 } else 615 b43legacy_phy_write(dev, 0x0026, 0xCC00); 616 b43legacy_phy_write(dev, 0x0030, 0x00C6); 617 b43legacy_write16(dev, 0x03EC, 0x3F22); 618 619 if (phy->analog == 1) 620 b43legacy_phy_write(dev, 0x0020, 0x3E1C); 621 else 622 b43legacy_phy_write(dev, 0x0020, 0x301C); 623 624 if (phy->analog == 0) 625 b43legacy_write16(dev, 0x03E4, 0x3000); 626 627 old_channel = (phy->channel == 0xFF) ? 1 : phy->channel; 628 /* Force to channel 7, even if not supported. */ 629 b43legacy_radio_selectchannel(dev, 7, 0); 630 631 if (phy->radio_ver != 0x2050) { 632 b43legacy_radio_write16(dev, 0x0075, 0x0080); 633 b43legacy_radio_write16(dev, 0x0079, 0x0081); 634 } 635 636 b43legacy_radio_write16(dev, 0x0050, 0x0020); 637 b43legacy_radio_write16(dev, 0x0050, 0x0023); 638 639 if (phy->radio_ver == 0x2050) { 640 b43legacy_radio_write16(dev, 0x0050, 0x0020); 641 b43legacy_radio_write16(dev, 0x005A, 0x0070); 642 } 643 644 b43legacy_radio_write16(dev, 0x005B, 0x007B); 645 b43legacy_radio_write16(dev, 0x005C, 0x00B0); 646 647 b43legacy_radio_write16(dev, 0x007A, b43legacy_radio_read16(dev, 648 0x007A) | 0x0007); 649 650 b43legacy_radio_selectchannel(dev, old_channel, 0); 651 652 b43legacy_phy_write(dev, 0x0014, 0x0080); 653 b43legacy_phy_write(dev, 0x0032, 0x00CA); 654 b43legacy_phy_write(dev, 0x002A, 0x88A3); 655 656 b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF); 657 658 if (phy->radio_ver == 0x2050) 659 b43legacy_radio_write16(dev, 0x005D, 0x000D); 660 661 b43legacy_write16(dev, 0x03E4, (b43legacy_read16(dev, 0x03E4) & 662 0xFFC0) | 0x0004); 663 } 664 665 static void b43legacy_phy_initb6(struct b43legacy_wldev *dev) 666 { 667 struct b43legacy_phy *phy = &dev->phy; 668 u16 offset; 669 u16 val; 670 u8 old_channel; 671 672 b43legacy_phy_write(dev, 0x003E, 0x817A); 673 b43legacy_radio_write16(dev, 0x007A, 674 (b43legacy_radio_read16(dev, 0x007A) | 0x0058)); 675 if (phy->radio_rev == 4 || 676 phy->radio_rev == 5) { 677 b43legacy_radio_write16(dev, 0x0051, 0x0037); 678 b43legacy_radio_write16(dev, 0x0052, 0x0070); 679 b43legacy_radio_write16(dev, 0x0053, 0x00B3); 680 b43legacy_radio_write16(dev, 0x0054, 0x009B); 681 b43legacy_radio_write16(dev, 0x005A, 0x0088); 682 b43legacy_radio_write16(dev, 0x005B, 0x0088); 683 b43legacy_radio_write16(dev, 0x005D, 0x0088); 684 b43legacy_radio_write16(dev, 0x005E, 0x0088); 685 b43legacy_radio_write16(dev, 0x007D, 0x0088); 686 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 687 B43legacy_UCODEFLAGS_OFFSET, 688 (b43legacy_shm_read32(dev, 689 B43legacy_SHM_SHARED, 690 B43legacy_UCODEFLAGS_OFFSET) 691 | 0x00000200)); 692 } 693 if (phy->radio_rev == 8) { 694 b43legacy_radio_write16(dev, 0x0051, 0x0000); 695 b43legacy_radio_write16(dev, 0x0052, 0x0040); 696 b43legacy_radio_write16(dev, 0x0053, 0x00B7); 697 b43legacy_radio_write16(dev, 0x0054, 0x0098); 698 b43legacy_radio_write16(dev, 0x005A, 0x0088); 699 b43legacy_radio_write16(dev, 0x005B, 0x006B); 700 b43legacy_radio_write16(dev, 0x005C, 0x000F); 701 if (dev->dev->bus->sprom.boardflags_lo & 0x8000) { 702 b43legacy_radio_write16(dev, 0x005D, 0x00FA); 703 b43legacy_radio_write16(dev, 0x005E, 0x00D8); 704 } else { 705 b43legacy_radio_write16(dev, 0x005D, 0x00F5); 706 b43legacy_radio_write16(dev, 0x005E, 0x00B8); 707 } 708 b43legacy_radio_write16(dev, 0x0073, 0x0003); 709 b43legacy_radio_write16(dev, 0x007D, 0x00A8); 710 b43legacy_radio_write16(dev, 0x007C, 0x0001); 711 b43legacy_radio_write16(dev, 0x007E, 0x0008); 712 } 713 val = 0x1E1F; 714 for (offset = 0x0088; offset < 0x0098; offset++) { 715 b43legacy_phy_write(dev, offset, val); 716 val -= 0x0202; 717 } 718 val = 0x3E3F; 719 for (offset = 0x0098; offset < 0x00A8; offset++) { 720 b43legacy_phy_write(dev, offset, val); 721 val -= 0x0202; 722 } 723 val = 0x2120; 724 for (offset = 0x00A8; offset < 0x00C8; offset++) { 725 b43legacy_phy_write(dev, offset, (val & 0x3F3F)); 726 val += 0x0202; 727 } 728 if (phy->type == B43legacy_PHYTYPE_G) { 729 b43legacy_radio_write16(dev, 0x007A, 730 b43legacy_radio_read16(dev, 0x007A) | 731 0x0020); 732 b43legacy_radio_write16(dev, 0x0051, 733 b43legacy_radio_read16(dev, 0x0051) | 734 0x0004); 735 b43legacy_phy_write(dev, 0x0802, 736 b43legacy_phy_read(dev, 0x0802) | 0x0100); 737 b43legacy_phy_write(dev, 0x042B, 738 b43legacy_phy_read(dev, 0x042B) | 0x2000); 739 b43legacy_phy_write(dev, 0x5B, 0x0000); 740 b43legacy_phy_write(dev, 0x5C, 0x0000); 741 } 742 743 old_channel = phy->channel; 744 if (old_channel >= 8) 745 b43legacy_radio_selectchannel(dev, 1, 0); 746 else 747 b43legacy_radio_selectchannel(dev, 13, 0); 748 749 b43legacy_radio_write16(dev, 0x0050, 0x0020); 750 b43legacy_radio_write16(dev, 0x0050, 0x0023); 751 udelay(40); 752 if (phy->radio_rev < 6 || phy->radio_rev == 8) { 753 b43legacy_radio_write16(dev, 0x007C, 754 (b43legacy_radio_read16(dev, 0x007C) 755 | 0x0002)); 756 b43legacy_radio_write16(dev, 0x0050, 0x0020); 757 } 758 if (phy->radio_rev <= 2) { 759 b43legacy_radio_write16(dev, 0x0050, 0x0020); 760 b43legacy_radio_write16(dev, 0x005A, 0x0070); 761 b43legacy_radio_write16(dev, 0x005B, 0x007B); 762 b43legacy_radio_write16(dev, 0x005C, 0x00B0); 763 } 764 b43legacy_radio_write16(dev, 0x007A, 765 (b43legacy_radio_read16(dev, 766 0x007A) & 0x00F8) | 0x0007); 767 768 b43legacy_radio_selectchannel(dev, old_channel, 0); 769 770 b43legacy_phy_write(dev, 0x0014, 0x0200); 771 if (phy->radio_rev >= 6) 772 b43legacy_phy_write(dev, 0x002A, 0x88C2); 773 else 774 b43legacy_phy_write(dev, 0x002A, 0x8AC0); 775 b43legacy_phy_write(dev, 0x0038, 0x0668); 776 b43legacy_radio_set_txpower_bg(dev, 0xFFFF, 0xFFFF, 0xFFFF); 777 if (phy->radio_rev == 4 || phy->radio_rev == 5) 778 b43legacy_phy_write(dev, 0x005D, (b43legacy_phy_read(dev, 779 0x005D) & 0xFF80) | 0x0003); 780 if (phy->radio_rev <= 2) 781 b43legacy_radio_write16(dev, 0x005D, 0x000D); 782 783 if (phy->analog == 4) { 784 b43legacy_write16(dev, 0x03E4, 0x0009); 785 b43legacy_phy_write(dev, 0x61, b43legacy_phy_read(dev, 0x61) 786 & 0xFFF); 787 } else 788 b43legacy_phy_write(dev, 0x0002, (b43legacy_phy_read(dev, 789 0x0002) & 0xFFC0) | 0x0004); 790 if (phy->type == B43legacy_PHYTYPE_G) 791 b43legacy_write16(dev, 0x03E6, 0x0); 792 if (phy->type == B43legacy_PHYTYPE_B) { 793 b43legacy_write16(dev, 0x03E6, 0x8140); 794 b43legacy_phy_write(dev, 0x0016, 0x0410); 795 b43legacy_phy_write(dev, 0x0017, 0x0820); 796 b43legacy_phy_write(dev, 0x0062, 0x0007); 797 b43legacy_radio_init2050(dev); 798 b43legacy_phy_lo_g_measure(dev); 799 if (dev->dev->bus->sprom.boardflags_lo & 800 B43legacy_BFL_RSSI) { 801 b43legacy_calc_nrssi_slope(dev); 802 b43legacy_calc_nrssi_threshold(dev); 803 } 804 b43legacy_phy_init_pctl(dev); 805 } 806 } 807 808 static void b43legacy_calc_loopback_gain(struct b43legacy_wldev *dev) 809 { 810 struct b43legacy_phy *phy = &dev->phy; 811 u16 backup_phy[15] = {0}; 812 u16 backup_radio[3]; 813 u16 backup_bband; 814 u16 i; 815 u16 loop1_cnt; 816 u16 loop1_done; 817 u16 loop1_omitted; 818 u16 loop2_done; 819 820 backup_phy[0] = b43legacy_phy_read(dev, 0x0429); 821 backup_phy[1] = b43legacy_phy_read(dev, 0x0001); 822 backup_phy[2] = b43legacy_phy_read(dev, 0x0811); 823 backup_phy[3] = b43legacy_phy_read(dev, 0x0812); 824 if (phy->rev != 1) { 825 backup_phy[4] = b43legacy_phy_read(dev, 0x0814); 826 backup_phy[5] = b43legacy_phy_read(dev, 0x0815); 827 } 828 backup_phy[6] = b43legacy_phy_read(dev, 0x005A); 829 backup_phy[7] = b43legacy_phy_read(dev, 0x0059); 830 backup_phy[8] = b43legacy_phy_read(dev, 0x0058); 831 backup_phy[9] = b43legacy_phy_read(dev, 0x000A); 832 backup_phy[10] = b43legacy_phy_read(dev, 0x0003); 833 backup_phy[11] = b43legacy_phy_read(dev, 0x080F); 834 backup_phy[12] = b43legacy_phy_read(dev, 0x0810); 835 backup_phy[13] = b43legacy_phy_read(dev, 0x002B); 836 backup_phy[14] = b43legacy_phy_read(dev, 0x0015); 837 b43legacy_phy_read(dev, 0x002D); /* dummy read */ 838 backup_bband = phy->bbatt; 839 backup_radio[0] = b43legacy_radio_read16(dev, 0x0052); 840 backup_radio[1] = b43legacy_radio_read16(dev, 0x0043); 841 backup_radio[2] = b43legacy_radio_read16(dev, 0x007A); 842 843 b43legacy_phy_write(dev, 0x0429, 844 b43legacy_phy_read(dev, 0x0429) & 0x3FFF); 845 b43legacy_phy_write(dev, 0x0001, 846 b43legacy_phy_read(dev, 0x0001) & 0x8000); 847 b43legacy_phy_write(dev, 0x0811, 848 b43legacy_phy_read(dev, 0x0811) | 0x0002); 849 b43legacy_phy_write(dev, 0x0812, 850 b43legacy_phy_read(dev, 0x0812) & 0xFFFD); 851 b43legacy_phy_write(dev, 0x0811, 852 b43legacy_phy_read(dev, 0x0811) | 0x0001); 853 b43legacy_phy_write(dev, 0x0812, 854 b43legacy_phy_read(dev, 0x0812) & 0xFFFE); 855 if (phy->rev != 1) { 856 b43legacy_phy_write(dev, 0x0814, 857 b43legacy_phy_read(dev, 0x0814) | 0x0001); 858 b43legacy_phy_write(dev, 0x0815, 859 b43legacy_phy_read(dev, 0x0815) & 0xFFFE); 860 b43legacy_phy_write(dev, 0x0814, 861 b43legacy_phy_read(dev, 0x0814) | 0x0002); 862 b43legacy_phy_write(dev, 0x0815, 863 b43legacy_phy_read(dev, 0x0815) & 0xFFFD); 864 } 865 b43legacy_phy_write(dev, 0x0811, b43legacy_phy_read(dev, 0x0811) | 866 0x000C); 867 b43legacy_phy_write(dev, 0x0812, b43legacy_phy_read(dev, 0x0812) | 868 0x000C); 869 870 b43legacy_phy_write(dev, 0x0811, (b43legacy_phy_read(dev, 0x0811) 871 & 0xFFCF) | 0x0030); 872 b43legacy_phy_write(dev, 0x0812, (b43legacy_phy_read(dev, 0x0812) 873 & 0xFFCF) | 0x0010); 874 875 b43legacy_phy_write(dev, 0x005A, 0x0780); 876 b43legacy_phy_write(dev, 0x0059, 0xC810); 877 b43legacy_phy_write(dev, 0x0058, 0x000D); 878 if (phy->analog == 0) 879 b43legacy_phy_write(dev, 0x0003, 0x0122); 880 else 881 b43legacy_phy_write(dev, 0x000A, 882 b43legacy_phy_read(dev, 0x000A) 883 | 0x2000); 884 if (phy->rev != 1) { 885 b43legacy_phy_write(dev, 0x0814, 886 b43legacy_phy_read(dev, 0x0814) | 0x0004); 887 b43legacy_phy_write(dev, 0x0815, 888 b43legacy_phy_read(dev, 0x0815) & 0xFFFB); 889 } 890 b43legacy_phy_write(dev, 0x0003, 891 (b43legacy_phy_read(dev, 0x0003) 892 & 0xFF9F) | 0x0040); 893 if (phy->radio_ver == 0x2050 && phy->radio_rev == 2) { 894 b43legacy_radio_write16(dev, 0x0052, 0x0000); 895 b43legacy_radio_write16(dev, 0x0043, 896 (b43legacy_radio_read16(dev, 0x0043) 897 & 0xFFF0) | 0x0009); 898 loop1_cnt = 9; 899 } else if (phy->radio_rev == 8) { 900 b43legacy_radio_write16(dev, 0x0043, 0x000F); 901 loop1_cnt = 15; 902 } else 903 loop1_cnt = 0; 904 905 b43legacy_phy_set_baseband_attenuation(dev, 11); 906 907 if (phy->rev >= 3) 908 b43legacy_phy_write(dev, 0x080F, 0xC020); 909 else 910 b43legacy_phy_write(dev, 0x080F, 0x8020); 911 b43legacy_phy_write(dev, 0x0810, 0x0000); 912 913 b43legacy_phy_write(dev, 0x002B, 914 (b43legacy_phy_read(dev, 0x002B) 915 & 0xFFC0) | 0x0001); 916 b43legacy_phy_write(dev, 0x002B, 917 (b43legacy_phy_read(dev, 0x002B) 918 & 0xC0FF) | 0x0800); 919 b43legacy_phy_write(dev, 0x0811, 920 b43legacy_phy_read(dev, 0x0811) | 0x0100); 921 b43legacy_phy_write(dev, 0x0812, 922 b43legacy_phy_read(dev, 0x0812) & 0xCFFF); 923 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_EXTLNA) { 924 if (phy->rev >= 7) { 925 b43legacy_phy_write(dev, 0x0811, 926 b43legacy_phy_read(dev, 0x0811) 927 | 0x0800); 928 b43legacy_phy_write(dev, 0x0812, 929 b43legacy_phy_read(dev, 0x0812) 930 | 0x8000); 931 } 932 } 933 b43legacy_radio_write16(dev, 0x007A, 934 b43legacy_radio_read16(dev, 0x007A) 935 & 0x00F7); 936 937 for (i = 0; i < loop1_cnt; i++) { 938 b43legacy_radio_write16(dev, 0x0043, loop1_cnt); 939 b43legacy_phy_write(dev, 0x0812, 940 (b43legacy_phy_read(dev, 0x0812) 941 & 0xF0FF) | (i << 8)); 942 b43legacy_phy_write(dev, 0x0015, 943 (b43legacy_phy_read(dev, 0x0015) 944 & 0x0FFF) | 0xA000); 945 b43legacy_phy_write(dev, 0x0015, 946 (b43legacy_phy_read(dev, 0x0015) 947 & 0x0FFF) | 0xF000); 948 udelay(20); 949 if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC) 950 break; 951 } 952 loop1_done = i; 953 loop1_omitted = loop1_cnt - loop1_done; 954 955 loop2_done = 0; 956 if (loop1_done >= 8) { 957 b43legacy_phy_write(dev, 0x0812, 958 b43legacy_phy_read(dev, 0x0812) 959 | 0x0030); 960 for (i = loop1_done - 8; i < 16; i++) { 961 b43legacy_phy_write(dev, 0x0812, 962 (b43legacy_phy_read(dev, 0x0812) 963 & 0xF0FF) | (i << 8)); 964 b43legacy_phy_write(dev, 0x0015, 965 (b43legacy_phy_read(dev, 0x0015) 966 & 0x0FFF) | 0xA000); 967 b43legacy_phy_write(dev, 0x0015, 968 (b43legacy_phy_read(dev, 0x0015) 969 & 0x0FFF) | 0xF000); 970 udelay(20); 971 if (b43legacy_phy_read(dev, 0x002D) >= 0x0DFC) 972 break; 973 } 974 } 975 976 if (phy->rev != 1) { 977 b43legacy_phy_write(dev, 0x0814, backup_phy[4]); 978 b43legacy_phy_write(dev, 0x0815, backup_phy[5]); 979 } 980 b43legacy_phy_write(dev, 0x005A, backup_phy[6]); 981 b43legacy_phy_write(dev, 0x0059, backup_phy[7]); 982 b43legacy_phy_write(dev, 0x0058, backup_phy[8]); 983 b43legacy_phy_write(dev, 0x000A, backup_phy[9]); 984 b43legacy_phy_write(dev, 0x0003, backup_phy[10]); 985 b43legacy_phy_write(dev, 0x080F, backup_phy[11]); 986 b43legacy_phy_write(dev, 0x0810, backup_phy[12]); 987 b43legacy_phy_write(dev, 0x002B, backup_phy[13]); 988 b43legacy_phy_write(dev, 0x0015, backup_phy[14]); 989 990 b43legacy_phy_set_baseband_attenuation(dev, backup_bband); 991 992 b43legacy_radio_write16(dev, 0x0052, backup_radio[0]); 993 b43legacy_radio_write16(dev, 0x0043, backup_radio[1]); 994 b43legacy_radio_write16(dev, 0x007A, backup_radio[2]); 995 996 b43legacy_phy_write(dev, 0x0811, backup_phy[2] | 0x0003); 997 udelay(10); 998 b43legacy_phy_write(dev, 0x0811, backup_phy[2]); 999 b43legacy_phy_write(dev, 0x0812, backup_phy[3]); 1000 b43legacy_phy_write(dev, 0x0429, backup_phy[0]); 1001 b43legacy_phy_write(dev, 0x0001, backup_phy[1]); 1002 1003 phy->loopback_gain[0] = ((loop1_done * 6) - (loop1_omitted * 4)) - 11; 1004 phy->loopback_gain[1] = (24 - (3 * loop2_done)) * 2; 1005 } 1006 1007 static void b43legacy_phy_initg(struct b43legacy_wldev *dev) 1008 { 1009 struct b43legacy_phy *phy = &dev->phy; 1010 u16 tmp; 1011 1012 if (phy->rev == 1) 1013 b43legacy_phy_initb5(dev); 1014 else 1015 b43legacy_phy_initb6(dev); 1016 if (phy->rev >= 2 && phy->gmode) 1017 b43legacy_phy_inita(dev); 1018 1019 if (phy->rev >= 2) { 1020 b43legacy_phy_write(dev, 0x0814, 0x0000); 1021 b43legacy_phy_write(dev, 0x0815, 0x0000); 1022 } 1023 if (phy->rev == 2) { 1024 b43legacy_phy_write(dev, 0x0811, 0x0000); 1025 b43legacy_phy_write(dev, 0x0015, 0x00C0); 1026 } 1027 if (phy->rev > 5) { 1028 b43legacy_phy_write(dev, 0x0811, 0x0400); 1029 b43legacy_phy_write(dev, 0x0015, 0x00C0); 1030 } 1031 if (phy->gmode) { 1032 tmp = b43legacy_phy_read(dev, 0x0400) & 0xFF; 1033 if (tmp == 3) { 1034 b43legacy_phy_write(dev, 0x04C2, 0x1816); 1035 b43legacy_phy_write(dev, 0x04C3, 0x8606); 1036 } 1037 if (tmp == 4 || tmp == 5) { 1038 b43legacy_phy_write(dev, 0x04C2, 0x1816); 1039 b43legacy_phy_write(dev, 0x04C3, 0x8006); 1040 b43legacy_phy_write(dev, 0x04CC, 1041 (b43legacy_phy_read(dev, 1042 0x04CC) & 0x00FF) | 1043 0x1F00); 1044 } 1045 if (phy->rev >= 2) 1046 b43legacy_phy_write(dev, 0x047E, 0x0078); 1047 } 1048 if (phy->radio_rev == 8) { 1049 b43legacy_phy_write(dev, 0x0801, b43legacy_phy_read(dev, 0x0801) 1050 | 0x0080); 1051 b43legacy_phy_write(dev, 0x043E, b43legacy_phy_read(dev, 0x043E) 1052 | 0x0004); 1053 } 1054 if (phy->rev >= 2 && phy->gmode) 1055 b43legacy_calc_loopback_gain(dev); 1056 if (phy->radio_rev != 8) { 1057 if (phy->initval == 0xFFFF) 1058 phy->initval = b43legacy_radio_init2050(dev); 1059 else 1060 b43legacy_radio_write16(dev, 0x0078, phy->initval); 1061 } 1062 if (phy->txctl2 == 0xFFFF) 1063 b43legacy_phy_lo_g_measure(dev); 1064 else { 1065 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) 1066 b43legacy_radio_write16(dev, 0x0052, 1067 (phy->txctl1 << 4) | 1068 phy->txctl2); 1069 else 1070 b43legacy_radio_write16(dev, 0x0052, 1071 (b43legacy_radio_read16(dev, 1072 0x0052) & 0xFFF0) | 1073 phy->txctl1); 1074 if (phy->rev >= 6) 1075 b43legacy_phy_write(dev, 0x0036, 1076 (b43legacy_phy_read(dev, 0x0036) 1077 & 0x0FFF) | (phy->txctl2 << 12)); 1078 if (dev->dev->bus->sprom.boardflags_lo & 1079 B43legacy_BFL_PACTRL) 1080 b43legacy_phy_write(dev, 0x002E, 0x8075); 1081 else 1082 b43legacy_phy_write(dev, 0x002E, 0x807F); 1083 if (phy->rev < 2) 1084 b43legacy_phy_write(dev, 0x002F, 0x0101); 1085 else 1086 b43legacy_phy_write(dev, 0x002F, 0x0202); 1087 } 1088 if (phy->gmode) { 1089 b43legacy_phy_lo_adjust(dev, 0); 1090 b43legacy_phy_write(dev, 0x080F, 0x8078); 1091 } 1092 1093 if (!(dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI)) { 1094 /* The specs state to update the NRSSI LT with 1095 * the value 0x7FFFFFFF here. I think that is some weird 1096 * compiler optimization in the original driver. 1097 * Essentially, what we do here is resetting all NRSSI LT 1098 * entries to -32 (see the clamp_val() in nrssi_hw_update()) 1099 */ 1100 b43legacy_nrssi_hw_update(dev, 0xFFFF); 1101 b43legacy_calc_nrssi_threshold(dev); 1102 } else if (phy->gmode || phy->rev >= 2) { 1103 if (phy->nrssi[0] == -1000) { 1104 B43legacy_WARN_ON(phy->nrssi[1] != -1000); 1105 b43legacy_calc_nrssi_slope(dev); 1106 } else { 1107 B43legacy_WARN_ON(phy->nrssi[1] == -1000); 1108 b43legacy_calc_nrssi_threshold(dev); 1109 } 1110 } 1111 if (phy->radio_rev == 8) 1112 b43legacy_phy_write(dev, 0x0805, 0x3230); 1113 b43legacy_phy_init_pctl(dev); 1114 if (dev->dev->bus->chip_id == 0x4306 1115 && dev->dev->bus->chip_package == 2) { 1116 b43legacy_phy_write(dev, 0x0429, 1117 b43legacy_phy_read(dev, 0x0429) & 0xBFFF); 1118 b43legacy_phy_write(dev, 0x04C3, 1119 b43legacy_phy_read(dev, 0x04C3) & 0x7FFF); 1120 } 1121 } 1122 1123 static u16 b43legacy_phy_lo_b_r15_loop(struct b43legacy_wldev *dev) 1124 { 1125 int i; 1126 u16 ret = 0; 1127 unsigned long flags; 1128 1129 local_irq_save(flags); 1130 for (i = 0; i < 10; i++) { 1131 b43legacy_phy_write(dev, 0x0015, 0xAFA0); 1132 udelay(1); 1133 b43legacy_phy_write(dev, 0x0015, 0xEFA0); 1134 udelay(10); 1135 b43legacy_phy_write(dev, 0x0015, 0xFFA0); 1136 udelay(40); 1137 ret += b43legacy_phy_read(dev, 0x002C); 1138 } 1139 local_irq_restore(flags); 1140 b43legacy_voluntary_preempt(); 1141 1142 return ret; 1143 } 1144 1145 void b43legacy_phy_lo_b_measure(struct b43legacy_wldev *dev) 1146 { 1147 struct b43legacy_phy *phy = &dev->phy; 1148 u16 regstack[12] = { 0 }; 1149 u16 mls; 1150 u16 fval; 1151 int i; 1152 int j; 1153 1154 regstack[0] = b43legacy_phy_read(dev, 0x0015); 1155 regstack[1] = b43legacy_radio_read16(dev, 0x0052) & 0xFFF0; 1156 1157 if (phy->radio_ver == 0x2053) { 1158 regstack[2] = b43legacy_phy_read(dev, 0x000A); 1159 regstack[3] = b43legacy_phy_read(dev, 0x002A); 1160 regstack[4] = b43legacy_phy_read(dev, 0x0035); 1161 regstack[5] = b43legacy_phy_read(dev, 0x0003); 1162 regstack[6] = b43legacy_phy_read(dev, 0x0001); 1163 regstack[7] = b43legacy_phy_read(dev, 0x0030); 1164 1165 regstack[8] = b43legacy_radio_read16(dev, 0x0043); 1166 regstack[9] = b43legacy_radio_read16(dev, 0x007A); 1167 regstack[10] = b43legacy_read16(dev, 0x03EC); 1168 regstack[11] = b43legacy_radio_read16(dev, 0x0052) & 0x00F0; 1169 1170 b43legacy_phy_write(dev, 0x0030, 0x00FF); 1171 b43legacy_write16(dev, 0x03EC, 0x3F3F); 1172 b43legacy_phy_write(dev, 0x0035, regstack[4] & 0xFF7F); 1173 b43legacy_radio_write16(dev, 0x007A, regstack[9] & 0xFFF0); 1174 } 1175 b43legacy_phy_write(dev, 0x0015, 0xB000); 1176 b43legacy_phy_write(dev, 0x002B, 0x0004); 1177 1178 if (phy->radio_ver == 0x2053) { 1179 b43legacy_phy_write(dev, 0x002B, 0x0203); 1180 b43legacy_phy_write(dev, 0x002A, 0x08A3); 1181 } 1182 1183 phy->minlowsig[0] = 0xFFFF; 1184 1185 for (i = 0; i < 4; i++) { 1186 b43legacy_radio_write16(dev, 0x0052, regstack[1] | i); 1187 b43legacy_phy_lo_b_r15_loop(dev); 1188 } 1189 for (i = 0; i < 10; i++) { 1190 b43legacy_radio_write16(dev, 0x0052, regstack[1] | i); 1191 mls = b43legacy_phy_lo_b_r15_loop(dev) / 10; 1192 if (mls < phy->minlowsig[0]) { 1193 phy->minlowsig[0] = mls; 1194 phy->minlowsigpos[0] = i; 1195 } 1196 } 1197 b43legacy_radio_write16(dev, 0x0052, regstack[1] 1198 | phy->minlowsigpos[0]); 1199 1200 phy->minlowsig[1] = 0xFFFF; 1201 1202 for (i = -4; i < 5; i += 2) { 1203 for (j = -4; j < 5; j += 2) { 1204 if (j < 0) 1205 fval = (0x0100 * i) + j + 0x0100; 1206 else 1207 fval = (0x0100 * i) + j; 1208 b43legacy_phy_write(dev, 0x002F, fval); 1209 mls = b43legacy_phy_lo_b_r15_loop(dev) / 10; 1210 if (mls < phy->minlowsig[1]) { 1211 phy->minlowsig[1] = mls; 1212 phy->minlowsigpos[1] = fval; 1213 } 1214 } 1215 } 1216 phy->minlowsigpos[1] += 0x0101; 1217 1218 b43legacy_phy_write(dev, 0x002F, phy->minlowsigpos[1]); 1219 if (phy->radio_ver == 0x2053) { 1220 b43legacy_phy_write(dev, 0x000A, regstack[2]); 1221 b43legacy_phy_write(dev, 0x002A, regstack[3]); 1222 b43legacy_phy_write(dev, 0x0035, regstack[4]); 1223 b43legacy_phy_write(dev, 0x0003, regstack[5]); 1224 b43legacy_phy_write(dev, 0x0001, regstack[6]); 1225 b43legacy_phy_write(dev, 0x0030, regstack[7]); 1226 1227 b43legacy_radio_write16(dev, 0x0043, regstack[8]); 1228 b43legacy_radio_write16(dev, 0x007A, regstack[9]); 1229 1230 b43legacy_radio_write16(dev, 0x0052, 1231 (b43legacy_radio_read16(dev, 0x0052) 1232 & 0x000F) | regstack[11]); 1233 1234 b43legacy_write16(dev, 0x03EC, regstack[10]); 1235 } 1236 b43legacy_phy_write(dev, 0x0015, regstack[0]); 1237 } 1238 1239 static inline 1240 u16 b43legacy_phy_lo_g_deviation_subval(struct b43legacy_wldev *dev, 1241 u16 control) 1242 { 1243 struct b43legacy_phy *phy = &dev->phy; 1244 u16 ret; 1245 unsigned long flags; 1246 1247 local_irq_save(flags); 1248 if (phy->gmode) { 1249 b43legacy_phy_write(dev, 0x15, 0xE300); 1250 control <<= 8; 1251 b43legacy_phy_write(dev, 0x0812, control | 0x00B0); 1252 udelay(5); 1253 b43legacy_phy_write(dev, 0x0812, control | 0x00B2); 1254 udelay(2); 1255 b43legacy_phy_write(dev, 0x0812, control | 0x00B3); 1256 udelay(4); 1257 b43legacy_phy_write(dev, 0x0015, 0xF300); 1258 udelay(8); 1259 } else { 1260 b43legacy_phy_write(dev, 0x0015, control | 0xEFA0); 1261 udelay(2); 1262 b43legacy_phy_write(dev, 0x0015, control | 0xEFE0); 1263 udelay(4); 1264 b43legacy_phy_write(dev, 0x0015, control | 0xFFE0); 1265 udelay(8); 1266 } 1267 ret = b43legacy_phy_read(dev, 0x002D); 1268 local_irq_restore(flags); 1269 b43legacy_voluntary_preempt(); 1270 1271 return ret; 1272 } 1273 1274 static u32 b43legacy_phy_lo_g_singledeviation(struct b43legacy_wldev *dev, 1275 u16 control) 1276 { 1277 int i; 1278 u32 ret = 0; 1279 1280 for (i = 0; i < 8; i++) 1281 ret += b43legacy_phy_lo_g_deviation_subval(dev, control); 1282 1283 return ret; 1284 } 1285 1286 /* Write the LocalOscillator CONTROL */ 1287 static inline 1288 void b43legacy_lo_write(struct b43legacy_wldev *dev, 1289 struct b43legacy_lopair *pair) 1290 { 1291 u16 value; 1292 1293 value = (u8)(pair->low); 1294 value |= ((u8)(pair->high)) << 8; 1295 1296 #ifdef CONFIG_B43LEGACY_DEBUG 1297 /* Sanity check. */ 1298 if (pair->low < -8 || pair->low > 8 || 1299 pair->high < -8 || pair->high > 8) { 1300 b43legacydbg(dev->wl, 1301 "WARNING: Writing invalid LOpair " 1302 "(low: %d, high: %d)\n", 1303 pair->low, pair->high); 1304 dump_stack(); 1305 } 1306 #endif 1307 1308 b43legacy_phy_write(dev, B43legacy_PHY_G_LO_CONTROL, value); 1309 } 1310 1311 static inline 1312 struct b43legacy_lopair *b43legacy_find_lopair(struct b43legacy_wldev *dev, 1313 u16 bbatt, 1314 u16 rfatt, 1315 u16 tx) 1316 { 1317 static const u8 dict[10] = { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 }; 1318 struct b43legacy_phy *phy = &dev->phy; 1319 1320 if (bbatt > 6) 1321 bbatt = 6; 1322 B43legacy_WARN_ON(rfatt >= 10); 1323 1324 if (tx == 3) 1325 return b43legacy_get_lopair(phy, rfatt, bbatt); 1326 return b43legacy_get_lopair(phy, dict[rfatt], bbatt); 1327 } 1328 1329 static inline 1330 struct b43legacy_lopair *b43legacy_current_lopair(struct b43legacy_wldev *dev) 1331 { 1332 struct b43legacy_phy *phy = &dev->phy; 1333 1334 return b43legacy_find_lopair(dev, phy->bbatt, 1335 phy->rfatt, phy->txctl1); 1336 } 1337 1338 /* Adjust B/G LO */ 1339 void b43legacy_phy_lo_adjust(struct b43legacy_wldev *dev, int fixed) 1340 { 1341 struct b43legacy_lopair *pair; 1342 1343 if (fixed) { 1344 /* Use fixed values. Only for initialization. */ 1345 pair = b43legacy_find_lopair(dev, 2, 3, 0); 1346 } else 1347 pair = b43legacy_current_lopair(dev); 1348 b43legacy_lo_write(dev, pair); 1349 } 1350 1351 static void b43legacy_phy_lo_g_measure_txctl2(struct b43legacy_wldev *dev) 1352 { 1353 struct b43legacy_phy *phy = &dev->phy; 1354 u16 txctl2 = 0; 1355 u16 i; 1356 u32 smallest; 1357 u32 tmp; 1358 1359 b43legacy_radio_write16(dev, 0x0052, 0x0000); 1360 udelay(10); 1361 smallest = b43legacy_phy_lo_g_singledeviation(dev, 0); 1362 for (i = 0; i < 16; i++) { 1363 b43legacy_radio_write16(dev, 0x0052, i); 1364 udelay(10); 1365 tmp = b43legacy_phy_lo_g_singledeviation(dev, 0); 1366 if (tmp < smallest) { 1367 smallest = tmp; 1368 txctl2 = i; 1369 } 1370 } 1371 phy->txctl2 = txctl2; 1372 } 1373 1374 static 1375 void b43legacy_phy_lo_g_state(struct b43legacy_wldev *dev, 1376 const struct b43legacy_lopair *in_pair, 1377 struct b43legacy_lopair *out_pair, 1378 u16 r27) 1379 { 1380 static const struct b43legacy_lopair transitions[8] = { 1381 { .high = 1, .low = 1, }, 1382 { .high = 1, .low = 0, }, 1383 { .high = 1, .low = -1, }, 1384 { .high = 0, .low = -1, }, 1385 { .high = -1, .low = -1, }, 1386 { .high = -1, .low = 0, }, 1387 { .high = -1, .low = 1, }, 1388 { .high = 0, .low = 1, }, 1389 }; 1390 struct b43legacy_lopair lowest_transition = { 1391 .high = in_pair->high, 1392 .low = in_pair->low, 1393 }; 1394 struct b43legacy_lopair tmp_pair; 1395 struct b43legacy_lopair transition; 1396 int i = 12; 1397 int state = 0; 1398 int found_lower; 1399 int j; 1400 int begin; 1401 int end; 1402 u32 lowest_deviation; 1403 u32 tmp; 1404 1405 /* Note that in_pair and out_pair can point to the same pair. 1406 * Be careful. */ 1407 1408 b43legacy_lo_write(dev, &lowest_transition); 1409 lowest_deviation = b43legacy_phy_lo_g_singledeviation(dev, r27); 1410 do { 1411 found_lower = 0; 1412 B43legacy_WARN_ON(!(state >= 0 && state <= 8)); 1413 if (state == 0) { 1414 begin = 1; 1415 end = 8; 1416 } else if (state % 2 == 0) { 1417 begin = state - 1; 1418 end = state + 1; 1419 } else { 1420 begin = state - 2; 1421 end = state + 2; 1422 } 1423 if (begin < 1) 1424 begin += 8; 1425 if (end > 8) 1426 end -= 8; 1427 1428 j = begin; 1429 tmp_pair.high = lowest_transition.high; 1430 tmp_pair.low = lowest_transition.low; 1431 while (1) { 1432 B43legacy_WARN_ON(!(j >= 1 && j <= 8)); 1433 transition.high = tmp_pair.high + 1434 transitions[j - 1].high; 1435 transition.low = tmp_pair.low + transitions[j - 1].low; 1436 if ((abs(transition.low) < 9) 1437 && (abs(transition.high) < 9)) { 1438 b43legacy_lo_write(dev, &transition); 1439 tmp = b43legacy_phy_lo_g_singledeviation(dev, 1440 r27); 1441 if (tmp < lowest_deviation) { 1442 lowest_deviation = tmp; 1443 state = j; 1444 found_lower = 1; 1445 1446 lowest_transition.high = 1447 transition.high; 1448 lowest_transition.low = transition.low; 1449 } 1450 } 1451 if (j == end) 1452 break; 1453 if (j == 8) 1454 j = 1; 1455 else 1456 j++; 1457 } 1458 } while (i-- && found_lower); 1459 1460 out_pair->high = lowest_transition.high; 1461 out_pair->low = lowest_transition.low; 1462 } 1463 1464 /* Set the baseband attenuation value on chip. */ 1465 void b43legacy_phy_set_baseband_attenuation(struct b43legacy_wldev *dev, 1466 u16 bbatt) 1467 { 1468 struct b43legacy_phy *phy = &dev->phy; 1469 u16 value; 1470 1471 if (phy->analog == 0) { 1472 value = (b43legacy_read16(dev, 0x03E6) & 0xFFF0); 1473 value |= (bbatt & 0x000F); 1474 b43legacy_write16(dev, 0x03E6, value); 1475 return; 1476 } 1477 1478 if (phy->analog > 1) { 1479 value = b43legacy_phy_read(dev, 0x0060) & 0xFFC3; 1480 value |= (bbatt << 2) & 0x003C; 1481 } else { 1482 value = b43legacy_phy_read(dev, 0x0060) & 0xFF87; 1483 value |= (bbatt << 3) & 0x0078; 1484 } 1485 b43legacy_phy_write(dev, 0x0060, value); 1486 } 1487 1488 /* http://bcm-specs.sipsolutions.net/LocalOscillator/Measure */ 1489 void b43legacy_phy_lo_g_measure(struct b43legacy_wldev *dev) 1490 { 1491 static const u8 pairorder[10] = { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8 }; 1492 const int is_initializing = (b43legacy_status(dev) 1493 < B43legacy_STAT_STARTED); 1494 struct b43legacy_phy *phy = &dev->phy; 1495 u16 h; 1496 u16 i; 1497 u16 oldi = 0; 1498 u16 j; 1499 struct b43legacy_lopair control; 1500 struct b43legacy_lopair *tmp_control; 1501 u16 tmp; 1502 u16 regstack[16] = { 0 }; 1503 u8 oldchannel; 1504 1505 /* XXX: What are these? */ 1506 u8 r27 = 0; 1507 u16 r31; 1508 1509 oldchannel = phy->channel; 1510 /* Setup */ 1511 if (phy->gmode) { 1512 regstack[0] = b43legacy_phy_read(dev, B43legacy_PHY_G_CRS); 1513 regstack[1] = b43legacy_phy_read(dev, 0x0802); 1514 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0] 1515 & 0x7FFF); 1516 b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC); 1517 } 1518 regstack[3] = b43legacy_read16(dev, 0x03E2); 1519 b43legacy_write16(dev, 0x03E2, regstack[3] | 0x8000); 1520 regstack[4] = b43legacy_read16(dev, B43legacy_MMIO_CHANNEL_EXT); 1521 regstack[5] = b43legacy_phy_read(dev, 0x15); 1522 regstack[6] = b43legacy_phy_read(dev, 0x2A); 1523 regstack[7] = b43legacy_phy_read(dev, 0x35); 1524 regstack[8] = b43legacy_phy_read(dev, 0x60); 1525 regstack[9] = b43legacy_radio_read16(dev, 0x43); 1526 regstack[10] = b43legacy_radio_read16(dev, 0x7A); 1527 regstack[11] = b43legacy_radio_read16(dev, 0x52); 1528 if (phy->gmode) { 1529 regstack[12] = b43legacy_phy_read(dev, 0x0811); 1530 regstack[13] = b43legacy_phy_read(dev, 0x0812); 1531 regstack[14] = b43legacy_phy_read(dev, 0x0814); 1532 regstack[15] = b43legacy_phy_read(dev, 0x0815); 1533 } 1534 b43legacy_radio_selectchannel(dev, 6, 0); 1535 if (phy->gmode) { 1536 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0] 1537 & 0x7FFF); 1538 b43legacy_phy_write(dev, 0x0802, regstack[1] & 0xFFFC); 1539 b43legacy_dummy_transmission(dev); 1540 } 1541 b43legacy_radio_write16(dev, 0x0043, 0x0006); 1542 1543 b43legacy_phy_set_baseband_attenuation(dev, 2); 1544 1545 b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, 0x0000); 1546 b43legacy_phy_write(dev, 0x002E, 0x007F); 1547 b43legacy_phy_write(dev, 0x080F, 0x0078); 1548 b43legacy_phy_write(dev, 0x0035, regstack[7] & ~(1 << 7)); 1549 b43legacy_radio_write16(dev, 0x007A, regstack[10] & 0xFFF0); 1550 b43legacy_phy_write(dev, 0x002B, 0x0203); 1551 b43legacy_phy_write(dev, 0x002A, 0x08A3); 1552 if (phy->gmode) { 1553 b43legacy_phy_write(dev, 0x0814, regstack[14] | 0x0003); 1554 b43legacy_phy_write(dev, 0x0815, regstack[15] & 0xFFFC); 1555 b43legacy_phy_write(dev, 0x0811, 0x01B3); 1556 b43legacy_phy_write(dev, 0x0812, 0x00B2); 1557 } 1558 if (is_initializing) 1559 b43legacy_phy_lo_g_measure_txctl2(dev); 1560 b43legacy_phy_write(dev, 0x080F, 0x8078); 1561 1562 /* Measure */ 1563 control.low = 0; 1564 control.high = 0; 1565 for (h = 0; h < 10; h++) { 1566 /* Loop over each possible RadioAttenuation (0-9) */ 1567 i = pairorder[h]; 1568 if (is_initializing) { 1569 if (i == 3) { 1570 control.low = 0; 1571 control.high = 0; 1572 } else if (((i % 2 == 1) && (oldi % 2 == 1)) || 1573 ((i % 2 == 0) && (oldi % 2 == 0))) { 1574 tmp_control = b43legacy_get_lopair(phy, oldi, 1575 0); 1576 memcpy(&control, tmp_control, sizeof(control)); 1577 } else { 1578 tmp_control = b43legacy_get_lopair(phy, 3, 0); 1579 memcpy(&control, tmp_control, sizeof(control)); 1580 } 1581 } 1582 /* Loop over each possible BasebandAttenuation/2 */ 1583 for (j = 0; j < 4; j++) { 1584 if (is_initializing) { 1585 tmp = i * 2 + j; 1586 r27 = 0; 1587 r31 = 0; 1588 if (tmp > 14) { 1589 r31 = 1; 1590 if (tmp > 17) 1591 r27 = 1; 1592 if (tmp > 19) 1593 r27 = 2; 1594 } 1595 } else { 1596 tmp_control = b43legacy_get_lopair(phy, i, 1597 j * 2); 1598 if (!tmp_control->used) 1599 continue; 1600 memcpy(&control, tmp_control, sizeof(control)); 1601 r27 = 3; 1602 r31 = 0; 1603 } 1604 b43legacy_radio_write16(dev, 0x43, i); 1605 b43legacy_radio_write16(dev, 0x52, phy->txctl2); 1606 udelay(10); 1607 b43legacy_voluntary_preempt(); 1608 1609 b43legacy_phy_set_baseband_attenuation(dev, j * 2); 1610 1611 tmp = (regstack[10] & 0xFFF0); 1612 if (r31) 1613 tmp |= 0x0008; 1614 b43legacy_radio_write16(dev, 0x007A, tmp); 1615 1616 tmp_control = b43legacy_get_lopair(phy, i, j * 2); 1617 b43legacy_phy_lo_g_state(dev, &control, tmp_control, 1618 r27); 1619 } 1620 oldi = i; 1621 } 1622 /* Loop over each possible RadioAttenuation (10-13) */ 1623 for (i = 10; i < 14; i++) { 1624 /* Loop over each possible BasebandAttenuation/2 */ 1625 for (j = 0; j < 4; j++) { 1626 if (is_initializing) { 1627 tmp_control = b43legacy_get_lopair(phy, i - 9, 1628 j * 2); 1629 memcpy(&control, tmp_control, sizeof(control)); 1630 /* FIXME: The next line is wrong, as the 1631 * following if statement can never trigger. */ 1632 tmp = (i - 9) * 2 + j - 5; 1633 r27 = 0; 1634 r31 = 0; 1635 if (tmp > 14) { 1636 r31 = 1; 1637 if (tmp > 17) 1638 r27 = 1; 1639 if (tmp > 19) 1640 r27 = 2; 1641 } 1642 } else { 1643 tmp_control = b43legacy_get_lopair(phy, i - 9, 1644 j * 2); 1645 if (!tmp_control->used) 1646 continue; 1647 memcpy(&control, tmp_control, sizeof(control)); 1648 r27 = 3; 1649 r31 = 0; 1650 } 1651 b43legacy_radio_write16(dev, 0x43, i - 9); 1652 /* FIXME: shouldn't txctl1 be zero in the next line 1653 * and 3 in the loop above? */ 1654 b43legacy_radio_write16(dev, 0x52, 1655 phy->txctl2 1656 | (3/*txctl1*/ << 4)); 1657 udelay(10); 1658 b43legacy_voluntary_preempt(); 1659 1660 b43legacy_phy_set_baseband_attenuation(dev, j * 2); 1661 1662 tmp = (regstack[10] & 0xFFF0); 1663 if (r31) 1664 tmp |= 0x0008; 1665 b43legacy_radio_write16(dev, 0x7A, tmp); 1666 1667 tmp_control = b43legacy_get_lopair(phy, i, j * 2); 1668 b43legacy_phy_lo_g_state(dev, &control, tmp_control, 1669 r27); 1670 } 1671 } 1672 1673 /* Restoration */ 1674 if (phy->gmode) { 1675 b43legacy_phy_write(dev, 0x0015, 0xE300); 1676 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA0); 1677 udelay(5); 1678 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA2); 1679 udelay(2); 1680 b43legacy_phy_write(dev, 0x0812, (r27 << 8) | 0xA3); 1681 b43legacy_voluntary_preempt(); 1682 } else 1683 b43legacy_phy_write(dev, 0x0015, r27 | 0xEFA0); 1684 b43legacy_phy_lo_adjust(dev, is_initializing); 1685 b43legacy_phy_write(dev, 0x002E, 0x807F); 1686 if (phy->gmode) 1687 b43legacy_phy_write(dev, 0x002F, 0x0202); 1688 else 1689 b43legacy_phy_write(dev, 0x002F, 0x0101); 1690 b43legacy_write16(dev, B43legacy_MMIO_CHANNEL_EXT, regstack[4]); 1691 b43legacy_phy_write(dev, 0x0015, regstack[5]); 1692 b43legacy_phy_write(dev, 0x002A, regstack[6]); 1693 b43legacy_phy_write(dev, 0x0035, regstack[7]); 1694 b43legacy_phy_write(dev, 0x0060, regstack[8]); 1695 b43legacy_radio_write16(dev, 0x0043, regstack[9]); 1696 b43legacy_radio_write16(dev, 0x007A, regstack[10]); 1697 regstack[11] &= 0x00F0; 1698 regstack[11] |= (b43legacy_radio_read16(dev, 0x52) & 0x000F); 1699 b43legacy_radio_write16(dev, 0x52, regstack[11]); 1700 b43legacy_write16(dev, 0x03E2, regstack[3]); 1701 if (phy->gmode) { 1702 b43legacy_phy_write(dev, 0x0811, regstack[12]); 1703 b43legacy_phy_write(dev, 0x0812, regstack[13]); 1704 b43legacy_phy_write(dev, 0x0814, regstack[14]); 1705 b43legacy_phy_write(dev, 0x0815, regstack[15]); 1706 b43legacy_phy_write(dev, B43legacy_PHY_G_CRS, regstack[0]); 1707 b43legacy_phy_write(dev, 0x0802, regstack[1]); 1708 } 1709 b43legacy_radio_selectchannel(dev, oldchannel, 1); 1710 1711 #ifdef CONFIG_B43LEGACY_DEBUG 1712 { 1713 /* Sanity check for all lopairs. */ 1714 for (i = 0; i < B43legacy_LO_COUNT; i++) { 1715 tmp_control = phy->_lo_pairs + i; 1716 if (tmp_control->low < -8 || tmp_control->low > 8 || 1717 tmp_control->high < -8 || tmp_control->high > 8) 1718 b43legacywarn(dev->wl, 1719 "WARNING: Invalid LOpair (low: %d, high:" 1720 " %d, index: %d)\n", 1721 tmp_control->low, tmp_control->high, i); 1722 } 1723 } 1724 #endif /* CONFIG_B43LEGACY_DEBUG */ 1725 } 1726 1727 static 1728 void b43legacy_phy_lo_mark_current_used(struct b43legacy_wldev *dev) 1729 { 1730 struct b43legacy_lopair *pair; 1731 1732 pair = b43legacy_current_lopair(dev); 1733 pair->used = 1; 1734 } 1735 1736 void b43legacy_phy_lo_mark_all_unused(struct b43legacy_wldev *dev) 1737 { 1738 struct b43legacy_phy *phy = &dev->phy; 1739 struct b43legacy_lopair *pair; 1740 int i; 1741 1742 for (i = 0; i < B43legacy_LO_COUNT; i++) { 1743 pair = phy->_lo_pairs + i; 1744 pair->used = 0; 1745 } 1746 } 1747 1748 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut 1749 * This function converts a TSSI value to dBm in Q5.2 1750 */ 1751 static s8 b43legacy_phy_estimate_power_out(struct b43legacy_wldev *dev, s8 tssi) 1752 { 1753 struct b43legacy_phy *phy = &dev->phy; 1754 s8 dbm = 0; 1755 s32 tmp; 1756 1757 tmp = phy->idle_tssi; 1758 tmp += tssi; 1759 tmp -= phy->savedpctlreg; 1760 1761 switch (phy->type) { 1762 case B43legacy_PHYTYPE_B: 1763 case B43legacy_PHYTYPE_G: 1764 tmp = clamp_val(tmp, 0x00, 0x3F); 1765 dbm = phy->tssi2dbm[tmp]; 1766 break; 1767 default: 1768 B43legacy_BUG_ON(1); 1769 } 1770 1771 return dbm; 1772 } 1773 1774 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */ 1775 void b43legacy_phy_xmitpower(struct b43legacy_wldev *dev) 1776 { 1777 struct b43legacy_phy *phy = &dev->phy; 1778 u16 tmp; 1779 u16 txpower; 1780 s8 v0; 1781 s8 v1; 1782 s8 v2; 1783 s8 v3; 1784 s8 average; 1785 int max_pwr; 1786 s16 desired_pwr; 1787 s16 estimated_pwr; 1788 s16 pwr_adjust; 1789 s16 radio_att_delta; 1790 s16 baseband_att_delta; 1791 s16 radio_attenuation; 1792 s16 baseband_attenuation; 1793 1794 if (phy->savedpctlreg == 0xFFFF) 1795 return; 1796 if ((dev->dev->bus->boardinfo.type == 0x0416) && 1797 is_bcm_board_vendor(dev)) 1798 return; 1799 #ifdef CONFIG_B43LEGACY_DEBUG 1800 if (phy->manual_txpower_control) 1801 return; 1802 #endif 1803 1804 B43legacy_BUG_ON(!(phy->type == B43legacy_PHYTYPE_B || 1805 phy->type == B43legacy_PHYTYPE_G)); 1806 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x0058); 1807 v0 = (s8)(tmp & 0x00FF); 1808 v1 = (s8)((tmp & 0xFF00) >> 8); 1809 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005A); 1810 v2 = (s8)(tmp & 0x00FF); 1811 v3 = (s8)((tmp & 0xFF00) >> 8); 1812 tmp = 0; 1813 1814 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) { 1815 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1816 0x0070); 1817 v0 = (s8)(tmp & 0x00FF); 1818 v1 = (s8)((tmp & 0xFF00) >> 8); 1819 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 1820 0x0072); 1821 v2 = (s8)(tmp & 0x00FF); 1822 v3 = (s8)((tmp & 0xFF00) >> 8); 1823 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) 1824 return; 1825 v0 = (v0 + 0x20) & 0x3F; 1826 v1 = (v1 + 0x20) & 0x3F; 1827 v2 = (v2 + 0x20) & 0x3F; 1828 v3 = (v3 + 0x20) & 0x3F; 1829 tmp = 1; 1830 } 1831 b43legacy_radio_clear_tssi(dev); 1832 1833 average = (v0 + v1 + v2 + v3 + 2) / 4; 1834 1835 if (tmp && (b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x005E) 1836 & 0x8)) 1837 average -= 13; 1838 1839 estimated_pwr = b43legacy_phy_estimate_power_out(dev, average); 1840 1841 max_pwr = dev->dev->bus->sprom.maxpwr_bg; 1842 1843 if ((dev->dev->bus->sprom.boardflags_lo 1844 & B43legacy_BFL_PACTRL) && 1845 (phy->type == B43legacy_PHYTYPE_G)) 1846 max_pwr -= 0x3; 1847 if (unlikely(max_pwr <= 0)) { 1848 b43legacywarn(dev->wl, "Invalid max-TX-power value in SPROM." 1849 "\n"); 1850 max_pwr = 74; /* fake it */ 1851 dev->dev->bus->sprom.maxpwr_bg = max_pwr; 1852 } 1853 1854 /* Use regulatory information to get the maximum power. 1855 * In the absence of such data from mac80211, we will use 20 dBm, which 1856 * is the value for the EU, US, Canada, and most of the world. 1857 * The regulatory maximum is reduced by the antenna gain (from sprom) 1858 * and 1.5 dBm (a safety factor??). The result is in Q5.2 format 1859 * which accounts for the factor of 4 */ 1860 #define REG_MAX_PWR 20 1861 max_pwr = min(REG_MAX_PWR * 4 1862 - dev->dev->bus->sprom.antenna_gain.a0 1863 - 0x6, max_pwr); 1864 1865 /* find the desired power in Q5.2 - power_level is in dBm 1866 * and limit it - max_pwr is already in Q5.2 */ 1867 desired_pwr = clamp_val(phy->power_level << 2, 0, max_pwr); 1868 if (b43legacy_debug(dev, B43legacy_DBG_XMITPOWER)) 1869 b43legacydbg(dev->wl, "Current TX power output: " Q52_FMT 1870 " dBm, Desired TX power output: " Q52_FMT 1871 " dBm\n", Q52_ARG(estimated_pwr), 1872 Q52_ARG(desired_pwr)); 1873 /* Check if we need to adjust the current power. The factor of 2 is 1874 * for damping */ 1875 pwr_adjust = (desired_pwr - estimated_pwr) / 2; 1876 /* RF attenuation delta 1877 * The minus sign is because lower attenuation => more power */ 1878 radio_att_delta = -(pwr_adjust + 7) >> 3; 1879 /* Baseband attenuation delta */ 1880 baseband_att_delta = -(pwr_adjust >> 1) - (4 * radio_att_delta); 1881 /* Do we need to adjust anything? */ 1882 if ((radio_att_delta == 0) && (baseband_att_delta == 0)) { 1883 b43legacy_phy_lo_mark_current_used(dev); 1884 return; 1885 } 1886 1887 /* Calculate the new attenuation values. */ 1888 baseband_attenuation = phy->bbatt; 1889 baseband_attenuation += baseband_att_delta; 1890 radio_attenuation = phy->rfatt; 1891 radio_attenuation += radio_att_delta; 1892 1893 /* Get baseband and radio attenuation values into permitted ranges. 1894 * baseband 0-11, radio 0-9. 1895 * Radio attenuation affects power level 4 times as much as baseband. 1896 */ 1897 if (radio_attenuation < 0) { 1898 baseband_attenuation -= (4 * -radio_attenuation); 1899 radio_attenuation = 0; 1900 } else if (radio_attenuation > 9) { 1901 baseband_attenuation += (4 * (radio_attenuation - 9)); 1902 radio_attenuation = 9; 1903 } else { 1904 while (baseband_attenuation < 0 && radio_attenuation > 0) { 1905 baseband_attenuation += 4; 1906 radio_attenuation--; 1907 } 1908 while (baseband_attenuation > 11 && radio_attenuation < 9) { 1909 baseband_attenuation -= 4; 1910 radio_attenuation++; 1911 } 1912 } 1913 baseband_attenuation = clamp_val(baseband_attenuation, 0, 11); 1914 1915 txpower = phy->txctl1; 1916 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) { 1917 if (radio_attenuation <= 1) { 1918 if (txpower == 0) { 1919 txpower = 3; 1920 radio_attenuation += 2; 1921 baseband_attenuation += 2; 1922 } else if (dev->dev->bus->sprom.boardflags_lo 1923 & B43legacy_BFL_PACTRL) { 1924 baseband_attenuation += 4 * 1925 (radio_attenuation - 2); 1926 radio_attenuation = 2; 1927 } 1928 } else if (radio_attenuation > 4 && txpower != 0) { 1929 txpower = 0; 1930 if (baseband_attenuation < 3) { 1931 radio_attenuation -= 3; 1932 baseband_attenuation += 2; 1933 } else { 1934 radio_attenuation -= 2; 1935 baseband_attenuation -= 2; 1936 } 1937 } 1938 } 1939 /* Save the control values */ 1940 phy->txctl1 = txpower; 1941 baseband_attenuation = clamp_val(baseband_attenuation, 0, 11); 1942 radio_attenuation = clamp_val(radio_attenuation, 0, 9); 1943 phy->rfatt = radio_attenuation; 1944 phy->bbatt = baseband_attenuation; 1945 1946 /* Adjust the hardware */ 1947 b43legacy_phy_lock(dev); 1948 b43legacy_radio_lock(dev); 1949 b43legacy_radio_set_txpower_bg(dev, baseband_attenuation, 1950 radio_attenuation, txpower); 1951 b43legacy_phy_lo_mark_current_used(dev); 1952 b43legacy_radio_unlock(dev); 1953 b43legacy_phy_unlock(dev); 1954 } 1955 1956 static inline 1957 s32 b43legacy_tssi2dbm_ad(s32 num, s32 den) 1958 { 1959 if (num < 0) 1960 return num/den; 1961 else 1962 return (num+den/2)/den; 1963 } 1964 1965 static inline 1966 s8 b43legacy_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2) 1967 { 1968 s32 m1; 1969 s32 m2; 1970 s32 f = 256; 1971 s32 q; 1972 s32 delta; 1973 s8 i = 0; 1974 1975 m1 = b43legacy_tssi2dbm_ad(16 * pab0 + index * pab1, 32); 1976 m2 = max(b43legacy_tssi2dbm_ad(32768 + index * pab2, 256), 1); 1977 do { 1978 if (i > 15) 1979 return -EINVAL; 1980 q = b43legacy_tssi2dbm_ad(f * 4096 - 1981 b43legacy_tssi2dbm_ad(m2 * f, 16) * 1982 f, 2048); 1983 delta = abs(q - f); 1984 f = q; 1985 i++; 1986 } while (delta >= 2); 1987 entry[index] = clamp_val(b43legacy_tssi2dbm_ad(m1 * f, 8192), 1988 -127, 128); 1989 return 0; 1990 } 1991 1992 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */ 1993 int b43legacy_phy_init_tssi2dbm_table(struct b43legacy_wldev *dev) 1994 { 1995 struct b43legacy_phy *phy = &dev->phy; 1996 s16 pab0; 1997 s16 pab1; 1998 s16 pab2; 1999 u8 idx; 2000 s8 *dyn_tssi2dbm; 2001 2002 B43legacy_WARN_ON(!(phy->type == B43legacy_PHYTYPE_B || 2003 phy->type == B43legacy_PHYTYPE_G)); 2004 pab0 = (s16)(dev->dev->bus->sprom.pa0b0); 2005 pab1 = (s16)(dev->dev->bus->sprom.pa0b1); 2006 pab2 = (s16)(dev->dev->bus->sprom.pa0b2); 2007 2008 if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) { 2009 phy->idle_tssi = 0x34; 2010 phy->tssi2dbm = b43legacy_tssi2dbm_b_table; 2011 return 0; 2012 } 2013 2014 if (pab0 != 0 && pab1 != 0 && pab2 != 0 && 2015 pab0 != -1 && pab1 != -1 && pab2 != -1) { 2016 /* The pabX values are set in SPROM. Use them. */ 2017 if ((s8)dev->dev->bus->sprom.itssi_bg != 0 && 2018 (s8)dev->dev->bus->sprom.itssi_bg != -1) 2019 phy->idle_tssi = (s8)(dev->dev->bus->sprom. 2020 itssi_bg); 2021 else 2022 phy->idle_tssi = 62; 2023 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL); 2024 if (dyn_tssi2dbm == NULL) { 2025 b43legacyerr(dev->wl, "Could not allocate memory " 2026 "for tssi2dbm table\n"); 2027 return -ENOMEM; 2028 } 2029 for (idx = 0; idx < 64; idx++) 2030 if (b43legacy_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0, 2031 pab1, pab2)) { 2032 phy->tssi2dbm = NULL; 2033 b43legacyerr(dev->wl, "Could not generate " 2034 "tssi2dBm table\n"); 2035 kfree(dyn_tssi2dbm); 2036 return -ENODEV; 2037 } 2038 phy->tssi2dbm = dyn_tssi2dbm; 2039 phy->dyn_tssi_tbl = 1; 2040 } else { 2041 /* pabX values not set in SPROM. */ 2042 switch (phy->type) { 2043 case B43legacy_PHYTYPE_B: 2044 phy->idle_tssi = 0x34; 2045 phy->tssi2dbm = b43legacy_tssi2dbm_b_table; 2046 break; 2047 case B43legacy_PHYTYPE_G: 2048 phy->idle_tssi = 0x34; 2049 phy->tssi2dbm = b43legacy_tssi2dbm_g_table; 2050 break; 2051 } 2052 } 2053 2054 return 0; 2055 } 2056 2057 int b43legacy_phy_init(struct b43legacy_wldev *dev) 2058 { 2059 struct b43legacy_phy *phy = &dev->phy; 2060 int err = -ENODEV; 2061 2062 switch (phy->type) { 2063 case B43legacy_PHYTYPE_B: 2064 switch (phy->rev) { 2065 case 2: 2066 b43legacy_phy_initb2(dev); 2067 err = 0; 2068 break; 2069 case 4: 2070 b43legacy_phy_initb4(dev); 2071 err = 0; 2072 break; 2073 case 5: 2074 b43legacy_phy_initb5(dev); 2075 err = 0; 2076 break; 2077 case 6: 2078 b43legacy_phy_initb6(dev); 2079 err = 0; 2080 break; 2081 } 2082 break; 2083 case B43legacy_PHYTYPE_G: 2084 b43legacy_phy_initg(dev); 2085 err = 0; 2086 break; 2087 } 2088 if (err) 2089 b43legacyerr(dev->wl, "Unknown PHYTYPE found\n"); 2090 2091 return err; 2092 } 2093 2094 void b43legacy_phy_set_antenna_diversity(struct b43legacy_wldev *dev) 2095 { 2096 struct b43legacy_phy *phy = &dev->phy; 2097 u16 antennadiv; 2098 u16 offset; 2099 u16 value; 2100 u32 ucodeflags; 2101 2102 antennadiv = phy->antenna_diversity; 2103 2104 if (antennadiv == 0xFFFF) 2105 antennadiv = 3; 2106 B43legacy_WARN_ON(antennadiv > 3); 2107 2108 ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 2109 B43legacy_UCODEFLAGS_OFFSET); 2110 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 2111 B43legacy_UCODEFLAGS_OFFSET, 2112 ucodeflags & ~B43legacy_UCODEFLAG_AUTODIV); 2113 2114 switch (phy->type) { 2115 case B43legacy_PHYTYPE_G: 2116 offset = 0x0400; 2117 2118 if (antennadiv == 2) 2119 value = (3/*automatic*/ << 7); 2120 else 2121 value = (antennadiv << 7); 2122 b43legacy_phy_write(dev, offset + 1, 2123 (b43legacy_phy_read(dev, offset + 1) 2124 & 0x7E7F) | value); 2125 2126 if (antennadiv >= 2) { 2127 if (antennadiv == 2) 2128 value = (antennadiv << 7); 2129 else 2130 value = (0/*force0*/ << 7); 2131 b43legacy_phy_write(dev, offset + 0x2B, 2132 (b43legacy_phy_read(dev, 2133 offset + 0x2B) 2134 & 0xFEFF) | value); 2135 } 2136 2137 if (phy->type == B43legacy_PHYTYPE_G) { 2138 if (antennadiv >= 2) 2139 b43legacy_phy_write(dev, 0x048C, 2140 b43legacy_phy_read(dev, 2141 0x048C) | 0x2000); 2142 else 2143 b43legacy_phy_write(dev, 0x048C, 2144 b43legacy_phy_read(dev, 2145 0x048C) & ~0x2000); 2146 if (phy->rev >= 2) { 2147 b43legacy_phy_write(dev, 0x0461, 2148 b43legacy_phy_read(dev, 2149 0x0461) | 0x0010); 2150 b43legacy_phy_write(dev, 0x04AD, 2151 (b43legacy_phy_read(dev, 2152 0x04AD) 2153 & 0x00FF) | 0x0015); 2154 if (phy->rev == 2) 2155 b43legacy_phy_write(dev, 0x0427, 2156 0x0008); 2157 else 2158 b43legacy_phy_write(dev, 0x0427, 2159 (b43legacy_phy_read(dev, 0x0427) 2160 & 0x00FF) | 0x0008); 2161 } else if (phy->rev >= 6) 2162 b43legacy_phy_write(dev, 0x049B, 0x00DC); 2163 } else { 2164 if (phy->rev < 3) 2165 b43legacy_phy_write(dev, 0x002B, 2166 (b43legacy_phy_read(dev, 2167 0x002B) & 0x00FF) 2168 | 0x0024); 2169 else { 2170 b43legacy_phy_write(dev, 0x0061, 2171 b43legacy_phy_read(dev, 2172 0x0061) | 0x0010); 2173 if (phy->rev == 3) { 2174 b43legacy_phy_write(dev, 0x0093, 2175 0x001D); 2176 b43legacy_phy_write(dev, 0x0027, 2177 0x0008); 2178 } else { 2179 b43legacy_phy_write(dev, 0x0093, 2180 0x003A); 2181 b43legacy_phy_write(dev, 0x0027, 2182 (b43legacy_phy_read(dev, 0x0027) 2183 & 0x00FF) | 0x0008); 2184 } 2185 } 2186 } 2187 break; 2188 case B43legacy_PHYTYPE_B: 2189 if (dev->dev->id.revision == 2) 2190 value = (3/*automatic*/ << 7); 2191 else 2192 value = (antennadiv << 7); 2193 b43legacy_phy_write(dev, 0x03E2, 2194 (b43legacy_phy_read(dev, 0x03E2) 2195 & 0xFE7F) | value); 2196 break; 2197 default: 2198 B43legacy_WARN_ON(1); 2199 } 2200 2201 if (antennadiv >= 2) { 2202 ucodeflags = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 2203 B43legacy_UCODEFLAGS_OFFSET); 2204 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 2205 B43legacy_UCODEFLAGS_OFFSET, 2206 ucodeflags | B43legacy_UCODEFLAG_AUTODIV); 2207 } 2208 2209 phy->antenna_diversity = antennadiv; 2210 } 2211 2212 /* Set the PowerSavingControlBits. 2213 * Bitvalues: 2214 * 0 => unset the bit 2215 * 1 => set the bit 2216 * -1 => calculate the bit 2217 */ 2218 void b43legacy_power_saving_ctl_bits(struct b43legacy_wldev *dev, 2219 int bit25, int bit26) 2220 { 2221 int i; 2222 u32 status; 2223 2224 /* FIXME: Force 25 to off and 26 to on for now: */ 2225 bit25 = 0; 2226 bit26 = 1; 2227 2228 if (bit25 == -1) { 2229 /* TODO: If powersave is not off and FIXME is not set and we 2230 * are not in adhoc and thus is not an AP and we arei 2231 * associated, set bit 25 */ 2232 } 2233 if (bit26 == -1) { 2234 /* TODO: If the device is awake or this is an AP, or we are 2235 * scanning, or FIXME, or we are associated, or FIXME, 2236 * or the latest PS-Poll packet sent was successful, 2237 * set bit26 */ 2238 } 2239 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL); 2240 if (bit25) 2241 status |= B43legacy_MACCTL_HWPS; 2242 else 2243 status &= ~B43legacy_MACCTL_HWPS; 2244 if (bit26) 2245 status |= B43legacy_MACCTL_AWAKE; 2246 else 2247 status &= ~B43legacy_MACCTL_AWAKE; 2248 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status); 2249 if (bit26 && dev->dev->id.revision >= 5) { 2250 for (i = 0; i < 100; i++) { 2251 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 2252 0x0040) != 4) 2253 break; 2254 udelay(10); 2255 } 2256 } 2257 } 2258