1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef B43_RADIO_2055_H_ 3 #define B43_RADIO_2055_H_ 4 5 #include <linux/types.h> 6 7 #include "tables_nphy.h" 8 9 #define B2055_GEN_SPARE 0x00 /* GEN spare */ 10 #define B2055_SP_PINPD 0x02 /* SP PIN PD */ 11 #define B2055_C1_SP_RSSI 0x03 /* SP RSSI Core 1 */ 12 #define B2055_C1_SP_PDMISC 0x04 /* SP PD MISC Core 1 */ 13 #define B2055_C2_SP_RSSI 0x05 /* SP RSSI Core 2 */ 14 #define B2055_C2_SP_PDMISC 0x06 /* SP PD MISC Core 2 */ 15 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */ 16 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */ 17 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */ 18 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */ 19 #define B2055_C1_SP_LPFBWSEL 0x0B /* SP LPF BW select Core 1 */ 20 #define B2055_C2_SP_LPFBWSEL 0x0C /* SP LPF BW select Core 2 */ 21 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */ 22 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */ 23 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */ 24 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */ 25 #define B2055_MASTER1 0x11 /* Master control 1 */ 26 #define B2055_MASTER2 0x12 /* Master control 2 */ 27 #define B2055_PD_LGEN 0x13 /* PD LGEN */ 28 #define B2055_PD_PLLTS 0x14 /* PD PLL TS */ 29 #define B2055_C1_PD_LGBUF 0x15 /* PD Core 1 LGBUF */ 30 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */ 31 #define B2055_C1_PD_RXTX 0x17 /* PD Core 1 RXTX */ 32 #define B2055_C1_PD_RSSIMISC 0x18 /* PD Core 1 RSSI MISC */ 33 #define B2055_C2_PD_LGBUF 0x19 /* PD Core 2 LGBUF */ 34 #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */ 35 #define B2055_C2_PD_RXTX 0x1B /* PD Core 2 RXTX */ 36 #define B2055_C2_PD_RSSIMISC 0x1C /* PD Core 2 RSSI MISC */ 37 #define B2055_PWRDET_LGEN 0x1D /* PWRDET LGEN */ 38 #define B2055_C1_PWRDET_LGBUF 0x1E /* PWRDET LGBUF Core 1 */ 39 #define B2055_C1_PWRDET_RXTX 0x1F /* PWRDET RXTX Core 1 */ 40 #define B2055_C2_PWRDET_LGBUF 0x20 /* PWRDET LGBUF Core 2 */ 41 #define B2055_C2_PWRDET_RXTX 0x21 /* PWRDET RXTX Core 2 */ 42 #define B2055_RRCCAL_CS 0x22 /* RRCCAL Control spare */ 43 #define B2055_RRCCAL_NOPTSEL 0x23 /* RRCCAL N OPT SEL */ 44 #define B2055_CAL_MISC 0x24 /* CAL MISC */ 45 #define B2055_CAL_COUT 0x25 /* CAL Counter out */ 46 #define B2055_CAL_COUT2 0x26 /* CAL Counter out 2 */ 47 #define B2055_CAL_CVARCTL 0x27 /* CAL CVAR Control */ 48 #define B2055_CAL_RVARCTL 0x28 /* CAL RVAR Control */ 49 #define B2055_CAL_LPOCTL 0x29 /* CAL LPO Control */ 50 #define B2055_CAL_TS 0x2A /* CAL TS */ 51 #define B2055_CAL_RCCALRTS 0x2B /* CAL RCCAL READ TS */ 52 #define B2055_CAL_RCALRTS 0x2C /* CAL RCAL READ TS */ 53 #define B2055_PADDRV 0x2D /* PAD driver */ 54 #define B2055_XOCTL1 0x2E /* XO Control 1 */ 55 #define B2055_XOCTL2 0x2F /* XO Control 2 */ 56 #define B2055_XOREGUL 0x30 /* XO Regulator */ 57 #define B2055_XOMISC 0x31 /* XO misc */ 58 #define B2055_PLL_LFC1 0x32 /* PLL LF C1 */ 59 #define B2055_PLL_CALVTH 0x33 /* PLL CAL VTH */ 60 #define B2055_PLL_LFC2 0x34 /* PLL LF C2 */ 61 #define B2055_PLL_REF 0x35 /* PLL reference */ 62 #define B2055_PLL_LFR1 0x36 /* PLL LF R1 */ 63 #define B2055_PLL_PFDCP 0x37 /* PLL PFD CP */ 64 #define B2055_PLL_IDAC_CPOPAMP 0x38 /* PLL IDAC CPOPAMP */ 65 #define B2055_PLL_CPREG 0x39 /* PLL CP Regulator */ 66 #define B2055_PLL_RCAL 0x3A /* PLL RCAL */ 67 #define B2055_RF_PLLMOD0 0x3B /* RF PLL MOD0 */ 68 #define B2055_RF_PLLMOD1 0x3C /* RF PLL MOD1 */ 69 #define B2055_RF_MMDIDAC1 0x3D /* RF MMD IDAC 1 */ 70 #define B2055_RF_MMDIDAC0 0x3E /* RF MMD IDAC 0 */ 71 #define B2055_RF_MMDSP 0x3F /* RF MMD spare */ 72 #define B2055_VCO_CAL1 0x40 /* VCO cal 1 */ 73 #define B2055_VCO_CAL2 0x41 /* VCO cal 2 */ 74 #define B2055_VCO_CAL3 0x42 /* VCO cal 3 */ 75 #define B2055_VCO_CAL4 0x43 /* VCO cal 4 */ 76 #define B2055_VCO_CAL5 0x44 /* VCO cal 5 */ 77 #define B2055_VCO_CAL6 0x45 /* VCO cal 6 */ 78 #define B2055_VCO_CAL7 0x46 /* VCO cal 7 */ 79 #define B2055_VCO_CAL8 0x47 /* VCO cal 8 */ 80 #define B2055_VCO_CAL9 0x48 /* VCO cal 9 */ 81 #define B2055_VCO_CAL10 0x49 /* VCO cal 10 */ 82 #define B2055_VCO_CAL11 0x4A /* VCO cal 11 */ 83 #define B2055_VCO_CAL12 0x4B /* VCO cal 12 */ 84 #define B2055_VCO_CAL13 0x4C /* VCO cal 13 */ 85 #define B2055_VCO_CAL14 0x4D /* VCO cal 14 */ 86 #define B2055_VCO_CAL15 0x4E /* VCO cal 15 */ 87 #define B2055_VCO_CAL16 0x4F /* VCO cal 16 */ 88 #define B2055_VCO_KVCO 0x50 /* VCO KVCO */ 89 #define B2055_VCO_CAPTAIL 0x51 /* VCO CAP TAIL */ 90 #define B2055_VCO_IDACVCO 0x52 /* VCO IDAC VCO */ 91 #define B2055_VCO_REG 0x53 /* VCO Regulator */ 92 #define B2055_PLL_RFVTH 0x54 /* PLL RF VTH */ 93 #define B2055_LGBUF_CENBUF 0x55 /* LGBUF CEN BUF */ 94 #define B2055_LGEN_TUNE1 0x56 /* LGEN tune 1 */ 95 #define B2055_LGEN_TUNE2 0x57 /* LGEN tune 2 */ 96 #define B2055_LGEN_IDAC1 0x58 /* LGEN IDAC 1 */ 97 #define B2055_LGEN_IDAC2 0x59 /* LGEN IDAC 2 */ 98 #define B2055_LGEN_BIASC 0x5A /* LGEN BIAS counter */ 99 #define B2055_LGEN_BIASIDAC 0x5B /* LGEN BIAS IDAC */ 100 #define B2055_LGEN_RCAL 0x5C /* LGEN RCAL */ 101 #define B2055_LGEN_DIV 0x5D /* LGEN div */ 102 #define B2055_LGEN_SPARE2 0x5E /* LGEN spare 2 */ 103 #define B2055_C1_LGBUF_ATUNE 0x5F /* Core 1 LGBUF A tune */ 104 #define B2055_C1_LGBUF_GTUNE 0x60 /* Core 1 LGBUF G tune */ 105 #define B2055_C1_LGBUF_DIV 0x61 /* Core 1 LGBUF div */ 106 #define B2055_C1_LGBUF_AIDAC 0x62 /* Core 1 LGBUF A IDAC */ 107 #define B2055_C1_LGBUF_GIDAC 0x63 /* Core 1 LGBUF G IDAC */ 108 #define B2055_C1_LGBUF_IDACFO 0x64 /* Core 1 LGBUF IDAC filter override */ 109 #define B2055_C1_LGBUF_SPARE 0x65 /* Core 1 LGBUF spare */ 110 #define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */ 111 #define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */ 112 #define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */ 113 #define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */ 114 #define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */ 115 #define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */ 116 #define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */ 117 #define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */ 118 #define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */ 119 #define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */ 120 #define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */ 121 #define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */ 122 #define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */ 123 #define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */ 124 #define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */ 125 #define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */ 126 #define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */ 127 #define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */ 128 #define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */ 129 #define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */ 130 #define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */ 131 #define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */ 132 #define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */ 133 #define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */ 134 #define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */ 135 #define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */ 136 #define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */ 137 #define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */ 138 #define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */ 139 #define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */ 140 #define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */ 141 #define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */ 142 #define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */ 143 #define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */ 144 #define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */ 145 #define B2055_C1_TXBB_RCCAL 0x89 /* Core 1 TXBB RC CAL Control */ 146 #define B2055_C1_TXBB_LPF1 0x8A /* Core 1 TXBB LPF 1 */ 147 #define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */ 148 #define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */ 149 #define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */ 150 #define B2055_C2_LGBUF_ATUNE 0x8E /* Core 2 LGBUF A tune */ 151 #define B2055_C2_LGBUF_GTUNE 0x8F /* Core 2 LGBUF G tune */ 152 #define B2055_C2_LGBUF_DIV 0x90 /* Core 2 LGBUF div */ 153 #define B2055_C2_LGBUF_AIDAC 0x91 /* Core 2 LGBUF A IDAC */ 154 #define B2055_C2_LGBUF_GIDAC 0x92 /* Core 2 LGBUF G IDAC */ 155 #define B2055_C2_LGBUF_IDACFO 0x93 /* Core 2 LGBUF IDAC filter override */ 156 #define B2055_C2_LGBUF_SPARE 0x94 /* Core 2 LGBUF spare */ 157 #define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */ 158 #define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */ 159 #define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */ 160 #define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */ 161 #define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */ 162 #define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */ 163 #define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */ 164 #define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */ 165 #define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */ 166 #define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */ 167 #define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */ 168 #define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */ 169 #define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */ 170 #define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */ 171 #define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */ 172 #define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */ 173 #define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */ 174 #define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */ 175 #define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */ 176 #define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */ 177 #define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */ 178 #define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */ 179 #define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */ 180 #define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */ 181 #define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */ 182 #define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */ 183 #define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */ 184 #define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */ 185 #define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */ 186 #define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */ 187 #define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */ 188 #define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */ 189 #define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */ 190 #define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */ 191 #define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */ 192 #define B2055_C2_TXBB_RCCAL 0xB8 /* Core 2 TXBB RC CAL Control */ 193 #define B2055_C2_TXBB_LPF1 0xB9 /* Core 2 TXBB LPF 1 */ 194 #define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */ 195 #define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */ 196 #define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */ 197 #define B2055_PRG_GCHP21 0xBD /* PRG GC HPVGA23 21 */ 198 #define B2055_PRG_GCHP22 0xBE /* PRG GC HPVGA23 22 */ 199 #define B2055_PRG_GCHP23 0xBF /* PRG GC HPVGA23 23 */ 200 #define B2055_PRG_GCHP24 0xC0 /* PRG GC HPVGA23 24 */ 201 #define B2055_PRG_GCHP25 0xC1 /* PRG GC HPVGA23 25 */ 202 #define B2055_PRG_GCHP26 0xC2 /* PRG GC HPVGA23 26 */ 203 #define B2055_PRG_GCHP27 0xC3 /* PRG GC HPVGA23 27 */ 204 #define B2055_PRG_GCHP28 0xC4 /* PRG GC HPVGA23 28 */ 205 #define B2055_PRG_GCHP29 0xC5 /* PRG GC HPVGA23 29 */ 206 #define B2055_PRG_GCHP30 0xC6 /* PRG GC HPVGA23 30 */ 207 #define B2055_C1_LNA_GAINBST 0xCD /* Core 1 LNA GAINBST */ 208 #define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */ 209 #define B2055_C1_GENSPARE2 0xD6 /* Core 1 GEN spare 2 */ 210 #define B2055_C2_LNA_GAINBST 0xD9 /* Core 2 LNA GAINBST */ 211 #define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */ 212 #define B2055_C2_GENSPARE2 0xE2 /* Core 2 GEN spare 2 */ 213 214 struct b43_nphy_channeltab_entry_rev2 { 215 /* The channel number */ 216 u8 channel; 217 /* The channel frequency in MHz */ 218 u16 freq; 219 /* An unknown value */ 220 u16 unk2; 221 /* Radio register values on channelswitch */ 222 u8 radio_pll_ref; 223 u8 radio_rf_pllmod0; 224 u8 radio_rf_pllmod1; 225 u8 radio_vco_captail; 226 u8 radio_vco_cal1; 227 u8 radio_vco_cal2; 228 u8 radio_pll_lfc1; 229 u8 radio_pll_lfr1; 230 u8 radio_pll_lfc2; 231 u8 radio_lgbuf_cenbuf; 232 u8 radio_lgen_tune1; 233 u8 radio_lgen_tune2; 234 u8 radio_c1_lgbuf_atune; 235 u8 radio_c1_lgbuf_gtune; 236 u8 radio_c1_rx_rfr1; 237 u8 radio_c1_tx_pgapadtn; 238 u8 radio_c1_tx_mxbgtrim; 239 u8 radio_c2_lgbuf_atune; 240 u8 radio_c2_lgbuf_gtune; 241 u8 radio_c2_rx_rfr1; 242 u8 radio_c2_tx_pgapadtn; 243 u8 radio_c2_tx_mxbgtrim; 244 /* PHY register values on channelswitch */ 245 struct b43_phy_n_sfo_cfg phy_regs; 246 }; 247 248 /* Upload the default register value table. 249 * If "ghz5" is true, we upload the 5Ghz table. Otherwise the 2.4Ghz 250 * table is uploaded. If "ignore_uploadflag" is true, we upload any value 251 * and ignore the "UPLOAD" flag. */ 252 void b2055_upload_inittab(struct b43_wldev *dev, 253 bool ghz5, bool ignore_uploadflag); 254 255 /* Get the NPHY Channel Switch Table entry for a channel. 256 * Returns NULL on failure to find an entry. */ 257 const struct b43_nphy_channeltab_entry_rev2 * 258 b43_nphy_get_chantabent_rev2(struct b43_wldev *dev, u8 channel); 259 260 #endif /* B43_RADIO_2055_H_ */ 261