1 /* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11n PHY support 5 6 Copyright (c) 2008 Michael Buesch <m@bues.ch> 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING. If not, write to 21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 22 Boston, MA 02110-1301, USA. 23 24 */ 25 26 #include <linux/cordic.h> 27 #include <linux/delay.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 31 #include "b43.h" 32 #include "phy_n.h" 33 #include "tables_nphy.h" 34 #include "radio_2055.h" 35 #include "radio_2056.h" 36 #include "radio_2057.h" 37 #include "main.h" 38 #include "ppr.h" 39 40 struct nphy_txgains { 41 u16 tx_lpf[2]; 42 u16 txgm[2]; 43 u16 pga[2]; 44 u16 pad[2]; 45 u16 ipa[2]; 46 }; 47 48 struct nphy_iqcal_params { 49 u16 tx_lpf; 50 u16 txgm; 51 u16 pga; 52 u16 pad; 53 u16 ipa; 54 u16 cal_gain; 55 u16 ncorr[5]; 56 }; 57 58 struct nphy_iq_est { 59 s32 iq0_prod; 60 u32 i0_pwr; 61 u32 q0_pwr; 62 s32 iq1_prod; 63 u32 i1_pwr; 64 u32 q1_pwr; 65 }; 66 67 enum b43_nphy_rf_sequence { 68 B43_RFSEQ_RX2TX, 69 B43_RFSEQ_TX2RX, 70 B43_RFSEQ_RESET2RX, 71 B43_RFSEQ_UPDATE_GAINH, 72 B43_RFSEQ_UPDATE_GAINL, 73 B43_RFSEQ_UPDATE_GAINU, 74 }; 75 76 enum n_rf_ctl_over_cmd { 77 N_RF_CTL_OVER_CMD_RXRF_PU = 0, 78 N_RF_CTL_OVER_CMD_RX_PU = 1, 79 N_RF_CTL_OVER_CMD_TX_PU = 2, 80 N_RF_CTL_OVER_CMD_RX_GAIN = 3, 81 N_RF_CTL_OVER_CMD_TX_GAIN = 4, 82 }; 83 84 enum n_intc_override { 85 N_INTC_OVERRIDE_OFF = 0, 86 N_INTC_OVERRIDE_TRSW = 1, 87 N_INTC_OVERRIDE_PA = 2, 88 N_INTC_OVERRIDE_EXT_LNA_PU = 3, 89 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4, 90 }; 91 92 enum n_rssi_type { 93 N_RSSI_W1 = 0, 94 N_RSSI_W2, 95 N_RSSI_NB, 96 N_RSSI_IQ, 97 N_RSSI_TSSI_2G, 98 N_RSSI_TSSI_5G, 99 N_RSSI_TBD, 100 }; 101 102 enum n_rail_type { 103 N_RAIL_I = 0, 104 N_RAIL_Q = 1, 105 }; 106 107 static inline bool b43_nphy_ipa(struct b43_wldev *dev) 108 { 109 enum nl80211_band band = b43_current_band(dev->wl); 110 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || 111 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); 112 } 113 114 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */ 115 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) 116 { 117 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> 118 B43_NPHY_RFSEQCA_RXEN_SHIFT; 119 } 120 121 /************************************************** 122 * RF (just without b43_nphy_rf_ctl_intc_override) 123 **************************************************/ 124 125 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 126 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 127 enum b43_nphy_rf_sequence seq) 128 { 129 static const u16 trigger[] = { 130 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, 131 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, 132 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, 133 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, 134 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, 135 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, 136 }; 137 int i; 138 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 139 140 B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); 141 142 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 143 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); 144 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); 145 for (i = 0; i < 200; i++) { 146 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) 147 goto ok; 148 msleep(1); 149 } 150 b43err(dev->wl, "RF sequence status timeout\n"); 151 ok: 152 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 153 } 154 155 static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, 156 u16 value, u8 core, bool off, 157 u8 override_id) 158 { 159 /* TODO */ 160 } 161 162 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ 163 static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, 164 u16 value, u8 core, bool off, 165 u8 override) 166 { 167 struct b43_phy *phy = &dev->phy; 168 const struct nphy_rf_control_override_rev7 *e; 169 u16 en_addrs[3][2] = { 170 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } 171 }; 172 u16 en_addr; 173 u16 en_mask = field; 174 u16 val_addr; 175 u8 i; 176 177 if (phy->rev >= 19 || phy->rev < 3) { 178 B43_WARN_ON(1); 179 return; 180 } 181 182 /* Remember: we can get NULL! */ 183 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); 184 185 for (i = 0; i < 2; i++) { 186 if (override >= ARRAY_SIZE(en_addrs)) { 187 b43err(dev->wl, "Invalid override value %d\n", override); 188 return; 189 } 190 en_addr = en_addrs[override][i]; 191 192 if (e) 193 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; 194 195 if (off) { 196 b43_phy_mask(dev, en_addr, ~en_mask); 197 if (e) /* Do it safer, better than wl */ 198 b43_phy_mask(dev, val_addr, ~e->val_mask); 199 } else { 200 if (!core || (core & (1 << i))) { 201 b43_phy_set(dev, en_addr, en_mask); 202 if (e) 203 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); 204 } 205 } 206 } 207 } 208 209 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ 210 static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, 211 enum n_rf_ctl_over_cmd cmd, 212 u16 value, u8 core, bool off) 213 { 214 struct b43_phy *phy = &dev->phy; 215 u16 tmp; 216 217 B43_WARN_ON(phy->rev < 7); 218 219 switch (cmd) { 220 case N_RF_CTL_OVER_CMD_RXRF_PU: 221 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); 222 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); 223 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); 224 break; 225 case N_RF_CTL_OVER_CMD_RX_PU: 226 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); 227 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 228 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); 229 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); 230 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); 231 break; 232 case N_RF_CTL_OVER_CMD_TX_PU: 233 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); 234 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 235 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); 236 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); 237 break; 238 case N_RF_CTL_OVER_CMD_RX_GAIN: 239 tmp = value & 0xFF; 240 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); 241 tmp = value >> 8; 242 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); 243 break; 244 case N_RF_CTL_OVER_CMD_TX_GAIN: 245 tmp = value & 0x7FFF; 246 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); 247 tmp = value >> 14; 248 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); 249 break; 250 } 251 } 252 253 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 254 static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, 255 u16 value, u8 core, bool off) 256 { 257 int i; 258 u8 index = fls(field); 259 u8 addr, en_addr, val_addr; 260 /* we expect only one bit set */ 261 B43_WARN_ON(field & (~(1 << (index - 1)))); 262 263 if (dev->phy.rev >= 3) { 264 const struct nphy_rf_control_override_rev3 *rf_ctrl; 265 for (i = 0; i < 2; i++) { 266 if (index == 0 || index == 16) { 267 b43err(dev->wl, 268 "Unsupported RF Ctrl Override call\n"); 269 return; 270 } 271 272 rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; 273 en_addr = B43_PHY_N((i == 0) ? 274 rf_ctrl->en_addr0 : rf_ctrl->en_addr1); 275 val_addr = B43_PHY_N((i == 0) ? 276 rf_ctrl->val_addr0 : rf_ctrl->val_addr1); 277 278 if (off) { 279 b43_phy_mask(dev, en_addr, ~(field)); 280 b43_phy_mask(dev, val_addr, 281 ~(rf_ctrl->val_mask)); 282 } else { 283 if (core == 0 || ((1 << i) & core)) { 284 b43_phy_set(dev, en_addr, field); 285 b43_phy_maskset(dev, val_addr, 286 ~(rf_ctrl->val_mask), 287 (value << rf_ctrl->val_shift)); 288 } 289 } 290 } 291 } else { 292 const struct nphy_rf_control_override_rev2 *rf_ctrl; 293 if (off) { 294 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); 295 value = 0; 296 } else { 297 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); 298 } 299 300 for (i = 0; i < 2; i++) { 301 if (index <= 1 || index == 16) { 302 b43err(dev->wl, 303 "Unsupported RF Ctrl Override call\n"); 304 return; 305 } 306 307 if (index == 2 || index == 10 || 308 (index >= 13 && index <= 15)) { 309 core = 1; 310 } 311 312 rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; 313 addr = B43_PHY_N((i == 0) ? 314 rf_ctrl->addr0 : rf_ctrl->addr1); 315 316 if ((1 << i) & core) 317 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), 318 (value << rf_ctrl->shift)); 319 320 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 321 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 322 B43_NPHY_RFCTL_CMD_START); 323 udelay(1); 324 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); 325 } 326 } 327 } 328 329 static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, 330 enum n_intc_override intc_override, 331 u16 value, u8 core_sel) 332 { 333 u16 reg, tmp, tmp2, val; 334 int core; 335 336 /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */ 337 338 for (core = 0; core < 2; core++) { 339 if ((core_sel == 1 && core != 0) || 340 (core_sel == 2 && core != 1)) 341 continue; 342 343 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 344 345 switch (intc_override) { 346 case N_INTC_OVERRIDE_OFF: 347 b43_phy_write(dev, reg, 0); 348 b43_phy_mask(dev, 0x2ff, ~0x2000); 349 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 350 break; 351 case N_INTC_OVERRIDE_TRSW: 352 b43_phy_maskset(dev, reg, ~0xC0, value << 6); 353 b43_phy_set(dev, reg, 0x400); 354 355 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); 356 b43_phy_set(dev, 0x2ff, 0x2000); 357 b43_phy_set(dev, 0x2ff, 0x0001); 358 break; 359 case N_INTC_OVERRIDE_PA: 360 tmp = 0x0030; 361 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 362 val = value << 5; 363 else 364 val = value << 4; 365 b43_phy_maskset(dev, reg, ~tmp, val); 366 b43_phy_set(dev, reg, 0x1000); 367 break; 368 case N_INTC_OVERRIDE_EXT_LNA_PU: 369 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 370 tmp = 0x0001; 371 tmp2 = 0x0004; 372 val = value; 373 } else { 374 tmp = 0x0004; 375 tmp2 = 0x0001; 376 val = value << 2; 377 } 378 b43_phy_maskset(dev, reg, ~tmp, val); 379 b43_phy_mask(dev, reg, ~tmp2); 380 break; 381 case N_INTC_OVERRIDE_EXT_LNA_GAIN: 382 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 383 tmp = 0x0002; 384 tmp2 = 0x0008; 385 val = value << 1; 386 } else { 387 tmp = 0x0008; 388 tmp2 = 0x0002; 389 val = value << 3; 390 } 391 b43_phy_maskset(dev, reg, ~tmp, val); 392 b43_phy_mask(dev, reg, ~tmp2); 393 break; 394 } 395 } 396 } 397 398 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 399 static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, 400 enum n_intc_override intc_override, 401 u16 value, u8 core) 402 { 403 u8 i, j; 404 u16 reg, tmp, val; 405 406 if (dev->phy.rev >= 7) { 407 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, 408 core); 409 return; 410 } 411 412 B43_WARN_ON(dev->phy.rev < 3); 413 414 for (i = 0; i < 2; i++) { 415 if ((core == 1 && i == 1) || (core == 2 && !i)) 416 continue; 417 418 reg = (i == 0) ? 419 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 420 b43_phy_set(dev, reg, 0x400); 421 422 switch (intc_override) { 423 case N_INTC_OVERRIDE_OFF: 424 b43_phy_write(dev, reg, 0); 425 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 426 break; 427 case N_INTC_OVERRIDE_TRSW: 428 if (!i) { 429 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 430 0xFC3F, (value << 6)); 431 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, 432 0xFFFE, 1); 433 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 434 B43_NPHY_RFCTL_CMD_START); 435 for (j = 0; j < 100; j++) { 436 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { 437 j = 0; 438 break; 439 } 440 udelay(10); 441 } 442 if (j) 443 b43err(dev->wl, 444 "intc override timeout\n"); 445 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, 446 0xFFFE); 447 } else { 448 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, 449 0xFC3F, (value << 6)); 450 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 451 0xFFFE, 1); 452 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 453 B43_NPHY_RFCTL_CMD_RXTX); 454 for (j = 0; j < 100; j++) { 455 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { 456 j = 0; 457 break; 458 } 459 udelay(10); 460 } 461 if (j) 462 b43err(dev->wl, 463 "intc override timeout\n"); 464 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 465 0xFFFE); 466 } 467 break; 468 case N_INTC_OVERRIDE_PA: 469 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 470 tmp = 0x0020; 471 val = value << 5; 472 } else { 473 tmp = 0x0010; 474 val = value << 4; 475 } 476 b43_phy_maskset(dev, reg, ~tmp, val); 477 break; 478 case N_INTC_OVERRIDE_EXT_LNA_PU: 479 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 480 tmp = 0x0001; 481 val = value; 482 } else { 483 tmp = 0x0004; 484 val = value << 2; 485 } 486 b43_phy_maskset(dev, reg, ~tmp, val); 487 break; 488 case N_INTC_OVERRIDE_EXT_LNA_GAIN: 489 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 490 tmp = 0x0002; 491 val = value << 1; 492 } else { 493 tmp = 0x0008; 494 val = value << 3; 495 } 496 b43_phy_maskset(dev, reg, ~tmp, val); 497 break; 498 } 499 } 500 } 501 502 /************************************************** 503 * Various PHY ops 504 **************************************************/ 505 506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 507 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, 508 const u16 *clip_st) 509 { 510 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); 511 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); 512 } 513 514 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 515 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 516 { 517 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); 518 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); 519 } 520 521 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ 522 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) 523 { 524 u16 tmp; 525 526 if (dev->dev->core_rev == 16) 527 b43_mac_suspend(dev); 528 529 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 530 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | 531 B43_NPHY_CLASSCTL_WAITEDEN); 532 tmp &= ~mask; 533 tmp |= (val & mask); 534 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 535 536 if (dev->dev->core_rev == 16) 537 b43_mac_enable(dev); 538 539 return tmp; 540 } 541 542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 543 static void b43_nphy_reset_cca(struct b43_wldev *dev) 544 { 545 u16 bbcfg; 546 547 b43_phy_force_clock(dev, 1); 548 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); 549 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); 550 udelay(1); 551 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); 552 b43_phy_force_clock(dev, 0); 553 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 554 } 555 556 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ 557 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) 558 { 559 struct b43_phy *phy = &dev->phy; 560 struct b43_phy_n *nphy = phy->n; 561 562 if (enable) { 563 static const u16 clip[] = { 0xFFFF, 0xFFFF }; 564 if (nphy->deaf_count++ == 0) { 565 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); 566 b43_nphy_classifier(dev, 0x7, 567 B43_NPHY_CLASSCTL_WAITEDEN); 568 b43_nphy_read_clip_detection(dev, nphy->clip_state); 569 b43_nphy_write_clip_detection(dev, clip); 570 } 571 b43_nphy_reset_cca(dev); 572 } else { 573 if (--nphy->deaf_count == 0) { 574 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); 575 b43_nphy_write_clip_detection(dev, nphy->clip_state); 576 } 577 } 578 } 579 580 /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ 581 static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) 582 { 583 if (!offset) 584 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; 585 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; 586 } 587 588 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ 589 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) 590 { 591 struct b43_phy_n *nphy = dev->phy.n; 592 593 u8 i; 594 s16 tmp; 595 u16 data[4]; 596 s16 gain[2]; 597 u16 minmax[2]; 598 static const u16 lna_gain[4] = { -2, 10, 19, 25 }; 599 600 if (nphy->hang_avoid) 601 b43_nphy_stay_in_carrier_search(dev, 1); 602 603 if (nphy->gain_boost) { 604 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 605 gain[0] = 6; 606 gain[1] = 6; 607 } else { 608 tmp = 40370 - 315 * dev->phy.channel; 609 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); 610 tmp = 23242 - 224 * dev->phy.channel; 611 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); 612 } 613 } else { 614 gain[0] = 0; 615 gain[1] = 0; 616 } 617 618 for (i = 0; i < 2; i++) { 619 if (nphy->elna_gain_config) { 620 data[0] = 19 + gain[i]; 621 data[1] = 25 + gain[i]; 622 data[2] = 25 + gain[i]; 623 data[3] = 25 + gain[i]; 624 } else { 625 data[0] = lna_gain[0] + gain[i]; 626 data[1] = lna_gain[1] + gain[i]; 627 data[2] = lna_gain[2] + gain[i]; 628 data[3] = lna_gain[3] + gain[i]; 629 } 630 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); 631 632 minmax[i] = 23 + gain[i]; 633 } 634 635 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, 636 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); 637 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, 638 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); 639 640 if (nphy->hang_avoid) 641 b43_nphy_stay_in_carrier_search(dev, 0); 642 } 643 644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ 645 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 646 u8 *events, u8 *delays, u8 length) 647 { 648 struct b43_phy_n *nphy = dev->phy.n; 649 u8 i; 650 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; 651 u16 offset1 = cmd << 4; 652 u16 offset2 = offset1 + 0x80; 653 654 if (nphy->hang_avoid) 655 b43_nphy_stay_in_carrier_search(dev, true); 656 657 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); 658 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); 659 660 for (i = length; i < 16; i++) { 661 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); 662 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); 663 } 664 665 if (nphy->hang_avoid) 666 b43_nphy_stay_in_carrier_search(dev, false); 667 } 668 669 /************************************************** 670 * Radio 0x2057 671 **************************************************/ 672 673 static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, 674 const struct b43_nphy_chantabent_rev7 *e_r7, 675 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g) 676 { 677 if (e_r7_2g) { 678 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); 679 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); 680 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize); 681 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); 682 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); 683 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); 684 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); 685 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); 686 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); 687 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); 688 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); 689 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); 690 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0); 691 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); 692 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); 693 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1); 694 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); 695 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); 696 697 } else { 698 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); 699 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); 700 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize); 701 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); 702 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); 703 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); 704 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); 705 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); 706 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); 707 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); 708 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); 709 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); 710 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); 711 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); 712 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); 713 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); 714 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); 715 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); 716 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); 717 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); 718 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); 719 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); 720 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); 721 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); 722 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); 723 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); 724 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); 725 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); 726 } 727 } 728 729 static void b43_radio_2057_setup(struct b43_wldev *dev, 730 const struct b43_nphy_chantabent_rev7 *tabent_r7, 731 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g) 732 { 733 struct b43_phy *phy = &dev->phy; 734 735 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); 736 737 switch (phy->radio_rev) { 738 case 0 ... 4: 739 case 6: 740 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 741 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); 742 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 743 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); 744 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); 745 } else { 746 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); 747 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 748 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); 749 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); 750 } 751 break; 752 case 9: /* e.g. PHY rev 16 */ 753 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); 754 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); 755 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 756 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); 757 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); 758 759 if (b43_is_40mhz(dev)) { 760 /* TODO */ 761 } else { 762 b43_radio_write(dev, 763 R2057_PAD_BIAS_FILTER_BWS_CORE0, 764 0x3c); 765 b43_radio_write(dev, 766 R2057_PAD_BIAS_FILTER_BWS_CORE1, 767 0x3c); 768 } 769 } 770 break; 771 case 14: /* 2 GHz only */ 772 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); 773 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 774 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); 775 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); 776 break; 777 } 778 779 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 780 u16 txmix2g_tune_boost_pu = 0; 781 u16 pad2g_tune_pus = 0; 782 783 if (b43_nphy_ipa(dev)) { 784 switch (phy->radio_rev) { 785 case 9: 786 txmix2g_tune_boost_pu = 0x0041; 787 /* TODO */ 788 break; 789 case 14: 790 txmix2g_tune_boost_pu = 0x21; 791 pad2g_tune_pus = 0x23; 792 break; 793 } 794 } 795 796 if (txmix2g_tune_boost_pu) 797 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 798 txmix2g_tune_boost_pu); 799 if (pad2g_tune_pus) 800 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, 801 pad2g_tune_pus); 802 if (txmix2g_tune_boost_pu) 803 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, 804 txmix2g_tune_boost_pu); 805 if (pad2g_tune_pus) 806 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, 807 pad2g_tune_pus); 808 } 809 810 usleep_range(50, 100); 811 812 /* VCO calibration */ 813 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); 814 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); 815 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); 816 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); 817 usleep_range(300, 600); 818 } 819 820 /* Calibrate resistors in LPF of PLL? 821 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal 822 */ 823 static u8 b43_radio_2057_rcal(struct b43_wldev *dev) 824 { 825 struct b43_phy *phy = &dev->phy; 826 u16 saved_regs_phy[12]; 827 u16 saved_regs_phy_rf[6]; 828 u16 saved_regs_radio[2] = { }; 829 static const u16 phy_to_store[] = { 830 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2, 831 B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2, 832 B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2, 833 B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2, 834 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, 835 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, 836 }; 837 static const u16 phy_to_store_rf[] = { 838 B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1, 839 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, 840 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, 841 }; 842 u16 tmp; 843 int i; 844 845 /* Save */ 846 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 847 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); 848 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) 849 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); 850 851 /* Set */ 852 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 853 b43_phy_write(dev, phy_to_store[i], 0); 854 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); 855 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); 856 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); 857 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); 858 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); 859 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); 860 861 switch (phy->radio_rev) { 862 case 5: 863 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); 864 udelay(10); 865 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); 866 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); 867 break; 868 case 9: 869 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); 870 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); 871 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); 872 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); 873 break; 874 case 14: 875 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); 876 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); 877 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); 878 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); 879 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); 880 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); 881 break; 882 } 883 884 /* Enable */ 885 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); 886 udelay(10); 887 888 /* Start */ 889 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); 890 usleep_range(100, 200); 891 892 /* Stop */ 893 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); 894 895 /* Wait and check for result */ 896 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { 897 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); 898 return 0; 899 } 900 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; 901 902 /* Disable */ 903 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); 904 905 /* Restore */ 906 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) 907 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); 908 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 909 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); 910 911 switch (phy->radio_rev) { 912 case 0 ... 4: 913 case 6: 914 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); 915 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, 916 tmp << 2); 917 break; 918 case 5: 919 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); 920 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); 921 break; 922 case 9: 923 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); 924 break; 925 case 14: 926 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); 927 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); 928 break; 929 } 930 931 return tmp & 0x3e; 932 } 933 934 /* Calibrate the internal RC oscillator? 935 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal 936 */ 937 static u16 b43_radio_2057_rccal(struct b43_wldev *dev) 938 { 939 struct b43_phy *phy = &dev->phy; 940 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 || 941 phy->radio_rev == 6); 942 u16 tmp; 943 944 /* Setup cal */ 945 if (special) { 946 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); 947 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); 948 } else { 949 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); 950 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); 951 } 952 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 953 954 /* Start, wait, stop */ 955 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 956 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 957 5000000)) 958 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); 959 usleep_range(35, 70); 960 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 961 usleep_range(70, 140); 962 963 /* Setup cal */ 964 if (special) { 965 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); 966 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); 967 } else { 968 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); 969 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); 970 } 971 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 972 973 /* Start, wait, stop */ 974 usleep_range(35, 70); 975 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 976 usleep_range(70, 140); 977 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 978 5000000)) 979 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); 980 usleep_range(35, 70); 981 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 982 usleep_range(70, 140); 983 984 /* Setup cal */ 985 if (special) { 986 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); 987 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); 988 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); 989 } else { 990 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); 991 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 992 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); 993 } 994 995 /* Start, wait, stop */ 996 usleep_range(35, 70); 997 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 998 usleep_range(70, 140); 999 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 1000 5000000)) { 1001 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); 1002 return 0; 1003 } 1004 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); 1005 usleep_range(35, 70); 1006 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 1007 usleep_range(70, 140); 1008 1009 if (special) 1010 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); 1011 else 1012 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); 1013 1014 return tmp; 1015 } 1016 1017 static void b43_radio_2057_init_pre(struct b43_wldev *dev) 1018 { 1019 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); 1020 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ 1021 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); 1022 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); 1023 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); 1024 } 1025 1026 static void b43_radio_2057_init_post(struct b43_wldev *dev) 1027 { 1028 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); 1029 1030 if (0) /* FIXME: Is this BCM43217 specific? */ 1031 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); 1032 1033 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); 1034 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); 1035 usleep_range(2000, 3000); 1036 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); 1037 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); 1038 1039 if (dev->phy.do_full_init) { 1040 b43_radio_2057_rcal(dev); 1041 b43_radio_2057_rccal(dev); 1042 } 1043 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); 1044 } 1045 1046 /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */ 1047 static void b43_radio_2057_init(struct b43_wldev *dev) 1048 { 1049 b43_radio_2057_init_pre(dev); 1050 r2057_upload_inittabs(dev); 1051 b43_radio_2057_init_post(dev); 1052 } 1053 1054 /************************************************** 1055 * Radio 0x2056 1056 **************************************************/ 1057 1058 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, 1059 const struct b43_nphy_channeltab_entry_rev3 *e) 1060 { 1061 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); 1062 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); 1063 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); 1064 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); 1065 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); 1066 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 1067 e->radio_syn_pll_loopfilter1); 1068 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 1069 e->radio_syn_pll_loopfilter2); 1070 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, 1071 e->radio_syn_pll_loopfilter3); 1072 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 1073 e->radio_syn_pll_loopfilter4); 1074 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, 1075 e->radio_syn_pll_loopfilter5); 1076 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, 1077 e->radio_syn_reserved_addr27); 1078 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, 1079 e->radio_syn_reserved_addr28); 1080 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, 1081 e->radio_syn_reserved_addr29); 1082 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, 1083 e->radio_syn_logen_vcobuf1); 1084 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); 1085 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); 1086 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); 1087 1088 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, 1089 e->radio_rx0_lnaa_tune); 1090 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, 1091 e->radio_rx0_lnag_tune); 1092 1093 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, 1094 e->radio_tx0_intpaa_boost_tune); 1095 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, 1096 e->radio_tx0_intpag_boost_tune); 1097 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, 1098 e->radio_tx0_pada_boost_tune); 1099 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, 1100 e->radio_tx0_padg_boost_tune); 1101 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, 1102 e->radio_tx0_pgaa_boost_tune); 1103 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, 1104 e->radio_tx0_pgag_boost_tune); 1105 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, 1106 e->radio_tx0_mixa_boost_tune); 1107 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, 1108 e->radio_tx0_mixg_boost_tune); 1109 1110 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, 1111 e->radio_rx1_lnaa_tune); 1112 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, 1113 e->radio_rx1_lnag_tune); 1114 1115 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, 1116 e->radio_tx1_intpaa_boost_tune); 1117 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, 1118 e->radio_tx1_intpag_boost_tune); 1119 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, 1120 e->radio_tx1_pada_boost_tune); 1121 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, 1122 e->radio_tx1_padg_boost_tune); 1123 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, 1124 e->radio_tx1_pgaa_boost_tune); 1125 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, 1126 e->radio_tx1_pgag_boost_tune); 1127 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, 1128 e->radio_tx1_mixa_boost_tune); 1129 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, 1130 e->radio_tx1_mixg_boost_tune); 1131 } 1132 1133 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */ 1134 static void b43_radio_2056_setup(struct b43_wldev *dev, 1135 const struct b43_nphy_channeltab_entry_rev3 *e) 1136 { 1137 struct b43_phy *phy = &dev->phy; 1138 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1139 enum nl80211_band band = b43_current_band(dev->wl); 1140 u16 offset; 1141 u8 i; 1142 u16 bias, cbias; 1143 u16 pag_boost, padg_boost, pgag_boost, mixg_boost; 1144 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost; 1145 bool is_pkg_fab_smic; 1146 1147 B43_WARN_ON(dev->phy.rev < 3); 1148 1149 is_pkg_fab_smic = 1150 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || 1151 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || 1152 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && 1153 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); 1154 1155 b43_chantab_radio_2056_upload(dev, e); 1156 b2056_upload_syn_pll_cp2(dev, band == NL80211_BAND_5GHZ); 1157 1158 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && 1159 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); 1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); 1162 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || 1163 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { 1164 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); 1165 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); 1166 } else { 1167 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); 1168 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); 1169 } 1170 } 1171 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 && 1172 b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 1173 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); 1174 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); 1175 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); 1176 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); 1177 } 1178 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR && 1179 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 1180 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); 1181 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); 1182 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); 1183 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); 1184 } 1185 1186 if (dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) { 1187 for (i = 0; i < 2; i++) { 1188 offset = i ? B2056_TX1 : B2056_TX0; 1189 if (dev->phy.rev >= 5) { 1190 b43_radio_write(dev, 1191 offset | B2056_TX_PADG_IDAC, 0xcc); 1192 1193 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || 1194 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { 1195 bias = 0x40; 1196 cbias = 0x45; 1197 pag_boost = 0x5; 1198 pgag_boost = 0x33; 1199 mixg_boost = 0x55; 1200 } else { 1201 bias = 0x25; 1202 cbias = 0x20; 1203 if (is_pkg_fab_smic) { 1204 bias = 0x2a; 1205 cbias = 0x38; 1206 } 1207 pag_boost = 0x4; 1208 pgag_boost = 0x03; 1209 mixg_boost = 0x65; 1210 } 1211 padg_boost = 0x77; 1212 1213 b43_radio_write(dev, 1214 offset | B2056_TX_INTPAG_IMAIN_STAT, 1215 bias); 1216 b43_radio_write(dev, 1217 offset | B2056_TX_INTPAG_IAUX_STAT, 1218 bias); 1219 b43_radio_write(dev, 1220 offset | B2056_TX_INTPAG_CASCBIAS, 1221 cbias); 1222 b43_radio_write(dev, 1223 offset | B2056_TX_INTPAG_BOOST_TUNE, 1224 pag_boost); 1225 b43_radio_write(dev, 1226 offset | B2056_TX_PGAG_BOOST_TUNE, 1227 pgag_boost); 1228 b43_radio_write(dev, 1229 offset | B2056_TX_PADG_BOOST_TUNE, 1230 padg_boost); 1231 b43_radio_write(dev, 1232 offset | B2056_TX_MIXG_BOOST_TUNE, 1233 mixg_boost); 1234 } else { 1235 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; 1236 b43_radio_write(dev, 1237 offset | B2056_TX_INTPAG_IMAIN_STAT, 1238 bias); 1239 b43_radio_write(dev, 1240 offset | B2056_TX_INTPAG_IAUX_STAT, 1241 bias); 1242 b43_radio_write(dev, 1243 offset | B2056_TX_INTPAG_CASCBIAS, 1244 0x30); 1245 } 1246 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); 1247 } 1248 } else if (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ) { 1249 u16 freq = phy->chandef->chan->center_freq; 1250 if (freq < 5100) { 1251 paa_boost = 0xA; 1252 pada_boost = 0x77; 1253 pgaa_boost = 0xF; 1254 mixa_boost = 0xF; 1255 } else if (freq < 5340) { 1256 paa_boost = 0x8; 1257 pada_boost = 0x77; 1258 pgaa_boost = 0xFB; 1259 mixa_boost = 0xF; 1260 } else if (freq < 5650) { 1261 paa_boost = 0x0; 1262 pada_boost = 0x77; 1263 pgaa_boost = 0xB; 1264 mixa_boost = 0xF; 1265 } else { 1266 paa_boost = 0x0; 1267 pada_boost = 0x77; 1268 if (freq != 5825) 1269 pgaa_boost = -(freq - 18) / 36 + 168; 1270 else 1271 pgaa_boost = 6; 1272 mixa_boost = 0xF; 1273 } 1274 1275 cbias = is_pkg_fab_smic ? 0x35 : 0x30; 1276 1277 for (i = 0; i < 2; i++) { 1278 offset = i ? B2056_TX1 : B2056_TX0; 1279 1280 b43_radio_write(dev, 1281 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost); 1282 b43_radio_write(dev, 1283 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost); 1284 b43_radio_write(dev, 1285 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost); 1286 b43_radio_write(dev, 1287 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost); 1288 b43_radio_write(dev, 1289 offset | B2056_TX_TXSPARE1, 0x30); 1290 b43_radio_write(dev, 1291 offset | B2056_TX_PA_SPARE2, 0xee); 1292 b43_radio_write(dev, 1293 offset | B2056_TX_PADA_CASCBIAS, 0x03); 1294 b43_radio_write(dev, 1295 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); 1296 b43_radio_write(dev, 1297 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); 1298 b43_radio_write(dev, 1299 offset | B2056_TX_INTPAA_CASCBIAS, cbias); 1300 } 1301 } 1302 1303 udelay(50); 1304 /* VCO calibration */ 1305 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); 1306 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); 1307 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); 1308 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); 1309 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); 1310 udelay(300); 1311 } 1312 1313 static u8 b43_radio_2056_rcal(struct b43_wldev *dev) 1314 { 1315 struct b43_phy *phy = &dev->phy; 1316 u16 mast2, tmp; 1317 1318 if (phy->rev != 3) 1319 return 0; 1320 1321 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); 1322 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); 1323 1324 udelay(10); 1325 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); 1326 udelay(10); 1327 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); 1328 1329 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, 1330 1000000)) { 1331 b43err(dev->wl, "Radio recalibration timeout\n"); 1332 return 0; 1333 } 1334 1335 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); 1336 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); 1337 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); 1338 1339 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); 1340 1341 return tmp & 0x1f; 1342 } 1343 1344 static void b43_radio_init2056_pre(struct b43_wldev *dev) 1345 { 1346 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1347 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 1348 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ 1349 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1350 B43_NPHY_RFCTL_CMD_OEPORFORCE); 1351 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1352 ~B43_NPHY_RFCTL_CMD_OEPORFORCE); 1353 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1354 B43_NPHY_RFCTL_CMD_CHIP0PU); 1355 } 1356 1357 static void b43_radio_init2056_post(struct b43_wldev *dev) 1358 { 1359 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); 1360 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); 1361 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); 1362 msleep(1); 1363 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); 1364 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); 1365 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); 1366 if (dev->phy.do_full_init) 1367 b43_radio_2056_rcal(dev); 1368 } 1369 1370 /* 1371 * Initialize a Broadcom 2056 N-radio 1372 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init 1373 */ 1374 static void b43_radio_init2056(struct b43_wldev *dev) 1375 { 1376 b43_radio_init2056_pre(dev); 1377 b2056_upload_inittabs(dev, 0, 0); 1378 b43_radio_init2056_post(dev); 1379 } 1380 1381 /************************************************** 1382 * Radio 0x2055 1383 **************************************************/ 1384 1385 static void b43_chantab_radio_upload(struct b43_wldev *dev, 1386 const struct b43_nphy_channeltab_entry_rev2 *e) 1387 { 1388 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); 1389 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); 1390 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); 1391 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); 1392 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1393 1394 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); 1395 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); 1396 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); 1397 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); 1398 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1399 1400 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); 1401 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); 1402 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); 1403 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); 1404 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1405 1406 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); 1407 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); 1408 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); 1409 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); 1410 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1411 1412 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); 1413 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); 1414 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); 1415 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); 1416 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1417 1418 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); 1419 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); 1420 } 1421 1422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ 1423 static void b43_radio_2055_setup(struct b43_wldev *dev, 1424 const struct b43_nphy_channeltab_entry_rev2 *e) 1425 { 1426 B43_WARN_ON(dev->phy.rev >= 3); 1427 1428 b43_chantab_radio_upload(dev, e); 1429 udelay(50); 1430 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); 1431 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); 1432 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1433 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); 1434 udelay(300); 1435 } 1436 1437 static void b43_radio_init2055_pre(struct b43_wldev *dev) 1438 { 1439 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1440 ~B43_NPHY_RFCTL_CMD_PORFORCE); 1441 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1442 B43_NPHY_RFCTL_CMD_CHIP0PU | 1443 B43_NPHY_RFCTL_CMD_OEPORFORCE); 1444 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1445 B43_NPHY_RFCTL_CMD_PORFORCE); 1446 } 1447 1448 static void b43_radio_init2055_post(struct b43_wldev *dev) 1449 { 1450 struct b43_phy_n *nphy = dev->phy.n; 1451 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1452 bool workaround = false; 1453 1454 if (sprom->revision < 4) 1455 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM 1456 && dev->dev->board_type == SSB_BOARD_CB2_4321 1457 && dev->dev->board_rev >= 0x41); 1458 else 1459 workaround = 1460 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS); 1461 1462 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 1463 if (workaround) { 1464 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); 1465 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); 1466 } 1467 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); 1468 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); 1469 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); 1470 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); 1471 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 1472 msleep(1); 1473 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 1474 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) 1475 b43err(dev->wl, "radio post init timeout\n"); 1476 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 1477 b43_switch_channel(dev, dev->phy.channel); 1478 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); 1479 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); 1480 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 1481 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); 1482 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); 1483 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); 1484 if (!nphy->gain_boost) { 1485 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); 1486 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); 1487 } else { 1488 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); 1489 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); 1490 } 1491 udelay(2); 1492 } 1493 1494 /* 1495 * Initialize a Broadcom 2055 N-radio 1496 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init 1497 */ 1498 static void b43_radio_init2055(struct b43_wldev *dev) 1499 { 1500 b43_radio_init2055_pre(dev); 1501 if (b43_status(dev) < B43_STAT_INITIALIZED) { 1502 /* Follow wl, not specs. Do not force uploading all regs */ 1503 b2055_upload_inittab(dev, 0, 0); 1504 } else { 1505 bool ghz5 = b43_current_band(dev->wl) == NL80211_BAND_5GHZ; 1506 b2055_upload_inittab(dev, ghz5, 0); 1507 } 1508 b43_radio_init2055_post(dev); 1509 } 1510 1511 /************************************************** 1512 * Samples 1513 **************************************************/ 1514 1515 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ 1516 static int b43_nphy_load_samples(struct b43_wldev *dev, 1517 struct cordic_iq *samples, u16 len) { 1518 struct b43_phy_n *nphy = dev->phy.n; 1519 u16 i; 1520 u32 *data; 1521 1522 data = kcalloc(len, sizeof(u32), GFP_KERNEL); 1523 if (!data) { 1524 b43err(dev->wl, "allocation for samples loading failed\n"); 1525 return -ENOMEM; 1526 } 1527 if (nphy->hang_avoid) 1528 b43_nphy_stay_in_carrier_search(dev, 1); 1529 1530 for (i = 0; i < len; i++) { 1531 data[i] = (samples[i].i & 0x3FF << 10); 1532 data[i] |= samples[i].q & 0x3FF; 1533 } 1534 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); 1535 1536 kfree(data); 1537 if (nphy->hang_avoid) 1538 b43_nphy_stay_in_carrier_search(dev, 0); 1539 return 0; 1540 } 1541 1542 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ 1543 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, 1544 bool test) 1545 { 1546 int i; 1547 u16 bw, len, rot, angle; 1548 struct cordic_iq *samples; 1549 1550 bw = b43_is_40mhz(dev) ? 40 : 20; 1551 len = bw << 3; 1552 1553 if (test) { 1554 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) 1555 bw = 82; 1556 else 1557 bw = 80; 1558 1559 if (b43_is_40mhz(dev)) 1560 bw <<= 1; 1561 1562 len = bw << 1; 1563 } 1564 1565 samples = kcalloc(len, sizeof(struct cordic_iq), GFP_KERNEL); 1566 if (!samples) { 1567 b43err(dev->wl, "allocation for samples generation failed\n"); 1568 return 0; 1569 } 1570 rot = (((freq * 36) / bw) << 16) / 100; 1571 angle = 0; 1572 1573 for (i = 0; i < len; i++) { 1574 samples[i] = cordic_calc_iq(CORDIC_FIXED(angle)); 1575 angle += rot; 1576 samples[i].q = CORDIC_FLOAT(samples[i].q * max); 1577 samples[i].i = CORDIC_FLOAT(samples[i].i * max); 1578 } 1579 1580 i = b43_nphy_load_samples(dev, samples, len); 1581 kfree(samples); 1582 return (i < 0) ? 0 : len; 1583 } 1584 1585 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ 1586 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, 1587 u16 wait, bool iqmode, bool dac_test, 1588 bool modify_bbmult) 1589 { 1590 struct b43_phy *phy = &dev->phy; 1591 struct b43_phy_n *nphy = dev->phy.n; 1592 int i; 1593 u16 seq_mode; 1594 u32 tmp; 1595 1596 b43_nphy_stay_in_carrier_search(dev, true); 1597 1598 if (phy->rev >= 7) { 1599 bool lpf_bw3, lpf_bw4; 1600 1601 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; 1602 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; 1603 1604 if (lpf_bw3 || lpf_bw4) { 1605 /* TODO */ 1606 } else { 1607 u16 value = b43_nphy_read_lpf_ctl(dev, 0); 1608 if (phy->rev >= 19) 1609 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, 1610 0, false, 1); 1611 else 1612 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, 1613 0, false, 1); 1614 nphy->lpf_bw_overrode_for_sample_play = true; 1615 } 1616 } 1617 1618 if ((nphy->bb_mult_save & 0x80000000) == 0) { 1619 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); 1620 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; 1621 } 1622 1623 if (modify_bbmult) { 1624 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; 1625 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 1626 } 1627 1628 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); 1629 1630 if (loops != 0xFFFF) 1631 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); 1632 else 1633 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); 1634 1635 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); 1636 1637 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1638 1639 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); 1640 if (iqmode) { 1641 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 1642 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); 1643 } else { 1644 tmp = dac_test ? 5 : 1; 1645 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); 1646 } 1647 for (i = 0; i < 100; i++) { 1648 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { 1649 i = 0; 1650 break; 1651 } 1652 udelay(10); 1653 } 1654 if (i) 1655 b43err(dev->wl, "run samples timeout\n"); 1656 1657 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1658 1659 b43_nphy_stay_in_carrier_search(dev, false); 1660 } 1661 1662 /************************************************** 1663 * RSSI 1664 **************************************************/ 1665 1666 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1667 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1668 s8 offset, u8 core, 1669 enum n_rail_type rail, 1670 enum n_rssi_type rssi_type) 1671 { 1672 u16 tmp; 1673 bool core1or5 = (core == 1) || (core == 5); 1674 bool core2or5 = (core == 2) || (core == 5); 1675 1676 offset = clamp_val(offset, -32, 31); 1677 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1678 1679 switch (rssi_type) { 1680 case N_RSSI_NB: 1681 if (core1or5 && rail == N_RAIL_I) 1682 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1683 if (core1or5 && rail == N_RAIL_Q) 1684 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1685 if (core2or5 && rail == N_RAIL_I) 1686 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1687 if (core2or5 && rail == N_RAIL_Q) 1688 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1689 break; 1690 case N_RSSI_W1: 1691 if (core1or5 && rail == N_RAIL_I) 1692 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1693 if (core1or5 && rail == N_RAIL_Q) 1694 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1695 if (core2or5 && rail == N_RAIL_I) 1696 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1697 if (core2or5 && rail == N_RAIL_Q) 1698 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1699 break; 1700 case N_RSSI_W2: 1701 if (core1or5 && rail == N_RAIL_I) 1702 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1703 if (core1or5 && rail == N_RAIL_Q) 1704 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1705 if (core2or5 && rail == N_RAIL_I) 1706 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1707 if (core2or5 && rail == N_RAIL_Q) 1708 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1709 break; 1710 case N_RSSI_TBD: 1711 if (core1or5 && rail == N_RAIL_I) 1712 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1713 if (core1or5 && rail == N_RAIL_Q) 1714 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1715 if (core2or5 && rail == N_RAIL_I) 1716 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1717 if (core2or5 && rail == N_RAIL_Q) 1718 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1719 break; 1720 case N_RSSI_IQ: 1721 if (core1or5 && rail == N_RAIL_I) 1722 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1723 if (core1or5 && rail == N_RAIL_Q) 1724 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1725 if (core2or5 && rail == N_RAIL_I) 1726 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1727 if (core2or5 && rail == N_RAIL_Q) 1728 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1729 break; 1730 case N_RSSI_TSSI_2G: 1731 if (core1or5) 1732 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1733 if (core2or5) 1734 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1735 break; 1736 case N_RSSI_TSSI_5G: 1737 if (core1or5) 1738 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1739 if (core2or5) 1740 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1741 break; 1742 } 1743 } 1744 1745 static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, 1746 enum n_rssi_type rssi_type) 1747 { 1748 /* TODO */ 1749 } 1750 1751 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, 1752 enum n_rssi_type rssi_type) 1753 { 1754 u8 i; 1755 u16 reg, val; 1756 1757 if (code == 0) { 1758 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); 1759 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); 1760 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); 1761 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); 1762 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); 1763 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); 1764 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); 1765 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); 1766 } else { 1767 for (i = 0; i < 2; i++) { 1768 if ((code == 1 && i == 1) || (code == 2 && !i)) 1769 continue; 1770 1771 reg = (i == 0) ? 1772 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1773 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1774 1775 if (rssi_type == N_RSSI_W1 || 1776 rssi_type == N_RSSI_W2 || 1777 rssi_type == N_RSSI_NB) { 1778 reg = (i == 0) ? 1779 B43_NPHY_AFECTL_C1 : 1780 B43_NPHY_AFECTL_C2; 1781 b43_phy_maskset(dev, reg, 0xFCFF, 0); 1782 1783 reg = (i == 0) ? 1784 B43_NPHY_RFCTL_LUT_TRSW_UP1 : 1785 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1786 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1787 1788 if (rssi_type == N_RSSI_W1) 1789 val = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 4 : 8; 1790 else if (rssi_type == N_RSSI_W2) 1791 val = 16; 1792 else 1793 val = 32; 1794 b43_phy_set(dev, reg, val); 1795 1796 reg = (i == 0) ? 1797 B43_NPHY_TXF_40CO_B1S0 : 1798 B43_NPHY_TXF_40CO_B32S1; 1799 b43_phy_set(dev, reg, 0x0020); 1800 } else { 1801 if (rssi_type == N_RSSI_TBD) 1802 val = 0x0100; 1803 else if (rssi_type == N_RSSI_IQ) 1804 val = 0x0200; 1805 else 1806 val = 0x0300; 1807 1808 reg = (i == 0) ? 1809 B43_NPHY_AFECTL_C1 : 1810 B43_NPHY_AFECTL_C2; 1811 1812 b43_phy_maskset(dev, reg, 0xFCFF, val); 1813 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1814 1815 if (rssi_type != N_RSSI_IQ && 1816 rssi_type != N_RSSI_TBD) { 1817 enum nl80211_band band = 1818 b43_current_band(dev->wl); 1819 1820 if (dev->phy.rev < 7) { 1821 if (b43_nphy_ipa(dev)) 1822 val = (band == NL80211_BAND_5GHZ) ? 0xC : 0xE; 1823 else 1824 val = 0x11; 1825 reg = (i == 0) ? B2056_TX0 : B2056_TX1; 1826 reg |= B2056_TX_TX_SSI_MUX; 1827 b43_radio_write(dev, reg, val); 1828 } 1829 1830 reg = (i == 0) ? 1831 B43_NPHY_AFECTL_OVER1 : 1832 B43_NPHY_AFECTL_OVER; 1833 b43_phy_set(dev, reg, 0x0200); 1834 } 1835 } 1836 } 1837 } 1838 } 1839 1840 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, 1841 enum n_rssi_type rssi_type) 1842 { 1843 u16 val; 1844 bool rssi_w1_w2_nb = false; 1845 1846 switch (rssi_type) { 1847 case N_RSSI_W1: 1848 case N_RSSI_W2: 1849 case N_RSSI_NB: 1850 val = 0; 1851 rssi_w1_w2_nb = true; 1852 break; 1853 case N_RSSI_TBD: 1854 val = 1; 1855 break; 1856 case N_RSSI_IQ: 1857 val = 2; 1858 break; 1859 default: 1860 val = 3; 1861 } 1862 1863 val = (val << 12) | (val << 14); 1864 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1865 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1866 1867 if (rssi_w1_w2_nb) { 1868 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1869 (rssi_type + 1) << 4); 1870 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1871 (rssi_type + 1) << 4); 1872 } 1873 1874 if (code == 0) { 1875 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); 1876 if (rssi_w1_w2_nb) { 1877 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1878 ~(B43_NPHY_RFCTL_CMD_RXEN | 1879 B43_NPHY_RFCTL_CMD_CORESEL)); 1880 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1881 ~(0x1 << 12 | 1882 0x1 << 5 | 1883 0x1 << 1 | 1884 0x1)); 1885 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1886 ~B43_NPHY_RFCTL_CMD_START); 1887 udelay(20); 1888 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1889 } 1890 } else { 1891 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); 1892 if (rssi_w1_w2_nb) { 1893 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1894 ~(B43_NPHY_RFCTL_CMD_RXEN | 1895 B43_NPHY_RFCTL_CMD_CORESEL), 1896 (B43_NPHY_RFCTL_CMD_RXEN | 1897 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT)); 1898 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 1899 (0x1 << 12 | 1900 0x1 << 5 | 1901 0x1 << 1 | 1902 0x1)); 1903 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1904 B43_NPHY_RFCTL_CMD_START); 1905 udelay(20); 1906 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1907 } 1908 } 1909 } 1910 1911 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1912 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, 1913 enum n_rssi_type type) 1914 { 1915 if (dev->phy.rev >= 19) 1916 b43_nphy_rssi_select_rev19(dev, code, type); 1917 else if (dev->phy.rev >= 3) 1918 b43_nphy_rev3_rssi_select(dev, code, type); 1919 else 1920 b43_nphy_rev2_rssi_select(dev, code, type); 1921 } 1922 1923 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1924 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, 1925 enum n_rssi_type rssi_type, u8 *buf) 1926 { 1927 int i; 1928 for (i = 0; i < 2; i++) { 1929 if (rssi_type == N_RSSI_NB) { 1930 if (i == 0) { 1931 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1932 0xFC, buf[0]); 1933 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1934 0xFC, buf[1]); 1935 } else { 1936 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, 1937 0xFC, buf[2 * i]); 1938 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1939 0xFC, buf[2 * i + 1]); 1940 } 1941 } else { 1942 if (i == 0) 1943 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1944 0xF3, buf[0] << 2); 1945 else 1946 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1947 0xF3, buf[2 * i + 1] << 2); 1948 } 1949 } 1950 } 1951 1952 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1953 static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, 1954 s32 *buf, u8 nsamp) 1955 { 1956 int i; 1957 int out; 1958 u16 save_regs_phy[9]; 1959 u16 s[2]; 1960 1961 /* TODO: rev7+ is treated like rev3+, what about rev19+? */ 1962 1963 if (dev->phy.rev >= 3) { 1964 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1965 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1966 save_regs_phy[2] = b43_phy_read(dev, 1967 B43_NPHY_RFCTL_LUT_TRSW_UP1); 1968 save_regs_phy[3] = b43_phy_read(dev, 1969 B43_NPHY_RFCTL_LUT_TRSW_UP2); 1970 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 1971 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1972 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); 1973 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); 1974 save_regs_phy[8] = 0; 1975 } else { 1976 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1977 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1978 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1979 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); 1980 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 1981 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 1982 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 1983 save_regs_phy[7] = 0; 1984 save_regs_phy[8] = 0; 1985 } 1986 1987 b43_nphy_rssi_select(dev, 5, rssi_type); 1988 1989 if (dev->phy.rev < 2) { 1990 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1991 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); 1992 } 1993 1994 for (i = 0; i < 4; i++) 1995 buf[i] = 0; 1996 1997 for (i = 0; i < nsamp; i++) { 1998 if (dev->phy.rev < 2) { 1999 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); 2000 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); 2001 } else { 2002 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); 2003 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); 2004 } 2005 2006 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; 2007 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; 2008 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; 2009 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; 2010 } 2011 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | 2012 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); 2013 2014 if (dev->phy.rev < 2) 2015 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 2016 2017 if (dev->phy.rev >= 3) { 2018 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); 2019 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); 2020 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 2021 save_regs_phy[2]); 2022 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2023 save_regs_phy[3]); 2024 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); 2025 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); 2026 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); 2027 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); 2028 } else { 2029 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); 2030 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); 2031 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); 2032 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); 2033 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); 2034 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); 2035 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); 2036 } 2037 2038 return out; 2039 } 2040 2041 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ 2042 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) 2043 { 2044 struct b43_phy *phy = &dev->phy; 2045 struct b43_phy_n *nphy = dev->phy.n; 2046 2047 u16 saved_regs_phy_rfctl[2]; 2048 u16 saved_regs_phy[22]; 2049 u16 regs_to_store_rev3[] = { 2050 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, 2051 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, 2052 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, 2053 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, 2054 B43_NPHY_RFCTL_CMD, 2055 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2056 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 2057 }; 2058 u16 regs_to_store_rev7[] = { 2059 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, 2060 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, 2061 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, 2062 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, 2063 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, 2064 0x2ff, 2065 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, 2066 B43_NPHY_RFCTL_CMD, 2067 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2068 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, 2069 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, 2070 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 2071 }; 2072 u16 *regs_to_store; 2073 int regs_amount; 2074 2075 u16 class; 2076 2077 u16 clip_state[2]; 2078 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 2079 2080 u8 vcm_final = 0; 2081 s32 offset[4]; 2082 s32 results[8][4] = { }; 2083 s32 results_min[4] = { }; 2084 s32 poll_results[4] = { }; 2085 2086 u16 *rssical_radio_regs = NULL; 2087 u16 *rssical_phy_regs = NULL; 2088 2089 u16 r; /* routing */ 2090 u8 rx_core_state; 2091 int core, i, j, vcm; 2092 2093 if (dev->phy.rev >= 7) { 2094 regs_to_store = regs_to_store_rev7; 2095 regs_amount = ARRAY_SIZE(regs_to_store_rev7); 2096 } else { 2097 regs_to_store = regs_to_store_rev3; 2098 regs_amount = ARRAY_SIZE(regs_to_store_rev3); 2099 } 2100 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy)); 2101 2102 class = b43_nphy_classifier(dev, 0, 0); 2103 b43_nphy_classifier(dev, 7, 4); 2104 b43_nphy_read_clip_detection(dev, clip_state); 2105 b43_nphy_write_clip_detection(dev, clip_off); 2106 2107 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2108 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2109 for (i = 0; i < regs_amount; i++) 2110 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); 2111 2112 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); 2113 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); 2114 2115 if (dev->phy.rev >= 7) { 2116 b43_nphy_rf_ctl_override_one_to_many(dev, 2117 N_RF_CTL_OVER_CMD_RXRF_PU, 2118 0, 0, false); 2119 b43_nphy_rf_ctl_override_one_to_many(dev, 2120 N_RF_CTL_OVER_CMD_RX_PU, 2121 1, 0, false); 2122 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); 2123 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); 2124 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 2125 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, 2126 0); 2127 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, 2128 0); 2129 } else { 2130 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, 2131 0); 2132 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, 2133 0); 2134 } 2135 } else { 2136 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); 2137 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); 2138 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); 2139 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); 2140 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 2141 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); 2142 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); 2143 } else { 2144 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); 2145 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); 2146 } 2147 } 2148 2149 rx_core_state = b43_nphy_get_rx_core_state(dev); 2150 for (core = 0; core < 2; core++) { 2151 if (!(rx_core_state & (1 << core))) 2152 continue; 2153 r = core ? B2056_RX1 : B2056_RX0; 2154 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, 2155 N_RSSI_NB); 2156 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, 2157 N_RSSI_NB); 2158 2159 /* Grab RSSI results for every possible VCM */ 2160 for (vcm = 0; vcm < 8; vcm++) { 2161 if (dev->phy.rev >= 7) 2162 b43_radio_maskset(dev, 2163 core ? R2057_NB_MASTER_CORE1 : 2164 R2057_NB_MASTER_CORE0, 2165 ~R2057_VCM_MASK, vcm); 2166 else 2167 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2168 0xE3, vcm << 2); 2169 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); 2170 } 2171 2172 /* Find out which VCM got the best results */ 2173 for (i = 0; i < 4; i += 2) { 2174 s32 currd; 2175 s32 mind = 0x100000; 2176 s32 minpoll = 249; 2177 u8 minvcm = 0; 2178 if (2 * core != i) 2179 continue; 2180 for (vcm = 0; vcm < 8; vcm++) { 2181 currd = results[vcm][i] * results[vcm][i] + 2182 results[vcm][i + 1] * results[vcm][i]; 2183 if (currd < mind) { 2184 mind = currd; 2185 minvcm = vcm; 2186 } 2187 if (results[vcm][i] < minpoll) 2188 minpoll = results[vcm][i]; 2189 } 2190 vcm_final = minvcm; 2191 results_min[i] = minpoll; 2192 } 2193 2194 /* Select the best VCM */ 2195 if (dev->phy.rev >= 7) 2196 b43_radio_maskset(dev, 2197 core ? R2057_NB_MASTER_CORE1 : 2198 R2057_NB_MASTER_CORE0, 2199 ~R2057_VCM_MASK, vcm); 2200 else 2201 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2202 0xE3, vcm_final << 2); 2203 2204 for (i = 0; i < 4; i++) { 2205 if (core != i / 2) 2206 continue; 2207 offset[i] = -results[vcm_final][i]; 2208 if (offset[i] < 0) 2209 offset[i] = -((abs(offset[i]) + 4) / 8); 2210 else 2211 offset[i] = (offset[i] + 4) / 8; 2212 if (results_min[i] == 248) 2213 offset[i] = -32; 2214 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2215 (i / 2 == 0) ? 1 : 2, 2216 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, 2217 N_RSSI_NB); 2218 } 2219 } 2220 2221 for (core = 0; core < 2; core++) { 2222 if (!(rx_core_state & (1 << core))) 2223 continue; 2224 for (i = 0; i < 2; i++) { 2225 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 2226 N_RAIL_I, i); 2227 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 2228 N_RAIL_Q, i); 2229 b43_nphy_poll_rssi(dev, i, poll_results, 8); 2230 for (j = 0; j < 4; j++) { 2231 if (j / 2 == core) { 2232 offset[j] = 232 - poll_results[j]; 2233 if (offset[j] < 0) 2234 offset[j] = -(abs(offset[j] + 4) / 8); 2235 else 2236 offset[j] = (offset[j] + 4) / 8; 2237 b43_nphy_scale_offset_rssi(dev, 0, 2238 offset[2 * core], core + 1, j % 2, i); 2239 } 2240 } 2241 } 2242 } 2243 2244 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); 2245 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); 2246 2247 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 2248 2249 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); 2250 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); 2251 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); 2252 2253 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 2254 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); 2255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 2256 2257 for (i = 0; i < regs_amount; i++) 2258 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); 2259 2260 /* Store for future configuration */ 2261 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 2262 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 2263 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 2264 } else { 2265 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 2266 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2267 } 2268 if (dev->phy.rev >= 7) { 2269 rssical_radio_regs[0] = b43_radio_read(dev, 2270 R2057_NB_MASTER_CORE0); 2271 rssical_radio_regs[1] = b43_radio_read(dev, 2272 R2057_NB_MASTER_CORE1); 2273 } else { 2274 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | 2275 B2056_RX_RSSI_MISC); 2276 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | 2277 B2056_RX_RSSI_MISC); 2278 } 2279 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); 2280 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); 2281 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); 2282 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); 2283 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); 2284 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); 2285 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); 2286 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); 2287 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); 2288 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); 2289 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); 2290 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); 2291 2292 /* Remember for which channel we store configuration */ 2293 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 2294 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq; 2295 else 2296 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq; 2297 2298 /* End of calibration, restore configuration */ 2299 b43_nphy_classifier(dev, 7, class); 2300 b43_nphy_write_clip_detection(dev, clip_state); 2301 } 2302 2303 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 2304 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) 2305 { 2306 int i, j, vcm; 2307 u8 state[4]; 2308 u8 code, val; 2309 u16 class, override; 2310 u8 regs_save_radio[2]; 2311 u16 regs_save_phy[2]; 2312 2313 s32 offset[4]; 2314 u8 core; 2315 u8 rail; 2316 2317 u16 clip_state[2]; 2318 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 2319 s32 results_min[4] = { }; 2320 u8 vcm_final[4] = { }; 2321 s32 results[4][4] = { }; 2322 s32 miniq[4][2] = { }; 2323 2324 if (type == N_RSSI_NB) { 2325 code = 0; 2326 val = 6; 2327 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) { 2328 code = 25; 2329 val = 4; 2330 } else { 2331 B43_WARN_ON(1); 2332 return; 2333 } 2334 2335 class = b43_nphy_classifier(dev, 0, 0); 2336 b43_nphy_classifier(dev, 7, 4); 2337 b43_nphy_read_clip_detection(dev, clip_state); 2338 b43_nphy_write_clip_detection(dev, clip_off); 2339 2340 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 2341 override = 0x140; 2342 else 2343 override = 0x110; 2344 2345 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2346 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); 2347 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 2348 b43_radio_write(dev, B2055_C1_PD_RXTX, val); 2349 2350 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2351 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); 2352 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 2353 b43_radio_write(dev, B2055_C2_PD_RXTX, val); 2354 2355 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; 2356 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; 2357 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 2358 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 2359 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; 2360 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; 2361 2362 b43_nphy_rssi_select(dev, 5, type); 2363 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); 2364 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); 2365 2366 for (vcm = 0; vcm < 4; vcm++) { 2367 u8 tmp[4]; 2368 for (j = 0; j < 4; j++) 2369 tmp[j] = vcm; 2370 if (type != N_RSSI_W2) 2371 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 2372 b43_nphy_poll_rssi(dev, type, results[vcm], 8); 2373 if (type == N_RSSI_W1 || type == N_RSSI_W2) 2374 for (j = 0; j < 2; j++) 2375 miniq[vcm][j] = min(results[vcm][2 * j], 2376 results[vcm][2 * j + 1]); 2377 } 2378 2379 for (i = 0; i < 4; i++) { 2380 s32 mind = 0x100000; 2381 u8 minvcm = 0; 2382 s32 minpoll = 249; 2383 s32 currd; 2384 for (vcm = 0; vcm < 4; vcm++) { 2385 if (type == N_RSSI_NB) 2386 currd = abs(results[vcm][i] - code * 8); 2387 else 2388 currd = abs(miniq[vcm][i / 2] - code * 8); 2389 2390 if (currd < mind) { 2391 mind = currd; 2392 minvcm = vcm; 2393 } 2394 2395 if (results[vcm][i] < minpoll) 2396 minpoll = results[vcm][i]; 2397 } 2398 results_min[i] = minpoll; 2399 vcm_final[i] = minvcm; 2400 } 2401 2402 if (type != N_RSSI_W2) 2403 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 2404 2405 for (i = 0; i < 4; i++) { 2406 offset[i] = (code * 8) - results[vcm_final[i]][i]; 2407 2408 if (offset[i] < 0) 2409 offset[i] = -((abs(offset[i]) + 4) / 8); 2410 else 2411 offset[i] = (offset[i] + 4) / 8; 2412 2413 if (results_min[i] == 248) 2414 offset[i] = code - 32; 2415 2416 core = (i / 2) ? 2 : 1; 2417 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I; 2418 2419 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, 2420 type); 2421 } 2422 2423 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); 2424 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); 2425 2426 switch (state[2]) { 2427 case 1: 2428 b43_nphy_rssi_select(dev, 1, N_RSSI_NB); 2429 break; 2430 case 4: 2431 b43_nphy_rssi_select(dev, 1, N_RSSI_W1); 2432 break; 2433 case 2: 2434 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); 2435 break; 2436 default: 2437 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); 2438 break; 2439 } 2440 2441 switch (state[3]) { 2442 case 1: 2443 b43_nphy_rssi_select(dev, 2, N_RSSI_NB); 2444 break; 2445 case 4: 2446 b43_nphy_rssi_select(dev, 2, N_RSSI_W1); 2447 break; 2448 default: 2449 b43_nphy_rssi_select(dev, 2, N_RSSI_W2); 2450 break; 2451 } 2452 2453 b43_nphy_rssi_select(dev, 0, type); 2454 2455 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 2456 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 2457 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 2458 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 2459 2460 b43_nphy_classifier(dev, 7, class); 2461 b43_nphy_write_clip_detection(dev, clip_state); 2462 /* Specs don't say about reset here, but it makes wl and b43 dumps 2463 identical, it really seems wl performs this */ 2464 b43_nphy_reset_cca(dev); 2465 } 2466 2467 /* 2468 * RSSI Calibration 2469 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal 2470 */ 2471 static void b43_nphy_rssi_cal(struct b43_wldev *dev) 2472 { 2473 if (dev->phy.rev >= 19) { 2474 /* TODO */ 2475 } else if (dev->phy.rev >= 3) { 2476 b43_nphy_rev3_rssi_cal(dev); 2477 } else { 2478 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); 2479 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); 2480 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); 2481 } 2482 } 2483 2484 /************************************************** 2485 * Workarounds 2486 **************************************************/ 2487 2488 static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) 2489 { 2490 /* TODO */ 2491 } 2492 2493 static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) 2494 { 2495 struct b43_phy *phy = &dev->phy; 2496 2497 switch (phy->rev) { 2498 /* TODO */ 2499 } 2500 } 2501 2502 static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) 2503 { 2504 struct ssb_sprom *sprom = dev->dev->bus_sprom; 2505 2506 bool ghz5; 2507 bool ext_lna; 2508 u16 rssi_gain; 2509 struct nphy_gain_ctl_workaround_entry *e; 2510 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; 2511 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; 2512 2513 /* Prepare values */ 2514 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) 2515 & B43_NPHY_BANDCTL_5GHZ; 2516 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ : 2517 sprom->boardflags_lo & B43_BFL_EXTLNA; 2518 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); 2519 if (ghz5 && dev->phy.rev >= 5) 2520 rssi_gain = 0x90; 2521 else 2522 rssi_gain = 0x50; 2523 2524 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); 2525 2526 /* Set Clip 2 detect */ 2527 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); 2528 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); 2529 2530 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 2531 0x17); 2532 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, 2533 0x17); 2534 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); 2535 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); 2536 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); 2537 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); 2538 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, 2539 rssi_gain); 2540 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, 2541 rssi_gain); 2542 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, 2543 0x17); 2544 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, 2545 0x17); 2546 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); 2547 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); 2548 2549 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); 2550 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); 2551 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); 2552 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); 2553 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); 2554 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); 2555 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); 2556 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); 2557 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); 2558 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); 2559 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); 2560 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); 2561 2562 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); 2563 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); 2564 2565 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, 2566 e->rfseq_init); 2567 2568 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); 2569 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); 2570 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); 2571 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); 2572 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); 2573 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); 2574 2575 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); 2576 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); 2577 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); 2578 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); 2579 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); 2580 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2581 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip); 2582 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 2583 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip); 2584 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 2585 } 2586 2587 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) 2588 { 2589 struct b43_phy_n *nphy = dev->phy.n; 2590 2591 u8 i, j; 2592 u8 code; 2593 u16 tmp; 2594 u8 rfseq_events[3] = { 6, 8, 7 }; 2595 u8 rfseq_delays[3] = { 10, 30, 1 }; 2596 2597 /* Set Clip 2 detect */ 2598 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); 2599 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); 2600 2601 /* Set narrowband clip threshold */ 2602 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 2603 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 2604 2605 if (!b43_is_40mhz(dev)) { 2606 /* Set dwell lengths */ 2607 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 2608 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 2609 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); 2610 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); 2611 } 2612 2613 /* Set wideband clip 2 threshold */ 2614 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2615 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21); 2616 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 2617 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21); 2618 2619 if (!b43_is_40mhz(dev)) { 2620 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 2621 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 2622 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 2623 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); 2624 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, 2625 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); 2626 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, 2627 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); 2628 } 2629 2630 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 2631 2632 if (nphy->gain_boost) { 2633 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ && 2634 b43_is_40mhz(dev)) 2635 code = 4; 2636 else 2637 code = 5; 2638 } else { 2639 code = b43_is_40mhz(dev) ? 6 : 7; 2640 } 2641 2642 /* Set HPVGA2 index */ 2643 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, 2644 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); 2645 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, 2646 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); 2647 2648 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 2649 /* specs say about 2 loops, but wl does 4 */ 2650 for (i = 0; i < 4; i++) 2651 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); 2652 2653 b43_nphy_adjust_lna_gain_table(dev); 2654 2655 if (nphy->elna_gain_config) { 2656 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); 2657 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 2658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2659 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2660 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2661 2662 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); 2663 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 2664 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2665 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2666 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2667 2668 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 2669 /* specs say about 2 loops, but wl does 4 */ 2670 for (i = 0; i < 4; i++) 2671 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 2672 (code << 8 | 0x74)); 2673 } 2674 2675 if (dev->phy.rev == 2) { 2676 for (i = 0; i < 4; i++) { 2677 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 2678 (0x0400 * i) + 0x0020); 2679 for (j = 0; j < 21; j++) { 2680 tmp = j * (i < 2 ? 3 : 1); 2681 b43_phy_write(dev, 2682 B43_NPHY_TABLE_DATALO, tmp); 2683 } 2684 } 2685 } 2686 2687 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); 2688 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, 2689 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 2690 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); 2691 2692 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 2693 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); 2694 } 2695 2696 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 2697 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) 2698 { 2699 if (dev->phy.rev >= 19) 2700 b43_nphy_gain_ctl_workarounds_rev19(dev); 2701 else if (dev->phy.rev >= 7) 2702 b43_nphy_gain_ctl_workarounds_rev7(dev); 2703 else if (dev->phy.rev >= 3) 2704 b43_nphy_gain_ctl_workarounds_rev3(dev); 2705 else 2706 b43_nphy_gain_ctl_workarounds_rev1_2(dev); 2707 } 2708 2709 static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) 2710 { 2711 struct ssb_sprom *sprom = dev->dev->bus_sprom; 2712 struct b43_phy *phy = &dev->phy; 2713 2714 /* TX to RX */ 2715 u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, }; 2716 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, }; 2717 /* RX to TX */ 2718 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 2719 0x1F }; 2720 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; 2721 2722 static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; 2723 u8 ntab7_138_146[] = { 0x11, 0x11 }; 2724 u8 ntab7_133[] = { 0x77, 0x11, 0x11 }; 2725 2726 u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2]; 2727 u16 bcap_val; 2728 s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2]; 2729 u16 scap_val; 2730 s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2]; 2731 bool rccal_ovrd = false; 2732 2733 u16 bias, conv, filt; 2734 2735 u32 noise_tbl[2]; 2736 2737 u32 tmp32; 2738 u8 core; 2739 2740 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); 2741 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); 2742 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); 2743 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); 2744 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); 2745 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 2746 2747 if (phy->rev == 7) { 2748 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); 2749 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); 2750 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); 2751 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); 2752 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); 2753 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); 2754 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); 2755 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); 2756 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); 2757 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); 2758 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); 2759 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); 2760 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); 2761 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); 2762 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); 2763 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); 2764 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2765 } 2766 2767 if (phy->rev >= 16) { 2768 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); 2769 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); 2770 } else if (phy->rev <= 8) { 2771 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); 2772 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); 2773 } 2774 2775 if (phy->rev >= 16) 2776 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); 2777 else if (phy->rev >= 8) 2778 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2779 2780 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); 2781 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); 2782 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2783 tmp32 &= 0xffffff; 2784 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); 2785 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); 2786 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); 2787 2788 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 2789 ARRAY_SIZE(tx2rx_events)); 2790 if (b43_nphy_ipa(dev)) 2791 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2792 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2793 2794 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); 2795 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); 2796 2797 for (core = 0; core < 2; core++) { 2798 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); 2799 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); 2800 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); 2801 } 2802 2803 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); 2804 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); 2805 2806 if (b43_nphy_ipa(dev)) { 2807 bool ghz2 = b43_current_band(dev->wl) == NL80211_BAND_2GHZ; 2808 2809 switch (phy->radio_rev) { 2810 case 5: 2811 /* Check radio version (to be 0) by PHY rev for now */ 2812 if (phy->rev == 8 && b43_is_40mhz(dev)) { 2813 for (core = 0; core < 2; core++) { 2814 scap_val_11b[core] = scap_val; 2815 bcap_val_11b[core] = bcap_val; 2816 scap_val_11n_20[core] = scap_val; 2817 bcap_val_11n_20[core] = bcap_val; 2818 scap_val_11n_40[core] = 0xc; 2819 bcap_val_11n_40[core] = 0xc; 2820 } 2821 2822 rccal_ovrd = true; 2823 } 2824 if (phy->rev == 9) { 2825 /* TODO: Radio version 1 (e.g. BCM5357B0) */ 2826 } 2827 break; 2828 case 7: 2829 case 8: 2830 for (core = 0; core < 2; core++) { 2831 scap_val_11b[core] = scap_val; 2832 bcap_val_11b[core] = bcap_val; 2833 lpf_ofdm_20mhz[core] = 4; 2834 lpf_11b[core] = 1; 2835 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 2836 scap_val_11n_20[core] = 0xc; 2837 bcap_val_11n_20[core] = 0xc; 2838 scap_val_11n_40[core] = 0xa; 2839 bcap_val_11n_40[core] = 0xa; 2840 } else { 2841 scap_val_11n_20[core] = 0x14; 2842 bcap_val_11n_20[core] = 0x14; 2843 scap_val_11n_40[core] = 0xf; 2844 bcap_val_11n_40[core] = 0xf; 2845 } 2846 } 2847 2848 rccal_ovrd = true; 2849 break; 2850 case 9: 2851 for (core = 0; core < 2; core++) { 2852 bcap_val_11b[core] = bcap_val; 2853 scap_val_11b[core] = scap_val; 2854 lpf_11b[core] = 1; 2855 2856 if (ghz2) { 2857 bcap_val_11n_20[core] = bcap_val + 13; 2858 scap_val_11n_20[core] = scap_val + 15; 2859 } else { 2860 bcap_val_11n_20[core] = bcap_val + 14; 2861 scap_val_11n_20[core] = scap_val + 15; 2862 } 2863 lpf_ofdm_20mhz[core] = 4; 2864 2865 if (ghz2) { 2866 bcap_val_11n_40[core] = bcap_val - 7; 2867 scap_val_11n_40[core] = scap_val - 5; 2868 } else { 2869 bcap_val_11n_40[core] = bcap_val + 2; 2870 scap_val_11n_40[core] = scap_val + 4; 2871 } 2872 lpf_ofdm_40mhz[core] = 4; 2873 } 2874 2875 rccal_ovrd = true; 2876 break; 2877 case 14: 2878 for (core = 0; core < 2; core++) { 2879 bcap_val_11b[core] = bcap_val; 2880 scap_val_11b[core] = scap_val; 2881 lpf_11b[core] = 1; 2882 } 2883 2884 bcap_val_11n_20[0] = bcap_val + 20; 2885 scap_val_11n_20[0] = scap_val + 20; 2886 lpf_ofdm_20mhz[0] = 3; 2887 2888 bcap_val_11n_20[1] = bcap_val + 16; 2889 scap_val_11n_20[1] = scap_val + 16; 2890 lpf_ofdm_20mhz[1] = 3; 2891 2892 bcap_val_11n_40[0] = bcap_val + 20; 2893 scap_val_11n_40[0] = scap_val + 20; 2894 lpf_ofdm_40mhz[0] = 4; 2895 2896 bcap_val_11n_40[1] = bcap_val + 10; 2897 scap_val_11n_40[1] = scap_val + 10; 2898 lpf_ofdm_40mhz[1] = 4; 2899 2900 rccal_ovrd = true; 2901 break; 2902 } 2903 } else { 2904 if (phy->radio_rev == 5) { 2905 for (core = 0; core < 2; core++) { 2906 lpf_ofdm_20mhz[core] = 1; 2907 lpf_ofdm_40mhz[core] = 3; 2908 scap_val_11b[core] = scap_val; 2909 bcap_val_11b[core] = bcap_val; 2910 scap_val_11n_20[core] = 0x11; 2911 scap_val_11n_40[core] = 0x11; 2912 bcap_val_11n_20[core] = 0x13; 2913 bcap_val_11n_40[core] = 0x13; 2914 } 2915 2916 rccal_ovrd = true; 2917 } 2918 } 2919 if (rccal_ovrd) { 2920 u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2]; 2921 u8 rx2tx_lut_extra = 1; 2922 2923 for (core = 0; core < 2; core++) { 2924 bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f); 2925 scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f); 2926 bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f); 2927 scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f); 2928 bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f); 2929 scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f); 2930 2931 rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) | 2932 (bcap_val_11b[core] << 8) | 2933 (scap_val_11b[core] << 3) | 2934 lpf_11b[core]; 2935 rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) | 2936 (bcap_val_11n_20[core] << 8) | 2937 (scap_val_11n_20[core] << 3) | 2938 lpf_ofdm_20mhz[core]; 2939 rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) | 2940 (bcap_val_11n_40[core] << 8) | 2941 (scap_val_11n_40[core] << 3) | 2942 lpf_ofdm_40mhz[core]; 2943 } 2944 2945 for (core = 0; core < 2; core++) { 2946 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), 2947 rx2tx_lut_20_11b[core]); 2948 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), 2949 rx2tx_lut_20_11n[core]); 2950 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), 2951 rx2tx_lut_20_11n[core]); 2952 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), 2953 rx2tx_lut_40_11n[core]); 2954 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), 2955 rx2tx_lut_40_11n[core]); 2956 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), 2957 rx2tx_lut_40_11n[core]); 2958 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), 2959 rx2tx_lut_40_11n[core]); 2960 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), 2961 rx2tx_lut_40_11n[core]); 2962 } 2963 } 2964 2965 b43_phy_write(dev, 0x32F, 0x3); 2966 2967 if (phy->radio_rev == 4 || phy->radio_rev == 6) 2968 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); 2969 2970 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { 2971 if (sprom->revision && 2972 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) { 2973 b43_radio_write(dev, 0x5, 0x05); 2974 b43_radio_write(dev, 0x6, 0x30); 2975 b43_radio_write(dev, 0x7, 0x00); 2976 b43_radio_set(dev, 0x4f, 0x1); 2977 b43_radio_set(dev, 0xd4, 0x1); 2978 bias = 0x1f; 2979 conv = 0x6f; 2980 filt = 0xaa; 2981 } else { 2982 bias = 0x2b; 2983 conv = 0x7f; 2984 filt = 0xee; 2985 } 2986 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 2987 for (core = 0; core < 2; core++) { 2988 if (core == 0) { 2989 b43_radio_write(dev, 0x5F, bias); 2990 b43_radio_write(dev, 0x64, conv); 2991 b43_radio_write(dev, 0x66, filt); 2992 } else { 2993 b43_radio_write(dev, 0xE8, bias); 2994 b43_radio_write(dev, 0xE9, conv); 2995 b43_radio_write(dev, 0xEB, filt); 2996 } 2997 } 2998 } 2999 } 3000 3001 if (b43_nphy_ipa(dev)) { 3002 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 3003 if (phy->radio_rev == 3 || phy->radio_rev == 4 || 3004 phy->radio_rev == 6) { 3005 for (core = 0; core < 2; core++) { 3006 if (core == 0) 3007 b43_radio_write(dev, 0x51, 3008 0x7f); 3009 else 3010 b43_radio_write(dev, 0xd6, 3011 0x7f); 3012 } 3013 } 3014 switch (phy->radio_rev) { 3015 case 3: 3016 for (core = 0; core < 2; core++) { 3017 if (core == 0) { 3018 b43_radio_write(dev, 0x64, 3019 0x13); 3020 b43_radio_write(dev, 0x5F, 3021 0x1F); 3022 b43_radio_write(dev, 0x66, 3023 0xEE); 3024 b43_radio_write(dev, 0x59, 3025 0x8A); 3026 b43_radio_write(dev, 0x80, 3027 0x3E); 3028 } else { 3029 b43_radio_write(dev, 0x69, 3030 0x13); 3031 b43_radio_write(dev, 0xE8, 3032 0x1F); 3033 b43_radio_write(dev, 0xEB, 3034 0xEE); 3035 b43_radio_write(dev, 0xDE, 3036 0x8A); 3037 b43_radio_write(dev, 0x105, 3038 0x3E); 3039 } 3040 } 3041 break; 3042 case 7: 3043 case 8: 3044 if (!b43_is_40mhz(dev)) { 3045 b43_radio_write(dev, 0x5F, 0x14); 3046 b43_radio_write(dev, 0xE8, 0x12); 3047 } else { 3048 b43_radio_write(dev, 0x5F, 0x16); 3049 b43_radio_write(dev, 0xE8, 0x16); 3050 } 3051 break; 3052 case 14: 3053 for (core = 0; core < 2; core++) { 3054 int o = core ? 0x85 : 0; 3055 3056 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); 3057 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); 3058 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); 3059 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); 3060 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); 3061 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); 3062 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); 3063 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); 3064 } 3065 break; 3066 } 3067 } else { 3068 u16 freq = phy->chandef->chan->center_freq; 3069 if ((freq >= 5180 && freq <= 5230) || 3070 (freq >= 5745 && freq <= 5805)) { 3071 b43_radio_write(dev, 0x7D, 0xFF); 3072 b43_radio_write(dev, 0xFE, 0xFF); 3073 } 3074 } 3075 } else { 3076 if (phy->radio_rev != 5) { 3077 for (core = 0; core < 2; core++) { 3078 if (core == 0) { 3079 b43_radio_write(dev, 0x5c, 0x61); 3080 b43_radio_write(dev, 0x51, 0x70); 3081 } else { 3082 b43_radio_write(dev, 0xe1, 0x61); 3083 b43_radio_write(dev, 0xd6, 0x70); 3084 } 3085 } 3086 } 3087 } 3088 3089 if (phy->radio_rev == 4) { 3090 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); 3091 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); 3092 for (core = 0; core < 2; core++) { 3093 if (core == 0) { 3094 b43_radio_write(dev, 0x1a1, 0x00); 3095 b43_radio_write(dev, 0x1a2, 0x3f); 3096 b43_radio_write(dev, 0x1a6, 0x3f); 3097 } else { 3098 b43_radio_write(dev, 0x1a7, 0x00); 3099 b43_radio_write(dev, 0x1ab, 0x3f); 3100 b43_radio_write(dev, 0x1ac, 0x3f); 3101 } 3102 } 3103 } else { 3104 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); 3105 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); 3106 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); 3107 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); 3108 3109 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); 3110 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); 3111 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); 3112 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); 3113 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); 3114 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); 3115 3116 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); 3117 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); 3118 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); 3119 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); 3120 } 3121 3122 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); 3123 3124 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); 3125 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); 3126 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); 3127 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); 3128 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); 3129 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); 3130 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); 3131 3132 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); 3133 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; 3134 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); 3135 3136 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); 3137 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; 3138 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); 3139 3140 b43_nphy_gain_ctl_workarounds(dev); 3141 3142 /* TODO 3143 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, 3144 aux_adc_vmid_rev7_core0); 3145 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, 3146 aux_adc_vmid_rev7_core1); 3147 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4, 3148 aux_adc_gain_rev7); 3149 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4, 3150 aux_adc_gain_rev7); 3151 */ 3152 } 3153 3154 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) 3155 { 3156 struct b43_phy_n *nphy = dev->phy.n; 3157 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3158 3159 /* TX to RX */ 3160 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; 3161 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 }; 3162 /* RX to TX */ 3163 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 3164 0x1F }; 3165 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; 3166 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; 3167 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; 3168 3169 u16 vmids[5][4] = { 3170 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ 3171 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ 3172 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ 3173 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ 3174 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ 3175 }; 3176 u16 gains[5][4] = { 3177 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ 3178 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ 3179 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ 3180 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ 3181 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ 3182 }; 3183 u16 *vmid, *gain; 3184 3185 u8 pdet_range; 3186 u16 tmp16; 3187 u32 tmp32; 3188 3189 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); 3190 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); 3191 3192 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 3193 tmp32 &= 0xffffff; 3194 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); 3195 3196 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); 3197 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); 3198 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); 3199 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); 3200 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); 3201 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 3202 3203 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); 3204 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); 3205 3206 /* TX to RX */ 3207 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 3208 ARRAY_SIZE(tx2rx_events)); 3209 3210 /* RX to TX */ 3211 if (b43_nphy_ipa(dev)) 3212 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 3213 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 3214 if (nphy->hw_phyrxchain != 3 && 3215 nphy->hw_phyrxchain != nphy->hw_phytxchain) { 3216 if (b43_nphy_ipa(dev)) { 3217 rx2tx_delays[5] = 59; 3218 rx2tx_delays[6] = 1; 3219 rx2tx_events[7] = 0x1F; 3220 } 3221 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, 3222 ARRAY_SIZE(rx2tx_events)); 3223 } 3224 3225 tmp16 = (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 3226 0x2 : 0x9C40; 3227 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); 3228 3229 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); 3230 3231 if (!b43_is_40mhz(dev)) { 3232 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 3233 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); 3234 } else { 3235 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); 3236 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); 3237 } 3238 3239 b43_nphy_gain_ctl_workarounds(dev); 3240 3241 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); 3242 b43_ntab_write(dev, B43_NTAB16(8, 16), 2); 3243 3244 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 3245 pdet_range = sprom->fem.ghz2.pdet_range; 3246 else 3247 pdet_range = sprom->fem.ghz5.pdet_range; 3248 vmid = vmids[min_t(u16, pdet_range, 4)]; 3249 gain = gains[min_t(u16, pdet_range, 4)]; 3250 switch (pdet_range) { 3251 case 3: 3252 if (!(dev->phy.rev >= 4 && 3253 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) 3254 break; 3255 /* FALL THROUGH */ 3256 case 0: 3257 case 1: 3258 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3259 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3260 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3261 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3262 break; 3263 case 2: 3264 if (dev->phy.rev >= 6) { 3265 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 3266 vmid[3] = 0x94; 3267 else 3268 vmid[3] = 0x8e; 3269 gain[3] = 3; 3270 } else if (dev->phy.rev == 5) { 3271 vmid[3] = 0x84; 3272 gain[3] = 2; 3273 } 3274 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3275 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3276 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3277 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3278 break; 3279 case 4: 3280 case 5: 3281 if (b43_current_band(dev->wl) != NL80211_BAND_2GHZ) { 3282 if (pdet_range == 4) { 3283 vmid[3] = 0x8e; 3284 tmp16 = 0x96; 3285 gain[3] = 0x2; 3286 } else { 3287 vmid[3] = 0x89; 3288 tmp16 = 0x89; 3289 gain[3] = 0; 3290 } 3291 } else { 3292 if (pdet_range == 4) { 3293 vmid[3] = 0x89; 3294 tmp16 = 0x8b; 3295 gain[3] = 0x2; 3296 } else { 3297 vmid[3] = 0x74; 3298 tmp16 = 0x70; 3299 gain[3] = 0; 3300 } 3301 } 3302 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3303 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3304 vmid[3] = tmp16; 3305 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3306 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3307 break; 3308 } 3309 3310 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); 3311 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); 3312 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); 3313 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); 3314 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); 3315 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); 3316 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); 3317 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); 3318 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); 3319 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); 3320 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); 3321 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); 3322 3323 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ 3324 3325 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && 3326 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) || 3327 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && 3328 b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) 3329 tmp32 = 0x00088888; 3330 else 3331 tmp32 = 0x88888888; 3332 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); 3333 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); 3334 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); 3335 3336 if (dev->phy.rev == 4 && 3337 b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 3338 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, 3339 0x70); 3340 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, 3341 0x70); 3342 } 3343 3344 /* Dropped probably-always-true condition */ 3345 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); 3346 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); 3347 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); 3348 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); 3349 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); 3350 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); 3351 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); 3352 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); 3353 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); 3354 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); 3355 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); 3356 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); 3357 3358 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) 3359 ; /* TODO: 0x0080000000000000 HF */ 3360 } 3361 3362 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) 3363 { 3364 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3365 struct b43_phy *phy = &dev->phy; 3366 struct b43_phy_n *nphy = phy->n; 3367 3368 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; 3369 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; 3370 3371 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 3372 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 3373 3374 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 3375 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { 3376 delays1[0] = 0x1; 3377 delays1[5] = 0x14; 3378 } 3379 3380 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ && 3381 nphy->band5g_pwrgain) { 3382 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 3383 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); 3384 } else { 3385 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); 3386 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); 3387 } 3388 3389 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); 3390 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); 3391 if (dev->phy.rev < 3) { 3392 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); 3393 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); 3394 } 3395 3396 if (dev->phy.rev < 2) { 3397 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); 3398 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); 3399 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); 3400 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); 3401 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); 3402 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); 3403 } 3404 3405 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 3406 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 3407 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 3408 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 3409 3410 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 3411 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 3412 3413 b43_nphy_gain_ctl_workarounds(dev); 3414 3415 if (dev->phy.rev < 2) { 3416 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) 3417 b43_hf_write(dev, b43_hf_read(dev) | 3418 B43_HF_MLADVW); 3419 } else if (dev->phy.rev == 2) { 3420 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); 3421 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); 3422 } 3423 3424 if (dev->phy.rev < 2) 3425 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, 3426 ~B43_NPHY_SCRAM_SIGCTL_SCM); 3427 3428 /* Set phase track alpha and beta */ 3429 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); 3430 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); 3431 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); 3432 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); 3433 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 3434 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 3435 3436 if (dev->phy.rev < 3) { 3437 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 3438 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 3439 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 3440 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 3441 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 3442 } 3443 3444 if (dev->phy.rev == 2) 3445 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 3446 B43_NPHY_FINERX2_CGC_DECGC); 3447 } 3448 3449 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 3450 static void b43_nphy_workarounds(struct b43_wldev *dev) 3451 { 3452 struct b43_phy *phy = &dev->phy; 3453 struct b43_phy_n *nphy = phy->n; 3454 3455 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 3456 b43_nphy_classifier(dev, 1, 0); 3457 else 3458 b43_nphy_classifier(dev, 1, 1); 3459 3460 if (nphy->hang_avoid) 3461 b43_nphy_stay_in_carrier_search(dev, 1); 3462 3463 b43_phy_set(dev, B43_NPHY_IQFLIP, 3464 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 3465 3466 /* TODO: rev19+ */ 3467 if (dev->phy.rev >= 7) 3468 b43_nphy_workarounds_rev7plus(dev); 3469 else if (dev->phy.rev >= 3) 3470 b43_nphy_workarounds_rev3plus(dev); 3471 else 3472 b43_nphy_workarounds_rev1_2(dev); 3473 3474 if (nphy->hang_avoid) 3475 b43_nphy_stay_in_carrier_search(dev, 0); 3476 } 3477 3478 /************************************************** 3479 * Tx/Rx common 3480 **************************************************/ 3481 3482 /* 3483 * Transmits a known value for LO calibration 3484 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone 3485 */ 3486 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, 3487 bool iqmode, bool dac_test, bool modify_bbmult) 3488 { 3489 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); 3490 if (samp == 0) 3491 return -1; 3492 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, 3493 modify_bbmult); 3494 return 0; 3495 } 3496 3497 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ 3498 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) 3499 { 3500 struct b43_phy_n *nphy = dev->phy.n; 3501 3502 bool override = false; 3503 u16 chain = 0x33; 3504 3505 if (nphy->txrx_chain == 0) { 3506 chain = 0x11; 3507 override = true; 3508 } else if (nphy->txrx_chain == 1) { 3509 chain = 0x22; 3510 override = true; 3511 } 3512 3513 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 3514 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), 3515 chain); 3516 3517 if (override) 3518 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 3519 B43_NPHY_RFSEQMODE_CAOVER); 3520 else 3521 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 3522 ~B43_NPHY_RFSEQMODE_CAOVER); 3523 } 3524 3525 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 3526 static void b43_nphy_stop_playback(struct b43_wldev *dev) 3527 { 3528 struct b43_phy *phy = &dev->phy; 3529 struct b43_phy_n *nphy = dev->phy.n; 3530 u16 tmp; 3531 3532 if (nphy->hang_avoid) 3533 b43_nphy_stay_in_carrier_search(dev, 1); 3534 3535 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); 3536 if (tmp & 0x1) 3537 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); 3538 else if (tmp & 0x2) 3539 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 3540 3541 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); 3542 3543 if (nphy->bb_mult_save & 0x80000000) { 3544 tmp = nphy->bb_mult_save & 0xFFFF; 3545 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 3546 nphy->bb_mult_save = 0; 3547 } 3548 3549 if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) { 3550 if (phy->rev >= 19) 3551 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, 3552 1); 3553 else 3554 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); 3555 nphy->lpf_bw_overrode_for_sample_play = false; 3556 } 3557 3558 if (nphy->hang_avoid) 3559 b43_nphy_stay_in_carrier_search(dev, 0); 3560 } 3561 3562 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ 3563 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, 3564 struct nphy_txgains target, 3565 struct nphy_iqcal_params *params) 3566 { 3567 struct b43_phy *phy = &dev->phy; 3568 int i, j, indx; 3569 u16 gain; 3570 3571 if (dev->phy.rev >= 3) { 3572 params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ 3573 params->txgm = target.txgm[core]; 3574 params->pga = target.pga[core]; 3575 params->pad = target.pad[core]; 3576 params->ipa = target.ipa[core]; 3577 if (phy->rev >= 19) { 3578 /* TODO */ 3579 } else if (phy->rev >= 7) { 3580 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); 3581 } else { 3582 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); 3583 } 3584 for (j = 0; j < 5; j++) 3585 params->ncorr[j] = 0x79; 3586 } else { 3587 gain = (target.pad[core]) | (target.pga[core] << 4) | 3588 (target.txgm[core] << 8); 3589 3590 indx = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 3591 1 : 0; 3592 for (i = 0; i < 9; i++) 3593 if (tbl_iqcal_gainparams[indx][i][0] == gain) 3594 break; 3595 i = min(i, 8); 3596 3597 params->txgm = tbl_iqcal_gainparams[indx][i][1]; 3598 params->pga = tbl_iqcal_gainparams[indx][i][2]; 3599 params->pad = tbl_iqcal_gainparams[indx][i][3]; 3600 params->cal_gain = (params->txgm << 7) | (params->pga << 4) | 3601 (params->pad << 2); 3602 for (j = 0; j < 4; j++) 3603 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; 3604 } 3605 } 3606 3607 /************************************************** 3608 * Tx and Rx 3609 **************************************************/ 3610 3611 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ 3612 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) 3613 { 3614 struct b43_phy *phy = &dev->phy; 3615 struct b43_phy_n *nphy = dev->phy.n; 3616 u8 i; 3617 u16 bmask, val, tmp; 3618 enum nl80211_band band = b43_current_band(dev->wl); 3619 3620 if (nphy->hang_avoid) 3621 b43_nphy_stay_in_carrier_search(dev, 1); 3622 3623 nphy->txpwrctrl = enable; 3624 if (!enable) { 3625 if (dev->phy.rev >= 3 && 3626 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & 3627 (B43_NPHY_TXPCTL_CMD_COEFF | 3628 B43_NPHY_TXPCTL_CMD_HWPCTLEN | 3629 B43_NPHY_TXPCTL_CMD_PCTLEN))) { 3630 /* We disable enabled TX pwr ctl, save it's state */ 3631 nphy->tx_pwr_idx[0] = b43_phy_read(dev, 3632 B43_NPHY_C1_TXPCTL_STAT) & 0x7f; 3633 nphy->tx_pwr_idx[1] = b43_phy_read(dev, 3634 B43_NPHY_C2_TXPCTL_STAT) & 0x7f; 3635 } 3636 3637 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); 3638 for (i = 0; i < 84; i++) 3639 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 3640 3641 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); 3642 for (i = 0; i < 84; i++) 3643 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 3644 3645 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3646 if (dev->phy.rev >= 3) 3647 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3648 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); 3649 3650 if (dev->phy.rev >= 3) { 3651 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 3652 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 3653 } else { 3654 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 3655 } 3656 3657 if (dev->phy.rev == 2) 3658 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3659 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53); 3660 else if (dev->phy.rev < 2) 3661 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3662 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); 3663 3664 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) 3665 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); 3666 } else { 3667 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, 3668 nphy->adj_pwr_tbl); 3669 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, 3670 nphy->adj_pwr_tbl); 3671 3672 bmask = B43_NPHY_TXPCTL_CMD_COEFF | 3673 B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3674 /* wl does useless check for "enable" param here */ 3675 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3676 if (dev->phy.rev >= 3) { 3677 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3678 if (val) 3679 val |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3680 } 3681 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); 3682 3683 if (band == NL80211_BAND_5GHZ) { 3684 if (phy->rev >= 19) { 3685 /* TODO */ 3686 } else if (phy->rev >= 7) { 3687 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3688 ~B43_NPHY_TXPCTL_CMD_INIT, 3689 0x32); 3690 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 3691 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 3692 0x32); 3693 } else { 3694 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3695 ~B43_NPHY_TXPCTL_CMD_INIT, 3696 0x64); 3697 if (phy->rev > 1) 3698 b43_phy_maskset(dev, 3699 B43_NPHY_TXPCTL_INIT, 3700 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 3701 0x64); 3702 } 3703 } 3704 3705 if (dev->phy.rev >= 3) { 3706 if (nphy->tx_pwr_idx[0] != 128 && 3707 nphy->tx_pwr_idx[1] != 128) { 3708 /* Recover TX pwr ctl state */ 3709 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3710 ~B43_NPHY_TXPCTL_CMD_INIT, 3711 nphy->tx_pwr_idx[0]); 3712 if (dev->phy.rev > 1) 3713 b43_phy_maskset(dev, 3714 B43_NPHY_TXPCTL_INIT, 3715 ~0xff, nphy->tx_pwr_idx[1]); 3716 } 3717 } 3718 3719 if (phy->rev >= 7) { 3720 /* TODO */ 3721 } 3722 3723 if (dev->phy.rev >= 3) { 3724 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); 3725 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); 3726 } else { 3727 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); 3728 } 3729 3730 if (dev->phy.rev == 2) 3731 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); 3732 else if (dev->phy.rev < 2) 3733 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); 3734 3735 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) 3736 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); 3737 3738 if (b43_nphy_ipa(dev)) { 3739 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); 3740 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); 3741 } 3742 } 3743 3744 if (nphy->hang_avoid) 3745 b43_nphy_stay_in_carrier_search(dev, 0); 3746 } 3747 3748 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ 3749 static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 3750 { 3751 struct b43_phy *phy = &dev->phy; 3752 struct b43_phy_n *nphy = dev->phy.n; 3753 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3754 3755 u8 txpi[2], bbmult, i; 3756 u16 tmp, radio_gain, dac_gain; 3757 u16 freq = phy->chandef->chan->center_freq; 3758 u32 txgain; 3759 /* u32 gaintbl; rev3+ */ 3760 3761 if (nphy->hang_avoid) 3762 b43_nphy_stay_in_carrier_search(dev, 1); 3763 3764 /* TODO: rev19+ */ 3765 if (dev->phy.rev >= 7) { 3766 txpi[0] = txpi[1] = 30; 3767 } else if (dev->phy.rev >= 3) { 3768 txpi[0] = 40; 3769 txpi[1] = 40; 3770 } else if (sprom->revision < 4) { 3771 txpi[0] = 72; 3772 txpi[1] = 72; 3773 } else { 3774 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 3775 txpi[0] = sprom->txpid2g[0]; 3776 txpi[1] = sprom->txpid2g[1]; 3777 } else if (freq >= 4900 && freq < 5100) { 3778 txpi[0] = sprom->txpid5gl[0]; 3779 txpi[1] = sprom->txpid5gl[1]; 3780 } else if (freq >= 5100 && freq < 5500) { 3781 txpi[0] = sprom->txpid5g[0]; 3782 txpi[1] = sprom->txpid5g[1]; 3783 } else if (freq >= 5500) { 3784 txpi[0] = sprom->txpid5gh[0]; 3785 txpi[1] = sprom->txpid5gh[1]; 3786 } else { 3787 txpi[0] = 91; 3788 txpi[1] = 91; 3789 } 3790 } 3791 if (dev->phy.rev < 7 && 3792 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) 3793 txpi[0] = txpi[1] = 91; 3794 3795 /* 3796 for (i = 0; i < 2; i++) { 3797 nphy->txpwrindex[i].index_internal = txpi[i]; 3798 nphy->txpwrindex[i].index_internal_save = txpi[i]; 3799 } 3800 */ 3801 3802 for (i = 0; i < 2; i++) { 3803 const u32 *table = b43_nphy_get_tx_gain_table(dev); 3804 3805 if (!table) 3806 break; 3807 txgain = *(table + txpi[i]); 3808 3809 if (dev->phy.rev >= 3) 3810 radio_gain = (txgain >> 16) & 0x1FFFF; 3811 else 3812 radio_gain = (txgain >> 16) & 0x1FFF; 3813 3814 if (dev->phy.rev >= 7) 3815 dac_gain = (txgain >> 8) & 0x7; 3816 else 3817 dac_gain = (txgain >> 8) & 0x3F; 3818 bbmult = txgain & 0xFF; 3819 3820 if (dev->phy.rev >= 3) { 3821 if (i == 0) 3822 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 3823 else 3824 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 3825 } else { 3826 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 3827 } 3828 3829 if (i == 0) 3830 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); 3831 else 3832 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); 3833 3834 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); 3835 3836 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); 3837 if (i == 0) 3838 tmp = (tmp & 0x00FF) | (bbmult << 8); 3839 else 3840 tmp = (tmp & 0xFF00) | bbmult; 3841 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); 3842 3843 if (b43_nphy_ipa(dev)) { 3844 u32 tmp32; 3845 u16 reg = (i == 0) ? 3846 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; 3847 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, 3848 576 + txpi[i])); 3849 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); 3850 b43_phy_set(dev, reg, 0x4); 3851 } 3852 } 3853 3854 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); 3855 3856 if (nphy->hang_avoid) 3857 b43_nphy_stay_in_carrier_search(dev, 0); 3858 } 3859 3860 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) 3861 { 3862 struct b43_phy *phy = &dev->phy; 3863 3864 u8 core; 3865 u16 r; /* routing */ 3866 3867 if (phy->rev >= 19) { 3868 /* TODO */ 3869 } else if (phy->rev >= 7) { 3870 for (core = 0; core < 2; core++) { 3871 r = core ? 0x190 : 0x170; 3872 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 3873 b43_radio_write(dev, r + 0x5, 0x5); 3874 b43_radio_write(dev, r + 0x9, 0xE); 3875 if (phy->rev != 5) 3876 b43_radio_write(dev, r + 0xA, 0); 3877 if (phy->rev != 7) 3878 b43_radio_write(dev, r + 0xB, 1); 3879 else 3880 b43_radio_write(dev, r + 0xB, 0x31); 3881 } else { 3882 b43_radio_write(dev, r + 0x5, 0x9); 3883 b43_radio_write(dev, r + 0x9, 0xC); 3884 b43_radio_write(dev, r + 0xB, 0x0); 3885 if (phy->rev != 5) 3886 b43_radio_write(dev, r + 0xA, 1); 3887 else 3888 b43_radio_write(dev, r + 0xA, 0x31); 3889 } 3890 b43_radio_write(dev, r + 0x6, 0); 3891 b43_radio_write(dev, r + 0x7, 0); 3892 b43_radio_write(dev, r + 0x8, 3); 3893 b43_radio_write(dev, r + 0xC, 0); 3894 } 3895 } else { 3896 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 3897 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); 3898 else 3899 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); 3900 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); 3901 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); 3902 3903 for (core = 0; core < 2; core++) { 3904 r = core ? B2056_TX1 : B2056_TX0; 3905 3906 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); 3907 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); 3908 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); 3909 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); 3910 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); 3911 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); 3912 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); 3913 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 3914 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, 3915 0x5); 3916 if (phy->rev != 5) 3917 b43_radio_write(dev, r | B2056_TX_TSSIA, 3918 0x00); 3919 if (phy->rev >= 5) 3920 b43_radio_write(dev, r | B2056_TX_TSSIG, 3921 0x31); 3922 else 3923 b43_radio_write(dev, r | B2056_TX_TSSIG, 3924 0x11); 3925 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, 3926 0xE); 3927 } else { 3928 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, 3929 0x9); 3930 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); 3931 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); 3932 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, 3933 0xC); 3934 } 3935 } 3936 } 3937 } 3938 3939 /* 3940 * Stop radio and transmit known signal. Then check received signal strength to 3941 * get TSSI (Transmit Signal Strength Indicator). 3942 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi 3943 */ 3944 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) 3945 { 3946 struct b43_phy *phy = &dev->phy; 3947 struct b43_phy_n *nphy = dev->phy.n; 3948 3949 u32 tmp; 3950 s32 rssi[4] = { }; 3951 3952 if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR) 3953 return; 3954 3955 if (b43_nphy_ipa(dev)) 3956 b43_nphy_ipa_internal_tssi_setup(dev); 3957 3958 if (phy->rev >= 19) 3959 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); 3960 else if (phy->rev >= 7) 3961 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); 3962 else if (phy->rev >= 3) 3963 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); 3964 3965 b43_nphy_stop_playback(dev); 3966 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); 3967 udelay(20); 3968 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); 3969 b43_nphy_stop_playback(dev); 3970 3971 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); 3972 3973 if (phy->rev >= 19) 3974 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); 3975 else if (phy->rev >= 7) 3976 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); 3977 else if (phy->rev >= 3) 3978 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); 3979 3980 if (phy->rev >= 19) { 3981 /* TODO */ 3982 return; 3983 } else if (phy->rev >= 3) { 3984 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; 3985 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; 3986 } else { 3987 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; 3988 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; 3989 } 3990 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; 3991 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; 3992 } 3993 3994 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */ 3995 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) 3996 { 3997 struct b43_phy_n *nphy = dev->phy.n; 3998 3999 u8 idx, delta; 4000 u8 i, stf_mode; 4001 4002 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of 4003 * 21 groups, each containing 4 entries. 4004 * 4005 * First group has entries for CCK modulation. 4006 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM). 4007 * 4008 * Group 0 is for CCK 4009 * Groups 1..4 use BPSK (group per coding rate) 4010 * Groups 5..8 use QPSK (group per coding rate) 4011 * Groups 9..12 use 16-QAM (group per coding rate) 4012 * Groups 13..16 use 64-QAM (group per coding rate) 4013 * Groups 17..20 are unknown 4014 */ 4015 4016 for (i = 0; i < 4; i++) 4017 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i]; 4018 4019 for (stf_mode = 0; stf_mode < 4; stf_mode++) { 4020 delta = 0; 4021 switch (stf_mode) { 4022 case 0: 4023 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { 4024 idx = 68; 4025 } else { 4026 delta = 1; 4027 idx = b43_is_40mhz(dev) ? 52 : 4; 4028 } 4029 break; 4030 case 1: 4031 idx = b43_is_40mhz(dev) ? 76 : 28; 4032 break; 4033 case 2: 4034 idx = b43_is_40mhz(dev) ? 84 : 36; 4035 break; 4036 case 3: 4037 idx = b43_is_40mhz(dev) ? 92 : 44; 4038 break; 4039 } 4040 4041 for (i = 0; i < 20; i++) { 4042 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] = 4043 nphy->tx_power_offset[idx]; 4044 if (i == 0) 4045 idx += delta; 4046 if (i == 14) 4047 idx += 1 - delta; 4048 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 || 4049 i == 13) 4050 idx += 1; 4051 } 4052 } 4053 } 4054 4055 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */ 4056 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) 4057 { 4058 struct b43_phy *phy = &dev->phy; 4059 struct b43_phy_n *nphy = dev->phy.n; 4060 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4061 4062 s16 a1[2], b0[2], b1[2]; 4063 u8 idle[2]; 4064 u8 ppr_max; 4065 s8 target[2]; 4066 s32 num, den, pwr; 4067 u32 regval[64]; 4068 4069 u16 freq = phy->chandef->chan->center_freq; 4070 u16 tmp; 4071 u16 r; /* routing */ 4072 u8 i, c; 4073 4074 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 4075 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); 4076 b43_read32(dev, B43_MMIO_MACCTL); 4077 udelay(1); 4078 } 4079 4080 if (nphy->hang_avoid) 4081 b43_nphy_stay_in_carrier_search(dev, true); 4082 4083 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); 4084 if (dev->phy.rev >= 3) 4085 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, 4086 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); 4087 else 4088 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, 4089 B43_NPHY_TXPCTL_CMD_PCTLEN); 4090 4091 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 4092 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); 4093 4094 if (sprom->revision < 4) { 4095 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; 4096 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g; 4097 target[0] = target[1] = 52; 4098 a1[0] = a1[1] = -424; 4099 b0[0] = b0[1] = 5612; 4100 b1[0] = b1[1] = -1393; 4101 } else { 4102 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 4103 for (c = 0; c < 2; c++) { 4104 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g; 4105 target[c] = sprom->core_pwr_info[c].maxpwr_2g; 4106 a1[c] = sprom->core_pwr_info[c].pa_2g[0]; 4107 b0[c] = sprom->core_pwr_info[c].pa_2g[1]; 4108 b1[c] = sprom->core_pwr_info[c].pa_2g[2]; 4109 } 4110 } else if (freq >= 4900 && freq < 5100) { 4111 for (c = 0; c < 2; c++) { 4112 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4113 target[c] = sprom->core_pwr_info[c].maxpwr_5gl; 4114 a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; 4115 b0[c] = sprom->core_pwr_info[c].pa_5gl[1]; 4116 b1[c] = sprom->core_pwr_info[c].pa_5gl[2]; 4117 } 4118 } else if (freq >= 5100 && freq < 5500) { 4119 for (c = 0; c < 2; c++) { 4120 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4121 target[c] = sprom->core_pwr_info[c].maxpwr_5g; 4122 a1[c] = sprom->core_pwr_info[c].pa_5g[0]; 4123 b0[c] = sprom->core_pwr_info[c].pa_5g[1]; 4124 b1[c] = sprom->core_pwr_info[c].pa_5g[2]; 4125 } 4126 } else if (freq >= 5500) { 4127 for (c = 0; c < 2; c++) { 4128 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4129 target[c] = sprom->core_pwr_info[c].maxpwr_5gh; 4130 a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; 4131 b0[c] = sprom->core_pwr_info[c].pa_5gh[1]; 4132 b1[c] = sprom->core_pwr_info[c].pa_5gh[2]; 4133 } 4134 } else { 4135 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; 4136 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g; 4137 target[0] = target[1] = 52; 4138 a1[0] = a1[1] = -424; 4139 b0[0] = b0[1] = 5612; 4140 b1[0] = b1[1] = -1393; 4141 } 4142 } 4143 4144 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); 4145 if (ppr_max) { 4146 target[0] = ppr_max; 4147 target[1] = ppr_max; 4148 } 4149 4150 if (dev->phy.rev >= 3) { 4151 if (sprom->fem.ghz2.tssipos) 4152 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); 4153 if (dev->phy.rev >= 7) { 4154 for (c = 0; c < 2; c++) { 4155 r = c ? 0x190 : 0x170; 4156 if (b43_nphy_ipa(dev)) 4157 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 0xE : 0xC); 4158 } 4159 } else { 4160 if (b43_nphy_ipa(dev)) { 4161 tmp = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 0xC : 0xE; 4162 b43_radio_write(dev, 4163 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp); 4164 b43_radio_write(dev, 4165 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp); 4166 } else { 4167 b43_radio_write(dev, 4168 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); 4169 b43_radio_write(dev, 4170 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); 4171 } 4172 } 4173 } 4174 4175 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 4176 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); 4177 b43_read32(dev, B43_MMIO_MACCTL); 4178 udelay(1); 4179 } 4180 4181 if (phy->rev >= 19) { 4182 /* TODO */ 4183 } else if (phy->rev >= 7) { 4184 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 4185 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19); 4186 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 4187 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19); 4188 } else { 4189 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 4190 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40); 4191 if (dev->phy.rev > 1) 4192 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 4193 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40); 4194 } 4195 4196 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 4197 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); 4198 4199 b43_phy_write(dev, B43_NPHY_TXPCTL_N, 4200 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT | 4201 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT); 4202 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, 4203 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT | 4204 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT | 4205 B43_NPHY_TXPCTL_ITSSI_BINF); 4206 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, 4207 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT | 4208 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT); 4209 4210 for (c = 0; c < 2; c++) { 4211 for (i = 0; i < 64; i++) { 4212 num = 8 * (16 * b0[c] + b1[c] * i); 4213 den = 32768 + a1[c] * i; 4214 pwr = max((4 * num + den / 2) / den, -8); 4215 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) 4216 pwr = max(pwr, target[c] + 1); 4217 regval[i] = pwr; 4218 } 4219 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); 4220 } 4221 4222 b43_nphy_tx_prepare_adjusted_power_table(dev); 4223 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); 4224 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); 4225 4226 if (nphy->hang_avoid) 4227 b43_nphy_stay_in_carrier_search(dev, false); 4228 } 4229 4230 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) 4231 { 4232 struct b43_phy *phy = &dev->phy; 4233 4234 const u32 *table = NULL; 4235 u32 rfpwr_offset; 4236 u8 pga_gain, pad_gain; 4237 int i; 4238 const s16 *uninitialized_var(rf_pwr_offset_table); 4239 4240 table = b43_nphy_get_tx_gain_table(dev); 4241 if (!table) 4242 return; 4243 4244 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); 4245 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); 4246 4247 if (phy->rev < 3) 4248 return; 4249 4250 #if 0 4251 nphy->gmval = (table[0] >> 16) & 0x7000; 4252 #endif 4253 4254 if (phy->rev >= 19) { 4255 return; 4256 } else if (phy->rev >= 7) { 4257 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); 4258 if (!rf_pwr_offset_table) 4259 return; 4260 /* TODO: Enable this once we have gains configured */ 4261 return; 4262 } 4263 4264 for (i = 0; i < 128; i++) { 4265 if (phy->rev >= 19) { 4266 /* TODO */ 4267 return; 4268 } else if (phy->rev >= 7) { 4269 pga_gain = (table[i] >> 24) & 0xf; 4270 pad_gain = (table[i] >> 19) & 0x1f; 4271 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 4272 rfpwr_offset = rf_pwr_offset_table[pad_gain]; 4273 else 4274 rfpwr_offset = rf_pwr_offset_table[pga_gain]; 4275 } else { 4276 pga_gain = (table[i] >> 24) & 0xF; 4277 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 4278 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; 4279 else 4280 rfpwr_offset = 0; /* FIXME */ 4281 } 4282 4283 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); 4284 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); 4285 } 4286 } 4287 4288 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ 4289 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) 4290 { 4291 struct b43_phy_n *nphy = dev->phy.n; 4292 enum nl80211_band band; 4293 u16 tmp; 4294 4295 if (!enable) { 4296 nphy->rfctrl_intc1_save = b43_phy_read(dev, 4297 B43_NPHY_RFCTL_INTC1); 4298 nphy->rfctrl_intc2_save = b43_phy_read(dev, 4299 B43_NPHY_RFCTL_INTC2); 4300 band = b43_current_band(dev->wl); 4301 if (dev->phy.rev >= 7) { 4302 tmp = 0x1480; 4303 } else if (dev->phy.rev >= 3) { 4304 if (band == NL80211_BAND_5GHZ) 4305 tmp = 0x600; 4306 else 4307 tmp = 0x480; 4308 } else { 4309 if (band == NL80211_BAND_5GHZ) 4310 tmp = 0x180; 4311 else 4312 tmp = 0x120; 4313 } 4314 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 4315 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 4316 } else { 4317 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 4318 nphy->rfctrl_intc1_save); 4319 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 4320 nphy->rfctrl_intc2_save); 4321 } 4322 } 4323 4324 /* 4325 * TX low-pass filter bandwidth setup 4326 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw 4327 */ 4328 static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) 4329 { 4330 u16 tmp; 4331 4332 if (dev->phy.rev < 3 || dev->phy.rev >= 7) 4333 return; 4334 4335 if (b43_nphy_ipa(dev)) 4336 tmp = b43_is_40mhz(dev) ? 5 : 4; 4337 else 4338 tmp = b43_is_40mhz(dev) ? 3 : 1; 4339 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, 4340 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); 4341 4342 if (b43_nphy_ipa(dev)) { 4343 tmp = b43_is_40mhz(dev) ? 4 : 1; 4344 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, 4345 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); 4346 } 4347 } 4348 4349 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ 4350 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, 4351 u16 samps, u8 time, bool wait) 4352 { 4353 int i; 4354 u16 tmp; 4355 4356 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); 4357 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); 4358 if (wait) 4359 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); 4360 else 4361 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); 4362 4363 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); 4364 4365 for (i = 1000; i; i--) { 4366 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); 4367 if (!(tmp & B43_NPHY_IQEST_CMD_START)) { 4368 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | 4369 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); 4370 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | 4371 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); 4372 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | 4373 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); 4374 4375 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | 4376 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); 4377 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | 4378 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); 4379 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | 4380 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); 4381 return; 4382 } 4383 udelay(10); 4384 } 4385 memset(est, 0, sizeof(*est)); 4386 } 4387 4388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ 4389 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, 4390 struct b43_phy_n_iq_comp *pcomp) 4391 { 4392 if (write) { 4393 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); 4394 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); 4395 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); 4396 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); 4397 } else { 4398 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); 4399 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); 4400 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); 4401 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); 4402 } 4403 } 4404 4405 #if 0 4406 /* Ready but not used anywhere */ 4407 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ 4408 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) 4409 { 4410 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 4411 4412 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); 4413 if (core == 0) { 4414 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); 4415 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 4416 } else { 4417 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 4418 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 4419 } 4420 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); 4421 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); 4422 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); 4423 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); 4424 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); 4425 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); 4426 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 4427 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 4428 } 4429 4430 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ 4431 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) 4432 { 4433 u8 rxval, txval; 4434 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 4435 4436 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 4437 if (core == 0) { 4438 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 4439 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 4440 } else { 4441 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 4442 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 4443 } 4444 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 4445 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 4446 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 4447 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 4448 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); 4449 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 4450 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 4451 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 4452 4453 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 4454 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 4455 4456 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 4457 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 4458 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 4459 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 4460 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); 4461 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 4462 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); 4463 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, 4464 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); 4465 4466 if (core == 0) { 4467 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); 4468 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); 4469 } else { 4470 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); 4471 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 4472 } 4473 4474 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3); 4475 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false); 4476 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 4477 4478 if (core == 0) { 4479 rxval = 1; 4480 txval = 8; 4481 } else { 4482 rxval = 4; 4483 txval = 2; 4484 } 4485 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval, 4486 core + 1); 4487 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval, 4488 2 - core); 4489 } 4490 #endif 4491 4492 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 4493 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) 4494 { 4495 int i; 4496 s32 iq; 4497 u32 ii; 4498 u32 qq; 4499 int iq_nbits, qq_nbits; 4500 int arsh, brsh; 4501 u16 tmp, a, b; 4502 4503 struct nphy_iq_est est; 4504 struct b43_phy_n_iq_comp old; 4505 struct b43_phy_n_iq_comp new = { }; 4506 bool error = false; 4507 4508 if (mask == 0) 4509 return; 4510 4511 b43_nphy_rx_iq_coeffs(dev, false, &old); 4512 b43_nphy_rx_iq_coeffs(dev, true, &new); 4513 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); 4514 new = old; 4515 4516 for (i = 0; i < 2; i++) { 4517 if (i == 0 && (mask & 1)) { 4518 iq = est.iq0_prod; 4519 ii = est.i0_pwr; 4520 qq = est.q0_pwr; 4521 } else if (i == 1 && (mask & 2)) { 4522 iq = est.iq1_prod; 4523 ii = est.i1_pwr; 4524 qq = est.q1_pwr; 4525 } else { 4526 continue; 4527 } 4528 4529 if (ii + qq < 2) { 4530 error = true; 4531 break; 4532 } 4533 4534 iq_nbits = fls(abs(iq)); 4535 qq_nbits = fls(qq); 4536 4537 arsh = iq_nbits - 20; 4538 if (arsh >= 0) { 4539 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); 4540 tmp = ii >> arsh; 4541 } else { 4542 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); 4543 tmp = ii << -arsh; 4544 } 4545 if (tmp == 0) { 4546 error = true; 4547 break; 4548 } 4549 a /= tmp; 4550 4551 brsh = qq_nbits - 11; 4552 if (brsh >= 0) { 4553 b = (qq << (31 - qq_nbits)); 4554 tmp = ii >> brsh; 4555 } else { 4556 b = (qq << (31 - qq_nbits)); 4557 tmp = ii << -brsh; 4558 } 4559 if (tmp == 0) { 4560 error = true; 4561 break; 4562 } 4563 b = int_sqrt(b / tmp - a * a) - (1 << 10); 4564 4565 if (i == 0 && (mask & 0x1)) { 4566 if (dev->phy.rev >= 3) { 4567 new.a0 = a & 0x3FF; 4568 new.b0 = b & 0x3FF; 4569 } else { 4570 new.a0 = b & 0x3FF; 4571 new.b0 = a & 0x3FF; 4572 } 4573 } else if (i == 1 && (mask & 0x2)) { 4574 if (dev->phy.rev >= 3) { 4575 new.a1 = a & 0x3FF; 4576 new.b1 = b & 0x3FF; 4577 } else { 4578 new.a1 = b & 0x3FF; 4579 new.b1 = a & 0x3FF; 4580 } 4581 } 4582 } 4583 4584 if (error) 4585 new = old; 4586 4587 b43_nphy_rx_iq_coeffs(dev, true, &new); 4588 } 4589 4590 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ 4591 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) 4592 { 4593 u16 array[4]; 4594 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); 4595 4596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); 4597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); 4598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); 4599 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); 4600 } 4601 4602 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ 4603 static void b43_nphy_spur_workaround(struct b43_wldev *dev) 4604 { 4605 struct b43_phy_n *nphy = dev->phy.n; 4606 4607 u8 channel = dev->phy.channel; 4608 int tone[2] = { 57, 58 }; 4609 u32 noise[2] = { 0x3FF, 0x3FF }; 4610 4611 B43_WARN_ON(dev->phy.rev < 3); 4612 4613 if (nphy->hang_avoid) 4614 b43_nphy_stay_in_carrier_search(dev, 1); 4615 4616 if (nphy->gband_spurwar_en) { 4617 /* TODO: N PHY Adjust Analog Pfbw (7) */ 4618 if (channel == 11 && b43_is_40mhz(dev)) 4619 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 4620 else 4621 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 4622 /* TODO: N PHY Adjust CRS Min Power (0x1E) */ 4623 } 4624 4625 if (nphy->aband_spurwar_en) { 4626 if (channel == 54) { 4627 tone[0] = 0x20; 4628 noise[0] = 0x25F; 4629 } else if (channel == 38 || channel == 102 || channel == 118) { 4630 if (0 /* FIXME */) { 4631 tone[0] = 0x20; 4632 noise[0] = 0x21F; 4633 } else { 4634 tone[0] = 0; 4635 noise[0] = 0; 4636 } 4637 } else if (channel == 134) { 4638 tone[0] = 0x20; 4639 noise[0] = 0x21F; 4640 } else if (channel == 151) { 4641 tone[0] = 0x10; 4642 noise[0] = 0x23F; 4643 } else if (channel == 153 || channel == 161) { 4644 tone[0] = 0x30; 4645 noise[0] = 0x23F; 4646 } else { 4647 tone[0] = 0; 4648 noise[0] = 0; 4649 } 4650 4651 if (!tone[0] && !noise[0]) 4652 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ 4653 else 4654 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 4655 } 4656 4657 if (nphy->hang_avoid) 4658 b43_nphy_stay_in_carrier_search(dev, 0); 4659 } 4660 4661 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ 4662 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) 4663 { 4664 struct b43_phy_n *nphy = dev->phy.n; 4665 int i, j; 4666 u32 tmp; 4667 u32 cur_real, cur_imag, real_part, imag_part; 4668 4669 u16 buffer[7]; 4670 4671 if (nphy->hang_avoid) 4672 b43_nphy_stay_in_carrier_search(dev, true); 4673 4674 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 4675 4676 for (i = 0; i < 2; i++) { 4677 tmp = ((buffer[i * 2] & 0x3FF) << 10) | 4678 (buffer[i * 2 + 1] & 0x3FF); 4679 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 4680 (((i + 26) << 10) | 320)); 4681 for (j = 0; j < 128; j++) { 4682 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 4683 ((tmp >> 16) & 0xFFFF)); 4684 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 4685 (tmp & 0xFFFF)); 4686 } 4687 } 4688 4689 for (i = 0; i < 2; i++) { 4690 tmp = buffer[5 + i]; 4691 real_part = (tmp >> 8) & 0xFF; 4692 imag_part = (tmp & 0xFF); 4693 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 4694 (((i + 26) << 10) | 448)); 4695 4696 if (dev->phy.rev >= 3) { 4697 cur_real = real_part; 4698 cur_imag = imag_part; 4699 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); 4700 } 4701 4702 for (j = 0; j < 128; j++) { 4703 if (dev->phy.rev < 3) { 4704 cur_real = (real_part * loscale[j] + 128) >> 8; 4705 cur_imag = (imag_part * loscale[j] + 128) >> 8; 4706 tmp = ((cur_real & 0xFF) << 8) | 4707 (cur_imag & 0xFF); 4708 } 4709 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 4710 ((tmp >> 16) & 0xFFFF)); 4711 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 4712 (tmp & 0xFFFF)); 4713 } 4714 } 4715 4716 if (dev->phy.rev >= 3) { 4717 b43_shm_write16(dev, B43_SHM_SHARED, 4718 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); 4719 b43_shm_write16(dev, B43_SHM_SHARED, 4720 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); 4721 } 4722 4723 if (nphy->hang_avoid) 4724 b43_nphy_stay_in_carrier_search(dev, false); 4725 } 4726 4727 /* 4728 * Restore RSSI Calibration 4729 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal 4730 */ 4731 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) 4732 { 4733 struct b43_phy_n *nphy = dev->phy.n; 4734 4735 u16 *rssical_radio_regs = NULL; 4736 u16 *rssical_phy_regs = NULL; 4737 4738 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 4739 if (!nphy->rssical_chanspec_2G.center_freq) 4740 return; 4741 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 4742 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 4743 } else { 4744 if (!nphy->rssical_chanspec_5G.center_freq) 4745 return; 4746 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 4747 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 4748 } 4749 4750 if (dev->phy.rev >= 19) { 4751 /* TODO */ 4752 } else if (dev->phy.rev >= 7) { 4753 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, 4754 rssical_radio_regs[0]); 4755 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, 4756 rssical_radio_regs[1]); 4757 } else { 4758 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, 4759 rssical_radio_regs[0]); 4760 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, 4761 rssical_radio_regs[1]); 4762 } 4763 4764 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 4765 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 4766 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); 4767 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); 4768 4769 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); 4770 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); 4771 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); 4772 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); 4773 4774 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); 4775 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); 4776 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); 4777 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); 4778 } 4779 4780 static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) 4781 { 4782 /* TODO */ 4783 } 4784 4785 static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) 4786 { 4787 struct b43_phy *phy = &dev->phy; 4788 struct b43_phy_n *nphy = dev->phy.n; 4789 u16 *save = nphy->tx_rx_cal_radio_saveregs; 4790 int core, off; 4791 u16 r, tmp; 4792 4793 for (core = 0; core < 2; core++) { 4794 r = core ? 0x20 : 0; 4795 off = core * 11; 4796 4797 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); 4798 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); 4799 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); 4800 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); 4801 save[off + 4] = 0; 4802 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); 4803 if (phy->radio_rev != 5) 4804 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); 4805 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); 4806 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); 4807 4808 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 4809 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); 4810 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4811 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4812 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4813 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); 4814 if (nphy->use_int_tx_iq_lo_cal) { 4815 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); 4816 tmp = true ? 0x31 : 0x21; /* TODO */ 4817 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); 4818 } 4819 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); 4820 } else { 4821 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); 4822 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4823 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4824 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4825 4826 if (phy->radio_rev != 5) 4827 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); 4828 if (nphy->use_int_tx_iq_lo_cal) { 4829 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); 4830 tmp = true ? 0x31 : 0x21; /* TODO */ 4831 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); 4832 } 4833 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); 4834 } 4835 } 4836 } 4837 4838 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ 4839 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) 4840 { 4841 struct b43_phy *phy = &dev->phy; 4842 struct b43_phy_n *nphy = dev->phy.n; 4843 u16 *save = nphy->tx_rx_cal_radio_saveregs; 4844 u16 tmp; 4845 u8 offset, i; 4846 4847 if (phy->rev >= 19) { 4848 b43_nphy_tx_cal_radio_setup_rev19(dev); 4849 } else if (phy->rev >= 7) { 4850 b43_nphy_tx_cal_radio_setup_rev7(dev); 4851 } else if (phy->rev >= 3) { 4852 for (i = 0; i < 2; i++) { 4853 tmp = (i == 0) ? 0x2000 : 0x3000; 4854 offset = i * 11; 4855 4856 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); 4857 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); 4858 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); 4859 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); 4860 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); 4861 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); 4862 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); 4863 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); 4864 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); 4865 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); 4866 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); 4867 4868 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) { 4869 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 4870 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); 4871 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); 4872 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); 4873 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); 4874 if (nphy->ipa5g_on) { 4875 b43_radio_write(dev, tmp | B2055_PADDRV, 4); 4876 b43_radio_write(dev, tmp | B2055_XOCTL1, 1); 4877 } else { 4878 b43_radio_write(dev, tmp | B2055_PADDRV, 0); 4879 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); 4880 } 4881 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); 4882 } else { 4883 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); 4884 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); 4885 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); 4886 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); 4887 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); 4888 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); 4889 if (nphy->ipa2g_on) { 4890 b43_radio_write(dev, tmp | B2055_PADDRV, 6); 4891 b43_radio_write(dev, tmp | B2055_XOCTL2, 4892 (dev->phy.rev < 5) ? 0x11 : 0x01); 4893 } else { 4894 b43_radio_write(dev, tmp | B2055_PADDRV, 0); 4895 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); 4896 } 4897 } 4898 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); 4899 b43_radio_write(dev, tmp | B2055_XOMISC, 0); 4900 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); 4901 } 4902 } else { 4903 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); 4904 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 4905 4906 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); 4907 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 4908 4909 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); 4910 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 4911 4912 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); 4913 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 4914 4915 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); 4916 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); 4917 4918 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 4919 B43_NPHY_BANDCTL_5GHZ)) { 4920 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); 4921 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); 4922 } else { 4923 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); 4924 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); 4925 } 4926 4927 if (dev->phy.rev < 2) { 4928 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); 4929 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); 4930 } else { 4931 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); 4932 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); 4933 } 4934 } 4935 } 4936 4937 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ 4938 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) 4939 { 4940 struct b43_phy_n *nphy = dev->phy.n; 4941 int i; 4942 u16 scale, entry; 4943 4944 u16 tmp = nphy->txcal_bbmult; 4945 if (core == 0) 4946 tmp >>= 8; 4947 tmp &= 0xff; 4948 4949 for (i = 0; i < 18; i++) { 4950 scale = (ladder_lo[i].percent * tmp) / 100; 4951 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; 4952 b43_ntab_write(dev, B43_NTAB16(15, i), entry); 4953 4954 scale = (ladder_iq[i].percent * tmp) / 100; 4955 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; 4956 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); 4957 } 4958 } 4959 4960 static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, 4961 const s16 *filter) 4962 { 4963 int i; 4964 4965 offset = B43_PHY_N(offset); 4966 4967 for (i = 0; i < 15; i++, offset++) 4968 b43_phy_write(dev, offset, filter[i]); 4969 } 4970 4971 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 4972 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 4973 { 4974 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, 4975 tbl_tx_filter_coef_rev4[2]); 4976 } 4977 4978 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 4979 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 4980 { 4981 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 4982 static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; 4983 static const s16 dig_filter_phy_rev16[] = { 4984 -375, 136, -407, 208, -1527, 4985 956, 93, 186, 93, 230, 4986 -44, 230, 201, -191, 201, 4987 }; 4988 int i; 4989 4990 for (i = 0; i < 3; i++) 4991 b43_nphy_pa_set_tx_dig_filter(dev, offset[i], 4992 tbl_tx_filter_coef_rev4[i]); 4993 4994 /* Verified with BCM43227 and BCM43228 */ 4995 if (dev->phy.rev == 16) 4996 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); 4997 4998 /* Verified with BCM43131 and BCM43217 */ 4999 if (dev->phy.rev == 17) { 5000 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); 5001 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, 5002 tbl_tx_filter_coef_rev4[1]); 5003 } 5004 5005 if (b43_is_40mhz(dev)) { 5006 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5007 tbl_tx_filter_coef_rev4[3]); 5008 } else { 5009 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 5010 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5011 tbl_tx_filter_coef_rev4[5]); 5012 if (dev->phy.channel == 14) 5013 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5014 tbl_tx_filter_coef_rev4[6]); 5015 } 5016 } 5017 5018 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 5019 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) 5020 { 5021 struct b43_phy_n *nphy = dev->phy.n; 5022 5023 u16 curr_gain[2]; 5024 struct nphy_txgains target; 5025 const u32 *table = NULL; 5026 5027 if (!nphy->txpwrctrl) { 5028 int i; 5029 5030 if (nphy->hang_avoid) 5031 b43_nphy_stay_in_carrier_search(dev, true); 5032 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); 5033 if (nphy->hang_avoid) 5034 b43_nphy_stay_in_carrier_search(dev, false); 5035 5036 for (i = 0; i < 2; ++i) { 5037 if (dev->phy.rev >= 7) { 5038 target.ipa[i] = curr_gain[i] & 0x0007; 5039 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; 5040 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 5041 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 5042 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; 5043 } else if (dev->phy.rev >= 3) { 5044 target.ipa[i] = curr_gain[i] & 0x000F; 5045 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 5046 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 5047 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 5048 } else { 5049 target.ipa[i] = curr_gain[i] & 0x0003; 5050 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; 5051 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; 5052 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; 5053 } 5054 } 5055 } else { 5056 int i; 5057 u16 index[2]; 5058 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & 5059 B43_NPHY_TXPCTL_STAT_BIDX) >> 5060 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 5061 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & 5062 B43_NPHY_TXPCTL_STAT_BIDX) >> 5063 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 5064 5065 for (i = 0; i < 2; ++i) { 5066 table = b43_nphy_get_tx_gain_table(dev); 5067 if (!table) 5068 break; 5069 5070 if (dev->phy.rev >= 7) { 5071 target.ipa[i] = (table[index[i]] >> 16) & 0x7; 5072 target.pad[i] = (table[index[i]] >> 19) & 0x1F; 5073 target.pga[i] = (table[index[i]] >> 24) & 0xF; 5074 target.txgm[i] = (table[index[i]] >> 28) & 0x7; 5075 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; 5076 } else if (dev->phy.rev >= 3) { 5077 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 5078 target.pad[i] = (table[index[i]] >> 20) & 0xF; 5079 target.pga[i] = (table[index[i]] >> 24) & 0xF; 5080 target.txgm[i] = (table[index[i]] >> 28) & 0xF; 5081 } else { 5082 target.ipa[i] = (table[index[i]] >> 16) & 0x3; 5083 target.pad[i] = (table[index[i]] >> 18) & 0x3; 5084 target.pga[i] = (table[index[i]] >> 20) & 0x7; 5085 target.txgm[i] = (table[index[i]] >> 23) & 0x7; 5086 } 5087 } 5088 } 5089 5090 return target; 5091 } 5092 5093 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ 5094 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) 5095 { 5096 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 5097 5098 if (dev->phy.rev >= 3) { 5099 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); 5100 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 5101 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 5102 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); 5103 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); 5104 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); 5105 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); 5106 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); 5107 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); 5108 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 5109 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 5110 b43_nphy_reset_cca(dev); 5111 } else { 5112 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); 5113 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); 5114 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 5115 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); 5116 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); 5117 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); 5118 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); 5119 } 5120 } 5121 5122 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ 5123 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 5124 { 5125 struct b43_phy *phy = &dev->phy; 5126 struct b43_phy_n *nphy = dev->phy.n; 5127 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 5128 u16 tmp; 5129 5130 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 5131 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 5132 if (dev->phy.rev >= 3) { 5133 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); 5134 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); 5135 5136 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 5137 regs[2] = tmp; 5138 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); 5139 5140 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5141 regs[3] = tmp; 5142 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); 5143 5144 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); 5145 b43_phy_mask(dev, B43_NPHY_BBCFG, 5146 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 5147 5148 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); 5149 regs[5] = tmp; 5150 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); 5151 5152 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); 5153 regs[6] = tmp; 5154 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); 5155 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 5156 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 5157 5158 if (!nphy->use_int_tx_iq_lo_cal) 5159 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 5160 1, 3); 5161 else 5162 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 5163 0, 3); 5164 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); 5165 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); 5166 5167 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 5168 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 5169 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 5170 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 5171 5172 tmp = b43_nphy_read_lpf_ctl(dev, 0); 5173 if (phy->rev >= 19) 5174 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, 5175 1); 5176 else if (phy->rev >= 7) 5177 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, 5178 1); 5179 5180 if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { 5181 if (phy->rev >= 19) { 5182 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, 5183 false, 0); 5184 } else if (phy->rev >= 8) { 5185 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, 5186 false, 0); 5187 } else if (phy->rev == 7) { 5188 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); 5189 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 5190 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); 5191 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); 5192 } else { 5193 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); 5194 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); 5195 } 5196 } 5197 } 5198 } else { 5199 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); 5200 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); 5201 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5202 regs[2] = tmp; 5203 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); 5204 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); 5205 regs[3] = tmp; 5206 tmp |= 0x2000; 5207 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); 5208 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); 5209 regs[4] = tmp; 5210 tmp |= 0x2000; 5211 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); 5212 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 5213 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 5214 if (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) 5215 tmp = 0x0180; 5216 else 5217 tmp = 0x0120; 5218 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 5219 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 5220 } 5221 } 5222 5223 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ 5224 static void b43_nphy_save_cal(struct b43_wldev *dev) 5225 { 5226 struct b43_phy *phy = &dev->phy; 5227 struct b43_phy_n *nphy = dev->phy.n; 5228 5229 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 5230 u16 *txcal_radio_regs = NULL; 5231 struct b43_chanspec *iqcal_chanspec; 5232 u16 *table = NULL; 5233 5234 if (nphy->hang_avoid) 5235 b43_nphy_stay_in_carrier_search(dev, 1); 5236 5237 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 5238 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 5239 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 5240 iqcal_chanspec = &nphy->iqcal_chanspec_2G; 5241 table = nphy->cal_cache.txcal_coeffs_2G; 5242 } else { 5243 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 5244 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 5245 iqcal_chanspec = &nphy->iqcal_chanspec_5G; 5246 table = nphy->cal_cache.txcal_coeffs_5G; 5247 } 5248 5249 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); 5250 /* TODO use some definitions */ 5251 if (phy->rev >= 19) { 5252 /* TODO */ 5253 } else if (phy->rev >= 7) { 5254 txcal_radio_regs[0] = b43_radio_read(dev, 5255 R2057_TX0_LOFT_FINE_I); 5256 txcal_radio_regs[1] = b43_radio_read(dev, 5257 R2057_TX0_LOFT_FINE_Q); 5258 txcal_radio_regs[4] = b43_radio_read(dev, 5259 R2057_TX0_LOFT_COARSE_I); 5260 txcal_radio_regs[5] = b43_radio_read(dev, 5261 R2057_TX0_LOFT_COARSE_Q); 5262 txcal_radio_regs[2] = b43_radio_read(dev, 5263 R2057_TX1_LOFT_FINE_I); 5264 txcal_radio_regs[3] = b43_radio_read(dev, 5265 R2057_TX1_LOFT_FINE_Q); 5266 txcal_radio_regs[6] = b43_radio_read(dev, 5267 R2057_TX1_LOFT_COARSE_I); 5268 txcal_radio_regs[7] = b43_radio_read(dev, 5269 R2057_TX1_LOFT_COARSE_Q); 5270 } else if (phy->rev >= 3) { 5271 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 5272 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); 5273 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); 5274 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); 5275 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); 5276 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); 5277 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); 5278 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); 5279 } else { 5280 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); 5281 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); 5282 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); 5283 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); 5284 } 5285 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; 5286 iqcal_chanspec->channel_type = 5287 cfg80211_get_chandef_type(dev->phy.chandef); 5288 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); 5289 5290 if (nphy->hang_avoid) 5291 b43_nphy_stay_in_carrier_search(dev, 0); 5292 } 5293 5294 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ 5295 static void b43_nphy_restore_cal(struct b43_wldev *dev) 5296 { 5297 struct b43_phy *phy = &dev->phy; 5298 struct b43_phy_n *nphy = dev->phy.n; 5299 5300 u16 coef[4]; 5301 u16 *loft = NULL; 5302 u16 *table = NULL; 5303 5304 int i; 5305 u16 *txcal_radio_regs = NULL; 5306 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 5307 5308 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 5309 if (!nphy->iqcal_chanspec_2G.center_freq) 5310 return; 5311 table = nphy->cal_cache.txcal_coeffs_2G; 5312 loft = &nphy->cal_cache.txcal_coeffs_2G[5]; 5313 } else { 5314 if (!nphy->iqcal_chanspec_5G.center_freq) 5315 return; 5316 table = nphy->cal_cache.txcal_coeffs_5G; 5317 loft = &nphy->cal_cache.txcal_coeffs_5G[5]; 5318 } 5319 5320 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); 5321 5322 for (i = 0; i < 4; i++) { 5323 if (dev->phy.rev >= 3) 5324 table[i] = coef[i]; 5325 else 5326 coef[i] = 0; 5327 } 5328 5329 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); 5330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); 5331 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); 5332 5333 if (dev->phy.rev < 2) 5334 b43_nphy_tx_iq_workaround(dev); 5335 5336 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 5337 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 5338 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 5339 } else { 5340 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 5341 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 5342 } 5343 5344 /* TODO use some definitions */ 5345 if (phy->rev >= 19) { 5346 /* TODO */ 5347 } else if (phy->rev >= 7) { 5348 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, 5349 txcal_radio_regs[0]); 5350 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, 5351 txcal_radio_regs[1]); 5352 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, 5353 txcal_radio_regs[4]); 5354 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, 5355 txcal_radio_regs[5]); 5356 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, 5357 txcal_radio_regs[2]); 5358 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, 5359 txcal_radio_regs[3]); 5360 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, 5361 txcal_radio_regs[6]); 5362 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, 5363 txcal_radio_regs[7]); 5364 } else if (phy->rev >= 3) { 5365 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 5366 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); 5367 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); 5368 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); 5369 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); 5370 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); 5371 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); 5372 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); 5373 } else { 5374 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); 5375 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); 5376 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); 5377 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); 5378 } 5379 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); 5380 } 5381 5382 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ 5383 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, 5384 struct nphy_txgains target, 5385 bool full, bool mphase) 5386 { 5387 struct b43_phy *phy = &dev->phy; 5388 struct b43_phy_n *nphy = dev->phy.n; 5389 int i; 5390 int error = 0; 5391 int freq; 5392 bool avoid = false; 5393 u8 length; 5394 u16 tmp, core, type, count, max, numb, last = 0, cmd; 5395 const u16 *table; 5396 bool phy6or5x; 5397 5398 u16 buffer[11]; 5399 u16 diq_start = 0; 5400 u16 save[2]; 5401 u16 gain[2]; 5402 struct nphy_iqcal_params params[2]; 5403 bool updated[2] = { }; 5404 5405 b43_nphy_stay_in_carrier_search(dev, true); 5406 5407 if (dev->phy.rev >= 4) { 5408 avoid = nphy->hang_avoid; 5409 nphy->hang_avoid = false; 5410 } 5411 5412 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 5413 5414 for (i = 0; i < 2; i++) { 5415 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); 5416 gain[i] = params[i].cal_gain; 5417 } 5418 5419 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); 5420 5421 b43_nphy_tx_cal_radio_setup(dev); 5422 b43_nphy_tx_cal_phy_setup(dev); 5423 5424 phy6or5x = dev->phy.rev >= 6 || 5425 (dev->phy.rev == 5 && nphy->ipa2g_on && 5426 b43_current_band(dev->wl) == NL80211_BAND_2GHZ); 5427 if (phy6or5x) { 5428 if (b43_is_40mhz(dev)) { 5429 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 5430 tbl_tx_iqlo_cal_loft_ladder_40); 5431 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 5432 tbl_tx_iqlo_cal_iqimb_ladder_40); 5433 } else { 5434 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 5435 tbl_tx_iqlo_cal_loft_ladder_20); 5436 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 5437 tbl_tx_iqlo_cal_iqimb_ladder_20); 5438 } 5439 } 5440 5441 if (phy->rev >= 19) { 5442 /* TODO */ 5443 } else if (phy->rev >= 7) { 5444 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); 5445 } else { 5446 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 5447 } 5448 5449 if (!b43_is_40mhz(dev)) 5450 freq = 2500; 5451 else 5452 freq = 5000; 5453 5454 if (nphy->mphase_cal_phase_id > 2) 5455 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, 5456 0xFFFF, 0, true, false, false); 5457 else 5458 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); 5459 5460 if (error == 0) { 5461 if (nphy->mphase_cal_phase_id > 2) { 5462 table = nphy->mphase_txcal_bestcoeffs; 5463 length = 11; 5464 if (dev->phy.rev < 3) 5465 length -= 2; 5466 } else { 5467 if (!full && nphy->txiqlocal_coeffsvalid) { 5468 table = nphy->txiqlocal_bestc; 5469 length = 11; 5470 if (dev->phy.rev < 3) 5471 length -= 2; 5472 } else { 5473 full = true; 5474 if (dev->phy.rev >= 3) { 5475 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; 5476 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; 5477 } else { 5478 table = tbl_tx_iqlo_cal_startcoefs; 5479 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; 5480 } 5481 } 5482 } 5483 5484 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); 5485 5486 if (full) { 5487 if (dev->phy.rev >= 3) 5488 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; 5489 else 5490 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; 5491 } else { 5492 if (dev->phy.rev >= 3) 5493 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; 5494 else 5495 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; 5496 } 5497 5498 if (mphase) { 5499 count = nphy->mphase_txcal_cmdidx; 5500 numb = min(max, 5501 (u16)(count + nphy->mphase_txcal_numcmds)); 5502 } else { 5503 count = 0; 5504 numb = max; 5505 } 5506 5507 for (; count < numb; count++) { 5508 if (full) { 5509 if (dev->phy.rev >= 3) 5510 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; 5511 else 5512 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; 5513 } else { 5514 if (dev->phy.rev >= 3) 5515 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; 5516 else 5517 cmd = tbl_tx_iqlo_cal_cmds_recal[count]; 5518 } 5519 5520 core = (cmd & 0x3000) >> 12; 5521 type = (cmd & 0x0F00) >> 8; 5522 5523 if (phy6or5x && updated[core] == 0) { 5524 b43_nphy_update_tx_cal_ladder(dev, core); 5525 updated[core] = true; 5526 } 5527 5528 tmp = (params[core].ncorr[type] << 8) | 0x66; 5529 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); 5530 5531 if (type == 1 || type == 3 || type == 4) { 5532 buffer[0] = b43_ntab_read(dev, 5533 B43_NTAB16(15, 69 + core)); 5534 diq_start = buffer[0]; 5535 buffer[0] = 0; 5536 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), 5537 0); 5538 } 5539 5540 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); 5541 for (i = 0; i < 2000; i++) { 5542 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); 5543 if (tmp & 0xC000) 5544 break; 5545 udelay(10); 5546 } 5547 5548 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5549 buffer); 5550 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, 5551 buffer); 5552 5553 if (type == 1 || type == 3 || type == 4) 5554 buffer[0] = diq_start; 5555 } 5556 5557 if (mphase) 5558 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; 5559 5560 last = (dev->phy.rev < 3) ? 6 : 7; 5561 5562 if (!mphase || nphy->mphase_cal_phase_id == last) { 5563 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); 5564 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); 5565 if (dev->phy.rev < 3) { 5566 buffer[0] = 0; 5567 buffer[1] = 0; 5568 buffer[2] = 0; 5569 buffer[3] = 0; 5570 } 5571 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 5572 buffer); 5573 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, 5574 buffer); 5575 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 5576 buffer); 5577 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 5578 buffer); 5579 length = 11; 5580 if (dev->phy.rev < 3) 5581 length -= 2; 5582 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5583 nphy->txiqlocal_bestc); 5584 nphy->txiqlocal_coeffsvalid = true; 5585 nphy->txiqlocal_chanspec.center_freq = 5586 phy->chandef->chan->center_freq; 5587 nphy->txiqlocal_chanspec.channel_type = 5588 cfg80211_get_chandef_type(phy->chandef); 5589 } else { 5590 length = 11; 5591 if (dev->phy.rev < 3) 5592 length -= 2; 5593 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5594 nphy->mphase_txcal_bestcoeffs); 5595 } 5596 5597 b43_nphy_stop_playback(dev); 5598 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); 5599 } 5600 5601 b43_nphy_tx_cal_phy_cleanup(dev); 5602 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 5603 5604 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) 5605 b43_nphy_tx_iq_workaround(dev); 5606 5607 if (dev->phy.rev >= 4) 5608 nphy->hang_avoid = avoid; 5609 5610 b43_nphy_stay_in_carrier_search(dev, false); 5611 5612 return error; 5613 } 5614 5615 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ 5616 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) 5617 { 5618 struct b43_phy_n *nphy = dev->phy.n; 5619 u8 i; 5620 u16 buffer[7]; 5621 bool equal = true; 5622 5623 if (!nphy->txiqlocal_coeffsvalid || 5624 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || 5625 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) 5626 return; 5627 5628 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 5629 for (i = 0; i < 4; i++) { 5630 if (buffer[i] != nphy->txiqlocal_bestc[i]) { 5631 equal = false; 5632 break; 5633 } 5634 } 5635 5636 if (!equal) { 5637 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, 5638 nphy->txiqlocal_bestc); 5639 for (i = 0; i < 4; i++) 5640 buffer[i] = 0; 5641 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 5642 buffer); 5643 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 5644 &nphy->txiqlocal_bestc[5]); 5645 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 5646 &nphy->txiqlocal_bestc[5]); 5647 } 5648 } 5649 5650 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ 5651 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, 5652 struct nphy_txgains target, u8 type, bool debug) 5653 { 5654 struct b43_phy_n *nphy = dev->phy.n; 5655 int i, j, index; 5656 u8 rfctl[2]; 5657 u8 afectl_core; 5658 u16 tmp[6]; 5659 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; 5660 u32 real, imag; 5661 enum nl80211_band band; 5662 5663 u8 use; 5664 u16 cur_hpf; 5665 u16 lna[3] = { 3, 3, 1 }; 5666 u16 hpf1[3] = { 7, 2, 0 }; 5667 u16 hpf2[3] = { 2, 0, 0 }; 5668 u32 power[3] = { }; 5669 u16 gain_save[2]; 5670 u16 cal_gain[2]; 5671 struct nphy_iqcal_params cal_params[2]; 5672 struct nphy_iq_est est; 5673 int ret = 0; 5674 bool playtone = true; 5675 int desired = 13; 5676 5677 b43_nphy_stay_in_carrier_search(dev, 1); 5678 5679 if (dev->phy.rev < 2) 5680 b43_nphy_reapply_tx_cal_coeffs(dev); 5681 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 5682 for (i = 0; i < 2; i++) { 5683 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); 5684 cal_gain[i] = cal_params[i].cal_gain; 5685 } 5686 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); 5687 5688 for (i = 0; i < 2; i++) { 5689 if (i == 0) { 5690 rfctl[0] = B43_NPHY_RFCTL_INTC1; 5691 rfctl[1] = B43_NPHY_RFCTL_INTC2; 5692 afectl_core = B43_NPHY_AFECTL_C1; 5693 } else { 5694 rfctl[0] = B43_NPHY_RFCTL_INTC2; 5695 rfctl[1] = B43_NPHY_RFCTL_INTC1; 5696 afectl_core = B43_NPHY_AFECTL_C2; 5697 } 5698 5699 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 5700 tmp[2] = b43_phy_read(dev, afectl_core); 5701 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5702 tmp[4] = b43_phy_read(dev, rfctl[0]); 5703 tmp[5] = b43_phy_read(dev, rfctl[1]); 5704 5705 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 5706 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 5707 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 5708 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 5709 (1 - i)); 5710 b43_phy_set(dev, afectl_core, 0x0006); 5711 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); 5712 5713 band = b43_current_band(dev->wl); 5714 5715 if (nphy->rxcalparams & 0xFF000000) { 5716 if (band == NL80211_BAND_5GHZ) 5717 b43_phy_write(dev, rfctl[0], 0x140); 5718 else 5719 b43_phy_write(dev, rfctl[0], 0x110); 5720 } else { 5721 if (band == NL80211_BAND_5GHZ) 5722 b43_phy_write(dev, rfctl[0], 0x180); 5723 else 5724 b43_phy_write(dev, rfctl[0], 0x120); 5725 } 5726 5727 if (band == NL80211_BAND_5GHZ) 5728 b43_phy_write(dev, rfctl[1], 0x148); 5729 else 5730 b43_phy_write(dev, rfctl[1], 0x114); 5731 5732 if (nphy->rxcalparams & 0x10000) { 5733 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, 5734 (i + 1)); 5735 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, 5736 (2 - i)); 5737 } 5738 5739 for (j = 0; j < 4; j++) { 5740 if (j < 3) { 5741 cur_lna = lna[j]; 5742 cur_hpf1 = hpf1[j]; 5743 cur_hpf2 = hpf2[j]; 5744 } else { 5745 if (power[1] > 10000) { 5746 use = 1; 5747 cur_hpf = cur_hpf1; 5748 index = 2; 5749 } else { 5750 if (power[0] > 10000) { 5751 use = 1; 5752 cur_hpf = cur_hpf1; 5753 index = 1; 5754 } else { 5755 index = 0; 5756 use = 2; 5757 cur_hpf = cur_hpf2; 5758 } 5759 } 5760 cur_lna = lna[index]; 5761 cur_hpf1 = hpf1[index]; 5762 cur_hpf2 = hpf2[index]; 5763 cur_hpf += desired - hweight32(power[index]); 5764 cur_hpf = clamp_val(cur_hpf, 0, 10); 5765 if (use == 1) 5766 cur_hpf1 = cur_hpf; 5767 else 5768 cur_hpf2 = cur_hpf; 5769 } 5770 5771 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 5772 (cur_lna << 2)); 5773 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, 5774 false); 5775 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5776 b43_nphy_stop_playback(dev); 5777 5778 if (playtone) { 5779 ret = b43_nphy_tx_tone(dev, 4000, 5780 (nphy->rxcalparams & 0xFFFF), 5781 false, false, true); 5782 playtone = false; 5783 } else { 5784 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, 5785 false, true); 5786 } 5787 5788 if (ret == 0) { 5789 if (j < 3) { 5790 b43_nphy_rx_iq_est(dev, &est, 1024, 32, 5791 false); 5792 if (i == 0) { 5793 real = est.i0_pwr; 5794 imag = est.q0_pwr; 5795 } else { 5796 real = est.i1_pwr; 5797 imag = est.q1_pwr; 5798 } 5799 power[i] = ((real + imag) / 1024) + 1; 5800 } else { 5801 b43_nphy_calc_rx_iq_comp(dev, 1 << i); 5802 } 5803 b43_nphy_stop_playback(dev); 5804 } 5805 5806 if (ret != 0) 5807 break; 5808 } 5809 5810 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); 5811 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); 5812 b43_phy_write(dev, rfctl[1], tmp[5]); 5813 b43_phy_write(dev, rfctl[0], tmp[4]); 5814 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); 5815 b43_phy_write(dev, afectl_core, tmp[2]); 5816 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); 5817 5818 if (ret != 0) 5819 break; 5820 } 5821 5822 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); 5823 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5824 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 5825 5826 b43_nphy_stay_in_carrier_search(dev, 0); 5827 5828 return ret; 5829 } 5830 5831 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, 5832 struct nphy_txgains target, u8 type, bool debug) 5833 { 5834 return -1; 5835 } 5836 5837 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ 5838 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, 5839 struct nphy_txgains target, u8 type, bool debug) 5840 { 5841 if (dev->phy.rev >= 7) 5842 type = 0; 5843 5844 if (dev->phy.rev >= 3) 5845 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); 5846 else 5847 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); 5848 } 5849 5850 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ 5851 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) 5852 { 5853 struct b43_phy *phy = &dev->phy; 5854 struct b43_phy_n *nphy = phy->n; 5855 /* u16 buf[16]; it's rev3+ */ 5856 5857 nphy->phyrxchain = mask; 5858 5859 if (0 /* FIXME clk */) 5860 return; 5861 5862 b43_mac_suspend(dev); 5863 5864 if (nphy->hang_avoid) 5865 b43_nphy_stay_in_carrier_search(dev, true); 5866 5867 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 5868 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); 5869 5870 if ((mask & 0x3) != 0x3) { 5871 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); 5872 if (dev->phy.rev >= 3) { 5873 /* TODO */ 5874 } 5875 } else { 5876 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); 5877 if (dev->phy.rev >= 3) { 5878 /* TODO */ 5879 } 5880 } 5881 5882 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5883 5884 if (nphy->hang_avoid) 5885 b43_nphy_stay_in_carrier_search(dev, false); 5886 5887 b43_mac_enable(dev); 5888 } 5889 5890 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, 5891 bool ignore_tssi) 5892 { 5893 struct b43_phy *phy = &dev->phy; 5894 struct b43_phy_n *nphy = dev->phy.n; 5895 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; 5896 struct b43_ppr *ppr = &nphy->tx_pwr_max_ppr; 5897 u8 max; /* qdBm */ 5898 5899 if (nphy->tx_pwr_last_recalc_freq == channel->center_freq && 5900 nphy->tx_pwr_last_recalc_limit == phy->desired_txpower) 5901 return B43_TXPWR_RES_DONE; 5902 5903 /* Make sure we have a clean PPR */ 5904 b43_ppr_clear(dev, ppr); 5905 5906 /* HW limitations */ 5907 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); 5908 5909 /* Regulatory & user settings */ 5910 max = INT_TO_Q52(phy->chandef->chan->max_power); 5911 if (phy->desired_txpower) 5912 max = min_t(u8, max, INT_TO_Q52(phy->desired_txpower)); 5913 b43_ppr_apply_max(dev, ppr, max); 5914 if (b43_debug(dev, B43_DBG_XMITPOWER)) 5915 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", 5916 Q52_ARG(b43_ppr_get_max(dev, ppr))); 5917 5918 /* TODO: Enable this once we get gains working */ 5919 #if 0 5920 /* Some extra gains */ 5921 hw_gain = 6; /* N-PHY specific */ 5922 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 5923 hw_gain += sprom->antenna_gain.a0; 5924 else 5925 hw_gain += sprom->antenna_gain.a1; 5926 b43_ppr_add(dev, ppr, -hw_gain); 5927 #endif 5928 5929 /* Make sure we didn't go too low */ 5930 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); 5931 5932 /* Apply */ 5933 b43_mac_suspend(dev); 5934 b43_nphy_tx_power_ctl_setup(dev); 5935 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 5936 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); 5937 b43_read32(dev, B43_MMIO_MACCTL); 5938 udelay(1); 5939 } 5940 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); 5941 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 5942 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); 5943 b43_mac_enable(dev); 5944 5945 nphy->tx_pwr_last_recalc_freq = channel->center_freq; 5946 nphy->tx_pwr_last_recalc_limit = phy->desired_txpower; 5947 5948 return B43_TXPWR_RES_DONE; 5949 } 5950 5951 /************************************************** 5952 * N-PHY init 5953 **************************************************/ 5954 5955 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 5956 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 5957 { 5958 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); 5959 5960 mimocfg |= B43_NPHY_MIMOCFG_AUTO; 5961 if (preamble == 1) 5962 mimocfg |= B43_NPHY_MIMOCFG_GFMIX; 5963 else 5964 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; 5965 5966 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); 5967 } 5968 5969 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ 5970 static void b43_nphy_bphy_init(struct b43_wldev *dev) 5971 { 5972 unsigned int i; 5973 u16 val; 5974 5975 val = 0x1E1F; 5976 for (i = 0; i < 16; i++) { 5977 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); 5978 val -= 0x202; 5979 } 5980 val = 0x3E3F; 5981 for (i = 0; i < 16; i++) { 5982 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); 5983 val -= 0x202; 5984 } 5985 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 5986 } 5987 5988 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ 5989 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) 5990 { 5991 if (dev->phy.rev >= 7) 5992 return; 5993 5994 if (dev->phy.rev >= 3) { 5995 if (!init) 5996 return; 5997 if (0 /* FIXME */) { 5998 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); 5999 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); 6000 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); 6001 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); 6002 } 6003 } else { 6004 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 6005 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 6006 6007 switch (dev->dev->bus_type) { 6008 #ifdef CONFIG_B43_BCMA 6009 case B43_BUS_BCMA: 6010 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, 6011 0xFC00, 0xFC00); 6012 break; 6013 #endif 6014 #ifdef CONFIG_B43_SSB 6015 case B43_BUS_SSB: 6016 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, 6017 0xFC00, 0xFC00); 6018 break; 6019 #endif 6020 } 6021 6022 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); 6023 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); 6024 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), 6025 0); 6026 6027 if (init) { 6028 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 6029 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 6030 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 6031 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 6032 } 6033 } 6034 } 6035 6036 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ 6037 static int b43_phy_initn(struct b43_wldev *dev) 6038 { 6039 struct ssb_sprom *sprom = dev->dev->bus_sprom; 6040 struct b43_phy *phy = &dev->phy; 6041 struct b43_phy_n *nphy = phy->n; 6042 u8 tx_pwr_state; 6043 struct nphy_txgains target; 6044 u16 tmp; 6045 bool do_rssi_cal; 6046 6047 u16 clip[2]; 6048 bool do_cal = false; 6049 6050 if ((dev->phy.rev >= 3) && 6051 (sprom->boardflags_lo & B43_BFL_EXTLNA) && 6052 (b43_current_band(dev->wl) == NL80211_BAND_2GHZ)) { 6053 switch (dev->dev->bus_type) { 6054 #ifdef CONFIG_B43_BCMA 6055 case B43_BUS_BCMA: 6056 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, 6057 BCMA_CC_CHIPCTL, 0x40); 6058 break; 6059 #endif 6060 #ifdef CONFIG_B43_SSB 6061 case B43_BUS_SSB: 6062 chipco_set32(&dev->dev->sdev->bus->chipco, 6063 SSB_CHIPCO_CHIPCTL, 0x40); 6064 break; 6065 #endif 6066 } 6067 } 6068 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || 6069 phy->rev >= 7 || 6070 (phy->rev >= 5 && 6071 sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL); 6072 nphy->deaf_count = 0; 6073 b43_nphy_tables_init(dev); 6074 nphy->crsminpwr_adjusted = false; 6075 nphy->noisevars_adjusted = false; 6076 6077 /* Clear all overrides */ 6078 if (dev->phy.rev >= 3) { 6079 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 6080 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 6081 if (phy->rev >= 7) { 6082 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); 6083 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); 6084 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); 6085 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); 6086 } 6087 if (phy->rev >= 19) { 6088 /* TODO */ 6089 } 6090 6091 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); 6092 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); 6093 } else { 6094 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 6095 } 6096 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); 6097 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); 6098 if (dev->phy.rev < 6) { 6099 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); 6100 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); 6101 } 6102 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 6103 ~(B43_NPHY_RFSEQMODE_CAOVER | 6104 B43_NPHY_RFSEQMODE_TROVER)); 6105 if (dev->phy.rev >= 3) 6106 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); 6107 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); 6108 6109 if (dev->phy.rev <= 2) { 6110 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; 6111 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 6112 ~B43_NPHY_BPHY_CTL3_SCALE, 6113 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); 6114 } 6115 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 6116 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 6117 6118 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 6119 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 6120 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) 6121 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 6122 else 6123 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 6124 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); 6125 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); 6126 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); 6127 6128 if (phy->rev < 8) 6129 b43_nphy_update_mimo_config(dev, nphy->preamble_override); 6130 6131 b43_nphy_update_txrx_chain(dev); 6132 6133 if (phy->rev < 2) { 6134 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); 6135 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); 6136 } 6137 6138 if (b43_nphy_ipa(dev)) { 6139 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); 6140 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, 6141 nphy->papd_epsilon_offset[0] << 7); 6142 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); 6143 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, 6144 nphy->papd_epsilon_offset[1] << 7); 6145 b43_nphy_int_pa_set_tx_dig_filters(dev); 6146 } else if (phy->rev >= 5) { 6147 b43_nphy_ext_pa_set_tx_dig_filters(dev); 6148 } 6149 6150 b43_nphy_workarounds(dev); 6151 6152 /* Reset CCA, in init code it differs a little from standard way */ 6153 b43_phy_force_clock(dev, 1); 6154 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); 6155 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); 6156 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); 6157 b43_phy_force_clock(dev, 0); 6158 6159 b43_mac_phy_clock_set(dev, true); 6160 6161 if (phy->rev < 7) { 6162 b43_nphy_pa_override(dev, false); 6163 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 6164 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 6165 b43_nphy_pa_override(dev, true); 6166 } 6167 6168 b43_nphy_classifier(dev, 0, 0); 6169 b43_nphy_read_clip_detection(dev, clip); 6170 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 6171 b43_nphy_bphy_init(dev); 6172 6173 tx_pwr_state = nphy->txpwrctrl; 6174 b43_nphy_tx_power_ctrl(dev, false); 6175 b43_nphy_tx_power_fix(dev); 6176 b43_nphy_tx_power_ctl_idle_tssi(dev); 6177 b43_nphy_tx_power_ctl_setup(dev); 6178 b43_nphy_tx_gain_table_upload(dev); 6179 6180 if (nphy->phyrxchain != 3) 6181 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); 6182 if (nphy->mphase_cal_phase_id > 0) 6183 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ 6184 6185 do_rssi_cal = false; 6186 if (phy->rev >= 3) { 6187 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 6188 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; 6189 else 6190 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; 6191 6192 if (do_rssi_cal) 6193 b43_nphy_rssi_cal(dev); 6194 else 6195 b43_nphy_restore_rssi_cal(dev); 6196 } else { 6197 b43_nphy_rssi_cal(dev); 6198 } 6199 6200 if (!((nphy->measure_hold & 0x6) != 0)) { 6201 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 6202 do_cal = !nphy->iqcal_chanspec_2G.center_freq; 6203 else 6204 do_cal = !nphy->iqcal_chanspec_5G.center_freq; 6205 6206 if (nphy->mute) 6207 do_cal = false; 6208 6209 if (do_cal) { 6210 target = b43_nphy_get_tx_gains(dev); 6211 6212 if (nphy->antsel_type == 2) 6213 b43_nphy_superswitch_init(dev, true); 6214 if (nphy->perical != 2) { 6215 b43_nphy_rssi_cal(dev); 6216 if (phy->rev >= 3) { 6217 nphy->cal_orig_pwr_idx[0] = 6218 nphy->txpwrindex[0].index_internal; 6219 nphy->cal_orig_pwr_idx[1] = 6220 nphy->txpwrindex[1].index_internal; 6221 /* TODO N PHY Pre Calibrate TX Gain */ 6222 target = b43_nphy_get_tx_gains(dev); 6223 } 6224 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) 6225 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) 6226 b43_nphy_save_cal(dev); 6227 } else if (nphy->mphase_cal_phase_id == 0) 6228 ;/* N PHY Periodic Calibration with arg 3 */ 6229 } else { 6230 b43_nphy_restore_cal(dev); 6231 } 6232 } 6233 6234 b43_nphy_tx_pwr_ctrl_coef_setup(dev); 6235 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); 6236 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); 6237 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); 6238 if (phy->rev >= 3 && phy->rev <= 6) 6239 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); 6240 b43_nphy_tx_lpf_bw(dev); 6241 if (phy->rev >= 3) 6242 b43_nphy_spur_workaround(dev); 6243 6244 return 0; 6245 } 6246 6247 /************************************************** 6248 * Channel switching ops. 6249 **************************************************/ 6250 6251 static void b43_chantab_phy_upload(struct b43_wldev *dev, 6252 const struct b43_phy_n_sfo_cfg *e) 6253 { 6254 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); 6255 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); 6256 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); 6257 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); 6258 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); 6259 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); 6260 } 6261 6262 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ 6263 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) 6264 { 6265 switch (dev->dev->bus_type) { 6266 #ifdef CONFIG_B43_BCMA 6267 case B43_BUS_BCMA: 6268 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, 6269 avoid); 6270 break; 6271 #endif 6272 #ifdef CONFIG_B43_SSB 6273 case B43_BUS_SSB: 6274 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, 6275 avoid); 6276 break; 6277 #endif 6278 } 6279 } 6280 6281 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ 6282 static void b43_nphy_channel_setup(struct b43_wldev *dev, 6283 const struct b43_phy_n_sfo_cfg *e, 6284 struct ieee80211_channel *new_channel) 6285 { 6286 struct b43_phy *phy = &dev->phy; 6287 struct b43_phy_n *nphy = dev->phy.n; 6288 int ch = new_channel->hw_value; 6289 u16 tmp16; 6290 6291 if (new_channel->band == NL80211_BAND_5GHZ) { 6292 /* Switch to 2 GHz for a moment to access B43_PHY_B_BBCFG */ 6293 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 6294 6295 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); 6296 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); 6297 /* Put BPHY in the reset */ 6298 b43_phy_set(dev, B43_PHY_B_BBCFG, 6299 B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX); 6300 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); 6301 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); 6302 } else if (new_channel->band == NL80211_BAND_2GHZ) { 6303 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 6304 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); 6305 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); 6306 /* Take BPHY out of the reset */ 6307 b43_phy_mask(dev, B43_PHY_B_BBCFG, 6308 (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX)); 6309 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); 6310 } 6311 6312 b43_chantab_phy_upload(dev, e); 6313 6314 if (new_channel->hw_value == 14) { 6315 b43_nphy_classifier(dev, 2, 0); 6316 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); 6317 } else { 6318 b43_nphy_classifier(dev, 2, 2); 6319 if (new_channel->band == NL80211_BAND_2GHZ) 6320 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); 6321 } 6322 6323 if (!nphy->txpwrctrl) 6324 b43_nphy_tx_power_fix(dev); 6325 6326 if (dev->phy.rev < 3) 6327 b43_nphy_adjust_lna_gain_table(dev); 6328 6329 b43_nphy_tx_lpf_bw(dev); 6330 6331 if (dev->phy.rev >= 3 && 6332 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { 6333 u8 spuravoid = 0; 6334 6335 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { 6336 spuravoid = 1; 6337 } else if (phy->rev >= 19) { 6338 /* TODO */ 6339 } else if (phy->rev >= 18) { 6340 /* TODO */ 6341 } else if (phy->rev >= 17) { 6342 /* TODO: Off for channels 1-11, but check 12-14! */ 6343 } else if (phy->rev >= 16) { 6344 /* TODO: Off for 2 GHz, but check 5 GHz! */ 6345 } else if (phy->rev >= 7) { 6346 if (!b43_is_40mhz(dev)) { /* 20MHz */ 6347 if (ch == 13 || ch == 14 || ch == 153) 6348 spuravoid = 1; 6349 } else { /* 40 MHz */ 6350 if (ch == 54) 6351 spuravoid = 1; 6352 } 6353 } else { 6354 if (!b43_is_40mhz(dev)) { /* 20MHz */ 6355 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14) 6356 spuravoid = 1; 6357 } else { /* 40MHz */ 6358 if (nphy->aband_spurwar_en && 6359 (ch == 38 || ch == 102 || ch == 118)) 6360 spuravoid = dev->dev->chip_id == 0x4716; 6361 } 6362 } 6363 6364 b43_nphy_pmu_spur_avoid(dev, spuravoid); 6365 6366 b43_mac_switch_freq(dev, spuravoid); 6367 6368 if (dev->phy.rev == 3 || dev->phy.rev == 4) 6369 b43_wireless_core_phy_pll_reset(dev); 6370 6371 if (spuravoid) 6372 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); 6373 else 6374 b43_phy_mask(dev, B43_NPHY_BBCFG, 6375 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 6376 6377 b43_nphy_reset_cca(dev); 6378 6379 /* wl sets useless phy_isspuravoid here */ 6380 } 6381 6382 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); 6383 6384 if (phy->rev >= 3) 6385 b43_nphy_spur_workaround(dev); 6386 } 6387 6388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ 6389 static int b43_nphy_set_channel(struct b43_wldev *dev, 6390 struct ieee80211_channel *channel, 6391 enum nl80211_channel_type channel_type) 6392 { 6393 struct b43_phy *phy = &dev->phy; 6394 6395 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL; 6396 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL; 6397 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL; 6398 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL; 6399 6400 u8 tmp; 6401 6402 if (phy->rev >= 19) { 6403 return -ESRCH; 6404 /* TODO */ 6405 } else if (phy->rev >= 7) { 6406 r2057_get_chantabent_rev7(dev, channel->center_freq, 6407 &tabent_r7, &tabent_r7_2g); 6408 if (!tabent_r7 && !tabent_r7_2g) 6409 return -ESRCH; 6410 } else if (phy->rev >= 3) { 6411 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, 6412 channel->center_freq); 6413 if (!tabent_r3) 6414 return -ESRCH; 6415 } else { 6416 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, 6417 channel->hw_value); 6418 if (!tabent_r2) 6419 return -ESRCH; 6420 } 6421 6422 /* Channel is set later in common code, but we need to set it on our 6423 own to let this function's subcalls work properly. */ 6424 phy->channel = channel->hw_value; 6425 6426 #if 0 6427 if (b43_channel_type_is_40mhz(phy->channel_type) != 6428 b43_channel_type_is_40mhz(channel_type)) 6429 ; /* TODO: BMAC BW Set (channel_type) */ 6430 #endif 6431 6432 if (channel_type == NL80211_CHAN_HT40PLUS) { 6433 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); 6434 if (phy->rev >= 7) 6435 b43_phy_set(dev, 0x310, 0x8000); 6436 } else if (channel_type == NL80211_CHAN_HT40MINUS) { 6437 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); 6438 if (phy->rev >= 7) 6439 b43_phy_mask(dev, 0x310, (u16)~0x8000); 6440 } 6441 6442 if (phy->rev >= 19) { 6443 /* TODO */ 6444 } else if (phy->rev >= 7) { 6445 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ? 6446 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs); 6447 6448 if (phy->radio_rev <= 4 || phy->radio_rev == 6) { 6449 tmp = (channel->band == NL80211_BAND_5GHZ) ? 2 : 0; 6450 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); 6451 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); 6452 } 6453 6454 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); 6455 b43_nphy_channel_setup(dev, phy_regs, channel); 6456 } else if (phy->rev >= 3) { 6457 tmp = (channel->band == NL80211_BAND_5GHZ) ? 4 : 0; 6458 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); 6459 b43_radio_2056_setup(dev, tabent_r3); 6460 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); 6461 } else { 6462 tmp = (channel->band == NL80211_BAND_5GHZ) ? 0x0020 : 0x0050; 6463 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); 6464 b43_radio_2055_setup(dev, tabent_r2); 6465 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); 6466 } 6467 6468 return 0; 6469 } 6470 6471 /************************************************** 6472 * Basic PHY ops. 6473 **************************************************/ 6474 6475 static int b43_nphy_op_allocate(struct b43_wldev *dev) 6476 { 6477 struct b43_phy_n *nphy; 6478 6479 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); 6480 if (!nphy) 6481 return -ENOMEM; 6482 6483 dev->phy.n = nphy; 6484 6485 return 0; 6486 } 6487 6488 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) 6489 { 6490 struct b43_phy *phy = &dev->phy; 6491 struct b43_phy_n *nphy = phy->n; 6492 struct ssb_sprom *sprom = dev->dev->bus_sprom; 6493 6494 memset(nphy, 0, sizeof(*nphy)); 6495 6496 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); 6497 nphy->spur_avoid = (phy->rev >= 3) ? 6498 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE; 6499 nphy->gain_boost = true; /* this way we follow wl, assume it is true */ 6500 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ 6501 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ 6502 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ 6503 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is 6504 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ 6505 nphy->tx_pwr_idx[0] = 128; 6506 nphy->tx_pwr_idx[1] = 128; 6507 6508 /* Hardware TX power control and 5GHz power gain */ 6509 nphy->txpwrctrl = false; 6510 nphy->pwg_gain_5ghz = false; 6511 if (dev->phy.rev >= 3 || 6512 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 6513 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { 6514 nphy->txpwrctrl = true; 6515 nphy->pwg_gain_5ghz = true; 6516 } else if (sprom->revision >= 4) { 6517 if (dev->phy.rev >= 2 && 6518 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) { 6519 nphy->txpwrctrl = true; 6520 #ifdef CONFIG_B43_SSB 6521 if (dev->dev->bus_type == B43_BUS_SSB && 6522 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { 6523 struct pci_dev *pdev = 6524 dev->dev->sdev->bus->host_pci; 6525 if (pdev->device == 0x4328 || 6526 pdev->device == 0x432a) 6527 nphy->pwg_gain_5ghz = true; 6528 } 6529 #endif 6530 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) { 6531 nphy->pwg_gain_5ghz = true; 6532 } 6533 } 6534 6535 if (dev->phy.rev >= 3) { 6536 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2; 6537 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2; 6538 } 6539 } 6540 6541 static void b43_nphy_op_free(struct b43_wldev *dev) 6542 { 6543 struct b43_phy *phy = &dev->phy; 6544 struct b43_phy_n *nphy = phy->n; 6545 6546 kfree(nphy); 6547 phy->n = NULL; 6548 } 6549 6550 static int b43_nphy_op_init(struct b43_wldev *dev) 6551 { 6552 return b43_phy_initn(dev); 6553 } 6554 6555 static inline void check_phyreg(struct b43_wldev *dev, u16 offset) 6556 { 6557 #if B43_DEBUG 6558 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { 6559 /* OFDM registers are onnly available on A/G-PHYs */ 6560 b43err(dev->wl, "Invalid OFDM PHY access at " 6561 "0x%04X on N-PHY\n", offset); 6562 dump_stack(); 6563 } 6564 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { 6565 /* Ext-G registers are only available on G-PHYs */ 6566 b43err(dev->wl, "Invalid EXT-G PHY access at " 6567 "0x%04X on N-PHY\n", offset); 6568 dump_stack(); 6569 } 6570 #endif /* B43_DEBUG */ 6571 } 6572 6573 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, 6574 u16 set) 6575 { 6576 check_phyreg(dev, reg); 6577 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); 6578 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); 6579 dev->phy.writes_counter = 1; 6580 } 6581 6582 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) 6583 { 6584 /* Register 1 is a 32-bit register. */ 6585 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); 6586 6587 if (dev->phy.rev >= 7) 6588 reg |= 0x200; /* Radio 0x2057 */ 6589 else 6590 reg |= 0x100; 6591 6592 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 6593 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 6594 } 6595 6596 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 6597 { 6598 /* Register 1 is a 32-bit register. */ 6599 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); 6600 6601 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 6602 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 6603 } 6604 6605 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ 6606 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, 6607 bool blocked) 6608 { 6609 struct b43_phy *phy = &dev->phy; 6610 6611 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) 6612 b43err(dev->wl, "MAC not suspended\n"); 6613 6614 if (blocked) { 6615 if (phy->rev >= 19) { 6616 /* TODO */ 6617 } else if (phy->rev >= 8) { 6618 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6619 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6620 } else if (phy->rev >= 7) { 6621 /* Nothing needed */ 6622 } else if (phy->rev >= 3) { 6623 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6624 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6625 6626 b43_radio_mask(dev, 0x09, ~0x2); 6627 6628 b43_radio_write(dev, 0x204D, 0); 6629 b43_radio_write(dev, 0x2053, 0); 6630 b43_radio_write(dev, 0x2058, 0); 6631 b43_radio_write(dev, 0x205E, 0); 6632 b43_radio_mask(dev, 0x2062, ~0xF0); 6633 b43_radio_write(dev, 0x2064, 0); 6634 6635 b43_radio_write(dev, 0x304D, 0); 6636 b43_radio_write(dev, 0x3053, 0); 6637 b43_radio_write(dev, 0x3058, 0); 6638 b43_radio_write(dev, 0x305E, 0); 6639 b43_radio_mask(dev, 0x3062, ~0xF0); 6640 b43_radio_write(dev, 0x3064, 0); 6641 } 6642 } else { 6643 if (phy->rev >= 19) { 6644 /* TODO */ 6645 } else if (phy->rev >= 7) { 6646 if (!dev->phy.radio_on) 6647 b43_radio_2057_init(dev); 6648 b43_switch_channel(dev, dev->phy.channel); 6649 } else if (phy->rev >= 3) { 6650 if (!dev->phy.radio_on) 6651 b43_radio_init2056(dev); 6652 b43_switch_channel(dev, dev->phy.channel); 6653 } else { 6654 b43_radio_init2055(dev); 6655 } 6656 } 6657 } 6658 6659 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ 6660 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 6661 { 6662 struct b43_phy *phy = &dev->phy; 6663 u16 override = on ? 0x0 : 0x7FFF; 6664 u16 core = on ? 0xD : 0x00FD; 6665 6666 if (phy->rev >= 19) { 6667 /* TODO */ 6668 } else if (phy->rev >= 3) { 6669 if (on) { 6670 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); 6671 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); 6672 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); 6673 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6674 } else { 6675 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); 6676 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); 6677 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6678 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); 6679 } 6680 } else { 6681 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6682 } 6683 } 6684 6685 static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 6686 unsigned int new_channel) 6687 { 6688 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; 6689 enum nl80211_channel_type channel_type = 6690 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); 6691 6692 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) { 6693 if ((new_channel < 1) || (new_channel > 14)) 6694 return -EINVAL; 6695 } else { 6696 if (new_channel > 200) 6697 return -EINVAL; 6698 } 6699 6700 return b43_nphy_set_channel(dev, channel, channel_type); 6701 } 6702 6703 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) 6704 { 6705 if (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) 6706 return 1; 6707 return 36; 6708 } 6709 6710 const struct b43_phy_operations b43_phyops_n = { 6711 .allocate = b43_nphy_op_allocate, 6712 .free = b43_nphy_op_free, 6713 .prepare_structs = b43_nphy_op_prepare_structs, 6714 .init = b43_nphy_op_init, 6715 .phy_maskset = b43_nphy_op_maskset, 6716 .radio_read = b43_nphy_op_radio_read, 6717 .radio_write = b43_nphy_op_radio_write, 6718 .software_rfkill = b43_nphy_op_software_rfkill, 6719 .switch_analog = b43_nphy_op_switch_analog, 6720 .switch_channel = b43_nphy_op_switch_channel, 6721 .get_default_chan = b43_nphy_op_get_default_chan, 6722 .recalc_txpower = b43_nphy_op_recalc_txpower, 6723 }; 6724