1 /* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11g PHY driver 5 6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, 7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> 8 Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> 9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> 10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> 11 12 This program is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 This program is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; see the file COPYING. If not, write to 24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 25 Boston, MA 02110-1301, USA. 26 27 */ 28 29 #include "b43.h" 30 #include "phy_g.h" 31 #include "phy_common.h" 32 #include "lo.h" 33 #include "main.h" 34 #include "wa.h" 35 36 #include <linux/bitrev.h> 37 #include <linux/slab.h> 38 39 40 static const s8 b43_tssi2dbm_g_table[] = { 41 77, 77, 77, 76, 42 76, 76, 75, 75, 43 74, 74, 73, 73, 44 73, 72, 72, 71, 45 71, 70, 70, 69, 46 68, 68, 67, 67, 47 66, 65, 65, 64, 48 63, 63, 62, 61, 49 60, 59, 58, 57, 50 56, 55, 54, 53, 51 52, 50, 49, 47, 52 45, 43, 40, 37, 53 33, 28, 22, 14, 54 5, -7, -20, -20, 55 -20, -20, -20, -20, 56 -20, -20, -20, -20, 57 }; 58 59 static const u8 b43_radio_channel_codes_bg[] = { 60 12, 17, 22, 27, 61 32, 37, 42, 47, 62 52, 57, 62, 67, 63 72, 84, 64 }; 65 66 67 static void b43_calc_nrssi_threshold(struct b43_wldev *dev); 68 69 70 #define bitrev4(tmp) (bitrev8(tmp) >> 4) 71 72 73 /* Get the freq, as it has to be written to the device. */ 74 static inline u16 channel2freq_bg(u8 channel) 75 { 76 B43_WARN_ON(!(channel >= 1 && channel <= 14)); 77 78 return b43_radio_channel_codes_bg[channel - 1]; 79 } 80 81 static void generate_rfatt_list(struct b43_wldev *dev, 82 struct b43_rfatt_list *list) 83 { 84 struct b43_phy *phy = &dev->phy; 85 86 /* APHY.rev < 5 || GPHY.rev < 6 */ 87 static const struct b43_rfatt rfatt_0[] = { 88 {.att = 3,.with_padmix = 0,}, 89 {.att = 1,.with_padmix = 0,}, 90 {.att = 5,.with_padmix = 0,}, 91 {.att = 7,.with_padmix = 0,}, 92 {.att = 9,.with_padmix = 0,}, 93 {.att = 2,.with_padmix = 0,}, 94 {.att = 0,.with_padmix = 0,}, 95 {.att = 4,.with_padmix = 0,}, 96 {.att = 6,.with_padmix = 0,}, 97 {.att = 8,.with_padmix = 0,}, 98 {.att = 1,.with_padmix = 1,}, 99 {.att = 2,.with_padmix = 1,}, 100 {.att = 3,.with_padmix = 1,}, 101 {.att = 4,.with_padmix = 1,}, 102 }; 103 /* Radio.rev == 8 && Radio.version == 0x2050 */ 104 static const struct b43_rfatt rfatt_1[] = { 105 {.att = 2,.with_padmix = 1,}, 106 {.att = 4,.with_padmix = 1,}, 107 {.att = 6,.with_padmix = 1,}, 108 {.att = 8,.with_padmix = 1,}, 109 {.att = 10,.with_padmix = 1,}, 110 {.att = 12,.with_padmix = 1,}, 111 {.att = 14,.with_padmix = 1,}, 112 }; 113 /* Otherwise */ 114 static const struct b43_rfatt rfatt_2[] = { 115 {.att = 0,.with_padmix = 1,}, 116 {.att = 2,.with_padmix = 1,}, 117 {.att = 4,.with_padmix = 1,}, 118 {.att = 6,.with_padmix = 1,}, 119 {.att = 8,.with_padmix = 1,}, 120 {.att = 9,.with_padmix = 1,}, 121 {.att = 9,.with_padmix = 1,}, 122 }; 123 124 if (!b43_has_hardware_pctl(dev)) { 125 /* Software pctl */ 126 list->list = rfatt_0; 127 list->len = ARRAY_SIZE(rfatt_0); 128 list->min_val = 0; 129 list->max_val = 9; 130 return; 131 } 132 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { 133 /* Hardware pctl */ 134 list->list = rfatt_1; 135 list->len = ARRAY_SIZE(rfatt_1); 136 list->min_val = 0; 137 list->max_val = 14; 138 return; 139 } 140 /* Hardware pctl */ 141 list->list = rfatt_2; 142 list->len = ARRAY_SIZE(rfatt_2); 143 list->min_val = 0; 144 list->max_val = 9; 145 } 146 147 static void generate_bbatt_list(struct b43_wldev *dev, 148 struct b43_bbatt_list *list) 149 { 150 static const struct b43_bbatt bbatt_0[] = { 151 {.att = 0,}, 152 {.att = 1,}, 153 {.att = 2,}, 154 {.att = 3,}, 155 {.att = 4,}, 156 {.att = 5,}, 157 {.att = 6,}, 158 {.att = 7,}, 159 {.att = 8,}, 160 }; 161 162 list->list = bbatt_0; 163 list->len = ARRAY_SIZE(bbatt_0); 164 list->min_val = 0; 165 list->max_val = 8; 166 } 167 168 static void b43_shm_clear_tssi(struct b43_wldev *dev) 169 { 170 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F); 171 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F); 172 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F); 173 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F); 174 } 175 176 /* Synthetic PU workaround */ 177 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel) 178 { 179 struct b43_phy *phy = &dev->phy; 180 181 might_sleep(); 182 183 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) { 184 /* We do not need the workaround. */ 185 return; 186 } 187 188 if (channel <= 10) { 189 b43_write16(dev, B43_MMIO_CHANNEL, 190 channel2freq_bg(channel + 4)); 191 } else { 192 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1)); 193 } 194 msleep(1); 195 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); 196 } 197 198 /* Set the baseband attenuation value on chip. */ 199 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev, 200 u16 baseband_attenuation) 201 { 202 struct b43_phy *phy = &dev->phy; 203 204 if (phy->analog == 0) { 205 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0) 206 & 0xFFF0) | 207 baseband_attenuation); 208 } else if (phy->analog > 1) { 209 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2)); 210 } else { 211 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3)); 212 } 213 } 214 215 /* Adjust the transmission power output (G-PHY) */ 216 static void b43_set_txpower_g(struct b43_wldev *dev, 217 const struct b43_bbatt *bbatt, 218 const struct b43_rfatt *rfatt, u8 tx_control) 219 { 220 struct b43_phy *phy = &dev->phy; 221 struct b43_phy_g *gphy = phy->g; 222 struct b43_txpower_lo_control *lo = gphy->lo_control; 223 u16 bb, rf; 224 u16 tx_bias, tx_magn; 225 226 bb = bbatt->att; 227 rf = rfatt->att; 228 tx_bias = lo->tx_bias; 229 tx_magn = lo->tx_magn; 230 if (unlikely(tx_bias == 0xFF)) 231 tx_bias = 0; 232 233 /* Save the values for later. Use memmove, because it's valid 234 * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */ 235 gphy->tx_control = tx_control; 236 memmove(&gphy->rfatt, rfatt, sizeof(*rfatt)); 237 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX); 238 memmove(&gphy->bbatt, bbatt, sizeof(*bbatt)); 239 240 if (b43_debug(dev, B43_DBG_XMITPOWER)) { 241 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), " 242 "rfatt(%u), tx_control(0x%02X), " 243 "tx_bias(0x%02X), tx_magn(0x%02X)\n", 244 bb, rf, tx_control, tx_bias, tx_magn); 245 } 246 247 b43_gphy_set_baseband_attenuation(dev, bb); 248 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf); 249 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { 250 b43_radio_write16(dev, 0x43, 251 (rf & 0x000F) | (tx_control & 0x0070)); 252 } else { 253 b43_radio_maskset(dev, 0x43, 0xFFF0, (rf & 0x000F)); 254 b43_radio_maskset(dev, 0x52, ~0x0070, (tx_control & 0x0070)); 255 } 256 if (has_tx_magnification(phy)) { 257 b43_radio_write16(dev, 0x52, tx_magn | tx_bias); 258 } else { 259 b43_radio_maskset(dev, 0x52, 0xFFF0, (tx_bias & 0x000F)); 260 } 261 b43_lo_g_adjust(dev); 262 } 263 264 /* GPHY_TSSI_Power_Lookup_Table_Init */ 265 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev) 266 { 267 struct b43_phy_g *gphy = dev->phy.g; 268 int i; 269 u16 value; 270 271 for (i = 0; i < 32; i++) 272 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]); 273 for (i = 32; i < 64; i++) 274 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]); 275 for (i = 0; i < 64; i += 2) { 276 value = (u16) gphy->tssi2dbm[i]; 277 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8; 278 b43_phy_write(dev, 0x380 + (i / 2), value); 279 } 280 } 281 282 /* GPHY_Gain_Lookup_Table_Init */ 283 static void b43_gphy_gain_lt_init(struct b43_wldev *dev) 284 { 285 struct b43_phy *phy = &dev->phy; 286 struct b43_phy_g *gphy = phy->g; 287 struct b43_txpower_lo_control *lo = gphy->lo_control; 288 u16 nr_written = 0; 289 u16 tmp; 290 u8 rf, bb; 291 292 for (rf = 0; rf < lo->rfatt_list.len; rf++) { 293 for (bb = 0; bb < lo->bbatt_list.len; bb++) { 294 if (nr_written >= 0x40) 295 return; 296 tmp = lo->bbatt_list.list[bb].att; 297 tmp <<= 8; 298 if (phy->radio_rev == 8) 299 tmp |= 0x50; 300 else 301 tmp |= 0x40; 302 tmp |= lo->rfatt_list.list[rf].att; 303 b43_phy_write(dev, 0x3C0 + nr_written, tmp); 304 nr_written++; 305 } 306 } 307 } 308 309 static void b43_set_all_gains(struct b43_wldev *dev, 310 s16 first, s16 second, s16 third) 311 { 312 struct b43_phy *phy = &dev->phy; 313 u16 i; 314 u16 start = 0x08, end = 0x18; 315 u16 tmp; 316 u16 table; 317 318 if (phy->rev <= 1) { 319 start = 0x10; 320 end = 0x20; 321 } 322 323 table = B43_OFDMTAB_GAINX; 324 if (phy->rev <= 1) 325 table = B43_OFDMTAB_GAINX_R1; 326 for (i = 0; i < 4; i++) 327 b43_ofdmtab_write16(dev, table, i, first); 328 329 for (i = start; i < end; i++) 330 b43_ofdmtab_write16(dev, table, i, second); 331 332 if (third != -1) { 333 tmp = ((u16) third << 14) | ((u16) third << 6); 334 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp); 335 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp); 336 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp); 337 } 338 b43_dummy_transmission(dev, false, true); 339 } 340 341 static void b43_set_original_gains(struct b43_wldev *dev) 342 { 343 struct b43_phy *phy = &dev->phy; 344 u16 i, tmp; 345 u16 table; 346 u16 start = 0x0008, end = 0x0018; 347 348 if (phy->rev <= 1) { 349 start = 0x0010; 350 end = 0x0020; 351 } 352 353 table = B43_OFDMTAB_GAINX; 354 if (phy->rev <= 1) 355 table = B43_OFDMTAB_GAINX_R1; 356 for (i = 0; i < 4; i++) { 357 tmp = (i & 0xFFFC); 358 tmp |= (i & 0x0001) << 1; 359 tmp |= (i & 0x0002) >> 1; 360 361 b43_ofdmtab_write16(dev, table, i, tmp); 362 } 363 364 for (i = start; i < end; i++) 365 b43_ofdmtab_write16(dev, table, i, i - start); 366 367 b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040); 368 b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040); 369 b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000); 370 b43_dummy_transmission(dev, false, true); 371 } 372 373 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ 374 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val) 375 { 376 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); 377 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val); 378 } 379 380 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ 381 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset) 382 { 383 u16 val; 384 385 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset); 386 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA); 387 388 return (s16) val; 389 } 390 391 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ 392 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val) 393 { 394 u16 i; 395 s16 tmp; 396 397 for (i = 0; i < 64; i++) { 398 tmp = b43_nrssi_hw_read(dev, i); 399 tmp -= val; 400 tmp = clamp_val(tmp, -32, 31); 401 b43_nrssi_hw_write(dev, i, tmp); 402 } 403 } 404 405 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */ 406 static void b43_nrssi_mem_update(struct b43_wldev *dev) 407 { 408 struct b43_phy_g *gphy = dev->phy.g; 409 s16 i, delta; 410 s32 tmp; 411 412 delta = 0x1F - gphy->nrssi[0]; 413 for (i = 0; i < 64; i++) { 414 tmp = (i - delta) * gphy->nrssislope; 415 tmp /= 0x10000; 416 tmp += 0x3A; 417 tmp = clamp_val(tmp, 0, 0x3F); 418 gphy->nrssi_lt[i] = tmp; 419 } 420 } 421 422 static void b43_calc_nrssi_offset(struct b43_wldev *dev) 423 { 424 struct b43_phy *phy = &dev->phy; 425 u16 backup[20] = { 0 }; 426 s16 v47F; 427 u16 i; 428 u16 saved = 0xFFFF; 429 430 backup[0] = b43_phy_read(dev, 0x0001); 431 backup[1] = b43_phy_read(dev, 0x0811); 432 backup[2] = b43_phy_read(dev, 0x0812); 433 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 434 backup[3] = b43_phy_read(dev, 0x0814); 435 backup[4] = b43_phy_read(dev, 0x0815); 436 } 437 backup[5] = b43_phy_read(dev, 0x005A); 438 backup[6] = b43_phy_read(dev, 0x0059); 439 backup[7] = b43_phy_read(dev, 0x0058); 440 backup[8] = b43_phy_read(dev, 0x000A); 441 backup[9] = b43_phy_read(dev, 0x0003); 442 backup[10] = b43_radio_read16(dev, 0x007A); 443 backup[11] = b43_radio_read16(dev, 0x0043); 444 445 b43_phy_mask(dev, 0x0429, 0x7FFF); 446 b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000); 447 b43_phy_set(dev, 0x0811, 0x000C); 448 b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004); 449 b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2)); 450 if (phy->rev >= 6) { 451 backup[12] = b43_phy_read(dev, 0x002E); 452 backup[13] = b43_phy_read(dev, 0x002F); 453 backup[14] = b43_phy_read(dev, 0x080F); 454 backup[15] = b43_phy_read(dev, 0x0810); 455 backup[16] = b43_phy_read(dev, 0x0801); 456 backup[17] = b43_phy_read(dev, 0x0060); 457 backup[18] = b43_phy_read(dev, 0x0014); 458 backup[19] = b43_phy_read(dev, 0x0478); 459 460 b43_phy_write(dev, 0x002E, 0); 461 b43_phy_write(dev, 0x002F, 0); 462 b43_phy_write(dev, 0x080F, 0); 463 b43_phy_write(dev, 0x0810, 0); 464 b43_phy_set(dev, 0x0478, 0x0100); 465 b43_phy_set(dev, 0x0801, 0x0040); 466 b43_phy_set(dev, 0x0060, 0x0040); 467 b43_phy_set(dev, 0x0014, 0x0200); 468 } 469 b43_radio_set(dev, 0x007A, 0x0070); 470 b43_radio_set(dev, 0x007A, 0x0080); 471 udelay(30); 472 473 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); 474 if (v47F >= 0x20) 475 v47F -= 0x40; 476 if (v47F == 31) { 477 for (i = 7; i >= 4; i--) { 478 b43_radio_write16(dev, 0x007B, i); 479 udelay(20); 480 v47F = 481 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); 482 if (v47F >= 0x20) 483 v47F -= 0x40; 484 if (v47F < 31 && saved == 0xFFFF) 485 saved = i; 486 } 487 if (saved == 0xFFFF) 488 saved = 4; 489 } else { 490 b43_radio_mask(dev, 0x007A, 0x007F); 491 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 492 b43_phy_set(dev, 0x0814, 0x0001); 493 b43_phy_mask(dev, 0x0815, 0xFFFE); 494 } 495 b43_phy_set(dev, 0x0811, 0x000C); 496 b43_phy_set(dev, 0x0812, 0x000C); 497 b43_phy_set(dev, 0x0811, 0x0030); 498 b43_phy_set(dev, 0x0812, 0x0030); 499 b43_phy_write(dev, 0x005A, 0x0480); 500 b43_phy_write(dev, 0x0059, 0x0810); 501 b43_phy_write(dev, 0x0058, 0x000D); 502 if (phy->rev == 0) { 503 b43_phy_write(dev, 0x0003, 0x0122); 504 } else { 505 b43_phy_set(dev, 0x000A, 0x2000); 506 } 507 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 508 b43_phy_set(dev, 0x0814, 0x0004); 509 b43_phy_mask(dev, 0x0815, 0xFFFB); 510 } 511 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); 512 b43_radio_set(dev, 0x007A, 0x000F); 513 b43_set_all_gains(dev, 3, 0, 1); 514 b43_radio_maskset(dev, 0x0043, 0x00F0, 0x000F); 515 udelay(30); 516 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); 517 if (v47F >= 0x20) 518 v47F -= 0x40; 519 if (v47F == -32) { 520 for (i = 0; i < 4; i++) { 521 b43_radio_write16(dev, 0x007B, i); 522 udelay(20); 523 v47F = 524 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 525 0x003F); 526 if (v47F >= 0x20) 527 v47F -= 0x40; 528 if (v47F > -31 && saved == 0xFFFF) 529 saved = i; 530 } 531 if (saved == 0xFFFF) 532 saved = 3; 533 } else 534 saved = 0; 535 } 536 b43_radio_write16(dev, 0x007B, saved); 537 538 if (phy->rev >= 6) { 539 b43_phy_write(dev, 0x002E, backup[12]); 540 b43_phy_write(dev, 0x002F, backup[13]); 541 b43_phy_write(dev, 0x080F, backup[14]); 542 b43_phy_write(dev, 0x0810, backup[15]); 543 } 544 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 545 b43_phy_write(dev, 0x0814, backup[3]); 546 b43_phy_write(dev, 0x0815, backup[4]); 547 } 548 b43_phy_write(dev, 0x005A, backup[5]); 549 b43_phy_write(dev, 0x0059, backup[6]); 550 b43_phy_write(dev, 0x0058, backup[7]); 551 b43_phy_write(dev, 0x000A, backup[8]); 552 b43_phy_write(dev, 0x0003, backup[9]); 553 b43_radio_write16(dev, 0x0043, backup[11]); 554 b43_radio_write16(dev, 0x007A, backup[10]); 555 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2); 556 b43_phy_set(dev, 0x0429, 0x8000); 557 b43_set_original_gains(dev); 558 if (phy->rev >= 6) { 559 b43_phy_write(dev, 0x0801, backup[16]); 560 b43_phy_write(dev, 0x0060, backup[17]); 561 b43_phy_write(dev, 0x0014, backup[18]); 562 b43_phy_write(dev, 0x0478, backup[19]); 563 } 564 b43_phy_write(dev, 0x0001, backup[0]); 565 b43_phy_write(dev, 0x0812, backup[2]); 566 b43_phy_write(dev, 0x0811, backup[1]); 567 } 568 569 static void b43_calc_nrssi_slope(struct b43_wldev *dev) 570 { 571 struct b43_phy *phy = &dev->phy; 572 struct b43_phy_g *gphy = phy->g; 573 u16 backup[18] = { 0 }; 574 u16 tmp; 575 s16 nrssi0, nrssi1; 576 577 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 578 579 if (phy->radio_rev >= 9) 580 return; 581 if (phy->radio_rev == 8) 582 b43_calc_nrssi_offset(dev); 583 584 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); 585 b43_phy_mask(dev, 0x0802, 0xFFFC); 586 backup[7] = b43_read16(dev, 0x03E2); 587 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000); 588 backup[0] = b43_radio_read16(dev, 0x007A); 589 backup[1] = b43_radio_read16(dev, 0x0052); 590 backup[2] = b43_radio_read16(dev, 0x0043); 591 backup[3] = b43_phy_read(dev, 0x0015); 592 backup[4] = b43_phy_read(dev, 0x005A); 593 backup[5] = b43_phy_read(dev, 0x0059); 594 backup[6] = b43_phy_read(dev, 0x0058); 595 backup[8] = b43_read16(dev, 0x03E6); 596 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT); 597 if (phy->rev >= 3) { 598 backup[10] = b43_phy_read(dev, 0x002E); 599 backup[11] = b43_phy_read(dev, 0x002F); 600 backup[12] = b43_phy_read(dev, 0x080F); 601 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL); 602 backup[14] = b43_phy_read(dev, 0x0801); 603 backup[15] = b43_phy_read(dev, 0x0060); 604 backup[16] = b43_phy_read(dev, 0x0014); 605 backup[17] = b43_phy_read(dev, 0x0478); 606 b43_phy_write(dev, 0x002E, 0); 607 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0); 608 switch (phy->rev) { 609 case 4: 610 case 6: 611 case 7: 612 b43_phy_set(dev, 0x0478, 0x0100); 613 b43_phy_set(dev, 0x0801, 0x0040); 614 break; 615 case 3: 616 case 5: 617 b43_phy_mask(dev, 0x0801, 0xFFBF); 618 break; 619 } 620 b43_phy_set(dev, 0x0060, 0x0040); 621 b43_phy_set(dev, 0x0014, 0x0200); 622 } 623 b43_radio_set(dev, 0x007A, 0x0070); 624 b43_set_all_gains(dev, 0, 8, 0); 625 b43_radio_mask(dev, 0x007A, 0x00F7); 626 if (phy->rev >= 2) { 627 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030); 628 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010); 629 } 630 b43_radio_set(dev, 0x007A, 0x0080); 631 udelay(20); 632 633 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); 634 if (nrssi0 >= 0x0020) 635 nrssi0 -= 0x0040; 636 637 b43_radio_mask(dev, 0x007A, 0x007F); 638 if (phy->rev >= 2) { 639 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040); 640 } 641 642 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 643 b43_read16(dev, B43_MMIO_CHANNEL_EXT) 644 | 0x2000); 645 b43_radio_set(dev, 0x007A, 0x000F); 646 b43_phy_write(dev, 0x0015, 0xF330); 647 if (phy->rev >= 2) { 648 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020); 649 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020); 650 } 651 652 b43_set_all_gains(dev, 3, 0, 1); 653 if (phy->radio_rev == 8) { 654 b43_radio_write16(dev, 0x0043, 0x001F); 655 } else { 656 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F; 657 b43_radio_write16(dev, 0x0052, tmp | 0x0060); 658 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0; 659 b43_radio_write16(dev, 0x0043, tmp | 0x0009); 660 } 661 b43_phy_write(dev, 0x005A, 0x0480); 662 b43_phy_write(dev, 0x0059, 0x0810); 663 b43_phy_write(dev, 0x0058, 0x000D); 664 udelay(20); 665 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F); 666 if (nrssi1 >= 0x0020) 667 nrssi1 -= 0x0040; 668 if (nrssi0 == nrssi1) 669 gphy->nrssislope = 0x00010000; 670 else 671 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1); 672 if (nrssi0 >= -4) { 673 gphy->nrssi[0] = nrssi1; 674 gphy->nrssi[1] = nrssi0; 675 } 676 if (phy->rev >= 3) { 677 b43_phy_write(dev, 0x002E, backup[10]); 678 b43_phy_write(dev, 0x002F, backup[11]); 679 b43_phy_write(dev, 0x080F, backup[12]); 680 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]); 681 } 682 if (phy->rev >= 2) { 683 b43_phy_mask(dev, 0x0812, 0xFFCF); 684 b43_phy_mask(dev, 0x0811, 0xFFCF); 685 } 686 687 b43_radio_write16(dev, 0x007A, backup[0]); 688 b43_radio_write16(dev, 0x0052, backup[1]); 689 b43_radio_write16(dev, 0x0043, backup[2]); 690 b43_write16(dev, 0x03E2, backup[7]); 691 b43_write16(dev, 0x03E6, backup[8]); 692 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]); 693 b43_phy_write(dev, 0x0015, backup[3]); 694 b43_phy_write(dev, 0x005A, backup[4]); 695 b43_phy_write(dev, 0x0059, backup[5]); 696 b43_phy_write(dev, 0x0058, backup[6]); 697 b43_synth_pu_workaround(dev, phy->channel); 698 b43_phy_set(dev, 0x0802, (0x0001 | 0x0002)); 699 b43_set_original_gains(dev); 700 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); 701 if (phy->rev >= 3) { 702 b43_phy_write(dev, 0x0801, backup[14]); 703 b43_phy_write(dev, 0x0060, backup[15]); 704 b43_phy_write(dev, 0x0014, backup[16]); 705 b43_phy_write(dev, 0x0478, backup[17]); 706 } 707 b43_nrssi_mem_update(dev); 708 b43_calc_nrssi_threshold(dev); 709 } 710 711 static void b43_calc_nrssi_threshold(struct b43_wldev *dev) 712 { 713 struct b43_phy *phy = &dev->phy; 714 struct b43_phy_g *gphy = phy->g; 715 s32 a, b; 716 s16 tmp16; 717 u16 tmp_u16; 718 719 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 720 721 if (!phy->gmode || 722 !(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { 723 tmp16 = b43_nrssi_hw_read(dev, 0x20); 724 if (tmp16 >= 0x20) 725 tmp16 -= 0x40; 726 if (tmp16 < 3) { 727 b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB); 728 } else { 729 b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED); 730 } 731 } else { 732 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) { 733 a = 0xE; 734 b = 0xA; 735 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) { 736 a = 0x13; 737 b = 0x12; 738 } else { 739 a = 0xE; 740 b = 0x11; 741 } 742 743 a = a * (gphy->nrssi[1] - gphy->nrssi[0]); 744 a += (gphy->nrssi[0] << 6); 745 if (a < 32) 746 a += 31; 747 else 748 a += 32; 749 a = a >> 6; 750 a = clamp_val(a, -31, 31); 751 752 b = b * (gphy->nrssi[1] - gphy->nrssi[0]); 753 b += (gphy->nrssi[0] << 6); 754 if (b < 32) 755 b += 31; 756 else 757 b += 32; 758 b = b >> 6; 759 b = clamp_val(b, -31, 31); 760 761 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000; 762 tmp_u16 |= ((u32) b & 0x0000003F); 763 tmp_u16 |= (((u32) a & 0x0000003F) << 6); 764 b43_phy_write(dev, 0x048A, tmp_u16); 765 } 766 } 767 768 /* Stack implementation to save/restore values from the 769 * interference mitigation code. 770 * It is save to restore values in random order. 771 */ 772 static void _stack_save(u32 *_stackptr, size_t *stackidx, 773 u8 id, u16 offset, u16 value) 774 { 775 u32 *stackptr = &(_stackptr[*stackidx]); 776 777 B43_WARN_ON(offset & 0xF000); 778 B43_WARN_ON(id & 0xF0); 779 *stackptr = offset; 780 *stackptr |= ((u32) id) << 12; 781 *stackptr |= ((u32) value) << 16; 782 (*stackidx)++; 783 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE); 784 } 785 786 static u16 _stack_restore(u32 *stackptr, u8 id, u16 offset) 787 { 788 size_t i; 789 790 B43_WARN_ON(offset & 0xF000); 791 B43_WARN_ON(id & 0xF0); 792 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) { 793 if ((*stackptr & 0x00000FFF) != offset) 794 continue; 795 if (((*stackptr & 0x0000F000) >> 12) != id) 796 continue; 797 return ((*stackptr & 0xFFFF0000) >> 16); 798 } 799 B43_WARN_ON(1); 800 801 return 0; 802 } 803 804 #define phy_stacksave(offset) \ 805 do { \ 806 _stack_save(stack, &stackidx, 0x1, (offset), \ 807 b43_phy_read(dev, (offset))); \ 808 } while (0) 809 #define phy_stackrestore(offset) \ 810 do { \ 811 b43_phy_write(dev, (offset), \ 812 _stack_restore(stack, 0x1, \ 813 (offset))); \ 814 } while (0) 815 #define radio_stacksave(offset) \ 816 do { \ 817 _stack_save(stack, &stackidx, 0x2, (offset), \ 818 b43_radio_read16(dev, (offset))); \ 819 } while (0) 820 #define radio_stackrestore(offset) \ 821 do { \ 822 b43_radio_write16(dev, (offset), \ 823 _stack_restore(stack, 0x2, \ 824 (offset))); \ 825 } while (0) 826 #define ofdmtab_stacksave(table, offset) \ 827 do { \ 828 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \ 829 b43_ofdmtab_read16(dev, (table), (offset))); \ 830 } while (0) 831 #define ofdmtab_stackrestore(table, offset) \ 832 do { \ 833 b43_ofdmtab_write16(dev, (table), (offset), \ 834 _stack_restore(stack, 0x3, \ 835 (offset)|(table))); \ 836 } while (0) 837 838 static void 839 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode) 840 { 841 struct b43_phy *phy = &dev->phy; 842 struct b43_phy_g *gphy = phy->g; 843 u16 tmp, flipped; 844 size_t stackidx = 0; 845 u32 *stack = gphy->interfstack; 846 847 switch (mode) { 848 case B43_INTERFMODE_NONWLAN: 849 if (phy->rev != 1) { 850 b43_phy_set(dev, 0x042B, 0x0800); 851 b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000); 852 break; 853 } 854 radio_stacksave(0x0078); 855 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E); 856 B43_WARN_ON(tmp > 15); 857 flipped = bitrev4(tmp); 858 if (flipped < 10 && flipped >= 8) 859 flipped = 7; 860 else if (flipped >= 10) 861 flipped -= 3; 862 flipped = (bitrev4(flipped) << 1) | 0x0020; 863 b43_radio_write16(dev, 0x0078, flipped); 864 865 b43_calc_nrssi_threshold(dev); 866 867 phy_stacksave(0x0406); 868 b43_phy_write(dev, 0x0406, 0x7E28); 869 870 b43_phy_set(dev, 0x042B, 0x0800); 871 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000); 872 873 phy_stacksave(0x04A0); 874 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008); 875 phy_stacksave(0x04A1); 876 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605); 877 phy_stacksave(0x04A2); 878 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204); 879 phy_stacksave(0x04A8); 880 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803); 881 phy_stacksave(0x04AB); 882 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605); 883 884 phy_stacksave(0x04A7); 885 b43_phy_write(dev, 0x04A7, 0x0002); 886 phy_stacksave(0x04A3); 887 b43_phy_write(dev, 0x04A3, 0x287A); 888 phy_stacksave(0x04A9); 889 b43_phy_write(dev, 0x04A9, 0x2027); 890 phy_stacksave(0x0493); 891 b43_phy_write(dev, 0x0493, 0x32F5); 892 phy_stacksave(0x04AA); 893 b43_phy_write(dev, 0x04AA, 0x2027); 894 phy_stacksave(0x04AC); 895 b43_phy_write(dev, 0x04AC, 0x32F5); 896 break; 897 case B43_INTERFMODE_MANUALWLAN: 898 if (b43_phy_read(dev, 0x0033) & 0x0800) 899 break; 900 901 gphy->aci_enable = true; 902 903 phy_stacksave(B43_PHY_RADIO_BITFIELD); 904 phy_stacksave(B43_PHY_G_CRS); 905 if (phy->rev < 2) { 906 phy_stacksave(0x0406); 907 } else { 908 phy_stacksave(0x04C0); 909 phy_stacksave(0x04C1); 910 } 911 phy_stacksave(0x0033); 912 phy_stacksave(0x04A7); 913 phy_stacksave(0x04A3); 914 phy_stacksave(0x04A9); 915 phy_stacksave(0x04AA); 916 phy_stacksave(0x04AC); 917 phy_stacksave(0x0493); 918 phy_stacksave(0x04A1); 919 phy_stacksave(0x04A0); 920 phy_stacksave(0x04A2); 921 phy_stacksave(0x048A); 922 phy_stacksave(0x04A8); 923 phy_stacksave(0x04AB); 924 if (phy->rev == 2) { 925 phy_stacksave(0x04AD); 926 phy_stacksave(0x04AE); 927 } else if (phy->rev >= 3) { 928 phy_stacksave(0x04AD); 929 phy_stacksave(0x0415); 930 phy_stacksave(0x0416); 931 phy_stacksave(0x0417); 932 ofdmtab_stacksave(0x1A00, 0x2); 933 ofdmtab_stacksave(0x1A00, 0x3); 934 } 935 phy_stacksave(0x042B); 936 phy_stacksave(0x048C); 937 938 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000); 939 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002); 940 941 b43_phy_write(dev, 0x0033, 0x0800); 942 b43_phy_write(dev, 0x04A3, 0x2027); 943 b43_phy_write(dev, 0x04A9, 0x1CA8); 944 b43_phy_write(dev, 0x0493, 0x287A); 945 b43_phy_write(dev, 0x04AA, 0x1CA8); 946 b43_phy_write(dev, 0x04AC, 0x287A); 947 948 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A); 949 b43_phy_write(dev, 0x04A7, 0x000D); 950 951 if (phy->rev < 2) { 952 b43_phy_write(dev, 0x0406, 0xFF0D); 953 } else if (phy->rev == 2) { 954 b43_phy_write(dev, 0x04C0, 0xFFFF); 955 b43_phy_write(dev, 0x04C1, 0x00A9); 956 } else { 957 b43_phy_write(dev, 0x04C0, 0x00C1); 958 b43_phy_write(dev, 0x04C1, 0x0059); 959 } 960 961 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800); 962 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015); 963 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000); 964 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00); 965 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000); 966 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800); 967 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010); 968 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005); 969 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010); 970 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006); 971 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800); 972 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500); 973 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B); 974 975 if (phy->rev >= 3) { 976 b43_phy_mask(dev, 0x048A, 0x7FFF); 977 b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8); 978 b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8); 979 b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D); 980 } else { 981 b43_phy_set(dev, 0x048A, 0x1000); 982 b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000); 983 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW); 984 } 985 if (phy->rev >= 2) { 986 b43_phy_set(dev, 0x042B, 0x0800); 987 } 988 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200); 989 if (phy->rev == 2) { 990 b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F); 991 b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300); 992 } else if (phy->rev >= 6) { 993 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F); 994 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F); 995 b43_phy_mask(dev, 0x04AD, 0x00FF); 996 } 997 b43_calc_nrssi_slope(dev); 998 break; 999 default: 1000 B43_WARN_ON(1); 1001 } 1002 } 1003 1004 static void 1005 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode) 1006 { 1007 struct b43_phy *phy = &dev->phy; 1008 struct b43_phy_g *gphy = phy->g; 1009 u32 *stack = gphy->interfstack; 1010 1011 switch (mode) { 1012 case B43_INTERFMODE_NONWLAN: 1013 if (phy->rev != 1) { 1014 b43_phy_mask(dev, 0x042B, ~0x0800); 1015 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); 1016 break; 1017 } 1018 radio_stackrestore(0x0078); 1019 b43_calc_nrssi_threshold(dev); 1020 phy_stackrestore(0x0406); 1021 b43_phy_mask(dev, 0x042B, ~0x0800); 1022 if (!dev->bad_frames_preempt) { 1023 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11)); 1024 } 1025 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000); 1026 phy_stackrestore(0x04A0); 1027 phy_stackrestore(0x04A1); 1028 phy_stackrestore(0x04A2); 1029 phy_stackrestore(0x04A8); 1030 phy_stackrestore(0x04AB); 1031 phy_stackrestore(0x04A7); 1032 phy_stackrestore(0x04A3); 1033 phy_stackrestore(0x04A9); 1034 phy_stackrestore(0x0493); 1035 phy_stackrestore(0x04AA); 1036 phy_stackrestore(0x04AC); 1037 break; 1038 case B43_INTERFMODE_MANUALWLAN: 1039 if (!(b43_phy_read(dev, 0x0033) & 0x0800)) 1040 break; 1041 1042 gphy->aci_enable = false; 1043 1044 phy_stackrestore(B43_PHY_RADIO_BITFIELD); 1045 phy_stackrestore(B43_PHY_G_CRS); 1046 phy_stackrestore(0x0033); 1047 phy_stackrestore(0x04A3); 1048 phy_stackrestore(0x04A9); 1049 phy_stackrestore(0x0493); 1050 phy_stackrestore(0x04AA); 1051 phy_stackrestore(0x04AC); 1052 phy_stackrestore(0x04A0); 1053 phy_stackrestore(0x04A7); 1054 if (phy->rev >= 2) { 1055 phy_stackrestore(0x04C0); 1056 phy_stackrestore(0x04C1); 1057 } else 1058 phy_stackrestore(0x0406); 1059 phy_stackrestore(0x04A1); 1060 phy_stackrestore(0x04AB); 1061 phy_stackrestore(0x04A8); 1062 if (phy->rev == 2) { 1063 phy_stackrestore(0x04AD); 1064 phy_stackrestore(0x04AE); 1065 } else if (phy->rev >= 3) { 1066 phy_stackrestore(0x04AD); 1067 phy_stackrestore(0x0415); 1068 phy_stackrestore(0x0416); 1069 phy_stackrestore(0x0417); 1070 ofdmtab_stackrestore(0x1A00, 0x2); 1071 ofdmtab_stackrestore(0x1A00, 0x3); 1072 } 1073 phy_stackrestore(0x04A2); 1074 phy_stackrestore(0x048A); 1075 phy_stackrestore(0x042B); 1076 phy_stackrestore(0x048C); 1077 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW); 1078 b43_calc_nrssi_slope(dev); 1079 break; 1080 default: 1081 B43_WARN_ON(1); 1082 } 1083 } 1084 1085 #undef phy_stacksave 1086 #undef phy_stackrestore 1087 #undef radio_stacksave 1088 #undef radio_stackrestore 1089 #undef ofdmtab_stacksave 1090 #undef ofdmtab_stackrestore 1091 1092 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev) 1093 { 1094 u16 reg, index, ret; 1095 1096 static const u8 rcc_table[] = { 1097 0x02, 0x03, 0x01, 0x0F, 1098 0x06, 0x07, 0x05, 0x0F, 1099 0x0A, 0x0B, 0x09, 0x0F, 1100 0x0E, 0x0F, 0x0D, 0x0F, 1101 }; 1102 1103 reg = b43_radio_read16(dev, 0x60); 1104 index = (reg & 0x001E) >> 1; 1105 ret = rcc_table[index] << 1; 1106 ret |= (reg & 0x0001); 1107 ret |= 0x0020; 1108 1109 return ret; 1110 } 1111 1112 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0)) 1113 static u16 radio2050_rfover_val(struct b43_wldev *dev, 1114 u16 phy_register, unsigned int lpd) 1115 { 1116 struct b43_phy *phy = &dev->phy; 1117 struct b43_phy_g *gphy = phy->g; 1118 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1119 1120 if (!phy->gmode) 1121 return 0; 1122 1123 if (has_loopback_gain(phy)) { 1124 int max_lb_gain = gphy->max_lb_gain; 1125 u16 extlna; 1126 u16 i; 1127 1128 if (phy->radio_rev == 8) 1129 max_lb_gain += 0x3E; 1130 else 1131 max_lb_gain += 0x26; 1132 if (max_lb_gain >= 0x46) { 1133 extlna = 0x3000; 1134 max_lb_gain -= 0x46; 1135 } else if (max_lb_gain >= 0x3A) { 1136 extlna = 0x1000; 1137 max_lb_gain -= 0x3A; 1138 } else if (max_lb_gain >= 0x2E) { 1139 extlna = 0x2000; 1140 max_lb_gain -= 0x2E; 1141 } else { 1142 extlna = 0; 1143 max_lb_gain -= 0x10; 1144 } 1145 1146 for (i = 0; i < 16; i++) { 1147 max_lb_gain -= (i * 6); 1148 if (max_lb_gain < 6) 1149 break; 1150 } 1151 1152 if ((phy->rev < 7) || 1153 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { 1154 if (phy_register == B43_PHY_RFOVER) { 1155 return 0x1B3; 1156 } else if (phy_register == B43_PHY_RFOVERVAL) { 1157 extlna |= (i << 8); 1158 switch (lpd) { 1159 case LPD(0, 1, 1): 1160 return 0x0F92; 1161 case LPD(0, 0, 1): 1162 case LPD(1, 0, 1): 1163 return (0x0092 | extlna); 1164 case LPD(1, 0, 0): 1165 return (0x0093 | extlna); 1166 } 1167 B43_WARN_ON(1); 1168 } 1169 B43_WARN_ON(1); 1170 } else { 1171 if (phy_register == B43_PHY_RFOVER) { 1172 return 0x9B3; 1173 } else if (phy_register == B43_PHY_RFOVERVAL) { 1174 if (extlna) 1175 extlna |= 0x8000; 1176 extlna |= (i << 8); 1177 switch (lpd) { 1178 case LPD(0, 1, 1): 1179 return 0x8F92; 1180 case LPD(0, 0, 1): 1181 return (0x8092 | extlna); 1182 case LPD(1, 0, 1): 1183 return (0x2092 | extlna); 1184 case LPD(1, 0, 0): 1185 return (0x2093 | extlna); 1186 } 1187 B43_WARN_ON(1); 1188 } 1189 B43_WARN_ON(1); 1190 } 1191 } else { 1192 if ((phy->rev < 7) || 1193 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) { 1194 if (phy_register == B43_PHY_RFOVER) { 1195 return 0x1B3; 1196 } else if (phy_register == B43_PHY_RFOVERVAL) { 1197 switch (lpd) { 1198 case LPD(0, 1, 1): 1199 return 0x0FB2; 1200 case LPD(0, 0, 1): 1201 return 0x00B2; 1202 case LPD(1, 0, 1): 1203 return 0x30B2; 1204 case LPD(1, 0, 0): 1205 return 0x30B3; 1206 } 1207 B43_WARN_ON(1); 1208 } 1209 B43_WARN_ON(1); 1210 } else { 1211 if (phy_register == B43_PHY_RFOVER) { 1212 return 0x9B3; 1213 } else if (phy_register == B43_PHY_RFOVERVAL) { 1214 switch (lpd) { 1215 case LPD(0, 1, 1): 1216 return 0x8FB2; 1217 case LPD(0, 0, 1): 1218 return 0x80B2; 1219 case LPD(1, 0, 1): 1220 return 0x20B2; 1221 case LPD(1, 0, 0): 1222 return 0x20B3; 1223 } 1224 B43_WARN_ON(1); 1225 } 1226 B43_WARN_ON(1); 1227 } 1228 } 1229 return 0; 1230 } 1231 1232 struct init2050_saved_values { 1233 /* Core registers */ 1234 u16 reg_3EC; 1235 u16 reg_3E6; 1236 u16 reg_3F4; 1237 /* Radio registers */ 1238 u16 radio_43; 1239 u16 radio_51; 1240 u16 radio_52; 1241 /* PHY registers */ 1242 u16 phy_pgactl; 1243 u16 phy_cck_5A; 1244 u16 phy_cck_59; 1245 u16 phy_cck_58; 1246 u16 phy_cck_30; 1247 u16 phy_rfover; 1248 u16 phy_rfoverval; 1249 u16 phy_analogover; 1250 u16 phy_analogoverval; 1251 u16 phy_crs0; 1252 u16 phy_classctl; 1253 u16 phy_lo_mask; 1254 u16 phy_lo_ctl; 1255 u16 phy_syncctl; 1256 }; 1257 1258 static u16 b43_radio_init2050(struct b43_wldev *dev) 1259 { 1260 struct b43_phy *phy = &dev->phy; 1261 struct init2050_saved_values sav; 1262 u16 rcc; 1263 u16 radio78; 1264 u16 ret; 1265 u16 i, j; 1266 u32 tmp1 = 0, tmp2 = 0; 1267 1268 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */ 1269 1270 sav.radio_43 = b43_radio_read16(dev, 0x43); 1271 sav.radio_51 = b43_radio_read16(dev, 0x51); 1272 sav.radio_52 = b43_radio_read16(dev, 0x52); 1273 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL); 1274 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A)); 1275 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59)); 1276 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58)); 1277 1278 if (phy->type == B43_PHYTYPE_B) { 1279 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30)); 1280 sav.reg_3EC = b43_read16(dev, 0x3EC); 1281 1282 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF); 1283 b43_write16(dev, 0x3EC, 0x3F3F); 1284 } else if (phy->gmode || phy->rev >= 2) { 1285 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER); 1286 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); 1287 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER); 1288 sav.phy_analogoverval = 1289 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); 1290 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0); 1291 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL); 1292 1293 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003); 1294 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC); 1295 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF); 1296 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC); 1297 if (has_loopback_gain(phy)) { 1298 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK); 1299 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL); 1300 1301 if (phy->rev >= 3) 1302 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); 1303 else 1304 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); 1305 b43_phy_write(dev, B43_PHY_LO_CTL, 0); 1306 } 1307 1308 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1309 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, 1310 LPD(0, 1, 1))); 1311 b43_phy_write(dev, B43_PHY_RFOVER, 1312 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0)); 1313 } 1314 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000); 1315 1316 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL); 1317 b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F); 1318 sav.reg_3E6 = b43_read16(dev, 0x3E6); 1319 sav.reg_3F4 = b43_read16(dev, 0x3F4); 1320 1321 if (phy->analog == 0) { 1322 b43_write16(dev, 0x03E6, 0x0122); 1323 } else { 1324 if (phy->analog >= 2) { 1325 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40); 1326 } 1327 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 1328 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000)); 1329 } 1330 1331 rcc = b43_radio_core_calibration_value(dev); 1332 1333 if (phy->type == B43_PHYTYPE_B) 1334 b43_radio_write16(dev, 0x78, 0x26); 1335 if (phy->gmode || phy->rev >= 2) { 1336 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1337 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, 1338 LPD(0, 1, 1))); 1339 } 1340 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF); 1341 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403); 1342 if (phy->gmode || phy->rev >= 2) { 1343 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1344 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL, 1345 LPD(0, 0, 1))); 1346 } 1347 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0); 1348 b43_radio_set(dev, 0x51, 0x0004); 1349 if (phy->radio_rev == 8) { 1350 b43_radio_write16(dev, 0x43, 0x1F); 1351 } else { 1352 b43_radio_write16(dev, 0x52, 0); 1353 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x0009); 1354 } 1355 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); 1356 1357 for (i = 0; i < 16; i++) { 1358 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480); 1359 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); 1360 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); 1361 if (phy->gmode || phy->rev >= 2) { 1362 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1363 radio2050_rfover_val(dev, 1364 B43_PHY_RFOVERVAL, 1365 LPD(1, 0, 1))); 1366 } 1367 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); 1368 udelay(10); 1369 if (phy->gmode || phy->rev >= 2) { 1370 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1371 radio2050_rfover_val(dev, 1372 B43_PHY_RFOVERVAL, 1373 LPD(1, 0, 1))); 1374 } 1375 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); 1376 udelay(10); 1377 if (phy->gmode || phy->rev >= 2) { 1378 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1379 radio2050_rfover_val(dev, 1380 B43_PHY_RFOVERVAL, 1381 LPD(1, 0, 0))); 1382 } 1383 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); 1384 udelay(20); 1385 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 1386 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); 1387 if (phy->gmode || phy->rev >= 2) { 1388 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1389 radio2050_rfover_val(dev, 1390 B43_PHY_RFOVERVAL, 1391 LPD(1, 0, 1))); 1392 } 1393 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); 1394 } 1395 udelay(10); 1396 1397 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); 1398 tmp1++; 1399 tmp1 >>= 9; 1400 1401 for (i = 0; i < 16; i++) { 1402 radio78 = (bitrev4(i) << 1) | 0x0020; 1403 b43_radio_write16(dev, 0x78, radio78); 1404 udelay(10); 1405 for (j = 0; j < 16; j++) { 1406 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80); 1407 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); 1408 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); 1409 if (phy->gmode || phy->rev >= 2) { 1410 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1411 radio2050_rfover_val(dev, 1412 B43_PHY_RFOVERVAL, 1413 LPD(1, 0, 1414 1))); 1415 } 1416 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); 1417 udelay(10); 1418 if (phy->gmode || phy->rev >= 2) { 1419 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1420 radio2050_rfover_val(dev, 1421 B43_PHY_RFOVERVAL, 1422 LPD(1, 0, 1423 1))); 1424 } 1425 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0); 1426 udelay(10); 1427 if (phy->gmode || phy->rev >= 2) { 1428 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1429 radio2050_rfover_val(dev, 1430 B43_PHY_RFOVERVAL, 1431 LPD(1, 0, 1432 0))); 1433 } 1434 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0); 1435 udelay(10); 1436 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 1437 b43_phy_write(dev, B43_PHY_CCK(0x58), 0); 1438 if (phy->gmode || phy->rev >= 2) { 1439 b43_phy_write(dev, B43_PHY_RFOVERVAL, 1440 radio2050_rfover_val(dev, 1441 B43_PHY_RFOVERVAL, 1442 LPD(1, 0, 1443 1))); 1444 } 1445 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0); 1446 } 1447 tmp2++; 1448 tmp2 >>= 8; 1449 if (tmp1 < tmp2) 1450 break; 1451 } 1452 1453 /* Restore the registers */ 1454 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl); 1455 b43_radio_write16(dev, 0x51, sav.radio_51); 1456 b43_radio_write16(dev, 0x52, sav.radio_52); 1457 b43_radio_write16(dev, 0x43, sav.radio_43); 1458 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A); 1459 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59); 1460 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58); 1461 b43_write16(dev, 0x3E6, sav.reg_3E6); 1462 if (phy->analog != 0) 1463 b43_write16(dev, 0x3F4, sav.reg_3F4); 1464 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl); 1465 b43_synth_pu_workaround(dev, phy->channel); 1466 if (phy->type == B43_PHYTYPE_B) { 1467 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30); 1468 b43_write16(dev, 0x3EC, sav.reg_3EC); 1469 } else if (phy->gmode) { 1470 b43_write16(dev, B43_MMIO_PHY_RADIO, 1471 b43_read16(dev, B43_MMIO_PHY_RADIO) 1472 & 0x7FFF); 1473 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover); 1474 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval); 1475 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover); 1476 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 1477 sav.phy_analogoverval); 1478 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0); 1479 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl); 1480 if (has_loopback_gain(phy)) { 1481 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask); 1482 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl); 1483 } 1484 } 1485 if (i > 15) 1486 ret = radio78; 1487 else 1488 ret = rcc; 1489 1490 return ret; 1491 } 1492 1493 static void b43_phy_initb5(struct b43_wldev *dev) 1494 { 1495 struct b43_phy *phy = &dev->phy; 1496 struct b43_phy_g *gphy = phy->g; 1497 u16 offset, value; 1498 u8 old_channel; 1499 1500 if (phy->analog == 1) { 1501 b43_radio_set(dev, 0x007A, 0x0050); 1502 } 1503 if ((dev->dev->board_vendor != SSB_BOARDVENDOR_BCM) && 1504 (dev->dev->board_type != SSB_BOARD_BU4306)) { 1505 value = 0x2120; 1506 for (offset = 0x00A8; offset < 0x00C7; offset++) { 1507 b43_phy_write(dev, offset, value); 1508 value += 0x202; 1509 } 1510 } 1511 b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700); 1512 if (phy->radio_ver == 0x2050) 1513 b43_phy_write(dev, 0x0038, 0x0667); 1514 1515 if (phy->gmode || phy->rev >= 2) { 1516 if (phy->radio_ver == 0x2050) { 1517 b43_radio_set(dev, 0x007A, 0x0020); 1518 b43_radio_set(dev, 0x0051, 0x0004); 1519 } 1520 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000); 1521 1522 b43_phy_set(dev, 0x0802, 0x0100); 1523 b43_phy_set(dev, 0x042B, 0x2000); 1524 1525 b43_phy_write(dev, 0x001C, 0x186A); 1526 1527 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900); 1528 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064); 1529 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A); 1530 } 1531 1532 if (dev->bad_frames_preempt) { 1533 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11)); 1534 } 1535 1536 if (phy->analog == 1) { 1537 b43_phy_write(dev, 0x0026, 0xCE00); 1538 b43_phy_write(dev, 0x0021, 0x3763); 1539 b43_phy_write(dev, 0x0022, 0x1BC3); 1540 b43_phy_write(dev, 0x0023, 0x06F9); 1541 b43_phy_write(dev, 0x0024, 0x037E); 1542 } else 1543 b43_phy_write(dev, 0x0026, 0xCC00); 1544 b43_phy_write(dev, 0x0030, 0x00C6); 1545 b43_write16(dev, 0x03EC, 0x3F22); 1546 1547 if (phy->analog == 1) 1548 b43_phy_write(dev, 0x0020, 0x3E1C); 1549 else 1550 b43_phy_write(dev, 0x0020, 0x301C); 1551 1552 if (phy->analog == 0) 1553 b43_write16(dev, 0x03E4, 0x3000); 1554 1555 old_channel = phy->channel; 1556 /* Force to channel 7, even if not supported. */ 1557 b43_gphy_channel_switch(dev, 7, 0); 1558 1559 if (phy->radio_ver != 0x2050) { 1560 b43_radio_write16(dev, 0x0075, 0x0080); 1561 b43_radio_write16(dev, 0x0079, 0x0081); 1562 } 1563 1564 b43_radio_write16(dev, 0x0050, 0x0020); 1565 b43_radio_write16(dev, 0x0050, 0x0023); 1566 1567 if (phy->radio_ver == 0x2050) { 1568 b43_radio_write16(dev, 0x0050, 0x0020); 1569 b43_radio_write16(dev, 0x005A, 0x0070); 1570 } 1571 1572 b43_radio_write16(dev, 0x005B, 0x007B); 1573 b43_radio_write16(dev, 0x005C, 0x00B0); 1574 1575 b43_radio_set(dev, 0x007A, 0x0007); 1576 1577 b43_gphy_channel_switch(dev, old_channel, 0); 1578 1579 b43_phy_write(dev, 0x0014, 0x0080); 1580 b43_phy_write(dev, 0x0032, 0x00CA); 1581 b43_phy_write(dev, 0x002A, 0x88A3); 1582 1583 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); 1584 1585 if (phy->radio_ver == 0x2050) 1586 b43_radio_write16(dev, 0x005D, 0x000D); 1587 1588 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004); 1589 } 1590 1591 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/B6 */ 1592 static void b43_phy_initb6(struct b43_wldev *dev) 1593 { 1594 struct b43_phy *phy = &dev->phy; 1595 struct b43_phy_g *gphy = phy->g; 1596 u16 offset, val; 1597 u8 old_channel; 1598 1599 b43_phy_write(dev, 0x003E, 0x817A); 1600 b43_radio_write16(dev, 0x007A, 1601 (b43_radio_read16(dev, 0x007A) | 0x0058)); 1602 if (phy->radio_rev == 4 || phy->radio_rev == 5) { 1603 b43_radio_write16(dev, 0x51, 0x37); 1604 b43_radio_write16(dev, 0x52, 0x70); 1605 b43_radio_write16(dev, 0x53, 0xB3); 1606 b43_radio_write16(dev, 0x54, 0x9B); 1607 b43_radio_write16(dev, 0x5A, 0x88); 1608 b43_radio_write16(dev, 0x5B, 0x88); 1609 b43_radio_write16(dev, 0x5D, 0x88); 1610 b43_radio_write16(dev, 0x5E, 0x88); 1611 b43_radio_write16(dev, 0x7D, 0x88); 1612 b43_hf_write(dev, b43_hf_read(dev) 1613 | B43_HF_TSSIRPSMW); 1614 } 1615 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */ 1616 if (phy->radio_rev == 8) { 1617 b43_radio_write16(dev, 0x51, 0); 1618 b43_radio_write16(dev, 0x52, 0x40); 1619 b43_radio_write16(dev, 0x53, 0xB7); 1620 b43_radio_write16(dev, 0x54, 0x98); 1621 b43_radio_write16(dev, 0x5A, 0x88); 1622 b43_radio_write16(dev, 0x5B, 0x6B); 1623 b43_radio_write16(dev, 0x5C, 0x0F); 1624 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_ALTIQ) { 1625 b43_radio_write16(dev, 0x5D, 0xFA); 1626 b43_radio_write16(dev, 0x5E, 0xD8); 1627 } else { 1628 b43_radio_write16(dev, 0x5D, 0xF5); 1629 b43_radio_write16(dev, 0x5E, 0xB8); 1630 } 1631 b43_radio_write16(dev, 0x0073, 0x0003); 1632 b43_radio_write16(dev, 0x007D, 0x00A8); 1633 b43_radio_write16(dev, 0x007C, 0x0001); 1634 b43_radio_write16(dev, 0x007E, 0x0008); 1635 } 1636 val = 0x1E1F; 1637 for (offset = 0x0088; offset < 0x0098; offset++) { 1638 b43_phy_write(dev, offset, val); 1639 val -= 0x0202; 1640 } 1641 val = 0x3E3F; 1642 for (offset = 0x0098; offset < 0x00A8; offset++) { 1643 b43_phy_write(dev, offset, val); 1644 val -= 0x0202; 1645 } 1646 val = 0x2120; 1647 for (offset = 0x00A8; offset < 0x00C8; offset++) { 1648 b43_phy_write(dev, offset, (val & 0x3F3F)); 1649 val += 0x0202; 1650 } 1651 if (phy->type == B43_PHYTYPE_G) { 1652 b43_radio_set(dev, 0x007A, 0x0020); 1653 b43_radio_set(dev, 0x0051, 0x0004); 1654 b43_phy_set(dev, 0x0802, 0x0100); 1655 b43_phy_set(dev, 0x042B, 0x2000); 1656 b43_phy_write(dev, 0x5B, 0); 1657 b43_phy_write(dev, 0x5C, 0); 1658 } 1659 1660 old_channel = phy->channel; 1661 if (old_channel >= 8) 1662 b43_gphy_channel_switch(dev, 1, 0); 1663 else 1664 b43_gphy_channel_switch(dev, 13, 0); 1665 1666 b43_radio_write16(dev, 0x0050, 0x0020); 1667 b43_radio_write16(dev, 0x0050, 0x0023); 1668 udelay(40); 1669 if (phy->radio_rev < 6 || phy->radio_rev == 8) { 1670 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C) 1671 | 0x0002)); 1672 b43_radio_write16(dev, 0x50, 0x20); 1673 } 1674 if (phy->radio_rev <= 2) { 1675 b43_radio_write16(dev, 0x50, 0x20); 1676 b43_radio_write16(dev, 0x5A, 0x70); 1677 b43_radio_write16(dev, 0x5B, 0x7B); 1678 b43_radio_write16(dev, 0x5C, 0xB0); 1679 } 1680 b43_radio_maskset(dev, 0x007A, 0x00F8, 0x0007); 1681 1682 b43_gphy_channel_switch(dev, old_channel, 0); 1683 1684 b43_phy_write(dev, 0x0014, 0x0200); 1685 if (phy->radio_rev >= 6) 1686 b43_phy_write(dev, 0x2A, 0x88C2); 1687 else 1688 b43_phy_write(dev, 0x2A, 0x8AC0); 1689 b43_phy_write(dev, 0x0038, 0x0668); 1690 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control); 1691 if (phy->radio_rev == 4 || phy->radio_rev == 5) 1692 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003); 1693 if (phy->radio_rev <= 2) 1694 b43_radio_write16(dev, 0x005D, 0x000D); 1695 1696 if (phy->analog == 4) { 1697 b43_write16(dev, 0x3E4, 9); 1698 b43_phy_mask(dev, 0x61, 0x0FFF); 1699 } else { 1700 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004); 1701 } 1702 if (phy->type == B43_PHYTYPE_B) 1703 B43_WARN_ON(1); 1704 else if (phy->type == B43_PHYTYPE_G) 1705 b43_write16(dev, 0x03E6, 0x0); 1706 } 1707 1708 static void b43_calc_loopback_gain(struct b43_wldev *dev) 1709 { 1710 struct b43_phy *phy = &dev->phy; 1711 struct b43_phy_g *gphy = phy->g; 1712 u16 backup_phy[16] = { 0 }; 1713 u16 backup_radio[3]; 1714 u16 backup_bband; 1715 u16 i, j, loop_i_max; 1716 u16 trsw_rx; 1717 u16 loop1_outer_done, loop1_inner_done; 1718 1719 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0); 1720 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG); 1721 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER); 1722 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL); 1723 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1724 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER); 1725 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL); 1726 } 1727 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A)); 1728 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59)); 1729 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58)); 1730 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A)); 1731 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03)); 1732 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK); 1733 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL); 1734 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B)); 1735 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL); 1736 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE); 1737 backup_bband = gphy->bbatt.att; 1738 backup_radio[0] = b43_radio_read16(dev, 0x52); 1739 backup_radio[1] = b43_radio_read16(dev, 0x43); 1740 backup_radio[2] = b43_radio_read16(dev, 0x7A); 1741 1742 b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF); 1743 b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000); 1744 b43_phy_set(dev, B43_PHY_RFOVER, 0x0002); 1745 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD); 1746 b43_phy_set(dev, B43_PHY_RFOVER, 0x0001); 1747 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE); 1748 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1749 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001); 1750 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE); 1751 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002); 1752 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD); 1753 } 1754 b43_phy_set(dev, B43_PHY_RFOVER, 0x000C); 1755 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C); 1756 b43_phy_set(dev, B43_PHY_RFOVER, 0x0030); 1757 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10); 1758 1759 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780); 1760 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810); 1761 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D); 1762 1763 b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000); 1764 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1765 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004); 1766 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB); 1767 } 1768 b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40); 1769 1770 if (phy->radio_rev == 8) { 1771 b43_radio_write16(dev, 0x43, 0x000F); 1772 } else { 1773 b43_radio_write16(dev, 0x52, 0); 1774 b43_radio_maskset(dev, 0x43, 0xFFF0, 0x9); 1775 } 1776 b43_gphy_set_baseband_attenuation(dev, 11); 1777 1778 if (phy->rev >= 3) 1779 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020); 1780 else 1781 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020); 1782 b43_phy_write(dev, B43_PHY_LO_CTL, 0); 1783 1784 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01); 1785 b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800); 1786 1787 b43_phy_set(dev, B43_PHY_RFOVER, 0x0100); 1788 b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF); 1789 1790 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_EXTLNA) { 1791 if (phy->rev >= 7) { 1792 b43_phy_set(dev, B43_PHY_RFOVER, 0x0800); 1793 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000); 1794 } 1795 } 1796 b43_radio_mask(dev, 0x7A, 0x00F7); 1797 1798 j = 0; 1799 loop_i_max = (phy->radio_rev == 8) ? 15 : 9; 1800 for (i = 0; i < loop_i_max; i++) { 1801 for (j = 0; j < 16; j++) { 1802 b43_radio_write16(dev, 0x43, i); 1803 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); 1804 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); 1805 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); 1806 udelay(20); 1807 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) 1808 goto exit_loop1; 1809 } 1810 } 1811 exit_loop1: 1812 loop1_outer_done = i; 1813 loop1_inner_done = j; 1814 if (j >= 8) { 1815 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30); 1816 trsw_rx = 0x1B; 1817 for (j = j - 8; j < 16; j++) { 1818 b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8)); 1819 b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000); 1820 b43_phy_set(dev, B43_PHY_PGACTL, 0xF000); 1821 udelay(20); 1822 trsw_rx -= 3; 1823 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC) 1824 goto exit_loop2; 1825 } 1826 } else 1827 trsw_rx = 0x18; 1828 exit_loop2: 1829 1830 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */ 1831 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]); 1832 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]); 1833 } 1834 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]); 1835 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]); 1836 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]); 1837 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]); 1838 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]); 1839 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]); 1840 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]); 1841 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]); 1842 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]); 1843 1844 b43_gphy_set_baseband_attenuation(dev, backup_bband); 1845 1846 b43_radio_write16(dev, 0x52, backup_radio[0]); 1847 b43_radio_write16(dev, 0x43, backup_radio[1]); 1848 b43_radio_write16(dev, 0x7A, backup_radio[2]); 1849 1850 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003); 1851 udelay(10); 1852 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]); 1853 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]); 1854 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]); 1855 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]); 1856 1857 gphy->max_lb_gain = 1858 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11; 1859 gphy->trsw_rx_gain = trsw_rx * 2; 1860 } 1861 1862 static void b43_hardware_pctl_early_init(struct b43_wldev *dev) 1863 { 1864 struct b43_phy *phy = &dev->phy; 1865 1866 if (!b43_has_hardware_pctl(dev)) { 1867 b43_phy_write(dev, 0x047A, 0xC111); 1868 return; 1869 } 1870 1871 b43_phy_mask(dev, 0x0036, 0xFEFF); 1872 b43_phy_write(dev, 0x002F, 0x0202); 1873 b43_phy_set(dev, 0x047C, 0x0002); 1874 b43_phy_set(dev, 0x047A, 0xF000); 1875 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) { 1876 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); 1877 b43_phy_set(dev, 0x005D, 0x8000); 1878 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); 1879 b43_phy_write(dev, 0x002E, 0xC07F); 1880 b43_phy_set(dev, 0x0036, 0x0400); 1881 } else { 1882 b43_phy_set(dev, 0x0036, 0x0200); 1883 b43_phy_set(dev, 0x0036, 0x0400); 1884 b43_phy_mask(dev, 0x005D, 0x7FFF); 1885 b43_phy_mask(dev, 0x004F, 0xFFFE); 1886 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010); 1887 b43_phy_write(dev, 0x002E, 0xC07F); 1888 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010); 1889 } 1890 } 1891 1892 /* Hardware power control for G-PHY */ 1893 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev) 1894 { 1895 struct b43_phy *phy = &dev->phy; 1896 struct b43_phy_g *gphy = phy->g; 1897 1898 if (!b43_has_hardware_pctl(dev)) { 1899 /* No hardware power control */ 1900 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL); 1901 return; 1902 } 1903 1904 b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); 1905 b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi)); 1906 b43_gphy_tssi_power_lt_init(dev); 1907 b43_gphy_gain_lt_init(dev); 1908 b43_phy_mask(dev, 0x0060, 0xFFBF); 1909 b43_phy_write(dev, 0x0014, 0x0000); 1910 1911 B43_WARN_ON(phy->rev < 6); 1912 b43_phy_set(dev, 0x0478, 0x0800); 1913 b43_phy_mask(dev, 0x0478, 0xFEFF); 1914 b43_phy_mask(dev, 0x0801, 0xFFBF); 1915 1916 b43_gphy_dc_lt_init(dev, 1); 1917 1918 /* Enable hardware pctl in firmware. */ 1919 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL); 1920 } 1921 1922 /* Initialize B/G PHY power control */ 1923 static void b43_phy_init_pctl(struct b43_wldev *dev) 1924 { 1925 struct b43_phy *phy = &dev->phy; 1926 struct b43_phy_g *gphy = phy->g; 1927 struct b43_rfatt old_rfatt; 1928 struct b43_bbatt old_bbatt; 1929 u8 old_tx_control = 0; 1930 1931 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 1932 1933 if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && 1934 (dev->dev->board_type == SSB_BOARD_BU4306)) 1935 return; 1936 1937 b43_phy_write(dev, 0x0028, 0x8018); 1938 1939 /* This does something with the Analog... */ 1940 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0) 1941 & 0xFFDF); 1942 1943 if (!phy->gmode) 1944 return; 1945 b43_hardware_pctl_early_init(dev); 1946 if (gphy->cur_idle_tssi == 0) { 1947 if (phy->radio_ver == 0x2050 && phy->analog == 0) { 1948 b43_radio_maskset(dev, 0x0076, 0x00F7, 0x0084); 1949 } else { 1950 struct b43_rfatt rfatt; 1951 struct b43_bbatt bbatt; 1952 1953 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt)); 1954 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt)); 1955 old_tx_control = gphy->tx_control; 1956 1957 bbatt.att = 11; 1958 if (phy->radio_rev == 8) { 1959 rfatt.att = 15; 1960 rfatt.with_padmix = true; 1961 } else { 1962 rfatt.att = 9; 1963 rfatt.with_padmix = false; 1964 } 1965 b43_set_txpower_g(dev, &bbatt, &rfatt, 0); 1966 } 1967 b43_dummy_transmission(dev, false, true); 1968 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI); 1969 if (B43_DEBUG) { 1970 /* Current-Idle-TSSI sanity check. */ 1971 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) { 1972 b43dbg(dev->wl, 1973 "!WARNING! Idle-TSSI phy->cur_idle_tssi " 1974 "measuring failed. (cur=%d, tgt=%d). Disabling TX power " 1975 "adjustment.\n", gphy->cur_idle_tssi, 1976 gphy->tgt_idle_tssi); 1977 gphy->cur_idle_tssi = 0; 1978 } 1979 } 1980 if (phy->radio_ver == 0x2050 && phy->analog == 0) { 1981 b43_radio_mask(dev, 0x0076, 0xFF7B); 1982 } else { 1983 b43_set_txpower_g(dev, &old_bbatt, 1984 &old_rfatt, old_tx_control); 1985 } 1986 } 1987 b43_hardware_pctl_init_gphy(dev); 1988 b43_shm_clear_tssi(dev); 1989 } 1990 1991 static void b43_phy_inita(struct b43_wldev *dev) 1992 { 1993 struct b43_phy *phy = &dev->phy; 1994 1995 might_sleep(); 1996 1997 if (phy->rev >= 6) { 1998 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN) 1999 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010); 2000 else 2001 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010); 2002 } 2003 2004 b43_wa_all(dev); 2005 2006 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) 2007 b43_phy_maskset(dev, B43_PHY_OFDM(0x6E), 0xE000, 0x3CF); 2008 } 2009 2010 static void b43_phy_initg(struct b43_wldev *dev) 2011 { 2012 struct b43_phy *phy = &dev->phy; 2013 struct b43_phy_g *gphy = phy->g; 2014 u16 tmp; 2015 2016 if (phy->rev == 1) 2017 b43_phy_initb5(dev); 2018 else 2019 b43_phy_initb6(dev); 2020 2021 if (phy->rev >= 2 || phy->gmode) 2022 b43_phy_inita(dev); 2023 2024 if (phy->rev >= 2) { 2025 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0); 2026 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0); 2027 } 2028 if (phy->rev == 2) { 2029 b43_phy_write(dev, B43_PHY_RFOVER, 0); 2030 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); 2031 } 2032 if (phy->rev > 5) { 2033 b43_phy_write(dev, B43_PHY_RFOVER, 0x400); 2034 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0); 2035 } 2036 if (phy->gmode || phy->rev >= 2) { 2037 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM); 2038 tmp &= B43_PHYVER_VERSION; 2039 if (tmp == 3 || tmp == 5) { 2040 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816); 2041 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006); 2042 } 2043 if (tmp == 5) { 2044 b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00); 2045 } 2046 } 2047 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2) 2048 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78); 2049 if (phy->radio_rev == 8) { 2050 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80); 2051 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4); 2052 } 2053 if (has_loopback_gain(phy)) 2054 b43_calc_loopback_gain(dev); 2055 2056 if (phy->radio_rev != 8) { 2057 if (gphy->initval == 0xFFFF) 2058 gphy->initval = b43_radio_init2050(dev); 2059 else 2060 b43_radio_write16(dev, 0x0078, gphy->initval); 2061 } 2062 b43_lo_g_init(dev); 2063 if (has_tx_magnification(phy)) { 2064 b43_radio_write16(dev, 0x52, 2065 (b43_radio_read16(dev, 0x52) & 0xFF00) 2066 | gphy->lo_control->tx_bias | gphy-> 2067 lo_control->tx_magn); 2068 } else { 2069 b43_radio_maskset(dev, 0x52, 0xFFF0, gphy->lo_control->tx_bias); 2070 } 2071 if (phy->rev >= 6) { 2072 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12)); 2073 } 2074 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) 2075 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075); 2076 else 2077 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F); 2078 if (phy->rev < 2) 2079 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101); 2080 else 2081 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202); 2082 if (phy->gmode || phy->rev >= 2) { 2083 b43_lo_g_adjust(dev); 2084 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078); 2085 } 2086 2087 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) { 2088 /* The specs state to update the NRSSI LT with 2089 * the value 0x7FFFFFFF here. I think that is some weird 2090 * compiler optimization in the original driver. 2091 * Essentially, what we do here is resetting all NRSSI LT 2092 * entries to -32 (see the clamp_val() in nrssi_hw_update()) 2093 */ 2094 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME? 2095 b43_calc_nrssi_threshold(dev); 2096 } else if (phy->gmode || phy->rev >= 2) { 2097 if (gphy->nrssi[0] == -1000) { 2098 B43_WARN_ON(gphy->nrssi[1] != -1000); 2099 b43_calc_nrssi_slope(dev); 2100 } else 2101 b43_calc_nrssi_threshold(dev); 2102 } 2103 if (phy->radio_rev == 8) 2104 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230); 2105 b43_phy_init_pctl(dev); 2106 /* FIXME: The spec says in the following if, the 0 should be replaced 2107 'if OFDM may not be used in the current locale' 2108 but OFDM is legal everywhere */ 2109 if ((dev->dev->chip_id == 0x4306 2110 && dev->dev->chip_pkg == 2) || 0) { 2111 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF); 2112 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF); 2113 } 2114 } 2115 2116 void b43_gphy_channel_switch(struct b43_wldev *dev, 2117 unsigned int channel, 2118 bool synthetic_pu_workaround) 2119 { 2120 if (synthetic_pu_workaround) 2121 b43_synth_pu_workaround(dev, channel); 2122 2123 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel)); 2124 2125 if (channel == 14) { 2126 if (dev->dev->bus_sprom->country_code == 2127 SSB_SPROM1CCODE_JAPAN) 2128 b43_hf_write(dev, 2129 b43_hf_read(dev) & ~B43_HF_ACPR); 2130 else 2131 b43_hf_write(dev, 2132 b43_hf_read(dev) | B43_HF_ACPR); 2133 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 2134 b43_read16(dev, B43_MMIO_CHANNEL_EXT) 2135 | (1 << 11)); 2136 } else { 2137 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 2138 b43_read16(dev, B43_MMIO_CHANNEL_EXT) 2139 & 0xF7BF); 2140 } 2141 } 2142 2143 static void default_baseband_attenuation(struct b43_wldev *dev, 2144 struct b43_bbatt *bb) 2145 { 2146 struct b43_phy *phy = &dev->phy; 2147 2148 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6) 2149 bb->att = 0; 2150 else 2151 bb->att = 2; 2152 } 2153 2154 static void default_radio_attenuation(struct b43_wldev *dev, 2155 struct b43_rfatt *rf) 2156 { 2157 struct b43_bus_dev *bdev = dev->dev; 2158 struct b43_phy *phy = &dev->phy; 2159 2160 rf->with_padmix = false; 2161 2162 if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM && 2163 dev->dev->board_type == SSB_BOARD_BCM4309G) { 2164 if (dev->dev->board_rev < 0x43) { 2165 rf->att = 2; 2166 return; 2167 } else if (dev->dev->board_rev < 0x51) { 2168 rf->att = 3; 2169 return; 2170 } 2171 } 2172 2173 switch (phy->radio_ver) { 2174 case 0x2053: 2175 switch (phy->radio_rev) { 2176 case 1: 2177 rf->att = 6; 2178 return; 2179 } 2180 break; 2181 case 0x2050: 2182 switch (phy->radio_rev) { 2183 case 0: 2184 rf->att = 5; 2185 return; 2186 case 1: 2187 if (phy->type == B43_PHYTYPE_G) { 2188 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM 2189 && bdev->board_type == SSB_BOARD_BCM4309G 2190 && bdev->board_rev >= 30) 2191 rf->att = 3; 2192 else if (bdev->board_vendor == 2193 SSB_BOARDVENDOR_BCM 2194 && bdev->board_type == 2195 SSB_BOARD_BU4306) 2196 rf->att = 3; 2197 else 2198 rf->att = 1; 2199 } else { 2200 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM 2201 && bdev->board_type == SSB_BOARD_BCM4309G 2202 && bdev->board_rev >= 30) 2203 rf->att = 7; 2204 else 2205 rf->att = 6; 2206 } 2207 return; 2208 case 2: 2209 if (phy->type == B43_PHYTYPE_G) { 2210 if (bdev->board_vendor == SSB_BOARDVENDOR_BCM 2211 && bdev->board_type == SSB_BOARD_BCM4309G 2212 && bdev->board_rev >= 30) 2213 rf->att = 3; 2214 else if (bdev->board_vendor == 2215 SSB_BOARDVENDOR_BCM 2216 && bdev->board_type == 2217 SSB_BOARD_BU4306) 2218 rf->att = 5; 2219 else if (bdev->chip_id == 0x4320) 2220 rf->att = 4; 2221 else 2222 rf->att = 3; 2223 } else 2224 rf->att = 6; 2225 return; 2226 case 3: 2227 rf->att = 5; 2228 return; 2229 case 4: 2230 case 5: 2231 rf->att = 1; 2232 return; 2233 case 6: 2234 case 7: 2235 rf->att = 5; 2236 return; 2237 case 8: 2238 rf->att = 0xA; 2239 rf->with_padmix = true; 2240 return; 2241 case 9: 2242 default: 2243 rf->att = 5; 2244 return; 2245 } 2246 } 2247 rf->att = 5; 2248 } 2249 2250 static u16 default_tx_control(struct b43_wldev *dev) 2251 { 2252 struct b43_phy *phy = &dev->phy; 2253 2254 if (phy->radio_ver != 0x2050) 2255 return 0; 2256 if (phy->radio_rev == 1) 2257 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX; 2258 if (phy->radio_rev < 6) 2259 return B43_TXCTL_PA2DB; 2260 if (phy->radio_rev == 8) 2261 return B43_TXCTL_TXMIX; 2262 return 0; 2263 } 2264 2265 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel) 2266 { 2267 struct b43_phy *phy = &dev->phy; 2268 struct b43_phy_g *gphy = phy->g; 2269 u8 ret = 0; 2270 u16 saved, rssi, temp; 2271 int i, j = 0; 2272 2273 saved = b43_phy_read(dev, 0x0403); 2274 b43_switch_channel(dev, channel); 2275 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5); 2276 if (gphy->aci_hw_rssi) 2277 rssi = b43_phy_read(dev, 0x048A) & 0x3F; 2278 else 2279 rssi = saved & 0x3F; 2280 /* clamp temp to signed 5bit */ 2281 if (rssi > 32) 2282 rssi -= 64; 2283 for (i = 0; i < 100; i++) { 2284 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F; 2285 if (temp > 32) 2286 temp -= 64; 2287 if (temp < rssi) 2288 j++; 2289 if (j >= 20) 2290 ret = 1; 2291 } 2292 b43_phy_write(dev, 0x0403, saved); 2293 2294 return ret; 2295 } 2296 2297 static u8 b43_gphy_aci_scan(struct b43_wldev *dev) 2298 { 2299 struct b43_phy *phy = &dev->phy; 2300 u8 ret[13]; 2301 unsigned int channel = phy->channel; 2302 unsigned int i, j, start, end; 2303 2304 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0))) 2305 return 0; 2306 2307 b43_phy_lock(dev); 2308 b43_radio_lock(dev); 2309 b43_phy_mask(dev, 0x0802, 0xFFFC); 2310 b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF); 2311 b43_set_all_gains(dev, 3, 8, 1); 2312 2313 start = (channel - 5 > 0) ? channel - 5 : 1; 2314 end = (channel + 5 < 14) ? channel + 5 : 13; 2315 2316 for (i = start; i <= end; i++) { 2317 if (abs(channel - i) > 2) 2318 ret[i - 1] = b43_gphy_aci_detect(dev, i); 2319 } 2320 b43_switch_channel(dev, channel); 2321 b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003); 2322 b43_phy_mask(dev, 0x0403, 0xFFF8); 2323 b43_phy_set(dev, B43_PHY_G_CRS, 0x8000); 2324 b43_set_original_gains(dev); 2325 for (i = 0; i < 13; i++) { 2326 if (!ret[i]) 2327 continue; 2328 end = (i + 5 < 13) ? i + 5 : 13; 2329 for (j = i; j < end; j++) 2330 ret[j] = 1; 2331 } 2332 b43_radio_unlock(dev); 2333 b43_phy_unlock(dev); 2334 2335 return ret[channel - 1]; 2336 } 2337 2338 static s32 b43_tssi2dbm_ad(s32 num, s32 den) 2339 { 2340 if (num < 0) 2341 return num / den; 2342 else 2343 return (num + den / 2) / den; 2344 } 2345 2346 static s8 b43_tssi2dbm_entry(s8 entry[], u8 index, 2347 s16 pab0, s16 pab1, s16 pab2) 2348 { 2349 s32 m1, m2, f = 256, q, delta; 2350 s8 i = 0; 2351 2352 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32); 2353 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1); 2354 do { 2355 if (i > 15) 2356 return -EINVAL; 2357 q = b43_tssi2dbm_ad(f * 4096 - 2358 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048); 2359 delta = abs(q - f); 2360 f = q; 2361 i++; 2362 } while (delta >= 2); 2363 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128); 2364 return 0; 2365 } 2366 2367 u8 *b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev, 2368 s16 pab0, s16 pab1, s16 pab2) 2369 { 2370 unsigned int i; 2371 u8 *tab; 2372 int err; 2373 2374 tab = kmalloc(64, GFP_KERNEL); 2375 if (!tab) { 2376 b43err(dev->wl, "Could not allocate memory " 2377 "for tssi2dbm table\n"); 2378 return NULL; 2379 } 2380 for (i = 0; i < 64; i++) { 2381 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2); 2382 if (err) { 2383 b43err(dev->wl, "Could not generate " 2384 "tssi2dBm table\n"); 2385 kfree(tab); 2386 return NULL; 2387 } 2388 } 2389 2390 return tab; 2391 } 2392 2393 /* Initialise the TSSI->dBm lookup table */ 2394 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev) 2395 { 2396 struct b43_phy *phy = &dev->phy; 2397 struct b43_phy_g *gphy = phy->g; 2398 s16 pab0, pab1, pab2; 2399 2400 pab0 = (s16) (dev->dev->bus_sprom->pa0b0); 2401 pab1 = (s16) (dev->dev->bus_sprom->pa0b1); 2402 pab2 = (s16) (dev->dev->bus_sprom->pa0b2); 2403 2404 B43_WARN_ON((dev->dev->chip_id == 0x4301) && 2405 (phy->radio_ver != 0x2050)); /* Not supported anymore */ 2406 2407 gphy->dyn_tssi_tbl = false; 2408 2409 if (pab0 != 0 && pab1 != 0 && pab2 != 0 && 2410 pab0 != -1 && pab1 != -1 && pab2 != -1) { 2411 /* The pabX values are set in SPROM. Use them. */ 2412 if ((s8) dev->dev->bus_sprom->itssi_bg != 0 && 2413 (s8) dev->dev->bus_sprom->itssi_bg != -1) { 2414 gphy->tgt_idle_tssi = 2415 (s8) (dev->dev->bus_sprom->itssi_bg); 2416 } else 2417 gphy->tgt_idle_tssi = 62; 2418 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0, 2419 pab1, pab2); 2420 if (!gphy->tssi2dbm) 2421 return -ENOMEM; 2422 gphy->dyn_tssi_tbl = true; 2423 } else { 2424 /* pabX values not set in SPROM. */ 2425 gphy->tgt_idle_tssi = 52; 2426 gphy->tssi2dbm = b43_tssi2dbm_g_table; 2427 } 2428 2429 return 0; 2430 } 2431 2432 static int b43_gphy_op_allocate(struct b43_wldev *dev) 2433 { 2434 struct b43_phy_g *gphy; 2435 struct b43_txpower_lo_control *lo; 2436 int err; 2437 2438 gphy = kzalloc(sizeof(*gphy), GFP_KERNEL); 2439 if (!gphy) { 2440 err = -ENOMEM; 2441 goto error; 2442 } 2443 dev->phy.g = gphy; 2444 2445 lo = kzalloc(sizeof(*lo), GFP_KERNEL); 2446 if (!lo) { 2447 err = -ENOMEM; 2448 goto err_free_gphy; 2449 } 2450 gphy->lo_control = lo; 2451 2452 err = b43_gphy_init_tssi2dbm_table(dev); 2453 if (err) 2454 goto err_free_lo; 2455 2456 return 0; 2457 2458 err_free_lo: 2459 kfree(lo); 2460 err_free_gphy: 2461 kfree(gphy); 2462 error: 2463 return err; 2464 } 2465 2466 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev) 2467 { 2468 struct b43_phy *phy = &dev->phy; 2469 struct b43_phy_g *gphy = phy->g; 2470 const void *tssi2dbm; 2471 int tgt_idle_tssi; 2472 struct b43_txpower_lo_control *lo; 2473 unsigned int i; 2474 2475 /* tssi2dbm table is constant, so it is initialized at alloc time. 2476 * Save a copy of the pointer. */ 2477 tssi2dbm = gphy->tssi2dbm; 2478 tgt_idle_tssi = gphy->tgt_idle_tssi; 2479 /* Save the LO pointer. */ 2480 lo = gphy->lo_control; 2481 2482 /* Zero out the whole PHY structure. */ 2483 memset(gphy, 0, sizeof(*gphy)); 2484 2485 /* Restore pointers. */ 2486 gphy->tssi2dbm = tssi2dbm; 2487 gphy->tgt_idle_tssi = tgt_idle_tssi; 2488 gphy->lo_control = lo; 2489 2490 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig)); 2491 2492 /* NRSSI */ 2493 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++) 2494 gphy->nrssi[i] = -1000; 2495 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++) 2496 gphy->nrssi_lt[i] = i; 2497 2498 gphy->lofcal = 0xFFFF; 2499 gphy->initval = 0xFFFF; 2500 2501 gphy->interfmode = B43_INTERFMODE_NONE; 2502 2503 /* OFDM-table address caching. */ 2504 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; 2505 2506 gphy->average_tssi = 0xFF; 2507 2508 /* Local Osciallator structure */ 2509 lo->tx_bias = 0xFF; 2510 INIT_LIST_HEAD(&lo->calib_list); 2511 } 2512 2513 static void b43_gphy_op_free(struct b43_wldev *dev) 2514 { 2515 struct b43_phy *phy = &dev->phy; 2516 struct b43_phy_g *gphy = phy->g; 2517 2518 kfree(gphy->lo_control); 2519 2520 if (gphy->dyn_tssi_tbl) 2521 kfree(gphy->tssi2dbm); 2522 gphy->dyn_tssi_tbl = false; 2523 gphy->tssi2dbm = NULL; 2524 2525 kfree(gphy); 2526 dev->phy.g = NULL; 2527 } 2528 2529 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev) 2530 { 2531 struct b43_phy *phy = &dev->phy; 2532 struct b43_phy_g *gphy = phy->g; 2533 struct b43_txpower_lo_control *lo = gphy->lo_control; 2534 2535 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2536 2537 default_baseband_attenuation(dev, &gphy->bbatt); 2538 default_radio_attenuation(dev, &gphy->rfatt); 2539 gphy->tx_control = (default_tx_control(dev) << 4); 2540 generate_rfatt_list(dev, &lo->rfatt_list); 2541 generate_bbatt_list(dev, &lo->bbatt_list); 2542 2543 /* Commit previous writes */ 2544 b43_read32(dev, B43_MMIO_MACCTL); 2545 2546 if (phy->rev == 1) { 2547 /* Workaround: Temporarly disable gmode through the early init 2548 * phase, as the gmode stuff is not needed for phy rev 1 */ 2549 phy->gmode = false; 2550 b43_wireless_core_reset(dev, 0); 2551 b43_phy_initg(dev); 2552 phy->gmode = true; 2553 b43_wireless_core_reset(dev, 1); 2554 } 2555 2556 return 0; 2557 } 2558 2559 static int b43_gphy_op_init(struct b43_wldev *dev) 2560 { 2561 b43_phy_initg(dev); 2562 2563 return 0; 2564 } 2565 2566 static void b43_gphy_op_exit(struct b43_wldev *dev) 2567 { 2568 b43_lo_g_cleanup(dev); 2569 } 2570 2571 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg) 2572 { 2573 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); 2574 return b43_read16(dev, B43_MMIO_PHY_DATA); 2575 } 2576 2577 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) 2578 { 2579 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); 2580 b43_write16(dev, B43_MMIO_PHY_DATA, value); 2581 } 2582 2583 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg) 2584 { 2585 /* Register 1 is a 32-bit register. */ 2586 B43_WARN_ON(reg == 1); 2587 /* G-PHY needs 0x80 for read access. */ 2588 reg |= 0x80; 2589 2590 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 2591 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 2592 } 2593 2594 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 2595 { 2596 /* Register 1 is a 32-bit register. */ 2597 B43_WARN_ON(reg == 1); 2598 2599 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 2600 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 2601 } 2602 2603 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev) 2604 { 2605 return (dev->phy.rev >= 6); 2606 } 2607 2608 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev, 2609 bool blocked) 2610 { 2611 struct b43_phy *phy = &dev->phy; 2612 struct b43_phy_g *gphy = phy->g; 2613 unsigned int channel; 2614 2615 might_sleep(); 2616 2617 if (!blocked) { 2618 /* Turn radio ON */ 2619 if (phy->radio_on) 2620 return; 2621 2622 b43_phy_write(dev, 0x0015, 0x8000); 2623 b43_phy_write(dev, 0x0015, 0xCC00); 2624 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000)); 2625 if (gphy->radio_off_context.valid) { 2626 /* Restore the RFover values. */ 2627 b43_phy_write(dev, B43_PHY_RFOVER, 2628 gphy->radio_off_context.rfover); 2629 b43_phy_write(dev, B43_PHY_RFOVERVAL, 2630 gphy->radio_off_context.rfoverval); 2631 gphy->radio_off_context.valid = false; 2632 } 2633 channel = phy->channel; 2634 b43_gphy_channel_switch(dev, 6, 1); 2635 b43_gphy_channel_switch(dev, channel, 0); 2636 } else { 2637 /* Turn radio OFF */ 2638 u16 rfover, rfoverval; 2639 2640 rfover = b43_phy_read(dev, B43_PHY_RFOVER); 2641 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL); 2642 gphy->radio_off_context.rfover = rfover; 2643 gphy->radio_off_context.rfoverval = rfoverval; 2644 gphy->radio_off_context.valid = true; 2645 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C); 2646 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73); 2647 } 2648 } 2649 2650 static int b43_gphy_op_switch_channel(struct b43_wldev *dev, 2651 unsigned int new_channel) 2652 { 2653 if ((new_channel < 1) || (new_channel > 14)) 2654 return -EINVAL; 2655 b43_gphy_channel_switch(dev, new_channel, 0); 2656 2657 return 0; 2658 } 2659 2660 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev) 2661 { 2662 return 1; /* Default to channel 1 */ 2663 } 2664 2665 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna) 2666 { 2667 struct b43_phy *phy = &dev->phy; 2668 u16 tmp; 2669 int autodiv = 0; 2670 2671 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1) 2672 autodiv = 1; 2673 2674 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ANTDIVHELP); 2675 2676 b43_phy_maskset(dev, B43_PHY_BBANDCFG, ~B43_PHY_BBANDCFG_RXANT, 2677 (autodiv ? B43_ANTENNA_AUTO1 : antenna) << 2678 B43_PHY_BBANDCFG_RXANT_SHIFT); 2679 2680 if (autodiv) { 2681 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL); 2682 if (antenna == B43_ANTENNA_AUTO1) 2683 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1; 2684 else 2685 tmp |= B43_PHY_ANTDWELL_AUTODIV1; 2686 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp); 2687 } 2688 2689 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT); 2690 if (autodiv) 2691 tmp |= B43_PHY_ANTWRSETT_ARXDIV; 2692 else 2693 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV; 2694 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp); 2695 2696 if (autodiv) 2697 b43_phy_set(dev, B43_PHY_ANTWRSETT, B43_PHY_ANTWRSETT_ARXDIV); 2698 else { 2699 b43_phy_mask(dev, B43_PHY_ANTWRSETT, 2700 B43_PHY_ANTWRSETT_ARXDIV); 2701 } 2702 2703 if (phy->rev >= 2) { 2704 b43_phy_set(dev, B43_PHY_OFDM61, B43_PHY_OFDM61_10); 2705 b43_phy_maskset(dev, B43_PHY_DIVSRCHGAINBACK, 0xFF00, 0x15); 2706 2707 if (phy->rev == 2) 2708 b43_phy_write(dev, B43_PHY_ADIVRELATED, 8); 2709 else 2710 b43_phy_maskset(dev, B43_PHY_ADIVRELATED, 0xFF00, 8); 2711 } 2712 if (phy->rev >= 6) 2713 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC); 2714 2715 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ANTDIVHELP); 2716 } 2717 2718 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev, 2719 enum b43_interference_mitigation mode) 2720 { 2721 struct b43_phy *phy = &dev->phy; 2722 struct b43_phy_g *gphy = phy->g; 2723 int currentmode; 2724 2725 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2726 if ((phy->rev == 0) || (!phy->gmode)) 2727 return -ENODEV; 2728 2729 gphy->aci_wlan_automatic = false; 2730 switch (mode) { 2731 case B43_INTERFMODE_AUTOWLAN: 2732 gphy->aci_wlan_automatic = true; 2733 if (gphy->aci_enable) 2734 mode = B43_INTERFMODE_MANUALWLAN; 2735 else 2736 mode = B43_INTERFMODE_NONE; 2737 break; 2738 case B43_INTERFMODE_NONE: 2739 case B43_INTERFMODE_NONWLAN: 2740 case B43_INTERFMODE_MANUALWLAN: 2741 break; 2742 default: 2743 return -EINVAL; 2744 } 2745 2746 currentmode = gphy->interfmode; 2747 if (currentmode == mode) 2748 return 0; 2749 if (currentmode != B43_INTERFMODE_NONE) 2750 b43_radio_interference_mitigation_disable(dev, currentmode); 2751 2752 if (mode == B43_INTERFMODE_NONE) { 2753 gphy->aci_enable = false; 2754 gphy->aci_hw_rssi = false; 2755 } else 2756 b43_radio_interference_mitigation_enable(dev, mode); 2757 gphy->interfmode = mode; 2758 2759 return 0; 2760 } 2761 2762 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut 2763 * This function converts a TSSI value to dBm in Q5.2 2764 */ 2765 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi) 2766 { 2767 struct b43_phy_g *gphy = dev->phy.g; 2768 s8 dbm; 2769 s32 tmp; 2770 2771 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi); 2772 tmp = clamp_val(tmp, 0x00, 0x3F); 2773 dbm = gphy->tssi2dbm[tmp]; 2774 2775 return dbm; 2776 } 2777 2778 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev, 2779 int *_bbatt, int *_rfatt) 2780 { 2781 int rfatt = *_rfatt; 2782 int bbatt = *_bbatt; 2783 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control; 2784 2785 /* Get baseband and radio attenuation values into their permitted ranges. 2786 * Radio attenuation affects power level 4 times as much as baseband. */ 2787 2788 /* Range constants */ 2789 const int rf_min = lo->rfatt_list.min_val; 2790 const int rf_max = lo->rfatt_list.max_val; 2791 const int bb_min = lo->bbatt_list.min_val; 2792 const int bb_max = lo->bbatt_list.max_val; 2793 2794 while (1) { 2795 if (rfatt > rf_max && bbatt > bb_max - 4) 2796 break; /* Can not get it into ranges */ 2797 if (rfatt < rf_min && bbatt < bb_min + 4) 2798 break; /* Can not get it into ranges */ 2799 if (bbatt > bb_max && rfatt > rf_max - 1) 2800 break; /* Can not get it into ranges */ 2801 if (bbatt < bb_min && rfatt < rf_min + 1) 2802 break; /* Can not get it into ranges */ 2803 2804 if (bbatt > bb_max) { 2805 bbatt -= 4; 2806 rfatt += 1; 2807 continue; 2808 } 2809 if (bbatt < bb_min) { 2810 bbatt += 4; 2811 rfatt -= 1; 2812 continue; 2813 } 2814 if (rfatt > rf_max) { 2815 rfatt -= 1; 2816 bbatt += 4; 2817 continue; 2818 } 2819 if (rfatt < rf_min) { 2820 rfatt += 1; 2821 bbatt -= 4; 2822 continue; 2823 } 2824 break; 2825 } 2826 2827 *_rfatt = clamp_val(rfatt, rf_min, rf_max); 2828 *_bbatt = clamp_val(bbatt, bb_min, bb_max); 2829 } 2830 2831 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev) 2832 { 2833 struct b43_phy *phy = &dev->phy; 2834 struct b43_phy_g *gphy = phy->g; 2835 int rfatt, bbatt; 2836 u8 tx_control; 2837 2838 b43_mac_suspend(dev); 2839 2840 /* Calculate the new attenuation values. */ 2841 bbatt = gphy->bbatt.att; 2842 bbatt += gphy->bbatt_delta; 2843 rfatt = gphy->rfatt.att; 2844 rfatt += gphy->rfatt_delta; 2845 2846 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); 2847 tx_control = gphy->tx_control; 2848 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) { 2849 if (rfatt <= 1) { 2850 if (tx_control == 0) { 2851 tx_control = 2852 B43_TXCTL_PA2DB | 2853 B43_TXCTL_TXMIX; 2854 rfatt += 2; 2855 bbatt += 2; 2856 } else if (dev->dev->bus_sprom-> 2857 boardflags_lo & 2858 B43_BFL_PACTRL) { 2859 bbatt += 4 * (rfatt - 2); 2860 rfatt = 2; 2861 } 2862 } else if (rfatt > 4 && tx_control) { 2863 tx_control = 0; 2864 if (bbatt < 3) { 2865 rfatt -= 3; 2866 bbatt += 2; 2867 } else { 2868 rfatt -= 2; 2869 bbatt -= 2; 2870 } 2871 } 2872 } 2873 /* Save the control values */ 2874 gphy->tx_control = tx_control; 2875 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt); 2876 gphy->rfatt.att = rfatt; 2877 gphy->bbatt.att = bbatt; 2878 2879 if (b43_debug(dev, B43_DBG_XMITPOWER)) 2880 b43dbg(dev->wl, "Adjusting TX power\n"); 2881 2882 /* Adjust the hardware */ 2883 b43_phy_lock(dev); 2884 b43_radio_lock(dev); 2885 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, 2886 gphy->tx_control); 2887 b43_radio_unlock(dev); 2888 b43_phy_unlock(dev); 2889 2890 b43_mac_enable(dev); 2891 } 2892 2893 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev, 2894 bool ignore_tssi) 2895 { 2896 struct b43_phy *phy = &dev->phy; 2897 struct b43_phy_g *gphy = phy->g; 2898 unsigned int average_tssi; 2899 int cck_result, ofdm_result; 2900 int estimated_pwr, desired_pwr, pwr_adjust; 2901 int rfatt_delta, bbatt_delta; 2902 unsigned int max_pwr; 2903 2904 /* First get the average TSSI */ 2905 cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK); 2906 ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G); 2907 if ((cck_result < 0) && (ofdm_result < 0)) { 2908 /* No TSSI information available */ 2909 if (!ignore_tssi) 2910 goto no_adjustment_needed; 2911 cck_result = 0; 2912 ofdm_result = 0; 2913 } 2914 if (cck_result < 0) 2915 average_tssi = ofdm_result; 2916 else if (ofdm_result < 0) 2917 average_tssi = cck_result; 2918 else 2919 average_tssi = (cck_result + ofdm_result) / 2; 2920 /* Merge the average with the stored value. */ 2921 if (likely(gphy->average_tssi != 0xFF)) 2922 average_tssi = (average_tssi + gphy->average_tssi) / 2; 2923 gphy->average_tssi = average_tssi; 2924 B43_WARN_ON(average_tssi >= B43_TSSI_MAX); 2925 2926 /* Estimate the TX power emission based on the TSSI */ 2927 estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi); 2928 2929 B43_WARN_ON(phy->type != B43_PHYTYPE_G); 2930 max_pwr = dev->dev->bus_sprom->maxpwr_bg; 2931 if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) 2932 max_pwr -= 3; /* minus 0.75 */ 2933 if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) { 2934 b43warn(dev->wl, 2935 "Invalid max-TX-power value in SPROM.\n"); 2936 max_pwr = INT_TO_Q52(20); /* fake it */ 2937 dev->dev->bus_sprom->maxpwr_bg = max_pwr; 2938 } 2939 2940 /* Get desired power (in Q5.2) */ 2941 if (phy->desired_txpower < 0) 2942 desired_pwr = INT_TO_Q52(0); 2943 else 2944 desired_pwr = INT_TO_Q52(phy->desired_txpower); 2945 /* And limit it. max_pwr already is Q5.2 */ 2946 desired_pwr = clamp_val(desired_pwr, 0, max_pwr); 2947 if (b43_debug(dev, B43_DBG_XMITPOWER)) { 2948 b43dbg(dev->wl, 2949 "[TX power] current = " Q52_FMT 2950 " dBm, desired = " Q52_FMT 2951 " dBm, max = " Q52_FMT "\n", 2952 Q52_ARG(estimated_pwr), 2953 Q52_ARG(desired_pwr), 2954 Q52_ARG(max_pwr)); 2955 } 2956 2957 /* Calculate the adjustment delta. */ 2958 pwr_adjust = desired_pwr - estimated_pwr; 2959 if (pwr_adjust == 0) 2960 goto no_adjustment_needed; 2961 2962 /* RF attenuation delta. */ 2963 rfatt_delta = ((pwr_adjust + 7) / 8); 2964 /* Lower attenuation => Bigger power output. Negate it. */ 2965 rfatt_delta = -rfatt_delta; 2966 2967 /* Baseband attenuation delta. */ 2968 bbatt_delta = pwr_adjust / 2; 2969 /* Lower attenuation => Bigger power output. Negate it. */ 2970 bbatt_delta = -bbatt_delta; 2971 /* RF att affects power level 4 times as much as 2972 * Baseband attennuation. Subtract it. */ 2973 bbatt_delta -= 4 * rfatt_delta; 2974 2975 #if B43_DEBUG 2976 if (b43_debug(dev, B43_DBG_XMITPOWER)) { 2977 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust; 2978 b43dbg(dev->wl, 2979 "[TX power deltas] %s" Q52_FMT " dBm => " 2980 "bbatt-delta = %d, rfatt-delta = %d\n", 2981 (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm), 2982 bbatt_delta, rfatt_delta); 2983 } 2984 #endif /* DEBUG */ 2985 2986 /* So do we finally need to adjust something in hardware? */ 2987 if ((rfatt_delta == 0) && (bbatt_delta == 0)) 2988 goto no_adjustment_needed; 2989 2990 /* Save the deltas for later when we adjust the power. */ 2991 gphy->bbatt_delta = bbatt_delta; 2992 gphy->rfatt_delta = rfatt_delta; 2993 2994 /* We need to adjust the TX power on the device. */ 2995 return B43_TXPWR_RES_NEED_ADJUST; 2996 2997 no_adjustment_needed: 2998 return B43_TXPWR_RES_DONE; 2999 } 3000 3001 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev) 3002 { 3003 struct b43_phy *phy = &dev->phy; 3004 struct b43_phy_g *gphy = phy->g; 3005 3006 b43_mac_suspend(dev); 3007 //TODO: update_aci_moving_average 3008 if (gphy->aci_enable && gphy->aci_wlan_automatic) { 3009 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) { 3010 if (0 /*TODO: bunch of conditions */ ) { 3011 phy->ops->interf_mitigation(dev, 3012 B43_INTERFMODE_MANUALWLAN); 3013 } 3014 } else if (0 /*TODO*/) { 3015 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev)) 3016 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE); 3017 } 3018 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN && 3019 phy->rev == 1) { 3020 //TODO: implement rev1 workaround 3021 } 3022 b43_lo_g_maintenance_work(dev); 3023 b43_mac_enable(dev); 3024 } 3025 3026 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev) 3027 { 3028 struct b43_phy *phy = &dev->phy; 3029 3030 if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_RSSI)) 3031 return; 3032 3033 b43_mac_suspend(dev); 3034 b43_calc_nrssi_slope(dev); 3035 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { 3036 u8 old_chan = phy->channel; 3037 3038 /* VCO Calibration */ 3039 if (old_chan >= 8) 3040 b43_switch_channel(dev, 1); 3041 else 3042 b43_switch_channel(dev, 13); 3043 b43_switch_channel(dev, old_chan); 3044 } 3045 b43_mac_enable(dev); 3046 } 3047 3048 const struct b43_phy_operations b43_phyops_g = { 3049 .allocate = b43_gphy_op_allocate, 3050 .free = b43_gphy_op_free, 3051 .prepare_structs = b43_gphy_op_prepare_structs, 3052 .prepare_hardware = b43_gphy_op_prepare_hardware, 3053 .init = b43_gphy_op_init, 3054 .exit = b43_gphy_op_exit, 3055 .phy_read = b43_gphy_op_read, 3056 .phy_write = b43_gphy_op_write, 3057 .radio_read = b43_gphy_op_radio_read, 3058 .radio_write = b43_gphy_op_radio_write, 3059 .supports_hwpctl = b43_gphy_op_supports_hwpctl, 3060 .software_rfkill = b43_gphy_op_software_rfkill, 3061 .switch_analog = b43_phyop_switch_analog_generic, 3062 .switch_channel = b43_gphy_op_switch_channel, 3063 .get_default_chan = b43_gphy_op_get_default_chan, 3064 .set_rx_antenna = b43_gphy_op_set_rx_antenna, 3065 .interf_mitigation = b43_gphy_op_interf_mitigation, 3066 .recalc_txpower = b43_gphy_op_recalc_txpower, 3067 .adjust_txpower = b43_gphy_op_adjust_txpower, 3068 .pwork_15sec = b43_gphy_op_pwork_15sec, 3069 .pwork_60sec = b43_gphy_op_pwork_60sec, 3070 }; 3071