1 /* 2 * Copyright (c) 2012-2014 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WIL6210_H__ 18 #define __WIL6210_H__ 19 20 #include <linux/netdevice.h> 21 #include <linux/wireless.h> 22 #include <net/cfg80211.h> 23 #include <linux/timex.h> 24 #include "wil_platform.h" 25 26 extern bool no_fw_recovery; 27 extern unsigned int mtu_max; 28 29 #define WIL_NAME "wil6210" 30 #define WIL_FW_NAME "wil6210.fw" 31 32 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 33 34 struct wil_board { 35 int board; 36 #define WIL_BOARD_MARLON (1) 37 #define WIL_BOARD_SPARROW (2) 38 const char * const name; 39 }; 40 41 /** 42 * extract bits [@b0:@b1] (inclusive) from the value @x 43 * it should be @b0 <= @b1, or result is incorrect 44 */ 45 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 46 { 47 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 48 } 49 50 #define WIL6210_MEM_SIZE (2*1024*1024UL) 51 52 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (9) 53 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (9) 54 /* limit ring size in range [32..32k] */ 55 #define WIL_RING_SIZE_ORDER_MIN (5) 56 #define WIL_RING_SIZE_ORDER_MAX (15) 57 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 58 #define WIL6210_MAX_CID (8) /* HW limit */ 59 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 60 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 61 #define WIL6210_ITR_TRSH_MAX (5000000) 62 #define WIL6210_ITR_TRSH_DEFAULT (300) /* usec */ 63 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 64 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 65 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 66 67 /* Hardware definitions begin */ 68 69 /* 70 * Mapping 71 * RGF File | Host addr | FW addr 72 * | | 73 * user_rgf | 0x000000 | 0x880000 74 * dma_rgf | 0x001000 | 0x881000 75 * pcie_rgf | 0x002000 | 0x882000 76 * | | 77 */ 78 79 /* Where various structures placed in host address space */ 80 #define WIL6210_FW_HOST_OFF (0x880000UL) 81 82 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 83 84 /* 85 * Interrupt control registers block 86 * 87 * each interrupt controlled by the same bit in all registers 88 */ 89 struct RGF_ICR { 90 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 91 u32 ICR; /* Cause, W1C/COR depending on ICC */ 92 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 93 u32 ICS; /* Cause Set, WO */ 94 u32 IMV; /* Mask, RW+S/C */ 95 u32 IMS; /* Mask Set, write 1 to set */ 96 u32 IMC; /* Mask Clear, write 1 to clear */ 97 } __packed; 98 99 /* registers - FW addresses */ 100 #define RGF_USER_USAGE_1 (0x880004) 101 #define RGF_USER_USAGE_6 (0x880018) 102 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 103 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 104 #define RGF_USER_USER_CPU_0 (0x8801e0) 105 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 106 #define RGF_USER_MAC_CPU_0 (0x8801fc) 107 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 108 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 109 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 110 #define RGF_USER_CLKS_CTL_0 (0x880abc) 111 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 112 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 113 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 114 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 115 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 116 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 117 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 118 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 119 #define BIT_CAR_PERST_RST BIT(7) 120 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 121 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 122 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 123 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 124 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 125 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 126 127 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 128 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 129 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 130 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 131 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 132 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 133 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 134 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 135 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 136 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 137 138 /* Interrupt moderation control */ 139 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 140 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 141 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 142 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 143 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 144 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 145 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 146 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 147 148 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 149 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 150 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 151 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 152 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 153 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 154 155 #define RGF_HP_CTRL (0x88265c) 156 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 157 158 /* MAC timer, usec, for packet lifetime */ 159 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 160 161 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 162 #define RGF_CAF_OSC_CONTROL (0x88afa4) 163 #define BIT_CAF_OSC_XTAL_EN BIT(0) 164 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 165 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 166 167 /* popular locations */ 168 #define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD) 169 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \ 170 offsetof(struct RGF_ICR, ICS)) 171 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 172 173 /* ISR register bits */ 174 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 175 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 176 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 177 178 /* Hardware definitions end */ 179 struct fw_map { 180 u32 from; /* linker address - from, inclusive */ 181 u32 to; /* linker address - to, exclusive */ 182 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 183 const char *name; /* for debugfs */ 184 }; 185 186 /* array size should be in sync with actual definition in the wmi.c */ 187 extern const struct fw_map fw_mapping[7]; 188 189 /** 190 * mk_cidxtid - construct @cidxtid field 191 * @cid: CID value 192 * @tid: TID value 193 * 194 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 195 */ 196 static inline u8 mk_cidxtid(u8 cid, u8 tid) 197 { 198 return ((tid & 0xf) << 4) | (cid & 0xf); 199 } 200 201 /** 202 * parse_cidxtid - parse @cidxtid field 203 * @cid: store CID value here 204 * @tid: store TID value here 205 * 206 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 207 */ 208 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 209 { 210 *cid = cidxtid & 0xf; 211 *tid = (cidxtid >> 4) & 0xf; 212 } 213 214 struct wil6210_mbox_ring { 215 u32 base; 216 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 217 u16 size; 218 u32 tail; 219 u32 head; 220 } __packed; 221 222 struct wil6210_mbox_ring_desc { 223 __le32 sync; 224 __le32 addr; 225 } __packed; 226 227 /* at HOST_OFF_WIL6210_MBOX_CTL */ 228 struct wil6210_mbox_ctl { 229 struct wil6210_mbox_ring tx; 230 struct wil6210_mbox_ring rx; 231 } __packed; 232 233 struct wil6210_mbox_hdr { 234 __le16 seq; 235 __le16 len; /* payload, bytes after this header */ 236 __le16 type; 237 u8 flags; 238 u8 reserved; 239 } __packed; 240 241 #define WIL_MBOX_HDR_TYPE_WMI (0) 242 243 /* max. value for wil6210_mbox_hdr.len */ 244 #define MAX_MBOXITEM_SIZE (240) 245 246 /** 247 * struct wil6210_mbox_hdr_wmi - WMI header 248 * 249 * @mid: MAC ID 250 * 00 - default, created by FW 251 * 01..0f - WiFi ports, driver to create 252 * 10..fe - debug 253 * ff - broadcast 254 * @id: command/event ID 255 * @timestamp: FW fills for events, free-running msec timer 256 */ 257 struct wil6210_mbox_hdr_wmi { 258 u8 mid; 259 u8 reserved; 260 __le16 id; 261 __le32 timestamp; 262 } __packed; 263 264 struct pending_wmi_event { 265 struct list_head list; 266 struct { 267 struct wil6210_mbox_hdr hdr; 268 struct wil6210_mbox_hdr_wmi wmi; 269 u8 data[0]; 270 } __packed event; 271 }; 272 273 enum { /* for wil_ctx.mapped_as */ 274 wil_mapped_as_none = 0, 275 wil_mapped_as_single = 1, 276 wil_mapped_as_page = 2, 277 }; 278 279 /** 280 * struct wil_ctx - software context for Vring descriptor 281 */ 282 struct wil_ctx { 283 struct sk_buff *skb; 284 u8 nr_frags; 285 u8 mapped_as; 286 }; 287 288 union vring_desc; 289 290 struct vring { 291 dma_addr_t pa; 292 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 293 u16 size; /* number of vring_desc elements */ 294 u32 swtail; 295 u32 swhead; 296 u32 hwtail; /* write here to inform hw */ 297 struct wil_ctx *ctx; /* ctx[size] - software context */ 298 }; 299 300 /** 301 * Additional data for Tx Vring 302 */ 303 struct vring_tx_data { 304 int enabled; 305 cycles_t idle, last_idle, begin; 306 }; 307 308 enum { /* for wil6210_priv.status */ 309 wil_status_fwready = 0, 310 wil_status_fwconnecting, 311 wil_status_fwconnected, 312 wil_status_dontscan, 313 wil_status_reset_done, 314 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 315 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 316 }; 317 318 struct pci_dev; 319 320 /** 321 * struct tid_ampdu_rx - TID aggregation information (Rx). 322 * 323 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 324 * @reorder_time: jiffies when skb was added 325 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 326 * @reorder_timer: releases expired frames from the reorder buffer. 327 * @last_rx: jiffies of last rx activity 328 * @head_seq_num: head sequence number in reordering buffer. 329 * @stored_mpdu_num: number of MPDUs in reordering buffer 330 * @ssn: Starting Sequence Number expected to be aggregated. 331 * @buf_size: buffer size for incoming A-MPDUs 332 * @timeout: reset timer value (in TUs). 333 * @dialog_token: dialog token for aggregation session 334 * @rcu_head: RCU head used for freeing this struct 335 * 336 * This structure's lifetime is managed by RCU, assignments to 337 * the array holding it must hold the aggregation mutex. 338 * 339 */ 340 struct wil_tid_ampdu_rx { 341 struct sk_buff **reorder_buf; 342 unsigned long *reorder_time; 343 struct timer_list session_timer; 344 struct timer_list reorder_timer; 345 unsigned long last_rx; 346 u16 head_seq_num; 347 u16 stored_mpdu_num; 348 u16 ssn; 349 u16 buf_size; 350 u16 timeout; 351 u16 ssn_last_drop; 352 u8 dialog_token; 353 bool first_time; /* is it 1-st time this buffer used? */ 354 }; 355 356 enum wil_sta_status { 357 wil_sta_unused = 0, 358 wil_sta_conn_pending = 1, 359 wil_sta_connected = 2, 360 }; 361 362 #define WIL_STA_TID_NUM (16) 363 364 struct wil_net_stats { 365 unsigned long rx_packets; 366 unsigned long tx_packets; 367 unsigned long rx_bytes; 368 unsigned long tx_bytes; 369 unsigned long tx_errors; 370 unsigned long rx_dropped; 371 u16 last_mcs_rx; 372 }; 373 374 /** 375 * struct wil_sta_info - data for peer 376 * 377 * Peer identified by its CID (connection ID) 378 * NIC performs beam forming for each peer; 379 * if no beam forming done, frame exchange is not 380 * possible. 381 */ 382 struct wil_sta_info { 383 u8 addr[ETH_ALEN]; 384 enum wil_sta_status status; 385 struct wil_net_stats stats; 386 bool data_port_open; /* can send any data, not only EAPOL */ 387 /* Rx BACK */ 388 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 389 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 390 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 391 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 392 }; 393 394 enum { 395 fw_recovery_idle = 0, 396 fw_recovery_pending = 1, 397 fw_recovery_running = 2, 398 }; 399 400 struct wil6210_priv { 401 struct pci_dev *pdev; 402 int n_msi; 403 struct wireless_dev *wdev; 404 void __iomem *csr; 405 ulong status; 406 u32 fw_version; 407 u32 hw_version; 408 struct wil_board *board; 409 u8 n_mids; /* number of additional MIDs as reported by FW */ 410 u32 recovery_count; /* num of FW recovery attempts in a short time */ 411 u32 recovery_state; /* FW recovery state machine */ 412 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 413 wait_queue_head_t wq; /* for all wait_event() use */ 414 /* profile */ 415 u32 monitor_flags; 416 u32 secure_pcp; /* create secure PCP? */ 417 int sinfo_gen; 418 u32 itr_trsh; 419 /* cached ISR registers */ 420 u32 isr_misc; 421 /* mailbox related */ 422 struct mutex wmi_mutex; 423 struct wil6210_mbox_ctl mbox_ctl; 424 struct completion wmi_ready; 425 struct completion wmi_call; 426 u16 wmi_seq; 427 u16 reply_id; /**< wait for this WMI event */ 428 void *reply_buf; 429 u16 reply_size; 430 struct workqueue_struct *wmi_wq; /* for deferred calls */ 431 struct work_struct wmi_event_worker; 432 struct workqueue_struct *wmi_wq_conn; /* for connect worker */ 433 struct work_struct connect_worker; 434 struct work_struct disconnect_worker; 435 struct work_struct fw_error_worker; /* for FW error recovery */ 436 struct timer_list connect_timer; 437 struct timer_list scan_timer; /* detect scan timeout */ 438 int pending_connect_cid; 439 struct list_head pending_wmi_ev; 440 /* 441 * protect pending_wmi_ev 442 * - fill in IRQ from wil6210_irq_misc, 443 * - consumed in thread by wmi_event_worker 444 */ 445 spinlock_t wmi_ev_lock; 446 struct napi_struct napi_rx; 447 struct napi_struct napi_tx; 448 /* DMA related */ 449 struct vring vring_rx; 450 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 451 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 452 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 453 struct wil_sta_info sta[WIL6210_MAX_CID]; 454 /* scan */ 455 struct cfg80211_scan_request *scan_request; 456 457 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 458 /* statistics */ 459 atomic_t isr_count_rx, isr_count_tx; 460 /* debugfs */ 461 struct dentry *debug; 462 struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)]; 463 464 void *platform_handle; 465 struct wil_platform_ops platform_ops; 466 }; 467 468 #define wil_to_wiphy(i) (i->wdev->wiphy) 469 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 470 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 471 #define wil_to_wdev(i) (i->wdev) 472 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 473 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 474 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 475 476 __printf(2, 3) 477 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 478 __printf(2, 3) 479 void wil_err(struct wil6210_priv *wil, const char *fmt, ...); 480 __printf(2, 3) 481 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 482 __printf(2, 3) 483 void wil_info(struct wil6210_priv *wil, const char *fmt, ...); 484 #define wil_dbg(wil, fmt, arg...) do { \ 485 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 486 wil_dbg_trace(wil, fmt, ##arg); \ 487 } while (0) 488 489 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 490 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 491 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 492 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 493 494 #if defined(CONFIG_DYNAMIC_DEBUG) 495 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 496 groupsize, buf, len, ascii) \ 497 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 498 prefix_type, rowsize, \ 499 groupsize, buf, len, ascii) 500 501 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 502 groupsize, buf, len, ascii) \ 503 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 504 prefix_type, rowsize, \ 505 groupsize, buf, len, ascii) 506 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 507 static inline 508 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 509 int groupsize, const void *buf, size_t len, bool ascii) 510 { 511 } 512 513 static inline 514 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 515 int groupsize, const void *buf, size_t len, bool ascii) 516 { 517 } 518 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 519 520 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 521 size_t count); 522 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 523 size_t count); 524 525 void *wil_if_alloc(struct device *dev, void __iomem *csr); 526 void wil_if_free(struct wil6210_priv *wil); 527 int wil_if_add(struct wil6210_priv *wil); 528 void wil_if_remove(struct wil6210_priv *wil); 529 int wil_priv_init(struct wil6210_priv *wil); 530 void wil_priv_deinit(struct wil6210_priv *wil); 531 int wil_reset(struct wil6210_priv *wil); 532 void wil_set_itr_trsh(struct wil6210_priv *wil); 533 void wil_fw_error_recovery(struct wil6210_priv *wil); 534 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 535 void wil_link_on(struct wil6210_priv *wil); 536 void wil_link_off(struct wil6210_priv *wil); 537 int wil_up(struct wil6210_priv *wil); 538 int __wil_up(struct wil6210_priv *wil); 539 int wil_down(struct wil6210_priv *wil); 540 int __wil_down(struct wil6210_priv *wil); 541 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 542 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 543 void wil_set_ethtoolops(struct net_device *ndev); 544 545 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 546 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 547 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 548 struct wil6210_mbox_hdr *hdr); 549 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 550 void wmi_recv_cmd(struct wil6210_priv *wil); 551 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 552 u16 reply_id, void *reply, u8 reply_size, int to_msec); 553 void wmi_event_worker(struct work_struct *work); 554 void wmi_event_flush(struct wil6210_priv *wil); 555 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 556 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 557 int wmi_set_channel(struct wil6210_priv *wil, int channel); 558 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 559 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 560 const void *mac_addr); 561 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 562 const void *mac_addr, int key_len, const void *key); 563 int wmi_echo(struct wil6210_priv *wil); 564 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 565 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 566 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel); 567 int wmi_rxon(struct wil6210_priv *wil, bool on); 568 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 569 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason); 570 571 void wil6210_clear_irq(struct wil6210_priv *wil); 572 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 573 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 574 void wil_mask_irq(struct wil6210_priv *wil); 575 void wil_unmask_irq(struct wil6210_priv *wil); 576 void wil_disable_irq(struct wil6210_priv *wil); 577 void wil_enable_irq(struct wil6210_priv *wil); 578 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 579 struct cfg80211_mgmt_tx_params *params, 580 u64 *cookie); 581 582 int wil6210_debugfs_init(struct wil6210_priv *wil); 583 void wil6210_debugfs_remove(struct wil6210_priv *wil); 584 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid, 585 struct station_info *sinfo); 586 587 struct wireless_dev *wil_cfg80211_init(struct device *dev); 588 void wil_wdev_free(struct wil6210_priv *wil); 589 590 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 591 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan); 592 int wmi_pcp_stop(struct wil6210_priv *wil); 593 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, 594 u16 reason_code, bool from_event); 595 596 int wil_rx_init(struct wil6210_priv *wil, u16 size); 597 void wil_rx_fini(struct wil6210_priv *wil); 598 599 /* TX API */ 600 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 601 int cid, int tid); 602 void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 603 604 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 605 int wil_tx_complete(struct wil6210_priv *wil, int ringid); 606 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 607 608 /* RX API */ 609 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 610 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 611 612 int wil_iftype_nl2wmi(enum nl80211_iftype type); 613 614 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd); 615 int wil_request_firmware(struct wil6210_priv *wil, const char *name); 616 617 #endif /* __WIL6210_H__ */ 618