1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef __WIL6210_H__ 8 #define __WIL6210_H__ 9 10 #include <linux/etherdevice.h> 11 #include <linux/netdevice.h> 12 #include <linux/wireless.h> 13 #include <net/cfg80211.h> 14 #include <linux/timex.h> 15 #include <linux/types.h> 16 #include <linux/irqreturn.h> 17 #include "wmi.h" 18 #include "wil_platform.h" 19 #include "fw.h" 20 21 extern bool no_fw_recovery; 22 extern unsigned int mtu_max; 23 extern unsigned short rx_ring_overflow_thrsh; 24 extern int agg_wsize; 25 extern bool rx_align_2; 26 extern bool rx_large_buf; 27 extern bool debug_fw; 28 extern bool disable_ap_sme; 29 extern bool ftm_mode; 30 extern bool drop_if_ring_full; 31 extern uint max_assoc_sta; 32 33 struct wil6210_priv; 34 struct wil6210_vif; 35 union wil_tx_desc; 36 37 #define WIL_NAME "wil6210" 38 39 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 40 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 41 42 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 43 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 44 45 #define WIL_FW_NAME_TALYN "wil6436.fw" 46 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 47 #define WIL_BRD_NAME_TALYN "wil6436.brd" 48 49 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 50 51 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 52 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 53 54 #define WIL_NUM_LATENCY_BINS 200 55 56 /* maximum number of virtual interfaces the driver supports 57 * (including the main interface) 58 */ 59 #define WIL_MAX_VIFS 4 60 61 /** 62 * extract bits [@b0:@b1] (inclusive) from the value @x 63 * it should be @b0 <= @b1, or result is incorrect 64 */ 65 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 66 { 67 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 68 } 69 70 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 71 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 72 73 #define WIL_TX_Q_LEN_DEFAULT (4000) 74 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 75 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 76 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 77 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 78 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 79 /* limit ring size in range [32..32k] */ 80 #define WIL_RING_SIZE_ORDER_MIN (5) 81 #define WIL_RING_SIZE_ORDER_MAX (15) 82 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 83 #define WIL6210_MAX_CID (20) /* max number of stations */ 84 #define WIL6210_RX_DESC_MAX_CID (8) /* HW limit */ 85 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 86 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 87 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 88 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 89 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 90 #define WIL6210_MAX_STATUS_RINGS (8) 91 #define WIL_WMI_CALL_GENERAL_TO_MS 100 92 93 /* Hardware offload block adds the following: 94 * 26 bytes - 3-address QoS data header 95 * 8 bytes - IV + EIV (for GCMP) 96 * 8 bytes - SNAP 97 * 16 bytes - MIC (for GCMP) 98 * 4 bytes - CRC 99 */ 100 #define WIL_MAX_MPDU_OVERHEAD (62) 101 102 struct wil_suspend_count_stats { 103 unsigned long successful_suspends; 104 unsigned long successful_resumes; 105 unsigned long failed_suspends; 106 unsigned long failed_resumes; 107 }; 108 109 struct wil_suspend_stats { 110 struct wil_suspend_count_stats r_off; 111 struct wil_suspend_count_stats r_on; 112 unsigned long rejected_by_device; /* only radio on */ 113 unsigned long rejected_by_host; 114 }; 115 116 /* Calculate MAC buffer size for the firmware. It includes all overhead, 117 * as it will go over the air, and need to be 8 byte aligned 118 */ 119 static inline u32 wil_mtu2macbuf(u32 mtu) 120 { 121 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 122 } 123 124 /* MTU for Ethernet need to take into account 8-byte SNAP header 125 * to be added when encapsulating Ethernet frame into 802.11 126 */ 127 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 128 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 129 #define WIL6210_ITR_TRSH_MAX (5000000) 130 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 131 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 132 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 133 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 134 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 135 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 136 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 137 #define WIL6210_DISCONNECT_TO_MS (2000) 138 #define WIL6210_RX_HIGH_TRSH_INIT (0) 139 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 140 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 141 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 142 * 802.11REVmc/D5.0, section 9.4.1.8) 143 */ 144 /* Hardware definitions begin */ 145 146 /* 147 * Mapping 148 * RGF File | Host addr | FW addr 149 * | | 150 * user_rgf | 0x000000 | 0x880000 151 * dma_rgf | 0x001000 | 0x881000 152 * pcie_rgf | 0x002000 | 0x882000 153 * | | 154 */ 155 156 /* Where various structures placed in host address space */ 157 #define WIL6210_FW_HOST_OFF (0x880000UL) 158 159 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 160 161 /* 162 * Interrupt control registers block 163 * 164 * each interrupt controlled by the same bit in all registers 165 */ 166 struct RGF_ICR { 167 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 168 u32 ICR; /* Cause, W1C/COR depending on ICC */ 169 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 170 u32 ICS; /* Cause Set, WO */ 171 u32 IMV; /* Mask, RW+S/C */ 172 u32 IMS; /* Mask Set, write 1 to set */ 173 u32 IMC; /* Mask Clear, write 1 to clear */ 174 } __packed; 175 176 /* registers - FW addresses */ 177 #define RGF_USER_USAGE_1 (0x880004) 178 #define RGF_USER_USAGE_2 (0x880008) 179 #define RGF_USER_USAGE_6 (0x880018) 180 #define BIT_USER_OOB_MODE BIT(31) 181 #define BIT_USER_OOB_R2_MODE BIT(30) 182 #define RGF_USER_USAGE_8 (0x880020) 183 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 184 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 185 #define BIT_USER_EXT_CLK BIT(2) 186 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 187 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 188 #define RGF_USER_USER_CPU_0 (0x8801e0) 189 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 190 #define RGF_USER_CPU_PC (0x8801e8) 191 #define RGF_USER_MAC_CPU_0 (0x8801fc) 192 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 193 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 194 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 195 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 196 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 197 * b8-15:signature 198 */ 199 #define CALIB_RESULT_SIGNATURE (0x11) 200 #define RGF_USER_CLKS_CTL_0 (0x880abc) 201 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 202 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 203 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 204 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 205 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 206 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 207 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 208 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 209 #define BIT_CAR_PERST_RST BIT(7) 210 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 211 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 212 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 213 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 214 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 215 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 216 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 217 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 218 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 219 #define BIT_NO_FLASH_INDICATION BIT(8) 220 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 221 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 222 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 223 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 224 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 225 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 226 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 227 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 228 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 229 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 230 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 231 232 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 233 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 234 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 235 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 236 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 237 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 238 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 239 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 240 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 241 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 242 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 243 244 /* Legacy interrupt moderation control (before Sparrow v2)*/ 245 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 246 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 247 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 248 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 249 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 250 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 251 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 252 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 253 254 /* Offload control (Sparrow B0+) */ 255 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 256 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 257 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 258 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 259 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 260 261 /* New (sparrow v2+) interrupt moderation control */ 262 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 263 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 264 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 265 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 266 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 267 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 268 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 269 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 270 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 271 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 272 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 273 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 274 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 275 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 276 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 277 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 278 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 279 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 280 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 281 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 282 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 283 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 284 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 285 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 286 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 287 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 288 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 289 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 290 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 291 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 292 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 293 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 294 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 295 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 296 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 297 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 298 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 299 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 300 #define RGF_DMA_MISC_CTL (0x881d6c) 301 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 302 303 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 304 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 305 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 306 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 307 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 308 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 309 310 #define RGF_HP_CTRL (0x88265c) 311 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 312 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 313 314 /* MAC timer, usec, for packet lifetime */ 315 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 316 317 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 318 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 319 #define RGF_CAF_OSC_CONTROL (0x88afa4) 320 #define BIT_CAF_OSC_XTAL_EN BIT(0) 321 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 322 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 323 324 #define RGF_OTP_QC_SECURED (0x8a0038) 325 #define BIT_BOOT_FROM_ROM BIT(31) 326 327 /* eDMA */ 328 #define RGF_SCM_PTRS_SUBQ_RD_PTR (0x8b4000) 329 #define RGF_SCM_PTRS_COMPQ_RD_PTR (0x8b4100) 330 #define RGF_DMA_SCM_SUBQ_CONS (0x8b60ec) 331 #define RGF_DMA_SCM_COMPQ_PROD (0x8b616c) 332 333 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 334 335 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 336 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 337 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 338 339 #define RGF_INT_GEN_CTRL (0x8bc0ec) 340 #define BIT_CONTROL_0 BIT(0) 341 342 /* eDMA status interrupts */ 343 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 344 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 345 #define RGF_INT_GEN_TX_ICR (0x8bc110) 346 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 347 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 348 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 349 350 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 351 352 #define USER_EXT_USER_PMU_3 (0x88d00c) 353 #define BIT_PMU_DEVICE_RDY BIT(0) 354 355 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 356 #define JTAG_DEV_ID_SPARROW (0x2632072f) 357 #define JTAG_DEV_ID_TALYN (0x7e0e1) 358 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 359 360 #define RGF_USER_REVISION_ID (0x88afe4) 361 #define RGF_USER_REVISION_ID_MASK (3) 362 #define REVISION_ID_SPARROW_B0 (0x0) 363 #define REVISION_ID_SPARROW_D0 (0x3) 364 365 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 366 #define RGF_OTP_OEM_MAC (0x8a0334) 367 #define RGF_OTP_MAC (0x8a0620) 368 369 /* Talyn-MB */ 370 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 371 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 372 373 /* crash codes for FW/Ucode stored here */ 374 375 /* ASSERT RGFs */ 376 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 377 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 378 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 379 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 380 381 enum { 382 HW_VER_UNKNOWN, 383 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 384 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 385 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 386 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 387 }; 388 389 /* popular locations */ 390 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 391 #define HOST_MBOX HOSTADDR(RGF_MBOX) 392 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 393 394 /* ISR register bits */ 395 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 396 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 397 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 398 399 #define WIL_DATA_COMPLETION_TO_MS 200 400 401 /* Hardware definitions end */ 402 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 403 #define TALYN_FW_MAPPING_TABLE_SIZE 13 404 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 405 #define MAX_FW_MAPPING_TABLE_SIZE 19 406 407 /* Common representation of physical address in wil ring */ 408 struct wil_ring_dma_addr { 409 __le32 addr_low; 410 __le16 addr_high; 411 } __packed; 412 413 struct fw_map { 414 u32 from; /* linker address - from, inclusive */ 415 u32 to; /* linker address - to, exclusive */ 416 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 417 const char *name; /* for debugfs */ 418 bool fw; /* true if FW mapping, false if UCODE mapping */ 419 bool crash_dump; /* true if should be dumped during crash dump */ 420 }; 421 422 /* array size should be in sync with actual definition in the wmi.c */ 423 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 424 extern const struct fw_map sparrow_d0_mac_rgf_ext; 425 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 426 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 427 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 428 429 /** 430 * mk_cidxtid - construct @cidxtid field 431 * @cid: CID value 432 * @tid: TID value 433 * 434 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 435 */ 436 static inline u8 mk_cidxtid(u8 cid, u8 tid) 437 { 438 return ((tid & 0xf) << 4) | (cid & 0xf); 439 } 440 441 /** 442 * parse_cidxtid - parse @cidxtid field 443 * @cid: store CID value here 444 * @tid: store TID value here 445 * 446 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 447 */ 448 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 449 { 450 *cid = cidxtid & 0xf; 451 *tid = (cidxtid >> 4) & 0xf; 452 } 453 454 struct wil6210_mbox_ring { 455 u32 base; 456 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 457 u16 size; 458 u32 tail; 459 u32 head; 460 } __packed; 461 462 struct wil6210_mbox_ring_desc { 463 __le32 sync; 464 __le32 addr; 465 } __packed; 466 467 /* at HOST_OFF_WIL6210_MBOX_CTL */ 468 struct wil6210_mbox_ctl { 469 struct wil6210_mbox_ring tx; 470 struct wil6210_mbox_ring rx; 471 } __packed; 472 473 struct wil6210_mbox_hdr { 474 __le16 seq; 475 __le16 len; /* payload, bytes after this header */ 476 __le16 type; 477 u8 flags; 478 u8 reserved; 479 } __packed; 480 481 #define WIL_MBOX_HDR_TYPE_WMI (0) 482 483 /* max. value for wil6210_mbox_hdr.len */ 484 #define MAX_MBOXITEM_SIZE (240) 485 486 struct pending_wmi_event { 487 struct list_head list; 488 struct { 489 struct wil6210_mbox_hdr hdr; 490 struct wmi_cmd_hdr wmi; 491 u8 data[0]; 492 } __packed event; 493 }; 494 495 enum { /* for wil_ctx.mapped_as */ 496 wil_mapped_as_none = 0, 497 wil_mapped_as_single = 1, 498 wil_mapped_as_page = 2, 499 }; 500 501 /** 502 * struct wil_ctx - software context for ring descriptor 503 */ 504 struct wil_ctx { 505 struct sk_buff *skb; 506 u8 nr_frags; 507 u8 mapped_as; 508 }; 509 510 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 511 u32 *va; 512 dma_addr_t pa; 513 }; 514 515 /** 516 * A general ring structure, used for RX and TX. 517 * In legacy DMA it represents the vring, 518 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 519 */ 520 struct wil_ring { 521 dma_addr_t pa; 522 volatile union wil_ring_desc *va; 523 u16 size; /* number of wil_ring_desc elements */ 524 u32 swtail; 525 u32 swhead; 526 u32 hwtail; /* write here to inform hw */ 527 struct wil_ctx *ctx; /* ctx[size] - software context */ 528 struct wil_desc_ring_rx_swtail edma_rx_swtail; 529 bool is_rx; 530 }; 531 532 /** 533 * Additional data for Rx ring. 534 * Used for enhanced DMA RX chaining. 535 */ 536 struct wil_ring_rx_data { 537 /* the skb being assembled */ 538 struct sk_buff *skb; 539 /* true if we are skipping a bad fragmented packet */ 540 bool skipping; 541 u16 buff_size; 542 }; 543 544 /** 545 * Status ring structure, used for enhanced DMA completions for RX and TX. 546 */ 547 struct wil_status_ring { 548 dma_addr_t pa; 549 void *va; /* pointer to ring_[tr]x_status elements */ 550 u16 size; /* number of status elements */ 551 size_t elem_size; /* status element size in bytes */ 552 u32 swhead; 553 u32 hwtail; /* write here to inform hw */ 554 bool is_rx; 555 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 556 struct wil_ring_rx_data rx_data; 557 u32 invalid_buff_id_cnt; /* relevant only for RX */ 558 }; 559 560 #define WIL_STA_TID_NUM (16) 561 #define WIL_MCS_MAX (15) /* Maximum MCS supported */ 562 563 struct wil_net_stats { 564 unsigned long rx_packets; 565 unsigned long tx_packets; 566 unsigned long rx_bytes; 567 unsigned long tx_bytes; 568 unsigned long tx_errors; 569 u32 tx_latency_min_us; 570 u32 tx_latency_max_us; 571 u64 tx_latency_total_us; 572 unsigned long rx_dropped; 573 unsigned long rx_non_data_frame; 574 unsigned long rx_short_frame; 575 unsigned long rx_large_frame; 576 unsigned long rx_replay; 577 unsigned long rx_mic_error; 578 unsigned long rx_key_error; /* eDMA specific */ 579 unsigned long rx_amsdu_error; /* eDMA specific */ 580 unsigned long rx_csum_err; 581 u16 last_mcs_rx; 582 u8 last_cb_mode_rx; 583 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 584 u32 ft_roams; /* relevant in STA mode */ 585 }; 586 587 /** 588 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 589 * DMA flow 590 */ 591 struct wil_txrx_ops { 592 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 593 /* TX ops */ 594 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 595 int size, int cid, int tid); 596 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 597 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 598 int (*tx_init)(struct wil6210_priv *wil); 599 void (*tx_fini)(struct wil6210_priv *wil); 600 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 601 u32 len, int ring_index); 602 void (*tx_desc_unmap)(struct device *dev, 603 union wil_tx_desc *desc, 604 struct wil_ctx *ctx); 605 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 606 struct wil_ring *ring, struct sk_buff *skb); 607 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 608 int cid, int tid); 609 irqreturn_t (*irq_tx)(int irq, void *cookie); 610 /* RX ops */ 611 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 612 void (*rx_fini)(struct wil6210_priv *wil); 613 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 614 u8 tid, u8 token, u16 status, bool amsdu, 615 u16 agg_wsize, u16 timeout); 616 void (*get_reorder_params)(struct wil6210_priv *wil, 617 struct sk_buff *skb, int *tid, int *cid, 618 int *mid, u16 *seq, int *mcast, int *retry); 619 void (*get_netif_rx_params)(struct sk_buff *skb, 620 int *cid, int *security); 621 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 622 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 623 struct wil_net_stats *stats); 624 bool (*is_rx_idle)(struct wil6210_priv *wil); 625 irqreturn_t (*irq_rx)(int irq, void *cookie); 626 }; 627 628 /** 629 * Additional data for Tx ring 630 */ 631 struct wil_ring_tx_data { 632 bool dot1x_open; 633 int enabled; 634 cycles_t idle, last_idle, begin; 635 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 636 u16 agg_timeout; 637 u8 agg_amsdu; 638 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 639 u8 mid; 640 spinlock_t lock; 641 }; 642 643 enum { /* for wil6210_priv.status */ 644 wil_status_fwready = 0, /* FW operational */ 645 wil_status_dontscan, 646 wil_status_mbox_ready, /* MBOX structures ready */ 647 wil_status_irqen, /* interrupts enabled - for debug */ 648 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 649 wil_status_resetting, /* reset in progress */ 650 wil_status_suspending, /* suspend in progress */ 651 wil_status_suspended, /* suspend completed, device is suspended */ 652 wil_status_resuming, /* resume in progress */ 653 wil_status_last /* keep last */ 654 }; 655 656 struct pci_dev; 657 658 /** 659 * struct tid_ampdu_rx - TID aggregation information (Rx). 660 * 661 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 662 * @last_rx: jiffies of last rx activity 663 * @head_seq_num: head sequence number in reordering buffer. 664 * @stored_mpdu_num: number of MPDUs in reordering buffer 665 * @ssn: Starting Sequence Number expected to be aggregated. 666 * @buf_size: buffer size for incoming A-MPDUs 667 * @ssn_last_drop: SSN of the last dropped frame 668 * @total: total number of processed incoming frames 669 * @drop_dup: duplicate frames dropped for this reorder buffer 670 * @drop_old: old frames dropped for this reorder buffer 671 * @first_time: true when this buffer used 1-st time 672 * @mcast_last_seq: sequence number (SN) of last received multicast packet 673 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 674 */ 675 struct wil_tid_ampdu_rx { 676 struct sk_buff **reorder_buf; 677 unsigned long last_rx; 678 u16 head_seq_num; 679 u16 stored_mpdu_num; 680 u16 ssn; 681 u16 buf_size; 682 u16 ssn_last_drop; 683 unsigned long long total; /* frames processed */ 684 unsigned long long drop_dup; 685 unsigned long long drop_old; 686 bool first_time; /* is it 1-st time this buffer used? */ 687 u16 mcast_last_seq; /* multicast dup detection */ 688 unsigned long long drop_dup_mcast; 689 }; 690 691 /** 692 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 693 * 694 * @pn: GCMP PN for the session 695 * @key_set: valid key present 696 */ 697 struct wil_tid_crypto_rx_single { 698 u8 pn[IEEE80211_GCMP_PN_LEN]; 699 bool key_set; 700 }; 701 702 struct wil_tid_crypto_rx { 703 struct wil_tid_crypto_rx_single key_id[4]; 704 }; 705 706 struct wil_p2p_info { 707 struct ieee80211_channel listen_chan; 708 u8 discovery_started; 709 u64 cookie; 710 struct wireless_dev *pending_listen_wdev; 711 unsigned int listen_duration; 712 struct timer_list discovery_timer; /* listen/search duration */ 713 struct work_struct discovery_expired_work; /* listen/search expire */ 714 struct work_struct delayed_listen_work; /* listen after scan done */ 715 }; 716 717 enum wil_sta_status { 718 wil_sta_unused = 0, 719 wil_sta_conn_pending = 1, 720 wil_sta_connected = 2, 721 }; 722 723 enum wil_rekey_state { 724 WIL_REKEY_IDLE = 0, 725 WIL_REKEY_M3_RECEIVED = 1, 726 WIL_REKEY_WAIT_M4_SENT = 2, 727 }; 728 729 /** 730 * struct wil_sta_info - data for peer 731 * 732 * Peer identified by its CID (connection ID) 733 * NIC performs beam forming for each peer; 734 * if no beam forming done, frame exchange is not 735 * possible. 736 */ 737 struct wil_sta_info { 738 u8 addr[ETH_ALEN]; 739 u8 mid; 740 enum wil_sta_status status; 741 struct wil_net_stats stats; 742 /** 743 * 20 latency bins. 1st bin counts packets with latency 744 * of 0..tx_latency_res, last bin counts packets with latency 745 * of 19*tx_latency_res and above. 746 * tx_latency_res is configured from "tx_latency" debug-fs. 747 */ 748 u64 *tx_latency_bins; 749 struct wmi_link_stats_basic fw_stats_basic; 750 /* Rx BACK */ 751 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 752 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 753 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 754 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 755 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 756 struct wil_tid_crypto_rx group_crypto_rx; 757 u8 aid; /* 1-254; 0 if unknown/not reported */ 758 }; 759 760 enum { 761 fw_recovery_idle = 0, 762 fw_recovery_pending = 1, 763 fw_recovery_running = 2, 764 }; 765 766 enum { 767 hw_capa_no_flash, 768 hw_capa_last 769 }; 770 771 struct wil_probe_client_req { 772 struct list_head list; 773 u64 cookie; 774 u8 cid; 775 }; 776 777 struct pmc_ctx { 778 /* alloc, free, and read operations must own the lock */ 779 struct mutex lock; 780 struct vring_tx_desc *pring_va; 781 dma_addr_t pring_pa; 782 struct desc_alloc_info *descriptors; 783 int last_cmd_status; 784 int num_descriptors; 785 int descriptor_size; 786 }; 787 788 struct wil_halp { 789 struct mutex lock; /* protect halp ref_cnt */ 790 unsigned int ref_cnt; 791 struct completion comp; 792 u8 handle_icr; 793 }; 794 795 struct wil_blob_wrapper { 796 struct wil6210_priv *wil; 797 struct debugfs_blob_wrapper blob; 798 }; 799 800 #define WIL_LED_MAX_ID (2) 801 #define WIL_LED_INVALID_ID (0xF) 802 #define WIL_LED_BLINK_ON_SLOW_MS (300) 803 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 804 #define WIL_LED_BLINK_ON_MED_MS (200) 805 #define WIL_LED_BLINK_OFF_MED_MS (200) 806 #define WIL_LED_BLINK_ON_FAST_MS (100) 807 #define WIL_LED_BLINK_OFF_FAST_MS (100) 808 enum { 809 WIL_LED_TIME_SLOW = 0, 810 WIL_LED_TIME_MED, 811 WIL_LED_TIME_FAST, 812 WIL_LED_TIME_LAST, 813 }; 814 815 struct blink_on_off_time { 816 u32 on_ms; 817 u32 off_ms; 818 }; 819 820 struct wil_debugfs_iomem_data { 821 void *offset; 822 struct wil6210_priv *wil; 823 }; 824 825 struct wil_debugfs_data { 826 struct wil_debugfs_iomem_data *data_arr; 827 int iomem_data_count; 828 }; 829 830 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 831 extern u8 led_id; 832 extern u8 led_polarity; 833 834 enum wil6210_vif_status { 835 wil_vif_fwconnecting, 836 wil_vif_fwconnected, 837 wil_vif_ft_roam, 838 wil_vif_status_last /* keep last */ 839 }; 840 841 struct wil6210_vif { 842 struct wireless_dev wdev; 843 struct net_device *ndev; 844 struct wil6210_priv *wil; 845 u8 mid; 846 DECLARE_BITMAP(status, wil_vif_status_last); 847 u32 privacy; /* secure connection? */ 848 u16 channel; /* relevant in AP mode */ 849 u8 wmi_edmg_channel; /* relevant in AP mode */ 850 u8 hidden_ssid; /* relevant in AP mode */ 851 u32 ap_isolate; /* no intra-BSS communication */ 852 bool pbss; 853 int bi; 854 u8 *proberesp, *proberesp_ies, *assocresp_ies; 855 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 856 u8 ssid[IEEE80211_MAX_SSID_LEN]; 857 size_t ssid_len; 858 u8 gtk_index; 859 u8 gtk[WMI_MAX_KEY_LEN]; 860 size_t gtk_len; 861 int bcast_ring; 862 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 863 int locally_generated_disc; /* relevant in STA mode */ 864 struct timer_list connect_timer; 865 struct work_struct disconnect_worker; 866 /* scan */ 867 struct cfg80211_scan_request *scan_request; 868 struct timer_list scan_timer; /* detect scan timeout */ 869 struct wil_p2p_info p2p; 870 /* keep alive */ 871 struct list_head probe_client_pending; 872 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 873 struct work_struct probe_client_worker; 874 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 875 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 876 u64 fw_stats_tsf; /* measurement timestamp */ 877 878 /* PTK rekey race prevention, this is relevant to station mode only */ 879 enum wil_rekey_state ptk_rekey_state; 880 struct work_struct enable_tx_key_worker; 881 }; 882 883 /** 884 * RX buffer allocated for enhanced DMA RX descriptors 885 */ 886 struct wil_rx_buff { 887 struct sk_buff *skb; 888 struct list_head list; 889 int id; 890 }; 891 892 /** 893 * During Rx completion processing, the driver extracts a buffer ID which 894 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 895 * is given to the network stack and the buffer is moved from the 'active' 896 * list to the 'free' list. 897 * During Rx refill, SKBs are attached to free buffers and moved to the 898 * 'active' list. 899 */ 900 struct wil_rx_buff_mgmt { 901 struct wil_rx_buff *buff_arr; 902 size_t size; /* number of items in buff_arr */ 903 struct list_head active; 904 struct list_head free; 905 unsigned long free_list_empty_cnt; /* statistics */ 906 }; 907 908 struct wil_fw_stats_global { 909 bool ready; 910 u64 tsf; /* measurement timestamp */ 911 struct wmi_link_stats_global stats; 912 }; 913 914 struct wil_brd_info { 915 u32 file_addr; 916 u32 file_max_size; 917 }; 918 919 struct wil6210_priv { 920 struct pci_dev *pdev; 921 u32 bar_size; 922 struct wiphy *wiphy; 923 struct net_device *main_ndev; 924 int n_msi; 925 void __iomem *csr; 926 DECLARE_BITMAP(status, wil_status_last); 927 u8 fw_version[ETHTOOL_FWVERS_LEN]; 928 u32 hw_version; 929 u8 chip_revision; 930 const char *hw_name; 931 const char *wil_fw_name; 932 char *board_file; 933 u32 num_of_brd_entries; 934 struct wil_brd_info *brd_info; 935 DECLARE_BITMAP(hw_capa, hw_capa_last); 936 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 937 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 938 u32 recovery_count; /* num of FW recovery attempts in a short time */ 939 u32 recovery_state; /* FW recovery state machine */ 940 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 941 wait_queue_head_t wq; /* for all wait_event() use */ 942 u8 max_vifs; /* maximum number of interfaces, including main */ 943 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 944 struct mutex vif_mutex; /* protects access to VIF entries */ 945 atomic_t connected_vifs; 946 u32 max_assoc_sta; /* max sta's supported by the driver and the FW */ 947 948 /* profile */ 949 struct cfg80211_chan_def monitor_chandef; 950 u32 monitor_flags; 951 int sinfo_gen; 952 /* interrupt moderation */ 953 u32 tx_max_burst_duration; 954 u32 tx_interframe_timeout; 955 u32 rx_max_burst_duration; 956 u32 rx_interframe_timeout; 957 /* cached ISR registers */ 958 u32 isr_misc; 959 /* mailbox related */ 960 struct mutex wmi_mutex; 961 struct wil6210_mbox_ctl mbox_ctl; 962 struct completion wmi_ready; 963 struct completion wmi_call; 964 u16 wmi_seq; 965 u16 reply_id; /**< wait for this WMI event */ 966 u8 reply_mid; 967 void *reply_buf; 968 u16 reply_size; 969 struct workqueue_struct *wmi_wq; /* for deferred calls */ 970 struct work_struct wmi_event_worker; 971 struct workqueue_struct *wq_service; 972 struct work_struct fw_error_worker; /* for FW error recovery */ 973 struct list_head pending_wmi_ev; 974 /* 975 * protect pending_wmi_ev 976 * - fill in IRQ from wil6210_irq_misc, 977 * - consumed in thread by wmi_event_worker 978 */ 979 spinlock_t wmi_ev_lock; 980 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 981 spinlock_t eap_lock; /* guarding access to eap rekey fields */ 982 struct napi_struct napi_rx; 983 struct napi_struct napi_tx; 984 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 985 986 /* DMA related */ 987 struct wil_ring ring_rx; 988 unsigned int rx_buf_len; 989 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 990 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 991 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 992 u8 num_rx_status_rings; 993 int tx_sring_idx; 994 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 995 struct wil_sta_info sta[WIL6210_MAX_CID]; 996 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 997 u32 dma_addr_size; /* indicates dma addr size */ 998 struct wil_rx_buff_mgmt rx_buff_mgmt; 999 bool use_enhanced_dma_hw; 1000 struct wil_txrx_ops txrx_ops; 1001 1002 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 1003 /* for synchronizing device memory access while reset or suspend */ 1004 struct rw_semaphore mem_lock; 1005 /* statistics */ 1006 atomic_t isr_count_rx, isr_count_tx; 1007 /* debugfs */ 1008 struct dentry *debug; 1009 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 1010 u8 discovery_mode; 1011 u8 abft_len; 1012 u8 wakeup_trigger; 1013 struct wil_suspend_stats suspend_stats; 1014 struct wil_debugfs_data dbg_data; 1015 bool tx_latency; /* collect TX latency measurements */ 1016 size_t tx_latency_res; /* bin resolution in usec */ 1017 1018 void *platform_handle; 1019 struct wil_platform_ops platform_ops; 1020 bool keep_radio_on_during_sleep; 1021 1022 struct pmc_ctx pmc; 1023 1024 u8 p2p_dev_started; 1025 1026 /* P2P_DEVICE vif */ 1027 struct wireless_dev *p2p_wdev; 1028 struct wireless_dev *radio_wdev; 1029 1030 /* High Access Latency Policy voting */ 1031 struct wil_halp halp; 1032 1033 enum wmi_ps_profile_type ps_profile; 1034 1035 int fw_calib_result; 1036 1037 struct notifier_block pm_notify; 1038 1039 bool suspend_resp_rcvd; 1040 bool suspend_resp_comp; 1041 u32 bus_request_kbps; 1042 u32 bus_request_kbps_pre_suspend; 1043 1044 u32 rgf_fw_assert_code_addr; 1045 u32 rgf_ucode_assert_code_addr; 1046 u32 iccm_base; 1047 1048 /* relevant only for eDMA */ 1049 bool use_compressed_rx_status; 1050 u32 rx_status_ring_order; 1051 u32 tx_status_ring_order; 1052 u32 rx_buff_id_count; 1053 bool amsdu_en; 1054 bool use_rx_hw_reordering; 1055 bool secured_boot; 1056 u8 boot_config; 1057 1058 struct wil_fw_stats_global fw_stats_global; 1059 1060 u32 max_agg_wsize; 1061 u32 max_ampdu_size; 1062 u8 multicast_to_unicast; 1063 s32 cqm_rssi_thold; 1064 }; 1065 1066 #define wil_to_wiphy(i) (i->wiphy) 1067 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1068 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1069 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1070 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1071 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1072 #define vif_to_wil(v) (v->wil) 1073 #define vif_to_ndev(v) (v->ndev) 1074 #define vif_to_wdev(v) (&v->wdev) 1075 #define GET_MAX_VIFS(wil) min_t(int, (wil)->max_vifs, WIL_MAX_VIFS) 1076 1077 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1078 struct wireless_dev *wdev) 1079 { 1080 /* main interface is shared with P2P device */ 1081 if (wdev == wil->p2p_wdev) 1082 return ndev_to_vif(wil->main_ndev); 1083 else 1084 return container_of(wdev, struct wil6210_vif, wdev); 1085 } 1086 1087 static inline struct wireless_dev * 1088 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1089 { 1090 /* main interface is shared with P2P device */ 1091 if (vif->mid) 1092 return vif_to_wdev(vif); 1093 else 1094 return wil->radio_wdev; 1095 } 1096 1097 __printf(2, 3) 1098 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1099 __printf(2, 3) 1100 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1101 __printf(2, 3) 1102 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1103 __printf(2, 3) 1104 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1105 __printf(2, 3) 1106 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1107 #define wil_dbg(wil, fmt, arg...) do { \ 1108 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1109 wil_dbg_trace(wil, fmt, ##arg); \ 1110 } while (0) 1111 1112 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1113 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1114 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1115 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1116 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1117 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1118 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1119 #define wil_err_ratelimited(wil, fmt, arg...) \ 1120 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1121 1122 /* target operations */ 1123 /* register read */ 1124 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1125 { 1126 return readl(wil->csr + HOSTADDR(reg)); 1127 } 1128 1129 /* register write. wmb() to make sure it is completed */ 1130 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1131 { 1132 writel(val, wil->csr + HOSTADDR(reg)); 1133 wmb(); /* wait for write to propagate to the HW */ 1134 } 1135 1136 /* register set = read, OR, write */ 1137 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1138 { 1139 wil_w(wil, reg, wil_r(wil, reg) | val); 1140 } 1141 1142 /* register clear = read, AND with inverted, write */ 1143 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1144 { 1145 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1146 } 1147 1148 /** 1149 * wil_cid_valid - check cid is valid 1150 */ 1151 static inline bool wil_cid_valid(struct wil6210_priv *wil, int cid) 1152 { 1153 return (cid >= 0 && cid < wil->max_assoc_sta && cid < WIL6210_MAX_CID); 1154 } 1155 1156 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1157 1158 #if defined(CONFIG_DYNAMIC_DEBUG) 1159 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1160 groupsize, buf, len, ascii) \ 1161 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1162 prefix_type, rowsize, \ 1163 groupsize, buf, len, ascii) 1164 1165 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1166 groupsize, buf, len, ascii) \ 1167 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1168 prefix_type, rowsize, \ 1169 groupsize, buf, len, ascii) 1170 1171 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1172 groupsize, buf, len, ascii) \ 1173 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1174 prefix_type, rowsize, \ 1175 groupsize, buf, len, ascii) 1176 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1177 static inline 1178 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1179 int groupsize, const void *buf, size_t len, bool ascii) 1180 { 1181 } 1182 1183 static inline 1184 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1185 int groupsize, const void *buf, size_t len, bool ascii) 1186 { 1187 } 1188 1189 static inline 1190 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1191 int groupsize, const void *buf, size_t len, bool ascii) 1192 { 1193 } 1194 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1195 1196 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1197 size_t count); 1198 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1199 size_t count); 1200 int wil_mem_access_lock(struct wil6210_priv *wil); 1201 void wil_mem_access_unlock(struct wil6210_priv *wil); 1202 1203 struct wil6210_vif * 1204 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1205 unsigned char name_assign_type, enum nl80211_iftype iftype); 1206 void wil_vif_free(struct wil6210_vif *vif); 1207 void *wil_if_alloc(struct device *dev); 1208 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1209 struct net_device *ndev, bool up, bool ok); 1210 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1211 void wil_if_free(struct wil6210_priv *wil); 1212 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1213 int wil_if_add(struct wil6210_priv *wil); 1214 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1215 void wil_if_remove(struct wil6210_priv *wil); 1216 int wil_priv_init(struct wil6210_priv *wil); 1217 void wil_priv_deinit(struct wil6210_priv *wil); 1218 int wil_ps_update(struct wil6210_priv *wil, 1219 enum wmi_ps_profile_type ps_profile); 1220 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1221 void wil_fw_error_recovery(struct wil6210_priv *wil); 1222 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1223 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1224 int wil_up(struct wil6210_priv *wil); 1225 int __wil_up(struct wil6210_priv *wil); 1226 int wil_down(struct wil6210_priv *wil); 1227 int __wil_down(struct wil6210_priv *wil); 1228 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1229 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1230 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1231 int wil_find_cid_by_idx(struct wil6210_priv *wil, u8 mid, int idx); 1232 void wil_set_ethtoolops(struct net_device *ndev); 1233 1234 struct fw_map *wil_find_fw_mapping(const char *section); 1235 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1236 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1237 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1238 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1239 struct wil6210_mbox_hdr *hdr); 1240 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1241 void wmi_recv_cmd(struct wil6210_priv *wil); 1242 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1243 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1244 void wmi_event_worker(struct work_struct *work); 1245 void wmi_event_flush(struct wil6210_priv *wil); 1246 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1247 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1248 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1249 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1250 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1251 const void *mac_addr, int key_usage); 1252 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1253 const void *mac_addr, int key_len, const void *key, 1254 int key_usage); 1255 int wmi_echo(struct wil6210_priv *wil); 1256 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1257 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1258 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1259 int wmi_rxon(struct wil6210_priv *wil, bool on); 1260 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1261 int wmi_get_all_temperatures(struct wil6210_priv *wil, 1262 struct wmi_temp_sense_all_done_event 1263 *sense_all_evt); 1264 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1265 bool del_sta); 1266 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1267 u8 ringid, u8 size, u16 timeout); 1268 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1269 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason); 1270 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1271 u8 mid, u8 cid, u8 tid, u8 token, 1272 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1273 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1274 enum wmi_ps_profile_type ps_profile); 1275 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1276 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1277 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1278 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1279 const u8 *mac, enum nl80211_iftype iftype); 1280 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1281 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1282 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, 1283 u8 dialog_token, __le16 ba_param_set, 1284 __le16 ba_timeout, __le16 ba_seq_ctrl); 1285 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1286 1287 void wil6210_clear_irq(struct wil6210_priv *wil); 1288 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1289 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1290 void wil_mask_irq(struct wil6210_priv *wil); 1291 void wil_unmask_irq(struct wil6210_priv *wil); 1292 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1293 void wil_disable_irq(struct wil6210_priv *wil); 1294 void wil_enable_irq(struct wil6210_priv *wil); 1295 void wil6210_mask_halp(struct wil6210_priv *wil); 1296 1297 /* P2P */ 1298 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1299 int wil_p2p_search(struct wil6210_vif *vif, 1300 struct cfg80211_scan_request *request); 1301 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1302 unsigned int duration, struct ieee80211_channel *chan, 1303 u64 *cookie); 1304 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1305 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1306 void wil_p2p_listen_expired(struct work_struct *work); 1307 void wil_p2p_search_expired(struct work_struct *work); 1308 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1309 void wil_p2p_delayed_listen_work(struct work_struct *work); 1310 1311 /* WMI for P2P */ 1312 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1313 int wmi_start_listen(struct wil6210_vif *vif); 1314 int wmi_start_search(struct wil6210_vif *vif); 1315 int wmi_stop_discovery(struct wil6210_vif *vif); 1316 1317 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1318 struct cfg80211_mgmt_tx_params *params, 1319 u64 *cookie); 1320 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1321 int wil_cfg80211_iface_combinations_from_fw( 1322 struct wil6210_priv *wil, 1323 const struct wil_fw_record_concurrency *conc); 1324 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1325 1326 #if defined(CONFIG_WIL6210_DEBUGFS) 1327 int wil6210_debugfs_init(struct wil6210_priv *wil); 1328 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1329 #else 1330 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1331 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1332 #endif 1333 1334 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1335 struct station_info *sinfo); 1336 1337 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1338 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1339 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1340 1341 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1342 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1343 u8 edmg_chan, u8 hidden_ssid, u8 is_go); 1344 int wmi_pcp_stop(struct wil6210_vif *vif); 1345 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1346 int wmi_abort_scan(struct wil6210_vif *vif); 1347 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1348 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1349 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1350 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1351 u16 reason_code); 1352 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1353 u16 reason_code); 1354 void wil_probe_client_flush(struct wil6210_vif *vif); 1355 void wil_probe_client_worker(struct work_struct *work); 1356 void wil_disconnect_worker(struct work_struct *work); 1357 void wil_enable_tx_key_worker(struct work_struct *work); 1358 1359 void wil_init_txrx_ops(struct wil6210_priv *wil); 1360 1361 /* TX API */ 1362 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1363 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1364 int wil_bcast_init(struct wil6210_vif *vif); 1365 void wil_bcast_fini(struct wil6210_vif *vif); 1366 void wil_bcast_fini_all(struct wil6210_priv *wil); 1367 1368 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1369 struct wil_ring *ring, bool should_stop); 1370 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1371 struct wil_ring *ring, bool check_stop); 1372 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1373 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1374 void wil_tx_complete_handle_eapol(struct wil6210_vif *vif, 1375 struct sk_buff *skb); 1376 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1377 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1378 1379 /* RX API */ 1380 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1381 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1382 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1383 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1384 struct wil_sta_info *cs, 1385 struct key_params *params); 1386 1387 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1388 1389 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1390 bool load); 1391 int wil_request_board(struct wil6210_priv *wil, const char *name); 1392 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1393 1394 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1395 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1396 int wil_pm_runtime_get(struct wil6210_priv *wil); 1397 void wil_pm_runtime_put(struct wil6210_priv *wil); 1398 1399 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1400 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1401 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1402 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1403 int wmi_resume(struct wil6210_priv *wil); 1404 int wmi_suspend(struct wil6210_priv *wil); 1405 bool wil_is_tx_idle(struct wil6210_priv *wil); 1406 1407 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1408 void wil_fw_core_dump(struct wil6210_priv *wil); 1409 1410 void wil_halp_vote(struct wil6210_priv *wil); 1411 void wil_halp_unvote(struct wil6210_priv *wil); 1412 void wil6210_set_halp(struct wil6210_priv *wil); 1413 void wil6210_clear_halp(struct wil6210_priv *wil); 1414 1415 int wmi_start_sched_scan(struct wil6210_priv *wil, 1416 struct cfg80211_sched_scan_request *request); 1417 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1418 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1419 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1420 u8 channel, u16 duration_ms); 1421 int wmi_rbufcap_cfg(struct wil6210_priv *wil, bool enable, u16 threshold); 1422 1423 int wil_wmi2spec_ch(u8 wmi_ch, u8 *spec_ch); 1424 int wil_spec2wmi_ch(u8 spec_ch, u8 *wmi_ch); 1425 void wil_update_supported_bands(struct wil6210_priv *wil); 1426 1427 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1428 1429 /* WMI for enhanced DMA */ 1430 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1431 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1432 u16 max_rx_pl_per_desc); 1433 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1434 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1435 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1436 int tid); 1437 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1438 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1439 u8 tid, u8 token, u16 status, bool amsdu, 1440 u16 agg_wsize, u16 timeout); 1441 1442 void update_supported_bands(struct wil6210_priv *wil); 1443 1444 void wil_clear_fw_log_addr(struct wil6210_priv *wil); 1445 int wmi_set_cqm_rssi_config(struct wil6210_priv *wil, 1446 s32 rssi_thold, u32 rssi_hyst); 1447 #endif /* __WIL6210_H__ */ 1448