1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 extern bool ftm_mode; 41 extern bool drop_if_ring_full; 42 extern uint max_assoc_sta; 43 44 struct wil6210_priv; 45 struct wil6210_vif; 46 union wil_tx_desc; 47 48 #define WIL_NAME "wil6210" 49 50 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 51 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 52 53 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 54 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 55 56 #define WIL_FW_NAME_TALYN "wil6436.fw" 57 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 58 #define WIL_BRD_NAME_TALYN "wil6436.brd" 59 60 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 61 62 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 63 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 64 65 #define WIL_NUM_LATENCY_BINS 200 66 67 /* maximum number of virtual interfaces the driver supports 68 * (including the main interface) 69 */ 70 #define WIL_MAX_VIFS 4 71 72 /** 73 * extract bits [@b0:@b1] (inclusive) from the value @x 74 * it should be @b0 <= @b1, or result is incorrect 75 */ 76 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 77 { 78 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 79 } 80 81 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 82 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 83 84 #define WIL_TX_Q_LEN_DEFAULT (4000) 85 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 86 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 87 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 88 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 89 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 90 /* limit ring size in range [32..32k] */ 91 #define WIL_RING_SIZE_ORDER_MIN (5) 92 #define WIL_RING_SIZE_ORDER_MAX (15) 93 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 94 #define WIL6210_MAX_CID (20) /* max number of stations */ 95 #define WIL6210_RX_DESC_MAX_CID (8) /* HW limit */ 96 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 97 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 98 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 99 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 100 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 101 #define WIL6210_MAX_STATUS_RINGS (8) 102 103 /* Hardware offload block adds the following: 104 * 26 bytes - 3-address QoS data header 105 * 8 bytes - IV + EIV (for GCMP) 106 * 8 bytes - SNAP 107 * 16 bytes - MIC (for GCMP) 108 * 4 bytes - CRC 109 */ 110 #define WIL_MAX_MPDU_OVERHEAD (62) 111 112 struct wil_suspend_count_stats { 113 unsigned long successful_suspends; 114 unsigned long successful_resumes; 115 unsigned long failed_suspends; 116 unsigned long failed_resumes; 117 }; 118 119 struct wil_suspend_stats { 120 struct wil_suspend_count_stats r_off; 121 struct wil_suspend_count_stats r_on; 122 unsigned long rejected_by_device; /* only radio on */ 123 unsigned long rejected_by_host; 124 }; 125 126 /* Calculate MAC buffer size for the firmware. It includes all overhead, 127 * as it will go over the air, and need to be 8 byte aligned 128 */ 129 static inline u32 wil_mtu2macbuf(u32 mtu) 130 { 131 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 132 } 133 134 /* MTU for Ethernet need to take into account 8-byte SNAP header 135 * to be added when encapsulating Ethernet frame into 802.11 136 */ 137 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 138 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 139 #define WIL6210_ITR_TRSH_MAX (5000000) 140 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 141 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 142 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 143 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 144 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 145 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 146 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 147 #define WIL6210_DISCONNECT_TO_MS (2000) 148 #define WIL6210_RX_HIGH_TRSH_INIT (0) 149 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 150 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 151 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 152 * 802.11REVmc/D5.0, section 9.4.1.8) 153 */ 154 /* Hardware definitions begin */ 155 156 /* 157 * Mapping 158 * RGF File | Host addr | FW addr 159 * | | 160 * user_rgf | 0x000000 | 0x880000 161 * dma_rgf | 0x001000 | 0x881000 162 * pcie_rgf | 0x002000 | 0x882000 163 * | | 164 */ 165 166 /* Where various structures placed in host address space */ 167 #define WIL6210_FW_HOST_OFF (0x880000UL) 168 169 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 170 171 /* 172 * Interrupt control registers block 173 * 174 * each interrupt controlled by the same bit in all registers 175 */ 176 struct RGF_ICR { 177 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 178 u32 ICR; /* Cause, W1C/COR depending on ICC */ 179 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 180 u32 ICS; /* Cause Set, WO */ 181 u32 IMV; /* Mask, RW+S/C */ 182 u32 IMS; /* Mask Set, write 1 to set */ 183 u32 IMC; /* Mask Clear, write 1 to clear */ 184 } __packed; 185 186 /* registers - FW addresses */ 187 #define RGF_USER_USAGE_1 (0x880004) 188 #define RGF_USER_USAGE_6 (0x880018) 189 #define BIT_USER_OOB_MODE BIT(31) 190 #define BIT_USER_OOB_R2_MODE BIT(30) 191 #define RGF_USER_USAGE_8 (0x880020) 192 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 193 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 194 #define BIT_USER_EXT_CLK BIT(2) 195 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 196 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 197 #define RGF_USER_USER_CPU_0 (0x8801e0) 198 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 199 #define RGF_USER_CPU_PC (0x8801e8) 200 #define RGF_USER_MAC_CPU_0 (0x8801fc) 201 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 202 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 203 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 204 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 205 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 206 * b8-15:signature 207 */ 208 #define CALIB_RESULT_SIGNATURE (0x11) 209 #define RGF_USER_CLKS_CTL_0 (0x880abc) 210 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 211 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 212 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 213 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 214 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 215 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 216 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 217 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 218 #define BIT_CAR_PERST_RST BIT(7) 219 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 220 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 221 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 222 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 223 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 224 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 225 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 226 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 227 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 228 #define BIT_NO_FLASH_INDICATION BIT(8) 229 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 230 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 231 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 232 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 233 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 234 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 235 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 236 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 237 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 238 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 239 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 240 241 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 242 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 243 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 244 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 245 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 246 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 247 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 248 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 249 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 250 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 251 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 252 253 /* Legacy interrupt moderation control (before Sparrow v2)*/ 254 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 255 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 256 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 257 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 258 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 259 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 260 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 261 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 262 263 /* Offload control (Sparrow B0+) */ 264 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 265 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 266 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 267 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 268 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 269 270 /* New (sparrow v2+) interrupt moderation control */ 271 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 272 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 273 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 274 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 275 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 276 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 277 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 278 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 279 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 280 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 281 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 282 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 283 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 284 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 285 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 286 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 287 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 288 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 289 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 290 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 291 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 292 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 293 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 294 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 295 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 296 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 297 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 298 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 299 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 300 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 301 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 302 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 303 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 304 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 305 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 306 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 307 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 308 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 309 #define RGF_DMA_MISC_CTL (0x881d6c) 310 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 311 312 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 313 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 314 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 315 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 316 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 317 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 318 319 #define RGF_HP_CTRL (0x88265c) 320 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 321 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 322 323 /* MAC timer, usec, for packet lifetime */ 324 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 325 326 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 327 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 328 #define RGF_CAF_OSC_CONTROL (0x88afa4) 329 #define BIT_CAF_OSC_XTAL_EN BIT(0) 330 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 331 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 332 333 #define RGF_OTP_QC_SECURED (0x8a0038) 334 #define BIT_BOOT_FROM_ROM BIT(31) 335 336 /* eDMA */ 337 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 338 339 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 340 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 341 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 342 343 #define RGF_INT_GEN_CTRL (0x8bc0ec) 344 #define BIT_CONTROL_0 BIT(0) 345 346 /* eDMA status interrupts */ 347 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 348 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 349 #define RGF_INT_GEN_TX_ICR (0x8bc110) 350 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 351 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 352 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 353 354 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 355 356 #define USER_EXT_USER_PMU_3 (0x88d00c) 357 #define BIT_PMU_DEVICE_RDY BIT(0) 358 359 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 360 #define JTAG_DEV_ID_SPARROW (0x2632072f) 361 #define JTAG_DEV_ID_TALYN (0x7e0e1) 362 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 363 364 #define RGF_USER_REVISION_ID (0x88afe4) 365 #define RGF_USER_REVISION_ID_MASK (3) 366 #define REVISION_ID_SPARROW_B0 (0x0) 367 #define REVISION_ID_SPARROW_D0 (0x3) 368 369 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 370 #define RGF_OTP_MAC (0x8a0620) 371 372 /* Talyn-MB */ 373 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 374 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 375 376 /* crash codes for FW/Ucode stored here */ 377 378 /* ASSERT RGFs */ 379 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 380 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 381 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 382 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 383 384 enum { 385 HW_VER_UNKNOWN, 386 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 387 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 388 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 389 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 390 }; 391 392 /* popular locations */ 393 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 394 #define HOST_MBOX HOSTADDR(RGF_MBOX) 395 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 396 397 /* ISR register bits */ 398 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 399 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 400 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 401 402 #define WIL_DATA_COMPLETION_TO_MS 200 403 404 /* Hardware definitions end */ 405 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 406 #define TALYN_FW_MAPPING_TABLE_SIZE 13 407 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 408 #define MAX_FW_MAPPING_TABLE_SIZE 19 409 410 /* Common representation of physical address in wil ring */ 411 struct wil_ring_dma_addr { 412 __le32 addr_low; 413 __le16 addr_high; 414 } __packed; 415 416 struct fw_map { 417 u32 from; /* linker address - from, inclusive */ 418 u32 to; /* linker address - to, exclusive */ 419 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 420 const char *name; /* for debugfs */ 421 bool fw; /* true if FW mapping, false if UCODE mapping */ 422 bool crash_dump; /* true if should be dumped during crash dump */ 423 }; 424 425 /* array size should be in sync with actual definition in the wmi.c */ 426 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 427 extern const struct fw_map sparrow_d0_mac_rgf_ext; 428 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 429 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 430 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 431 432 /** 433 * mk_cidxtid - construct @cidxtid field 434 * @cid: CID value 435 * @tid: TID value 436 * 437 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 438 */ 439 static inline u8 mk_cidxtid(u8 cid, u8 tid) 440 { 441 return ((tid & 0xf) << 4) | (cid & 0xf); 442 } 443 444 /** 445 * parse_cidxtid - parse @cidxtid field 446 * @cid: store CID value here 447 * @tid: store TID value here 448 * 449 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 450 */ 451 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 452 { 453 *cid = cidxtid & 0xf; 454 *tid = (cidxtid >> 4) & 0xf; 455 } 456 457 /** 458 * wil_cid_valid - check cid is valid 459 * @cid: CID value 460 */ 461 static inline bool wil_cid_valid(u8 cid) 462 { 463 return (cid >= 0 && cid < max_assoc_sta); 464 } 465 466 struct wil6210_mbox_ring { 467 u32 base; 468 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 469 u16 size; 470 u32 tail; 471 u32 head; 472 } __packed; 473 474 struct wil6210_mbox_ring_desc { 475 __le32 sync; 476 __le32 addr; 477 } __packed; 478 479 /* at HOST_OFF_WIL6210_MBOX_CTL */ 480 struct wil6210_mbox_ctl { 481 struct wil6210_mbox_ring tx; 482 struct wil6210_mbox_ring rx; 483 } __packed; 484 485 struct wil6210_mbox_hdr { 486 __le16 seq; 487 __le16 len; /* payload, bytes after this header */ 488 __le16 type; 489 u8 flags; 490 u8 reserved; 491 } __packed; 492 493 #define WIL_MBOX_HDR_TYPE_WMI (0) 494 495 /* max. value for wil6210_mbox_hdr.len */ 496 #define MAX_MBOXITEM_SIZE (240) 497 498 struct pending_wmi_event { 499 struct list_head list; 500 struct { 501 struct wil6210_mbox_hdr hdr; 502 struct wmi_cmd_hdr wmi; 503 u8 data[0]; 504 } __packed event; 505 }; 506 507 enum { /* for wil_ctx.mapped_as */ 508 wil_mapped_as_none = 0, 509 wil_mapped_as_single = 1, 510 wil_mapped_as_page = 2, 511 }; 512 513 /** 514 * struct wil_ctx - software context for ring descriptor 515 */ 516 struct wil_ctx { 517 struct sk_buff *skb; 518 u8 nr_frags; 519 u8 mapped_as; 520 }; 521 522 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 523 u32 *va; 524 dma_addr_t pa; 525 }; 526 527 /** 528 * A general ring structure, used for RX and TX. 529 * In legacy DMA it represents the vring, 530 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 531 */ 532 struct wil_ring { 533 dma_addr_t pa; 534 volatile union wil_ring_desc *va; 535 u16 size; /* number of wil_ring_desc elements */ 536 u32 swtail; 537 u32 swhead; 538 u32 hwtail; /* write here to inform hw */ 539 struct wil_ctx *ctx; /* ctx[size] - software context */ 540 struct wil_desc_ring_rx_swtail edma_rx_swtail; 541 bool is_rx; 542 }; 543 544 /** 545 * Additional data for Rx ring. 546 * Used for enhanced DMA RX chaining. 547 */ 548 struct wil_ring_rx_data { 549 /* the skb being assembled */ 550 struct sk_buff *skb; 551 /* true if we are skipping a bad fragmented packet */ 552 bool skipping; 553 u16 buff_size; 554 }; 555 556 /** 557 * Status ring structure, used for enhanced DMA completions for RX and TX. 558 */ 559 struct wil_status_ring { 560 dma_addr_t pa; 561 void *va; /* pointer to ring_[tr]x_status elements */ 562 u16 size; /* number of status elements */ 563 size_t elem_size; /* status element size in bytes */ 564 u32 swhead; 565 u32 hwtail; /* write here to inform hw */ 566 bool is_rx; 567 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 568 struct wil_ring_rx_data rx_data; 569 }; 570 571 #define WIL_STA_TID_NUM (16) 572 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 573 574 struct wil_net_stats { 575 unsigned long rx_packets; 576 unsigned long tx_packets; 577 unsigned long rx_bytes; 578 unsigned long tx_bytes; 579 unsigned long tx_errors; 580 u32 tx_latency_min_us; 581 u32 tx_latency_max_us; 582 u64 tx_latency_total_us; 583 unsigned long rx_dropped; 584 unsigned long rx_non_data_frame; 585 unsigned long rx_short_frame; 586 unsigned long rx_large_frame; 587 unsigned long rx_replay; 588 unsigned long rx_mic_error; 589 unsigned long rx_key_error; /* eDMA specific */ 590 unsigned long rx_amsdu_error; /* eDMA specific */ 591 unsigned long rx_csum_err; 592 u16 last_mcs_rx; 593 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 594 u32 ft_roams; /* relevant in STA mode */ 595 }; 596 597 /** 598 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 599 * DMA flow 600 */ 601 struct wil_txrx_ops { 602 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 603 /* TX ops */ 604 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 605 int size, int cid, int tid); 606 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 607 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 608 int (*tx_init)(struct wil6210_priv *wil); 609 void (*tx_fini)(struct wil6210_priv *wil); 610 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 611 u32 len, int ring_index); 612 void (*tx_desc_unmap)(struct device *dev, 613 union wil_tx_desc *desc, 614 struct wil_ctx *ctx); 615 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 616 struct wil_ring *ring, struct sk_buff *skb); 617 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 618 int cid, int tid); 619 irqreturn_t (*irq_tx)(int irq, void *cookie); 620 /* RX ops */ 621 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 622 void (*rx_fini)(struct wil6210_priv *wil); 623 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 624 u8 tid, u8 token, u16 status, bool amsdu, 625 u16 agg_wsize, u16 timeout); 626 void (*get_reorder_params)(struct wil6210_priv *wil, 627 struct sk_buff *skb, int *tid, int *cid, 628 int *mid, u16 *seq, int *mcast, int *retry); 629 void (*get_netif_rx_params)(struct sk_buff *skb, 630 int *cid, int *security); 631 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 632 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 633 struct wil_net_stats *stats); 634 bool (*is_rx_idle)(struct wil6210_priv *wil); 635 irqreturn_t (*irq_rx)(int irq, void *cookie); 636 }; 637 638 /** 639 * Additional data for Tx ring 640 */ 641 struct wil_ring_tx_data { 642 bool dot1x_open; 643 int enabled; 644 cycles_t idle, last_idle, begin; 645 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 646 u16 agg_timeout; 647 u8 agg_amsdu; 648 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 649 u8 mid; 650 spinlock_t lock; 651 }; 652 653 enum { /* for wil6210_priv.status */ 654 wil_status_fwready = 0, /* FW operational */ 655 wil_status_dontscan, 656 wil_status_mbox_ready, /* MBOX structures ready */ 657 wil_status_irqen, /* interrupts enabled - for debug */ 658 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 659 wil_status_resetting, /* reset in progress */ 660 wil_status_suspending, /* suspend in progress */ 661 wil_status_suspended, /* suspend completed, device is suspended */ 662 wil_status_resuming, /* resume in progress */ 663 wil_status_collecting_dumps, /* crashdump collection in progress */ 664 wil_status_last /* keep last */ 665 }; 666 667 struct pci_dev; 668 669 /** 670 * struct tid_ampdu_rx - TID aggregation information (Rx). 671 * 672 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 673 * @last_rx: jiffies of last rx activity 674 * @head_seq_num: head sequence number in reordering buffer. 675 * @stored_mpdu_num: number of MPDUs in reordering buffer 676 * @ssn: Starting Sequence Number expected to be aggregated. 677 * @buf_size: buffer size for incoming A-MPDUs 678 * @ssn_last_drop: SSN of the last dropped frame 679 * @total: total number of processed incoming frames 680 * @drop_dup: duplicate frames dropped for this reorder buffer 681 * @drop_old: old frames dropped for this reorder buffer 682 * @first_time: true when this buffer used 1-st time 683 * @mcast_last_seq: sequence number (SN) of last received multicast packet 684 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 685 */ 686 struct wil_tid_ampdu_rx { 687 struct sk_buff **reorder_buf; 688 unsigned long last_rx; 689 u16 head_seq_num; 690 u16 stored_mpdu_num; 691 u16 ssn; 692 u16 buf_size; 693 u16 ssn_last_drop; 694 unsigned long long total; /* frames processed */ 695 unsigned long long drop_dup; 696 unsigned long long drop_old; 697 bool first_time; /* is it 1-st time this buffer used? */ 698 u16 mcast_last_seq; /* multicast dup detection */ 699 unsigned long long drop_dup_mcast; 700 }; 701 702 /** 703 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 704 * 705 * @pn: GCMP PN for the session 706 * @key_set: valid key present 707 */ 708 struct wil_tid_crypto_rx_single { 709 u8 pn[IEEE80211_GCMP_PN_LEN]; 710 bool key_set; 711 }; 712 713 struct wil_tid_crypto_rx { 714 struct wil_tid_crypto_rx_single key_id[4]; 715 }; 716 717 struct wil_p2p_info { 718 struct ieee80211_channel listen_chan; 719 u8 discovery_started; 720 u64 cookie; 721 struct wireless_dev *pending_listen_wdev; 722 unsigned int listen_duration; 723 struct timer_list discovery_timer; /* listen/search duration */ 724 struct work_struct discovery_expired_work; /* listen/search expire */ 725 struct work_struct delayed_listen_work; /* listen after scan done */ 726 }; 727 728 enum wil_sta_status { 729 wil_sta_unused = 0, 730 wil_sta_conn_pending = 1, 731 wil_sta_connected = 2, 732 }; 733 734 /** 735 * struct wil_sta_info - data for peer 736 * 737 * Peer identified by its CID (connection ID) 738 * NIC performs beam forming for each peer; 739 * if no beam forming done, frame exchange is not 740 * possible. 741 */ 742 struct wil_sta_info { 743 u8 addr[ETH_ALEN]; 744 u8 mid; 745 enum wil_sta_status status; 746 struct wil_net_stats stats; 747 /** 748 * 20 latency bins. 1st bin counts packets with latency 749 * of 0..tx_latency_res, last bin counts packets with latency 750 * of 19*tx_latency_res and above. 751 * tx_latency_res is configured from "tx_latency" debug-fs. 752 */ 753 u64 *tx_latency_bins; 754 struct wmi_link_stats_basic fw_stats_basic; 755 /* Rx BACK */ 756 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 757 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 758 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 759 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 760 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 761 struct wil_tid_crypto_rx group_crypto_rx; 762 u8 aid; /* 1-254; 0 if unknown/not reported */ 763 }; 764 765 enum { 766 fw_recovery_idle = 0, 767 fw_recovery_pending = 1, 768 fw_recovery_running = 2, 769 }; 770 771 enum { 772 hw_capa_no_flash, 773 hw_capa_last 774 }; 775 776 struct wil_probe_client_req { 777 struct list_head list; 778 u64 cookie; 779 u8 cid; 780 }; 781 782 struct pmc_ctx { 783 /* alloc, free, and read operations must own the lock */ 784 struct mutex lock; 785 struct vring_tx_desc *pring_va; 786 dma_addr_t pring_pa; 787 struct desc_alloc_info *descriptors; 788 int last_cmd_status; 789 int num_descriptors; 790 int descriptor_size; 791 }; 792 793 struct wil_halp { 794 struct mutex lock; /* protect halp ref_cnt */ 795 unsigned int ref_cnt; 796 struct completion comp; 797 u8 handle_icr; 798 }; 799 800 struct wil_blob_wrapper { 801 struct wil6210_priv *wil; 802 struct debugfs_blob_wrapper blob; 803 }; 804 805 #define WIL_LED_MAX_ID (2) 806 #define WIL_LED_INVALID_ID (0xF) 807 #define WIL_LED_BLINK_ON_SLOW_MS (300) 808 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 809 #define WIL_LED_BLINK_ON_MED_MS (200) 810 #define WIL_LED_BLINK_OFF_MED_MS (200) 811 #define WIL_LED_BLINK_ON_FAST_MS (100) 812 #define WIL_LED_BLINK_OFF_FAST_MS (100) 813 enum { 814 WIL_LED_TIME_SLOW = 0, 815 WIL_LED_TIME_MED, 816 WIL_LED_TIME_FAST, 817 WIL_LED_TIME_LAST, 818 }; 819 820 struct blink_on_off_time { 821 u32 on_ms; 822 u32 off_ms; 823 }; 824 825 struct wil_debugfs_iomem_data { 826 void *offset; 827 struct wil6210_priv *wil; 828 }; 829 830 struct wil_debugfs_data { 831 struct wil_debugfs_iomem_data *data_arr; 832 int iomem_data_count; 833 }; 834 835 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 836 extern u8 led_id; 837 extern u8 led_polarity; 838 839 enum wil6210_vif_status { 840 wil_vif_fwconnecting, 841 wil_vif_fwconnected, 842 wil_vif_ft_roam, 843 wil_vif_status_last /* keep last */ 844 }; 845 846 struct wil6210_vif { 847 struct wireless_dev wdev; 848 struct net_device *ndev; 849 struct wil6210_priv *wil; 850 u8 mid; 851 DECLARE_BITMAP(status, wil_vif_status_last); 852 u32 privacy; /* secure connection? */ 853 u16 channel; /* relevant in AP mode */ 854 u8 hidden_ssid; /* relevant in AP mode */ 855 u32 ap_isolate; /* no intra-BSS communication */ 856 bool pbss; 857 int bi; 858 u8 *proberesp, *proberesp_ies, *assocresp_ies; 859 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 860 u8 ssid[IEEE80211_MAX_SSID_LEN]; 861 size_t ssid_len; 862 u8 gtk_index; 863 u8 gtk[WMI_MAX_KEY_LEN]; 864 size_t gtk_len; 865 int bcast_ring; 866 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 867 int locally_generated_disc; /* relevant in STA mode */ 868 struct timer_list connect_timer; 869 struct work_struct disconnect_worker; 870 /* scan */ 871 struct cfg80211_scan_request *scan_request; 872 struct timer_list scan_timer; /* detect scan timeout */ 873 struct wil_p2p_info p2p; 874 /* keep alive */ 875 struct list_head probe_client_pending; 876 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 877 struct work_struct probe_client_worker; 878 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 879 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 880 u64 fw_stats_tsf; /* measurement timestamp */ 881 }; 882 883 /** 884 * RX buffer allocated for enhanced DMA RX descriptors 885 */ 886 struct wil_rx_buff { 887 struct sk_buff *skb; 888 struct list_head list; 889 int id; 890 }; 891 892 /** 893 * During Rx completion processing, the driver extracts a buffer ID which 894 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 895 * is given to the network stack and the buffer is moved from the 'active' 896 * list to the 'free' list. 897 * During Rx refill, SKBs are attached to free buffers and moved to the 898 * 'active' list. 899 */ 900 struct wil_rx_buff_mgmt { 901 struct wil_rx_buff *buff_arr; 902 size_t size; /* number of items in buff_arr */ 903 struct list_head active; 904 struct list_head free; 905 unsigned long free_list_empty_cnt; /* statistics */ 906 }; 907 908 struct wil_fw_stats_global { 909 bool ready; 910 u64 tsf; /* measurement timestamp */ 911 struct wmi_link_stats_global stats; 912 }; 913 914 struct wil6210_priv { 915 struct pci_dev *pdev; 916 u32 bar_size; 917 struct wiphy *wiphy; 918 struct net_device *main_ndev; 919 int n_msi; 920 void __iomem *csr; 921 DECLARE_BITMAP(status, wil_status_last); 922 u8 fw_version[ETHTOOL_FWVERS_LEN]; 923 u32 hw_version; 924 u8 chip_revision; 925 const char *hw_name; 926 const char *wil_fw_name; 927 char *board_file; 928 u32 brd_file_addr; 929 u32 brd_file_max_size; 930 DECLARE_BITMAP(hw_capa, hw_capa_last); 931 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 932 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 933 u32 recovery_count; /* num of FW recovery attempts in a short time */ 934 u32 recovery_state; /* FW recovery state machine */ 935 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 936 wait_queue_head_t wq; /* for all wait_event() use */ 937 u8 max_vifs; /* maximum number of interfaces, including main */ 938 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 939 struct mutex vif_mutex; /* protects access to VIF entries */ 940 atomic_t connected_vifs; 941 /* profile */ 942 struct cfg80211_chan_def monitor_chandef; 943 u32 monitor_flags; 944 int sinfo_gen; 945 /* interrupt moderation */ 946 u32 tx_max_burst_duration; 947 u32 tx_interframe_timeout; 948 u32 rx_max_burst_duration; 949 u32 rx_interframe_timeout; 950 /* cached ISR registers */ 951 u32 isr_misc; 952 /* mailbox related */ 953 struct mutex wmi_mutex; 954 struct wil6210_mbox_ctl mbox_ctl; 955 struct completion wmi_ready; 956 struct completion wmi_call; 957 u16 wmi_seq; 958 u16 reply_id; /**< wait for this WMI event */ 959 u8 reply_mid; 960 void *reply_buf; 961 u16 reply_size; 962 struct workqueue_struct *wmi_wq; /* for deferred calls */ 963 struct work_struct wmi_event_worker; 964 struct workqueue_struct *wq_service; 965 struct work_struct fw_error_worker; /* for FW error recovery */ 966 struct list_head pending_wmi_ev; 967 /* 968 * protect pending_wmi_ev 969 * - fill in IRQ from wil6210_irq_misc, 970 * - consumed in thread by wmi_event_worker 971 */ 972 spinlock_t wmi_ev_lock; 973 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 974 struct napi_struct napi_rx; 975 struct napi_struct napi_tx; 976 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 977 978 /* DMA related */ 979 struct wil_ring ring_rx; 980 unsigned int rx_buf_len; 981 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 982 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 983 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 984 u8 num_rx_status_rings; 985 int tx_sring_idx; 986 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 987 struct wil_sta_info sta[WIL6210_MAX_CID]; 988 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 989 u32 dma_addr_size; /* indicates dma addr size */ 990 struct wil_rx_buff_mgmt rx_buff_mgmt; 991 bool use_enhanced_dma_hw; 992 struct wil_txrx_ops txrx_ops; 993 994 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 995 /* statistics */ 996 atomic_t isr_count_rx, isr_count_tx; 997 /* debugfs */ 998 struct dentry *debug; 999 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 1000 u8 discovery_mode; 1001 u8 abft_len; 1002 u8 wakeup_trigger; 1003 struct wil_suspend_stats suspend_stats; 1004 struct wil_debugfs_data dbg_data; 1005 bool tx_latency; /* collect TX latency measurements */ 1006 size_t tx_latency_res; /* bin resolution in usec */ 1007 1008 void *platform_handle; 1009 struct wil_platform_ops platform_ops; 1010 bool keep_radio_on_during_sleep; 1011 1012 struct pmc_ctx pmc; 1013 1014 u8 p2p_dev_started; 1015 1016 /* P2P_DEVICE vif */ 1017 struct wireless_dev *p2p_wdev; 1018 struct wireless_dev *radio_wdev; 1019 1020 /* High Access Latency Policy voting */ 1021 struct wil_halp halp; 1022 1023 enum wmi_ps_profile_type ps_profile; 1024 1025 int fw_calib_result; 1026 1027 struct notifier_block pm_notify; 1028 1029 bool suspend_resp_rcvd; 1030 bool suspend_resp_comp; 1031 u32 bus_request_kbps; 1032 u32 bus_request_kbps_pre_suspend; 1033 1034 u32 rgf_fw_assert_code_addr; 1035 u32 rgf_ucode_assert_code_addr; 1036 u32 iccm_base; 1037 1038 /* relevant only for eDMA */ 1039 bool use_compressed_rx_status; 1040 u32 rx_status_ring_order; 1041 u32 tx_status_ring_order; 1042 u32 rx_buff_id_count; 1043 bool amsdu_en; 1044 bool use_rx_hw_reordering; 1045 bool secured_boot; 1046 u8 boot_config; 1047 1048 struct wil_fw_stats_global fw_stats_global; 1049 1050 u32 max_agg_wsize; 1051 u32 max_ampdu_size; 1052 }; 1053 1054 #define wil_to_wiphy(i) (i->wiphy) 1055 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1056 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1057 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1058 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1059 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1060 #define vif_to_wil(v) (v->wil) 1061 #define vif_to_ndev(v) (v->ndev) 1062 #define vif_to_wdev(v) (&v->wdev) 1063 1064 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1065 struct wireless_dev *wdev) 1066 { 1067 /* main interface is shared with P2P device */ 1068 if (wdev == wil->p2p_wdev) 1069 return ndev_to_vif(wil->main_ndev); 1070 else 1071 return container_of(wdev, struct wil6210_vif, wdev); 1072 } 1073 1074 static inline struct wireless_dev * 1075 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1076 { 1077 /* main interface is shared with P2P device */ 1078 if (vif->mid) 1079 return vif_to_wdev(vif); 1080 else 1081 return wil->radio_wdev; 1082 } 1083 1084 __printf(2, 3) 1085 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1086 __printf(2, 3) 1087 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1088 __printf(2, 3) 1089 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1090 __printf(2, 3) 1091 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1092 __printf(2, 3) 1093 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1094 #define wil_dbg(wil, fmt, arg...) do { \ 1095 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1096 wil_dbg_trace(wil, fmt, ##arg); \ 1097 } while (0) 1098 1099 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1100 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1101 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1102 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1103 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1104 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1105 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1106 #define wil_err_ratelimited(wil, fmt, arg...) \ 1107 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1108 1109 /* target operations */ 1110 /* register read */ 1111 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1112 { 1113 return readl(wil->csr + HOSTADDR(reg)); 1114 } 1115 1116 /* register write. wmb() to make sure it is completed */ 1117 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1118 { 1119 writel(val, wil->csr + HOSTADDR(reg)); 1120 wmb(); /* wait for write to propagate to the HW */ 1121 } 1122 1123 /* register set = read, OR, write */ 1124 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1125 { 1126 wil_w(wil, reg, wil_r(wil, reg) | val); 1127 } 1128 1129 /* register clear = read, AND with inverted, write */ 1130 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1131 { 1132 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1133 } 1134 1135 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1136 1137 #if defined(CONFIG_DYNAMIC_DEBUG) 1138 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1139 groupsize, buf, len, ascii) \ 1140 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1141 prefix_type, rowsize, \ 1142 groupsize, buf, len, ascii) 1143 1144 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1145 groupsize, buf, len, ascii) \ 1146 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1147 prefix_type, rowsize, \ 1148 groupsize, buf, len, ascii) 1149 1150 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1151 groupsize, buf, len, ascii) \ 1152 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1153 prefix_type, rowsize, \ 1154 groupsize, buf, len, ascii) 1155 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1156 static inline 1157 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1158 int groupsize, const void *buf, size_t len, bool ascii) 1159 { 1160 } 1161 1162 static inline 1163 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1164 int groupsize, const void *buf, size_t len, bool ascii) 1165 { 1166 } 1167 1168 static inline 1169 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1170 int groupsize, const void *buf, size_t len, bool ascii) 1171 { 1172 } 1173 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1174 1175 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1176 size_t count); 1177 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1178 size_t count); 1179 1180 struct wil6210_vif * 1181 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1182 unsigned char name_assign_type, enum nl80211_iftype iftype); 1183 void wil_vif_free(struct wil6210_vif *vif); 1184 void *wil_if_alloc(struct device *dev); 1185 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1186 struct net_device *ndev, bool up, bool ok); 1187 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1188 void wil_if_free(struct wil6210_priv *wil); 1189 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1190 int wil_if_add(struct wil6210_priv *wil); 1191 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1192 void wil_if_remove(struct wil6210_priv *wil); 1193 int wil_priv_init(struct wil6210_priv *wil); 1194 void wil_priv_deinit(struct wil6210_priv *wil); 1195 int wil_ps_update(struct wil6210_priv *wil, 1196 enum wmi_ps_profile_type ps_profile); 1197 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1198 void wil_fw_error_recovery(struct wil6210_priv *wil); 1199 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1200 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1201 int wil_up(struct wil6210_priv *wil); 1202 int __wil_up(struct wil6210_priv *wil); 1203 int wil_down(struct wil6210_priv *wil); 1204 int __wil_down(struct wil6210_priv *wil); 1205 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1206 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1207 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1208 void wil_set_ethtoolops(struct net_device *ndev); 1209 1210 struct fw_map *wil_find_fw_mapping(const char *section); 1211 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1212 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1213 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1214 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1215 struct wil6210_mbox_hdr *hdr); 1216 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1217 void wmi_recv_cmd(struct wil6210_priv *wil); 1218 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1219 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1220 void wmi_event_worker(struct work_struct *work); 1221 void wmi_event_flush(struct wil6210_priv *wil); 1222 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1223 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1224 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1225 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1226 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1227 const void *mac_addr, int key_usage); 1228 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1229 const void *mac_addr, int key_len, const void *key, 1230 int key_usage); 1231 int wmi_echo(struct wil6210_priv *wil); 1232 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1233 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1234 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1235 int wmi_rxon(struct wil6210_priv *wil, bool on); 1236 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1237 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1238 bool del_sta); 1239 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1240 u8 ringid, u8 size, u16 timeout); 1241 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1242 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason); 1243 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1244 u8 mid, u8 cid, u8 tid, u8 token, 1245 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1246 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1247 enum wmi_ps_profile_type ps_profile); 1248 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1249 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1250 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1251 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1252 const u8 *mac, enum nl80211_iftype iftype); 1253 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1254 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1255 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, 1256 u8 dialog_token, __le16 ba_param_set, 1257 __le16 ba_timeout, __le16 ba_seq_ctrl); 1258 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1259 1260 void wil6210_clear_irq(struct wil6210_priv *wil); 1261 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1262 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1263 void wil_mask_irq(struct wil6210_priv *wil); 1264 void wil_unmask_irq(struct wil6210_priv *wil); 1265 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1266 void wil_disable_irq(struct wil6210_priv *wil); 1267 void wil_enable_irq(struct wil6210_priv *wil); 1268 void wil6210_mask_halp(struct wil6210_priv *wil); 1269 1270 /* P2P */ 1271 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1272 int wil_p2p_search(struct wil6210_vif *vif, 1273 struct cfg80211_scan_request *request); 1274 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1275 unsigned int duration, struct ieee80211_channel *chan, 1276 u64 *cookie); 1277 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1278 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1279 void wil_p2p_listen_expired(struct work_struct *work); 1280 void wil_p2p_search_expired(struct work_struct *work); 1281 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1282 void wil_p2p_delayed_listen_work(struct work_struct *work); 1283 1284 /* WMI for P2P */ 1285 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1286 int wmi_start_listen(struct wil6210_vif *vif); 1287 int wmi_start_search(struct wil6210_vif *vif); 1288 int wmi_stop_discovery(struct wil6210_vif *vif); 1289 1290 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1291 struct cfg80211_mgmt_tx_params *params, 1292 u64 *cookie); 1293 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1294 int wil_cfg80211_iface_combinations_from_fw( 1295 struct wil6210_priv *wil, 1296 const struct wil_fw_record_concurrency *conc); 1297 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1298 1299 #if defined(CONFIG_WIL6210_DEBUGFS) 1300 int wil6210_debugfs_init(struct wil6210_priv *wil); 1301 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1302 #else 1303 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1304 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1305 #endif 1306 1307 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1308 struct station_info *sinfo); 1309 1310 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1311 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1312 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1313 1314 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1315 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1316 u8 hidden_ssid, u8 is_go); 1317 int wmi_pcp_stop(struct wil6210_vif *vif); 1318 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1319 int wmi_abort_scan(struct wil6210_vif *vif); 1320 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1321 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1322 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1323 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1324 u16 reason_code); 1325 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1326 u16 reason_code); 1327 void wil_probe_client_flush(struct wil6210_vif *vif); 1328 void wil_probe_client_worker(struct work_struct *work); 1329 void wil_disconnect_worker(struct work_struct *work); 1330 1331 void wil_init_txrx_ops(struct wil6210_priv *wil); 1332 1333 /* TX API */ 1334 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1335 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1336 int wil_bcast_init(struct wil6210_vif *vif); 1337 void wil_bcast_fini(struct wil6210_vif *vif); 1338 void wil_bcast_fini_all(struct wil6210_priv *wil); 1339 1340 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1341 struct wil_ring *ring, bool should_stop); 1342 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1343 struct wil_ring *ring, bool check_stop); 1344 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1345 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1346 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1347 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1348 1349 /* RX API */ 1350 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1351 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1352 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1353 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1354 struct wil_sta_info *cs, 1355 struct key_params *params); 1356 1357 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1358 1359 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1360 bool load); 1361 int wil_request_board(struct wil6210_priv *wil, const char *name); 1362 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1363 1364 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1365 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1366 int wil_pm_runtime_get(struct wil6210_priv *wil); 1367 void wil_pm_runtime_put(struct wil6210_priv *wil); 1368 1369 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1370 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1371 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1372 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1373 int wmi_resume(struct wil6210_priv *wil); 1374 int wmi_suspend(struct wil6210_priv *wil); 1375 bool wil_is_tx_idle(struct wil6210_priv *wil); 1376 1377 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1378 void wil_fw_core_dump(struct wil6210_priv *wil); 1379 1380 void wil_halp_vote(struct wil6210_priv *wil); 1381 void wil_halp_unvote(struct wil6210_priv *wil); 1382 void wil6210_set_halp(struct wil6210_priv *wil); 1383 void wil6210_clear_halp(struct wil6210_priv *wil); 1384 1385 int wmi_start_sched_scan(struct wil6210_priv *wil, 1386 struct cfg80211_sched_scan_request *request); 1387 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1388 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1389 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1390 u8 channel, u16 duration_ms); 1391 1392 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1393 1394 /* WMI for enhanced DMA */ 1395 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1396 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1397 u16 max_rx_pl_per_desc); 1398 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1399 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1400 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1401 int tid); 1402 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1403 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1404 u8 tid, u8 token, u16 status, bool amsdu, 1405 u16 agg_wsize, u16 timeout); 1406 1407 void update_supported_bands(struct wil6210_priv *wil); 1408 1409 #endif /* __WIL6210_H__ */ 1410