1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef __WIL6210_H__ 8 #define __WIL6210_H__ 9 10 #include <linux/etherdevice.h> 11 #include <linux/netdevice.h> 12 #include <linux/wireless.h> 13 #include <net/cfg80211.h> 14 #include <linux/timex.h> 15 #include <linux/types.h> 16 #include <linux/irqreturn.h> 17 #include "wmi.h" 18 #include "wil_platform.h" 19 #include "fw.h" 20 21 extern bool no_fw_recovery; 22 extern unsigned int mtu_max; 23 extern unsigned short rx_ring_overflow_thrsh; 24 extern int agg_wsize; 25 extern bool rx_align_2; 26 extern bool rx_large_buf; 27 extern bool debug_fw; 28 extern bool disable_ap_sme; 29 extern bool ftm_mode; 30 extern bool drop_if_ring_full; 31 extern uint max_assoc_sta; 32 33 struct wil6210_priv; 34 struct wil6210_vif; 35 union wil_tx_desc; 36 37 #define WIL_NAME "wil6210" 38 39 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 40 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 41 42 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 43 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 44 45 #define WIL_FW_NAME_TALYN "wil6436.fw" 46 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 47 #define WIL_BRD_NAME_TALYN "wil6436.brd" 48 49 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 50 51 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 52 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 53 54 #define WIL_NUM_LATENCY_BINS 200 55 56 /* maximum number of virtual interfaces the driver supports 57 * (including the main interface) 58 */ 59 #define WIL_MAX_VIFS 4 60 61 /** 62 * extract bits [@b0:@b1] (inclusive) from the value @x 63 * it should be @b0 <= @b1, or result is incorrect 64 */ 65 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 66 { 67 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 68 } 69 70 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 71 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 72 73 #define WIL_TX_Q_LEN_DEFAULT (4000) 74 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 75 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 76 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 77 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 78 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 79 /* limit ring size in range [32..32k] */ 80 #define WIL_RING_SIZE_ORDER_MIN (5) 81 #define WIL_RING_SIZE_ORDER_MAX (15) 82 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 83 #define WIL6210_MAX_CID (20) /* max number of stations */ 84 #define WIL6210_RX_DESC_MAX_CID (8) /* HW limit */ 85 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 86 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 87 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 88 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 89 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 90 #define WIL6210_MAX_STATUS_RINGS (8) 91 #define WIL_WMI_CALL_GENERAL_TO_MS 100 92 #define WIL_EXTENDED_MCS_26 (26) /* FW reports MCS 12.1 to driver as "26" */ 93 #define WIL_BASE_MCS_FOR_EXTENDED_26 (7) /* MCS 7 is base MCS for MCS 12.1 */ 94 #define WIL_EXTENDED_MCS_CHECK(x) (((x) == WIL_EXTENDED_MCS_26) ? "12.1" : #x) 95 96 /* Hardware offload block adds the following: 97 * 26 bytes - 3-address QoS data header 98 * 8 bytes - IV + EIV (for GCMP) 99 * 8 bytes - SNAP 100 * 16 bytes - MIC (for GCMP) 101 * 4 bytes - CRC 102 */ 103 #define WIL_MAX_MPDU_OVERHEAD (62) 104 105 struct wil_suspend_count_stats { 106 unsigned long successful_suspends; 107 unsigned long successful_resumes; 108 unsigned long failed_suspends; 109 unsigned long failed_resumes; 110 }; 111 112 struct wil_suspend_stats { 113 struct wil_suspend_count_stats r_off; 114 struct wil_suspend_count_stats r_on; 115 unsigned long rejected_by_device; /* only radio on */ 116 unsigned long rejected_by_host; 117 }; 118 119 /* Calculate MAC buffer size for the firmware. It includes all overhead, 120 * as it will go over the air, and need to be 8 byte aligned 121 */ 122 static inline u32 wil_mtu2macbuf(u32 mtu) 123 { 124 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 125 } 126 127 /* MTU for Ethernet need to take into account 8-byte SNAP header 128 * to be added when encapsulating Ethernet frame into 802.11 129 */ 130 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 131 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 132 #define WIL6210_ITR_TRSH_MAX (5000000) 133 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 134 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 135 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 136 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 137 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 138 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 139 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 140 #define WIL6210_DISCONNECT_TO_MS (2000) 141 #define WIL6210_RX_HIGH_TRSH_INIT (0) 142 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 143 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 144 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 145 * 802.11REVmc/D5.0, section 9.4.1.8) 146 */ 147 /* Hardware definitions begin */ 148 149 /* 150 * Mapping 151 * RGF File | Host addr | FW addr 152 * | | 153 * user_rgf | 0x000000 | 0x880000 154 * dma_rgf | 0x001000 | 0x881000 155 * pcie_rgf | 0x002000 | 0x882000 156 * | | 157 */ 158 159 /* Where various structures placed in host address space */ 160 #define WIL6210_FW_HOST_OFF (0x880000UL) 161 162 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 163 164 /* 165 * Interrupt control registers block 166 * 167 * each interrupt controlled by the same bit in all registers 168 */ 169 struct RGF_ICR { 170 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 171 u32 ICR; /* Cause, W1C/COR depending on ICC */ 172 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 173 u32 ICS; /* Cause Set, WO */ 174 u32 IMV; /* Mask, RW+S/C */ 175 u32 IMS; /* Mask Set, write 1 to set */ 176 u32 IMC; /* Mask Clear, write 1 to clear */ 177 } __packed; 178 179 /* registers - FW addresses */ 180 #define RGF_USER_USAGE_1 (0x880004) 181 #define RGF_USER_USAGE_2 (0x880008) 182 #define RGF_USER_USAGE_6 (0x880018) 183 #define BIT_USER_OOB_MODE BIT(31) 184 #define BIT_USER_OOB_R2_MODE BIT(30) 185 #define RGF_USER_USAGE_8 (0x880020) 186 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 187 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 188 #define BIT_USER_EXT_CLK BIT(2) 189 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 190 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 191 #define RGF_USER_USER_CPU_0 (0x8801e0) 192 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 193 #define RGF_USER_CPU_PC (0x8801e8) 194 #define RGF_USER_MAC_CPU_0 (0x8801fc) 195 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 196 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 197 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 198 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 199 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 200 * b8-15:signature 201 */ 202 #define CALIB_RESULT_SIGNATURE (0x11) 203 #define RGF_USER_CLKS_CTL_0 (0x880abc) 204 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 205 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 206 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 207 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 208 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 209 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 210 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 211 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 212 #define BIT_CAR_PERST_RST BIT(7) 213 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 214 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 215 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 216 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 217 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 218 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 219 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 220 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 221 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 222 #define BIT_NO_FLASH_INDICATION BIT(8) 223 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 224 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 225 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 226 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 227 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 228 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 229 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 230 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 231 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 232 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 233 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 234 235 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 236 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 237 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 238 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 239 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 240 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 241 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 242 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 243 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 244 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 245 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 246 247 /* Legacy interrupt moderation control (before Sparrow v2)*/ 248 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 249 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 250 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 251 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 252 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 253 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 254 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 255 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 256 257 /* Offload control (Sparrow B0+) */ 258 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 259 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 260 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 261 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 262 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 263 264 /* New (sparrow v2+) interrupt moderation control */ 265 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 266 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 267 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 268 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 269 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 270 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 271 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 272 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 273 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 274 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 275 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 276 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 277 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 278 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 279 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 280 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 281 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 282 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 283 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 284 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 285 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 286 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 287 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 288 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 289 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 290 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 291 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 292 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 293 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 294 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 295 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 296 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 297 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 298 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 299 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 300 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 301 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 302 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 303 #define RGF_DMA_MISC_CTL (0x881d6c) 304 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 305 306 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 307 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 308 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 309 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 310 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 311 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 312 313 #define RGF_HP_CTRL (0x88265c) 314 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 315 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 316 317 /* MAC timer, usec, for packet lifetime */ 318 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 319 320 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 321 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 322 #define RGF_CAF_OSC_CONTROL (0x88afa4) 323 #define BIT_CAF_OSC_XTAL_EN BIT(0) 324 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 325 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 326 327 #define RGF_OTP_QC_SECURED (0x8a0038) 328 #define BIT_BOOT_FROM_ROM BIT(31) 329 330 /* eDMA */ 331 #define RGF_SCM_PTRS_SUBQ_RD_PTR (0x8b4000) 332 #define RGF_SCM_PTRS_COMPQ_RD_PTR (0x8b4100) 333 #define RGF_DMA_SCM_SUBQ_CONS (0x8b60ec) 334 #define RGF_DMA_SCM_COMPQ_PROD (0x8b616c) 335 336 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 337 338 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 339 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 340 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 341 342 #define RGF_INT_GEN_CTRL (0x8bc0ec) 343 #define BIT_CONTROL_0 BIT(0) 344 345 /* eDMA status interrupts */ 346 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 347 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 348 #define RGF_INT_GEN_TX_ICR (0x8bc110) 349 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 350 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 351 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 352 353 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 354 355 #define USER_EXT_USER_PMU_3 (0x88d00c) 356 #define BIT_PMU_DEVICE_RDY BIT(0) 357 358 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 359 #define JTAG_DEV_ID_SPARROW (0x2632072f) 360 #define JTAG_DEV_ID_TALYN (0x7e0e1) 361 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 362 363 #define RGF_USER_REVISION_ID (0x88afe4) 364 #define RGF_USER_REVISION_ID_MASK (3) 365 #define REVISION_ID_SPARROW_B0 (0x0) 366 #define REVISION_ID_SPARROW_D0 (0x3) 367 368 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 369 #define RGF_OTP_OEM_MAC (0x8a0334) 370 #define RGF_OTP_MAC (0x8a0620) 371 372 /* Talyn-MB */ 373 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 374 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 375 376 /* crash codes for FW/Ucode stored here */ 377 378 /* ASSERT RGFs */ 379 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 380 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 381 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 382 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 383 384 enum { 385 HW_VER_UNKNOWN, 386 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 387 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 388 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 389 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 390 }; 391 392 /* popular locations */ 393 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 394 #define HOST_MBOX HOSTADDR(RGF_MBOX) 395 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 396 397 /* ISR register bits */ 398 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 399 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 400 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 401 402 #define WIL_DATA_COMPLETION_TO_MS 200 403 404 /* Hardware definitions end */ 405 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 406 #define TALYN_FW_MAPPING_TABLE_SIZE 13 407 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 408 #define MAX_FW_MAPPING_TABLE_SIZE 19 409 410 /* Common representation of physical address in wil ring */ 411 struct wil_ring_dma_addr { 412 __le32 addr_low; 413 __le16 addr_high; 414 } __packed; 415 416 struct fw_map { 417 u32 from; /* linker address - from, inclusive */ 418 u32 to; /* linker address - to, exclusive */ 419 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 420 const char *name; /* for debugfs */ 421 bool fw; /* true if FW mapping, false if UCODE mapping */ 422 bool crash_dump; /* true if should be dumped during crash dump */ 423 }; 424 425 /* array size should be in sync with actual definition in the wmi.c */ 426 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 427 extern const struct fw_map sparrow_d0_mac_rgf_ext; 428 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 429 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 430 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 431 432 /** 433 * mk_cidxtid - construct @cidxtid field 434 * @cid: CID value 435 * @tid: TID value 436 * 437 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 438 */ 439 static inline u8 mk_cidxtid(u8 cid, u8 tid) 440 { 441 return ((tid & 0xf) << 4) | (cid & 0xf); 442 } 443 444 /** 445 * parse_cidxtid - parse @cidxtid field 446 * @cid: store CID value here 447 * @tid: store TID value here 448 * 449 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 450 */ 451 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 452 { 453 *cid = cidxtid & 0xf; 454 *tid = (cidxtid >> 4) & 0xf; 455 } 456 457 struct wil6210_mbox_ring { 458 u32 base; 459 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 460 u16 size; 461 u32 tail; 462 u32 head; 463 } __packed; 464 465 struct wil6210_mbox_ring_desc { 466 __le32 sync; 467 __le32 addr; 468 } __packed; 469 470 /* at HOST_OFF_WIL6210_MBOX_CTL */ 471 struct wil6210_mbox_ctl { 472 struct wil6210_mbox_ring tx; 473 struct wil6210_mbox_ring rx; 474 } __packed; 475 476 struct wil6210_mbox_hdr { 477 __le16 seq; 478 __le16 len; /* payload, bytes after this header */ 479 __le16 type; 480 u8 flags; 481 u8 reserved; 482 } __packed; 483 484 #define WIL_MBOX_HDR_TYPE_WMI (0) 485 486 /* max. value for wil6210_mbox_hdr.len */ 487 #define MAX_MBOXITEM_SIZE (240) 488 489 struct pending_wmi_event { 490 struct list_head list; 491 struct { 492 struct wil6210_mbox_hdr hdr; 493 struct wmi_cmd_hdr wmi; 494 u8 data[0]; 495 } __packed event; 496 }; 497 498 enum { /* for wil_ctx.mapped_as */ 499 wil_mapped_as_none = 0, 500 wil_mapped_as_single = 1, 501 wil_mapped_as_page = 2, 502 }; 503 504 /** 505 * struct wil_ctx - software context for ring descriptor 506 */ 507 struct wil_ctx { 508 struct sk_buff *skb; 509 u8 nr_frags; 510 u8 mapped_as; 511 }; 512 513 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 514 u32 *va; 515 dma_addr_t pa; 516 }; 517 518 /** 519 * A general ring structure, used for RX and TX. 520 * In legacy DMA it represents the vring, 521 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 522 */ 523 struct wil_ring { 524 dma_addr_t pa; 525 volatile union wil_ring_desc *va; 526 u16 size; /* number of wil_ring_desc elements */ 527 u32 swtail; 528 u32 swhead; 529 u32 hwtail; /* write here to inform hw */ 530 struct wil_ctx *ctx; /* ctx[size] - software context */ 531 struct wil_desc_ring_rx_swtail edma_rx_swtail; 532 bool is_rx; 533 }; 534 535 /** 536 * Additional data for Rx ring. 537 * Used for enhanced DMA RX chaining. 538 */ 539 struct wil_ring_rx_data { 540 /* the skb being assembled */ 541 struct sk_buff *skb; 542 /* true if we are skipping a bad fragmented packet */ 543 bool skipping; 544 u16 buff_size; 545 }; 546 547 /** 548 * Status ring structure, used for enhanced DMA completions for RX and TX. 549 */ 550 struct wil_status_ring { 551 dma_addr_t pa; 552 void *va; /* pointer to ring_[tr]x_status elements */ 553 u16 size; /* number of status elements */ 554 size_t elem_size; /* status element size in bytes */ 555 u32 swhead; 556 u32 hwtail; /* write here to inform hw */ 557 bool is_rx; 558 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 559 struct wil_ring_rx_data rx_data; 560 u32 invalid_buff_id_cnt; /* relevant only for RX */ 561 }; 562 563 #define WIL_STA_TID_NUM (16) 564 #define WIL_MCS_MAX (15) /* Maximum MCS supported */ 565 566 struct wil_net_stats { 567 unsigned long rx_packets; 568 unsigned long tx_packets; 569 unsigned long rx_bytes; 570 unsigned long tx_bytes; 571 unsigned long tx_errors; 572 u32 tx_latency_min_us; 573 u32 tx_latency_max_us; 574 u64 tx_latency_total_us; 575 unsigned long rx_dropped; 576 unsigned long rx_non_data_frame; 577 unsigned long rx_short_frame; 578 unsigned long rx_large_frame; 579 unsigned long rx_replay; 580 unsigned long rx_mic_error; 581 unsigned long rx_key_error; /* eDMA specific */ 582 unsigned long rx_amsdu_error; /* eDMA specific */ 583 unsigned long rx_csum_err; 584 u16 last_mcs_rx; 585 u8 last_cb_mode_rx; 586 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 587 u32 ft_roams; /* relevant in STA mode */ 588 }; 589 590 /** 591 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 592 * DMA flow 593 */ 594 struct wil_txrx_ops { 595 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 596 /* TX ops */ 597 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 598 int size, int cid, int tid); 599 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 600 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 601 int (*tx_init)(struct wil6210_priv *wil); 602 void (*tx_fini)(struct wil6210_priv *wil); 603 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 604 u32 len, int ring_index); 605 void (*tx_desc_unmap)(struct device *dev, 606 union wil_tx_desc *desc, 607 struct wil_ctx *ctx); 608 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 609 struct wil_ring *ring, struct sk_buff *skb); 610 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 611 int cid, int tid); 612 irqreturn_t (*irq_tx)(int irq, void *cookie); 613 /* RX ops */ 614 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 615 void (*rx_fini)(struct wil6210_priv *wil); 616 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 617 u8 tid, u8 token, u16 status, bool amsdu, 618 u16 agg_wsize, u16 timeout); 619 void (*get_reorder_params)(struct wil6210_priv *wil, 620 struct sk_buff *skb, int *tid, int *cid, 621 int *mid, u16 *seq, int *mcast, int *retry); 622 void (*get_netif_rx_params)(struct sk_buff *skb, 623 int *cid, int *security); 624 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 625 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 626 struct wil_net_stats *stats); 627 bool (*is_rx_idle)(struct wil6210_priv *wil); 628 irqreturn_t (*irq_rx)(int irq, void *cookie); 629 }; 630 631 /** 632 * Additional data for Tx ring 633 */ 634 struct wil_ring_tx_data { 635 bool dot1x_open; 636 int enabled; 637 cycles_t idle, last_idle, begin; 638 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 639 u16 agg_timeout; 640 u8 agg_amsdu; 641 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 642 u8 mid; 643 spinlock_t lock; 644 }; 645 646 enum { /* for wil6210_priv.status */ 647 wil_status_fwready = 0, /* FW operational */ 648 wil_status_dontscan, 649 wil_status_mbox_ready, /* MBOX structures ready */ 650 wil_status_irqen, /* interrupts enabled - for debug */ 651 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 652 wil_status_resetting, /* reset in progress */ 653 wil_status_suspending, /* suspend in progress */ 654 wil_status_suspended, /* suspend completed, device is suspended */ 655 wil_status_resuming, /* resume in progress */ 656 wil_status_last /* keep last */ 657 }; 658 659 struct pci_dev; 660 661 /** 662 * struct tid_ampdu_rx - TID aggregation information (Rx). 663 * 664 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 665 * @last_rx: jiffies of last rx activity 666 * @head_seq_num: head sequence number in reordering buffer. 667 * @stored_mpdu_num: number of MPDUs in reordering buffer 668 * @ssn: Starting Sequence Number expected to be aggregated. 669 * @buf_size: buffer size for incoming A-MPDUs 670 * @ssn_last_drop: SSN of the last dropped frame 671 * @total: total number of processed incoming frames 672 * @drop_dup: duplicate frames dropped for this reorder buffer 673 * @drop_old: old frames dropped for this reorder buffer 674 * @first_time: true when this buffer used 1-st time 675 * @mcast_last_seq: sequence number (SN) of last received multicast packet 676 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 677 */ 678 struct wil_tid_ampdu_rx { 679 struct sk_buff **reorder_buf; 680 unsigned long last_rx; 681 u16 head_seq_num; 682 u16 stored_mpdu_num; 683 u16 ssn; 684 u16 buf_size; 685 u16 ssn_last_drop; 686 unsigned long long total; /* frames processed */ 687 unsigned long long drop_dup; 688 unsigned long long drop_old; 689 bool first_time; /* is it 1-st time this buffer used? */ 690 u16 mcast_last_seq; /* multicast dup detection */ 691 unsigned long long drop_dup_mcast; 692 }; 693 694 /** 695 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 696 * 697 * @pn: GCMP PN for the session 698 * @key_set: valid key present 699 */ 700 struct wil_tid_crypto_rx_single { 701 u8 pn[IEEE80211_GCMP_PN_LEN]; 702 bool key_set; 703 }; 704 705 struct wil_tid_crypto_rx { 706 struct wil_tid_crypto_rx_single key_id[4]; 707 }; 708 709 struct wil_p2p_info { 710 struct ieee80211_channel listen_chan; 711 u8 discovery_started; 712 u64 cookie; 713 struct wireless_dev *pending_listen_wdev; 714 unsigned int listen_duration; 715 struct timer_list discovery_timer; /* listen/search duration */ 716 struct work_struct discovery_expired_work; /* listen/search expire */ 717 struct work_struct delayed_listen_work; /* listen after scan done */ 718 }; 719 720 enum wil_sta_status { 721 wil_sta_unused = 0, 722 wil_sta_conn_pending = 1, 723 wil_sta_connected = 2, 724 }; 725 726 enum wil_rekey_state { 727 WIL_REKEY_IDLE = 0, 728 WIL_REKEY_M3_RECEIVED = 1, 729 WIL_REKEY_WAIT_M4_SENT = 2, 730 }; 731 732 /** 733 * struct wil_sta_info - data for peer 734 * 735 * Peer identified by its CID (connection ID) 736 * NIC performs beam forming for each peer; 737 * if no beam forming done, frame exchange is not 738 * possible. 739 */ 740 struct wil_sta_info { 741 u8 addr[ETH_ALEN]; 742 u8 mid; 743 enum wil_sta_status status; 744 struct wil_net_stats stats; 745 /** 746 * 20 latency bins. 1st bin counts packets with latency 747 * of 0..tx_latency_res, last bin counts packets with latency 748 * of 19*tx_latency_res and above. 749 * tx_latency_res is configured from "tx_latency" debug-fs. 750 */ 751 u64 *tx_latency_bins; 752 struct wmi_link_stats_basic fw_stats_basic; 753 /* Rx BACK */ 754 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 755 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 756 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 757 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 758 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 759 struct wil_tid_crypto_rx group_crypto_rx; 760 u8 aid; /* 1-254; 0 if unknown/not reported */ 761 }; 762 763 enum { 764 fw_recovery_idle = 0, 765 fw_recovery_pending = 1, 766 fw_recovery_running = 2, 767 }; 768 769 enum { 770 hw_capa_no_flash, 771 hw_capa_last 772 }; 773 774 struct wil_probe_client_req { 775 struct list_head list; 776 u64 cookie; 777 u8 cid; 778 }; 779 780 struct pmc_ctx { 781 /* alloc, free, and read operations must own the lock */ 782 struct mutex lock; 783 struct vring_tx_desc *pring_va; 784 dma_addr_t pring_pa; 785 struct desc_alloc_info *descriptors; 786 int last_cmd_status; 787 int num_descriptors; 788 int descriptor_size; 789 }; 790 791 struct wil_halp { 792 struct mutex lock; /* protect halp ref_cnt */ 793 unsigned int ref_cnt; 794 struct completion comp; 795 u8 handle_icr; 796 }; 797 798 struct wil_blob_wrapper { 799 struct wil6210_priv *wil; 800 struct debugfs_blob_wrapper blob; 801 }; 802 803 #define WIL_LED_MAX_ID (2) 804 #define WIL_LED_INVALID_ID (0xF) 805 #define WIL_LED_BLINK_ON_SLOW_MS (300) 806 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 807 #define WIL_LED_BLINK_ON_MED_MS (200) 808 #define WIL_LED_BLINK_OFF_MED_MS (200) 809 #define WIL_LED_BLINK_ON_FAST_MS (100) 810 #define WIL_LED_BLINK_OFF_FAST_MS (100) 811 enum { 812 WIL_LED_TIME_SLOW = 0, 813 WIL_LED_TIME_MED, 814 WIL_LED_TIME_FAST, 815 WIL_LED_TIME_LAST, 816 }; 817 818 struct blink_on_off_time { 819 u32 on_ms; 820 u32 off_ms; 821 }; 822 823 struct wil_debugfs_iomem_data { 824 void *offset; 825 struct wil6210_priv *wil; 826 }; 827 828 struct wil_debugfs_data { 829 struct wil_debugfs_iomem_data *data_arr; 830 int iomem_data_count; 831 }; 832 833 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 834 extern u8 led_id; 835 extern u8 led_polarity; 836 837 enum wil6210_vif_status { 838 wil_vif_fwconnecting, 839 wil_vif_fwconnected, 840 wil_vif_ft_roam, 841 wil_vif_status_last /* keep last */ 842 }; 843 844 struct wil6210_vif { 845 struct wireless_dev wdev; 846 struct net_device *ndev; 847 struct wil6210_priv *wil; 848 u8 mid; 849 DECLARE_BITMAP(status, wil_vif_status_last); 850 u32 privacy; /* secure connection? */ 851 u16 channel; /* relevant in AP mode */ 852 u8 wmi_edmg_channel; /* relevant in AP mode */ 853 u8 hidden_ssid; /* relevant in AP mode */ 854 u32 ap_isolate; /* no intra-BSS communication */ 855 bool pbss; 856 int bi; 857 u8 *proberesp, *proberesp_ies, *assocresp_ies; 858 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 859 u8 ssid[IEEE80211_MAX_SSID_LEN]; 860 size_t ssid_len; 861 u8 gtk_index; 862 u8 gtk[WMI_MAX_KEY_LEN]; 863 size_t gtk_len; 864 int bcast_ring; 865 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 866 int locally_generated_disc; /* relevant in STA mode */ 867 struct timer_list connect_timer; 868 struct work_struct disconnect_worker; 869 /* scan */ 870 struct cfg80211_scan_request *scan_request; 871 struct timer_list scan_timer; /* detect scan timeout */ 872 struct wil_p2p_info p2p; 873 /* keep alive */ 874 struct list_head probe_client_pending; 875 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 876 struct work_struct probe_client_worker; 877 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 878 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 879 u64 fw_stats_tsf; /* measurement timestamp */ 880 881 /* PTK rekey race prevention, this is relevant to station mode only */ 882 enum wil_rekey_state ptk_rekey_state; 883 struct work_struct enable_tx_key_worker; 884 }; 885 886 /** 887 * RX buffer allocated for enhanced DMA RX descriptors 888 */ 889 struct wil_rx_buff { 890 struct sk_buff *skb; 891 struct list_head list; 892 int id; 893 }; 894 895 /** 896 * During Rx completion processing, the driver extracts a buffer ID which 897 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 898 * is given to the network stack and the buffer is moved from the 'active' 899 * list to the 'free' list. 900 * During Rx refill, SKBs are attached to free buffers and moved to the 901 * 'active' list. 902 */ 903 struct wil_rx_buff_mgmt { 904 struct wil_rx_buff *buff_arr; 905 size_t size; /* number of items in buff_arr */ 906 struct list_head active; 907 struct list_head free; 908 unsigned long free_list_empty_cnt; /* statistics */ 909 }; 910 911 struct wil_fw_stats_global { 912 bool ready; 913 u64 tsf; /* measurement timestamp */ 914 struct wmi_link_stats_global stats; 915 }; 916 917 struct wil_brd_info { 918 u32 file_addr; 919 u32 file_max_size; 920 }; 921 922 struct wil6210_priv { 923 struct pci_dev *pdev; 924 u32 bar_size; 925 struct wiphy *wiphy; 926 struct net_device *main_ndev; 927 int n_msi; 928 void __iomem *csr; 929 DECLARE_BITMAP(status, wil_status_last); 930 u8 fw_version[ETHTOOL_FWVERS_LEN]; 931 u32 hw_version; 932 u8 chip_revision; 933 const char *hw_name; 934 const char *wil_fw_name; 935 char *board_file; 936 u32 num_of_brd_entries; 937 struct wil_brd_info *brd_info; 938 DECLARE_BITMAP(hw_capa, hw_capa_last); 939 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 940 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 941 u32 recovery_count; /* num of FW recovery attempts in a short time */ 942 u32 recovery_state; /* FW recovery state machine */ 943 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 944 wait_queue_head_t wq; /* for all wait_event() use */ 945 u8 max_vifs; /* maximum number of interfaces, including main */ 946 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 947 struct mutex vif_mutex; /* protects access to VIF entries */ 948 atomic_t connected_vifs; 949 u32 max_assoc_sta; /* max sta's supported by the driver and the FW */ 950 951 /* profile */ 952 struct cfg80211_chan_def monitor_chandef; 953 u32 monitor_flags; 954 int sinfo_gen; 955 /* interrupt moderation */ 956 u32 tx_max_burst_duration; 957 u32 tx_interframe_timeout; 958 u32 rx_max_burst_duration; 959 u32 rx_interframe_timeout; 960 /* cached ISR registers */ 961 u32 isr_misc; 962 /* mailbox related */ 963 struct mutex wmi_mutex; 964 struct wil6210_mbox_ctl mbox_ctl; 965 struct completion wmi_ready; 966 struct completion wmi_call; 967 u16 wmi_seq; 968 u16 reply_id; /**< wait for this WMI event */ 969 u8 reply_mid; 970 void *reply_buf; 971 u16 reply_size; 972 struct workqueue_struct *wmi_wq; /* for deferred calls */ 973 struct work_struct wmi_event_worker; 974 struct workqueue_struct *wq_service; 975 struct work_struct fw_error_worker; /* for FW error recovery */ 976 struct list_head pending_wmi_ev; 977 /* 978 * protect pending_wmi_ev 979 * - fill in IRQ from wil6210_irq_misc, 980 * - consumed in thread by wmi_event_worker 981 */ 982 spinlock_t wmi_ev_lock; 983 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 984 spinlock_t eap_lock; /* guarding access to eap rekey fields */ 985 struct napi_struct napi_rx; 986 struct napi_struct napi_tx; 987 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 988 989 /* DMA related */ 990 struct wil_ring ring_rx; 991 unsigned int rx_buf_len; 992 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 993 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 994 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 995 u8 num_rx_status_rings; 996 int tx_sring_idx; 997 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 998 struct wil_sta_info sta[WIL6210_MAX_CID]; 999 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 1000 u32 dma_addr_size; /* indicates dma addr size */ 1001 struct wil_rx_buff_mgmt rx_buff_mgmt; 1002 bool use_enhanced_dma_hw; 1003 struct wil_txrx_ops txrx_ops; 1004 1005 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 1006 /* for synchronizing device memory access while reset or suspend */ 1007 struct rw_semaphore mem_lock; 1008 /* statistics */ 1009 atomic_t isr_count_rx, isr_count_tx; 1010 /* debugfs */ 1011 struct dentry *debug; 1012 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 1013 u8 discovery_mode; 1014 u8 abft_len; 1015 u8 wakeup_trigger; 1016 struct wil_suspend_stats suspend_stats; 1017 struct wil_debugfs_data dbg_data; 1018 bool tx_latency; /* collect TX latency measurements */ 1019 size_t tx_latency_res; /* bin resolution in usec */ 1020 1021 void *platform_handle; 1022 struct wil_platform_ops platform_ops; 1023 bool keep_radio_on_during_sleep; 1024 1025 struct pmc_ctx pmc; 1026 1027 u8 p2p_dev_started; 1028 1029 /* P2P_DEVICE vif */ 1030 struct wireless_dev *p2p_wdev; 1031 struct wireless_dev *radio_wdev; 1032 1033 /* High Access Latency Policy voting */ 1034 struct wil_halp halp; 1035 1036 enum wmi_ps_profile_type ps_profile; 1037 1038 int fw_calib_result; 1039 1040 struct notifier_block pm_notify; 1041 1042 bool suspend_resp_rcvd; 1043 bool suspend_resp_comp; 1044 u32 bus_request_kbps; 1045 u32 bus_request_kbps_pre_suspend; 1046 1047 u32 rgf_fw_assert_code_addr; 1048 u32 rgf_ucode_assert_code_addr; 1049 u32 iccm_base; 1050 1051 /* relevant only for eDMA */ 1052 bool use_compressed_rx_status; 1053 u32 rx_status_ring_order; 1054 u32 tx_status_ring_order; 1055 u32 rx_buff_id_count; 1056 bool amsdu_en; 1057 bool use_rx_hw_reordering; 1058 bool secured_boot; 1059 u8 boot_config; 1060 1061 struct wil_fw_stats_global fw_stats_global; 1062 1063 u32 max_agg_wsize; 1064 u32 max_ampdu_size; 1065 u8 multicast_to_unicast; 1066 s32 cqm_rssi_thold; 1067 }; 1068 1069 #define wil_to_wiphy(i) (i->wiphy) 1070 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1071 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1072 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1073 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1074 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1075 #define vif_to_wil(v) (v->wil) 1076 #define vif_to_ndev(v) (v->ndev) 1077 #define vif_to_wdev(v) (&v->wdev) 1078 #define GET_MAX_VIFS(wil) min_t(int, (wil)->max_vifs, WIL_MAX_VIFS) 1079 1080 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1081 struct wireless_dev *wdev) 1082 { 1083 /* main interface is shared with P2P device */ 1084 if (wdev == wil->p2p_wdev) 1085 return ndev_to_vif(wil->main_ndev); 1086 else 1087 return container_of(wdev, struct wil6210_vif, wdev); 1088 } 1089 1090 static inline struct wireless_dev * 1091 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1092 { 1093 /* main interface is shared with P2P device */ 1094 if (vif->mid) 1095 return vif_to_wdev(vif); 1096 else 1097 return wil->radio_wdev; 1098 } 1099 1100 __printf(2, 3) 1101 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1102 __printf(2, 3) 1103 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1104 __printf(2, 3) 1105 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1106 __printf(2, 3) 1107 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1108 __printf(2, 3) 1109 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1110 #define wil_dbg(wil, fmt, arg...) do { \ 1111 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1112 wil_dbg_trace(wil, fmt, ##arg); \ 1113 } while (0) 1114 1115 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1116 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1117 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1118 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1119 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1120 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1121 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1122 #define wil_err_ratelimited(wil, fmt, arg...) \ 1123 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1124 1125 /* target operations */ 1126 /* register read */ 1127 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1128 { 1129 return readl(wil->csr + HOSTADDR(reg)); 1130 } 1131 1132 /* register write. wmb() to make sure it is completed */ 1133 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1134 { 1135 writel(val, wil->csr + HOSTADDR(reg)); 1136 wmb(); /* wait for write to propagate to the HW */ 1137 } 1138 1139 /* register set = read, OR, write */ 1140 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1141 { 1142 wil_w(wil, reg, wil_r(wil, reg) | val); 1143 } 1144 1145 /* register clear = read, AND with inverted, write */ 1146 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1147 { 1148 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1149 } 1150 1151 /** 1152 * wil_cid_valid - check cid is valid 1153 */ 1154 static inline bool wil_cid_valid(struct wil6210_priv *wil, int cid) 1155 { 1156 return (cid >= 0 && cid < wil->max_assoc_sta && cid < WIL6210_MAX_CID); 1157 } 1158 1159 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1160 1161 #if defined(CONFIG_DYNAMIC_DEBUG) 1162 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1163 groupsize, buf, len, ascii) \ 1164 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1165 prefix_type, rowsize, \ 1166 groupsize, buf, len, ascii) 1167 1168 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1169 groupsize, buf, len, ascii) \ 1170 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1171 prefix_type, rowsize, \ 1172 groupsize, buf, len, ascii) 1173 1174 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1175 groupsize, buf, len, ascii) \ 1176 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1177 prefix_type, rowsize, \ 1178 groupsize, buf, len, ascii) 1179 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1180 static inline 1181 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1182 int groupsize, const void *buf, size_t len, bool ascii) 1183 { 1184 } 1185 1186 static inline 1187 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1188 int groupsize, const void *buf, size_t len, bool ascii) 1189 { 1190 } 1191 1192 static inline 1193 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1194 int groupsize, const void *buf, size_t len, bool ascii) 1195 { 1196 } 1197 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1198 1199 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1200 size_t count); 1201 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1202 size_t count); 1203 int wil_mem_access_lock(struct wil6210_priv *wil); 1204 void wil_mem_access_unlock(struct wil6210_priv *wil); 1205 1206 struct wil6210_vif * 1207 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1208 unsigned char name_assign_type, enum nl80211_iftype iftype); 1209 void wil_vif_free(struct wil6210_vif *vif); 1210 void *wil_if_alloc(struct device *dev); 1211 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1212 struct net_device *ndev, bool up, bool ok); 1213 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1214 void wil_if_free(struct wil6210_priv *wil); 1215 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1216 int wil_if_add(struct wil6210_priv *wil); 1217 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1218 void wil_if_remove(struct wil6210_priv *wil); 1219 int wil_priv_init(struct wil6210_priv *wil); 1220 void wil_priv_deinit(struct wil6210_priv *wil); 1221 int wil_ps_update(struct wil6210_priv *wil, 1222 enum wmi_ps_profile_type ps_profile); 1223 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1224 void wil_fw_error_recovery(struct wil6210_priv *wil); 1225 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1226 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1227 int wil_up(struct wil6210_priv *wil); 1228 int __wil_up(struct wil6210_priv *wil); 1229 int wil_down(struct wil6210_priv *wil); 1230 int __wil_down(struct wil6210_priv *wil); 1231 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1232 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1233 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1234 int wil_find_cid_by_idx(struct wil6210_priv *wil, u8 mid, int idx); 1235 void wil_set_ethtoolops(struct net_device *ndev); 1236 1237 struct fw_map *wil_find_fw_mapping(const char *section); 1238 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1239 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1240 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1241 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1242 struct wil6210_mbox_hdr *hdr); 1243 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1244 void wmi_recv_cmd(struct wil6210_priv *wil); 1245 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1246 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1247 void wmi_event_worker(struct work_struct *work); 1248 void wmi_event_flush(struct wil6210_priv *wil); 1249 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1250 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1251 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1252 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1253 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1254 const void *mac_addr, int key_usage); 1255 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1256 const void *mac_addr, int key_len, const void *key, 1257 int key_usage); 1258 int wmi_echo(struct wil6210_priv *wil); 1259 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1260 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1261 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1262 int wmi_rxon(struct wil6210_priv *wil, bool on); 1263 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1264 int wmi_get_all_temperatures(struct wil6210_priv *wil, 1265 struct wmi_temp_sense_all_done_event 1266 *sense_all_evt); 1267 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1268 bool del_sta); 1269 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1270 u8 ringid, u8 size, u16 timeout); 1271 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1272 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason); 1273 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1274 u8 mid, u8 cid, u8 tid, u8 token, 1275 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1276 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1277 enum wmi_ps_profile_type ps_profile); 1278 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1279 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1280 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1281 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1282 const u8 *mac, enum nl80211_iftype iftype); 1283 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1284 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1285 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, 1286 u8 dialog_token, __le16 ba_param_set, 1287 __le16 ba_timeout, __le16 ba_seq_ctrl); 1288 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1289 1290 void wil6210_clear_irq(struct wil6210_priv *wil); 1291 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1292 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1293 void wil_mask_irq(struct wil6210_priv *wil); 1294 void wil_unmask_irq(struct wil6210_priv *wil); 1295 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1296 void wil_disable_irq(struct wil6210_priv *wil); 1297 void wil_enable_irq(struct wil6210_priv *wil); 1298 void wil6210_mask_halp(struct wil6210_priv *wil); 1299 1300 /* P2P */ 1301 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1302 int wil_p2p_search(struct wil6210_vif *vif, 1303 struct cfg80211_scan_request *request); 1304 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1305 unsigned int duration, struct ieee80211_channel *chan, 1306 u64 *cookie); 1307 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1308 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1309 void wil_p2p_listen_expired(struct work_struct *work); 1310 void wil_p2p_search_expired(struct work_struct *work); 1311 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1312 void wil_p2p_delayed_listen_work(struct work_struct *work); 1313 1314 /* WMI for P2P */ 1315 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1316 int wmi_start_listen(struct wil6210_vif *vif); 1317 int wmi_start_search(struct wil6210_vif *vif); 1318 int wmi_stop_discovery(struct wil6210_vif *vif); 1319 1320 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1321 struct cfg80211_mgmt_tx_params *params, 1322 u64 *cookie); 1323 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1324 int wil_cfg80211_iface_combinations_from_fw( 1325 struct wil6210_priv *wil, 1326 const struct wil_fw_record_concurrency *conc); 1327 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1328 1329 #if defined(CONFIG_WIL6210_DEBUGFS) 1330 int wil6210_debugfs_init(struct wil6210_priv *wil); 1331 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1332 #else 1333 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1334 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1335 #endif 1336 1337 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1338 struct station_info *sinfo); 1339 1340 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1341 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1342 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1343 1344 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1345 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1346 u8 edmg_chan, u8 hidden_ssid, u8 is_go); 1347 int wmi_pcp_stop(struct wil6210_vif *vif); 1348 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1349 int wmi_abort_scan(struct wil6210_vif *vif); 1350 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1351 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1352 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1353 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1354 u16 reason_code); 1355 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1356 u16 reason_code); 1357 void wil_probe_client_flush(struct wil6210_vif *vif); 1358 void wil_probe_client_worker(struct work_struct *work); 1359 void wil_disconnect_worker(struct work_struct *work); 1360 void wil_enable_tx_key_worker(struct work_struct *work); 1361 1362 void wil_init_txrx_ops(struct wil6210_priv *wil); 1363 1364 /* TX API */ 1365 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1366 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1367 int wil_bcast_init(struct wil6210_vif *vif); 1368 void wil_bcast_fini(struct wil6210_vif *vif); 1369 void wil_bcast_fini_all(struct wil6210_priv *wil); 1370 1371 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1372 struct wil_ring *ring, bool should_stop); 1373 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1374 struct wil_ring *ring, bool check_stop); 1375 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1376 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1377 void wil_tx_complete_handle_eapol(struct wil6210_vif *vif, 1378 struct sk_buff *skb); 1379 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1380 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1381 1382 /* RX API */ 1383 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1384 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1385 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1386 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1387 struct wil_sta_info *cs, 1388 struct key_params *params); 1389 1390 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1391 1392 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1393 bool load); 1394 int wil_request_board(struct wil6210_priv *wil, const char *name); 1395 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1396 1397 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1398 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1399 int wil_pm_runtime_get(struct wil6210_priv *wil); 1400 void wil_pm_runtime_put(struct wil6210_priv *wil); 1401 1402 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1403 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1404 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1405 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1406 int wmi_resume(struct wil6210_priv *wil); 1407 int wmi_suspend(struct wil6210_priv *wil); 1408 bool wil_is_tx_idle(struct wil6210_priv *wil); 1409 1410 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1411 void wil_fw_core_dump(struct wil6210_priv *wil); 1412 1413 void wil_halp_vote(struct wil6210_priv *wil); 1414 void wil_halp_unvote(struct wil6210_priv *wil); 1415 void wil6210_set_halp(struct wil6210_priv *wil); 1416 void wil6210_clear_halp(struct wil6210_priv *wil); 1417 1418 int wmi_start_sched_scan(struct wil6210_priv *wil, 1419 struct cfg80211_sched_scan_request *request); 1420 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1421 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1422 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1423 u8 channel, u16 duration_ms); 1424 int wmi_rbufcap_cfg(struct wil6210_priv *wil, bool enable, u16 threshold); 1425 1426 int wil_wmi2spec_ch(u8 wmi_ch, u8 *spec_ch); 1427 int wil_spec2wmi_ch(u8 spec_ch, u8 *wmi_ch); 1428 void wil_update_supported_bands(struct wil6210_priv *wil); 1429 1430 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1431 1432 /* WMI for enhanced DMA */ 1433 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1434 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1435 u16 max_rx_pl_per_desc); 1436 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1437 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1438 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1439 int tid); 1440 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1441 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1442 u8 tid, u8 token, u16 status, bool amsdu, 1443 u16 agg_wsize, u16 timeout); 1444 1445 void update_supported_bands(struct wil6210_priv *wil); 1446 1447 void wil_clear_fw_log_addr(struct wil6210_priv *wil); 1448 int wmi_set_cqm_rssi_config(struct wil6210_priv *wil, 1449 s32 rssi_thold, u32 rssi_hyst); 1450 #endif /* __WIL6210_H__ */ 1451