1 /* 2 * Copyright (c) 2012-2015 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WIL6210_H__ 18 #define __WIL6210_H__ 19 20 #include <linux/netdevice.h> 21 #include <linux/wireless.h> 22 #include <net/cfg80211.h> 23 #include <linux/timex.h> 24 #include <linux/types.h> 25 #include "wil_platform.h" 26 27 extern bool no_fw_recovery; 28 extern unsigned int mtu_max; 29 extern unsigned short rx_ring_overflow_thrsh; 30 extern int agg_wsize; 31 extern u32 vring_idle_trsh; 32 extern bool rx_align_2; 33 extern bool debug_fw; 34 35 #define WIL_NAME "wil6210" 36 #define WIL_FW_NAME "wil6210.fw" /* code */ 37 #define WIL_FW2_NAME "wil6210.brd" /* board & radio parameters */ 38 39 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 40 41 /** 42 * extract bits [@b0:@b1] (inclusive) from the value @x 43 * it should be @b0 <= @b1, or result is incorrect 44 */ 45 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 46 { 47 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 48 } 49 50 #define WIL6210_MEM_SIZE (2*1024*1024UL) 51 52 #define WIL_TX_Q_LEN_DEFAULT (4000) 53 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 54 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (10) 55 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 56 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 57 /* limit ring size in range [32..32k] */ 58 #define WIL_RING_SIZE_ORDER_MIN (5) 59 #define WIL_RING_SIZE_ORDER_MAX (15) 60 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 61 #define WIL6210_MAX_CID (8) /* HW limit */ 62 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 63 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 64 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 65 /* Hardware offload block adds the following: 66 * 26 bytes - 3-address QoS data header 67 * 8 bytes - IV + EIV (for GCMP) 68 * 8 bytes - SNAP 69 * 16 bytes - MIC (for GCMP) 70 * 4 bytes - CRC 71 */ 72 #define WIL_MAX_MPDU_OVERHEAD (62) 73 74 /* Calculate MAC buffer size for the firmware. It includes all overhead, 75 * as it will go over the air, and need to be 8 byte aligned 76 */ 77 static inline u32 wil_mtu2macbuf(u32 mtu) 78 { 79 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 80 } 81 82 /* MTU for Ethernet need to take into account 8-byte SNAP header 83 * to be added when encapsulating Ethernet frame into 802.11 84 */ 85 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 86 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 87 #define WIL6210_ITR_TRSH_MAX (5000000) 88 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 89 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 90 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 91 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 92 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 93 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 94 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 95 #define WIL6210_RX_HIGH_TRSH_INIT (0) 96 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 97 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 98 /* Hardware definitions begin */ 99 100 /* 101 * Mapping 102 * RGF File | Host addr | FW addr 103 * | | 104 * user_rgf | 0x000000 | 0x880000 105 * dma_rgf | 0x001000 | 0x881000 106 * pcie_rgf | 0x002000 | 0x882000 107 * | | 108 */ 109 110 /* Where various structures placed in host address space */ 111 #define WIL6210_FW_HOST_OFF (0x880000UL) 112 113 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 114 115 /* 116 * Interrupt control registers block 117 * 118 * each interrupt controlled by the same bit in all registers 119 */ 120 struct RGF_ICR { 121 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 122 u32 ICR; /* Cause, W1C/COR depending on ICC */ 123 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 124 u32 ICS; /* Cause Set, WO */ 125 u32 IMV; /* Mask, RW+S/C */ 126 u32 IMS; /* Mask Set, write 1 to set */ 127 u32 IMC; /* Mask Clear, write 1 to clear */ 128 } __packed; 129 130 /* registers - FW addresses */ 131 #define RGF_USER_USAGE_1 (0x880004) 132 #define RGF_USER_USAGE_6 (0x880018) 133 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 134 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 135 #define RGF_USER_USER_CPU_0 (0x8801e0) 136 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 137 #define RGF_USER_MAC_CPU_0 (0x8801fc) 138 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 139 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 140 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 141 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 142 #define RGF_USER_CLKS_CTL_0 (0x880abc) 143 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 144 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 145 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 146 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 147 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 148 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 149 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 150 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 151 #define BIT_CAR_PERST_RST BIT(7) 152 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 153 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 154 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 155 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 156 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 157 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 158 159 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 160 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 161 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 162 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 163 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 164 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 165 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 166 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 167 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 168 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 169 170 /* Legacy interrupt moderation control (before Sparrow v2)*/ 171 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 172 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 173 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 174 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 175 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 176 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 177 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 178 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 179 180 /* Offload control (Sparrow B0+) */ 181 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 182 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 183 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 184 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 185 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 186 187 /* New (sparrow v2+) interrupt moderation control */ 188 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 189 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 190 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 191 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 192 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 193 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 194 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 195 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 196 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 197 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 198 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 199 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 200 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 201 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 202 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 203 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 204 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 205 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 206 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 207 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 208 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 209 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 210 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 211 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 212 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 213 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 214 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 215 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 216 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 217 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 218 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 219 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 220 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 221 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 222 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 223 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 224 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 225 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 226 227 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 228 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 229 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 230 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 231 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 232 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 233 234 #define RGF_HP_CTRL (0x88265c) 235 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 236 237 /* MAC timer, usec, for packet lifetime */ 238 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 239 240 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 241 #define RGF_CAF_OSC_CONTROL (0x88afa4) 242 #define BIT_CAF_OSC_XTAL_EN BIT(0) 243 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 244 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 245 246 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 247 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f) 248 249 /* crash codes for FW/Ucode stored here */ 250 #define RGF_FW_ASSERT_CODE (0x91f020) 251 #define RGF_UCODE_ASSERT_CODE (0x91f028) 252 253 enum { 254 HW_VER_UNKNOWN, 255 HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */ 256 }; 257 258 /* popular locations */ 259 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 260 #define HOST_MBOX HOSTADDR(RGF_MBOX) 261 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 262 263 /* ISR register bits */ 264 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 265 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 266 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 267 268 /* Hardware definitions end */ 269 struct fw_map { 270 u32 from; /* linker address - from, inclusive */ 271 u32 to; /* linker address - to, exclusive */ 272 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 273 const char *name; /* for debugfs */ 274 }; 275 276 /* array size should be in sync with actual definition in the wmi.c */ 277 extern const struct fw_map fw_mapping[8]; 278 279 /** 280 * mk_cidxtid - construct @cidxtid field 281 * @cid: CID value 282 * @tid: TID value 283 * 284 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 285 */ 286 static inline u8 mk_cidxtid(u8 cid, u8 tid) 287 { 288 return ((tid & 0xf) << 4) | (cid & 0xf); 289 } 290 291 /** 292 * parse_cidxtid - parse @cidxtid field 293 * @cid: store CID value here 294 * @tid: store TID value here 295 * 296 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 297 */ 298 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 299 { 300 *cid = cidxtid & 0xf; 301 *tid = (cidxtid >> 4) & 0xf; 302 } 303 304 struct wil6210_mbox_ring { 305 u32 base; 306 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 307 u16 size; 308 u32 tail; 309 u32 head; 310 } __packed; 311 312 struct wil6210_mbox_ring_desc { 313 __le32 sync; 314 __le32 addr; 315 } __packed; 316 317 /* at HOST_OFF_WIL6210_MBOX_CTL */ 318 struct wil6210_mbox_ctl { 319 struct wil6210_mbox_ring tx; 320 struct wil6210_mbox_ring rx; 321 } __packed; 322 323 struct wil6210_mbox_hdr { 324 __le16 seq; 325 __le16 len; /* payload, bytes after this header */ 326 __le16 type; 327 u8 flags; 328 u8 reserved; 329 } __packed; 330 331 #define WIL_MBOX_HDR_TYPE_WMI (0) 332 333 /* max. value for wil6210_mbox_hdr.len */ 334 #define MAX_MBOXITEM_SIZE (240) 335 336 /** 337 * struct wil6210_mbox_hdr_wmi - WMI header 338 * 339 * @mid: MAC ID 340 * 00 - default, created by FW 341 * 01..0f - WiFi ports, driver to create 342 * 10..fe - debug 343 * ff - broadcast 344 * @id: command/event ID 345 * @timestamp: FW fills for events, free-running msec timer 346 */ 347 struct wil6210_mbox_hdr_wmi { 348 u8 mid; 349 u8 reserved; 350 __le16 id; 351 __le32 timestamp; 352 } __packed; 353 354 struct pending_wmi_event { 355 struct list_head list; 356 struct { 357 struct wil6210_mbox_hdr hdr; 358 struct wil6210_mbox_hdr_wmi wmi; 359 u8 data[0]; 360 } __packed event; 361 }; 362 363 enum { /* for wil_ctx.mapped_as */ 364 wil_mapped_as_none = 0, 365 wil_mapped_as_single = 1, 366 wil_mapped_as_page = 2, 367 }; 368 369 /** 370 * struct wil_ctx - software context for Vring descriptor 371 */ 372 struct wil_ctx { 373 struct sk_buff *skb; 374 u8 nr_frags; 375 u8 mapped_as; 376 }; 377 378 union vring_desc; 379 380 struct vring { 381 dma_addr_t pa; 382 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 383 u16 size; /* number of vring_desc elements */ 384 u32 swtail; 385 u32 swhead; 386 u32 hwtail; /* write here to inform hw */ 387 struct wil_ctx *ctx; /* ctx[size] - software context */ 388 }; 389 390 /** 391 * Additional data for Tx Vring 392 */ 393 struct vring_tx_data { 394 bool dot1x_open; 395 int enabled; 396 cycles_t idle, last_idle, begin; 397 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 398 u16 agg_timeout; 399 u8 agg_amsdu; 400 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 401 spinlock_t lock; 402 }; 403 404 enum { /* for wil6210_priv.status */ 405 wil_status_fwready = 0, /* FW operational */ 406 wil_status_fwconnecting, 407 wil_status_fwconnected, 408 wil_status_dontscan, 409 wil_status_mbox_ready, /* MBOX structures ready */ 410 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 411 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 412 wil_status_resetting, /* reset in progress */ 413 wil_status_last /* keep last */ 414 }; 415 416 struct pci_dev; 417 418 /** 419 * struct tid_ampdu_rx - TID aggregation information (Rx). 420 * 421 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 422 * @reorder_time: jiffies when skb was added 423 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 424 * @reorder_timer: releases expired frames from the reorder buffer. 425 * @last_rx: jiffies of last rx activity 426 * @head_seq_num: head sequence number in reordering buffer. 427 * @stored_mpdu_num: number of MPDUs in reordering buffer 428 * @ssn: Starting Sequence Number expected to be aggregated. 429 * @buf_size: buffer size for incoming A-MPDUs 430 * @timeout: reset timer value (in TUs). 431 * @ssn_last_drop: SSN of the last dropped frame 432 * @total: total number of processed incoming frames 433 * @drop_dup: duplicate frames dropped for this reorder buffer 434 * @drop_old: old frames dropped for this reorder buffer 435 * @dialog_token: dialog token for aggregation session 436 * @first_time: true when this buffer used 1-st time 437 */ 438 struct wil_tid_ampdu_rx { 439 struct sk_buff **reorder_buf; 440 unsigned long *reorder_time; 441 struct timer_list session_timer; 442 struct timer_list reorder_timer; 443 unsigned long last_rx; 444 u16 head_seq_num; 445 u16 stored_mpdu_num; 446 u16 ssn; 447 u16 buf_size; 448 u16 timeout; 449 u16 ssn_last_drop; 450 unsigned long long total; /* frames processed */ 451 unsigned long long drop_dup; 452 unsigned long long drop_old; 453 u8 dialog_token; 454 bool first_time; /* is it 1-st time this buffer used? */ 455 }; 456 457 enum wil_sta_status { 458 wil_sta_unused = 0, 459 wil_sta_conn_pending = 1, 460 wil_sta_connected = 2, 461 }; 462 463 #define WIL_STA_TID_NUM (16) 464 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 465 466 struct wil_net_stats { 467 unsigned long rx_packets; 468 unsigned long tx_packets; 469 unsigned long rx_bytes; 470 unsigned long tx_bytes; 471 unsigned long tx_errors; 472 unsigned long rx_dropped; 473 unsigned long rx_non_data_frame; 474 unsigned long rx_short_frame; 475 unsigned long rx_large_frame; 476 u16 last_mcs_rx; 477 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 478 }; 479 480 /** 481 * struct wil_sta_info - data for peer 482 * 483 * Peer identified by its CID (connection ID) 484 * NIC performs beam forming for each peer; 485 * if no beam forming done, frame exchange is not 486 * possible. 487 */ 488 struct wil_sta_info { 489 u8 addr[ETH_ALEN]; 490 enum wil_sta_status status; 491 struct wil_net_stats stats; 492 /* Rx BACK */ 493 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 494 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 495 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 496 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 497 }; 498 499 enum { 500 fw_recovery_idle = 0, 501 fw_recovery_pending = 1, 502 fw_recovery_running = 2, 503 }; 504 505 enum { 506 hw_capability_last 507 }; 508 509 struct wil_back_rx { 510 struct list_head list; 511 /* request params, converted to CPU byte order - what we asked for */ 512 u8 cidxtid; 513 u8 dialog_token; 514 u16 ba_param_set; 515 u16 ba_timeout; 516 u16 ba_seq_ctrl; 517 }; 518 519 struct wil_back_tx { 520 struct list_head list; 521 /* request params, converted to CPU byte order - what we asked for */ 522 u8 ringid; 523 u8 agg_wsize; 524 u16 agg_timeout; 525 }; 526 527 struct wil_probe_client_req { 528 struct list_head list; 529 u64 cookie; 530 u8 cid; 531 }; 532 533 struct pmc_ctx { 534 /* alloc, free, and read operations must own the lock */ 535 struct mutex lock; 536 struct vring_tx_desc *pring_va; 537 dma_addr_t pring_pa; 538 struct desc_alloc_info *descriptors; 539 int last_cmd_status; 540 int num_descriptors; 541 int descriptor_size; 542 }; 543 544 struct wil6210_priv { 545 struct pci_dev *pdev; 546 struct wireless_dev *wdev; 547 void __iomem *csr; 548 DECLARE_BITMAP(status, wil_status_last); 549 u32 fw_version; 550 u32 hw_version; 551 const char *hw_name; 552 DECLARE_BITMAP(hw_capabilities, hw_capability_last); 553 u8 n_mids; /* number of additional MIDs as reported by FW */ 554 u32 recovery_count; /* num of FW recovery attempts in a short time */ 555 u32 recovery_state; /* FW recovery state machine */ 556 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 557 wait_queue_head_t wq; /* for all wait_event() use */ 558 /* profile */ 559 u32 monitor_flags; 560 u32 privacy; /* secure connection? */ 561 u8 hidden_ssid; /* relevant in AP mode */ 562 u16 channel; /* relevant in AP mode */ 563 int sinfo_gen; 564 u32 ap_isolate; /* no intra-BSS communication */ 565 /* interrupt moderation */ 566 u32 tx_max_burst_duration; 567 u32 tx_interframe_timeout; 568 u32 rx_max_burst_duration; 569 u32 rx_interframe_timeout; 570 /* cached ISR registers */ 571 u32 isr_misc; 572 /* mailbox related */ 573 struct mutex wmi_mutex; 574 struct wil6210_mbox_ctl mbox_ctl; 575 struct completion wmi_ready; 576 struct completion wmi_call; 577 u16 wmi_seq; 578 u16 reply_id; /**< wait for this WMI event */ 579 void *reply_buf; 580 u16 reply_size; 581 struct workqueue_struct *wmi_wq; /* for deferred calls */ 582 struct work_struct wmi_event_worker; 583 struct workqueue_struct *wq_service; 584 struct work_struct connect_worker; 585 struct work_struct disconnect_worker; 586 struct work_struct fw_error_worker; /* for FW error recovery */ 587 struct timer_list connect_timer; 588 struct timer_list scan_timer; /* detect scan timeout */ 589 int pending_connect_cid; 590 struct list_head pending_wmi_ev; 591 /* 592 * protect pending_wmi_ev 593 * - fill in IRQ from wil6210_irq_misc, 594 * - consumed in thread by wmi_event_worker 595 */ 596 spinlock_t wmi_ev_lock; 597 struct napi_struct napi_rx; 598 struct napi_struct napi_tx; 599 /* BACK */ 600 struct list_head back_rx_pending; 601 struct mutex back_rx_mutex; /* protect @back_rx_pending */ 602 struct work_struct back_rx_worker; 603 struct list_head back_tx_pending; 604 struct mutex back_tx_mutex; /* protect @back_tx_pending */ 605 struct work_struct back_tx_worker; 606 /* keep alive */ 607 struct list_head probe_client_pending; 608 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 609 struct work_struct probe_client_worker; 610 /* DMA related */ 611 struct vring vring_rx; 612 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 613 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 614 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 615 struct wil_sta_info sta[WIL6210_MAX_CID]; 616 int bcast_vring; 617 /* scan */ 618 struct cfg80211_scan_request *scan_request; 619 620 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 621 /* statistics */ 622 atomic_t isr_count_rx, isr_count_tx; 623 /* debugfs */ 624 struct dentry *debug; 625 struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)]; 626 627 void *platform_handle; 628 struct wil_platform_ops platform_ops; 629 630 struct pmc_ctx pmc; 631 }; 632 633 #define wil_to_wiphy(i) (i->wdev->wiphy) 634 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 635 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 636 #define wil_to_wdev(i) (i->wdev) 637 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 638 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 639 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 640 641 __printf(2, 3) 642 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 643 __printf(2, 3) 644 void wil_err(struct wil6210_priv *wil, const char *fmt, ...); 645 __printf(2, 3) 646 void wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 647 __printf(2, 3) 648 void wil_info(struct wil6210_priv *wil, const char *fmt, ...); 649 #define wil_dbg(wil, fmt, arg...) do { \ 650 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 651 wil_dbg_trace(wil, fmt, ##arg); \ 652 } while (0) 653 654 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 655 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 656 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 657 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 658 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 659 660 /* target operations */ 661 /* register read */ 662 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 663 { 664 return readl(wil->csr + HOSTADDR(reg)); 665 } 666 667 /* register write. wmb() to make sure it is completed */ 668 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 669 { 670 writel(val, wil->csr + HOSTADDR(reg)); 671 wmb(); /* wait for write to propagate to the HW */ 672 } 673 674 /* register set = read, OR, write */ 675 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 676 { 677 wil_w(wil, reg, wil_r(wil, reg) | val); 678 } 679 680 /* register clear = read, AND with inverted, write */ 681 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 682 { 683 wil_w(wil, reg, wil_r(wil, reg) & ~val); 684 } 685 686 #if defined(CONFIG_DYNAMIC_DEBUG) 687 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 688 groupsize, buf, len, ascii) \ 689 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 690 prefix_type, rowsize, \ 691 groupsize, buf, len, ascii) 692 693 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 694 groupsize, buf, len, ascii) \ 695 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 696 prefix_type, rowsize, \ 697 groupsize, buf, len, ascii) 698 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 699 static inline 700 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 701 int groupsize, const void *buf, size_t len, bool ascii) 702 { 703 } 704 705 static inline 706 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 707 int groupsize, const void *buf, size_t len, bool ascii) 708 { 709 } 710 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 711 712 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 713 size_t count); 714 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 715 size_t count); 716 717 void *wil_if_alloc(struct device *dev); 718 void wil_if_free(struct wil6210_priv *wil); 719 int wil_if_add(struct wil6210_priv *wil); 720 void wil_if_remove(struct wil6210_priv *wil); 721 int wil_priv_init(struct wil6210_priv *wil); 722 void wil_priv_deinit(struct wil6210_priv *wil); 723 int wil_reset(struct wil6210_priv *wil, bool no_fw); 724 void wil_fw_error_recovery(struct wil6210_priv *wil); 725 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 726 int wil_up(struct wil6210_priv *wil); 727 int __wil_up(struct wil6210_priv *wil); 728 int wil_down(struct wil6210_priv *wil); 729 int __wil_down(struct wil6210_priv *wil); 730 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 731 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 732 void wil_set_ethtoolops(struct net_device *ndev); 733 734 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 735 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 736 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 737 struct wil6210_mbox_hdr *hdr); 738 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 739 void wmi_recv_cmd(struct wil6210_priv *wil); 740 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 741 u16 reply_id, void *reply, u8 reply_size, int to_msec); 742 void wmi_event_worker(struct work_struct *work); 743 void wmi_event_flush(struct wil6210_priv *wil); 744 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 745 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 746 int wmi_set_channel(struct wil6210_priv *wil, int channel); 747 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 748 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 749 const void *mac_addr, int key_usage); 750 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 751 const void *mac_addr, int key_len, const void *key, 752 int key_usage); 753 int wmi_echo(struct wil6210_priv *wil); 754 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 755 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 756 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel); 757 int wmi_rxon(struct wil6210_priv *wil, bool on); 758 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 759 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason); 760 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout); 761 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason); 762 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason); 763 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, 764 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 765 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid, 766 u8 dialog_token, __le16 ba_param_set, 767 __le16 ba_timeout, __le16 ba_seq_ctrl); 768 void wil_back_rx_worker(struct work_struct *work); 769 void wil_back_rx_flush(struct wil6210_priv *wil); 770 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 771 void wil_back_tx_worker(struct work_struct *work); 772 void wil_back_tx_flush(struct wil6210_priv *wil); 773 774 void wil6210_clear_irq(struct wil6210_priv *wil); 775 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi); 776 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 777 void wil_mask_irq(struct wil6210_priv *wil); 778 void wil_unmask_irq(struct wil6210_priv *wil); 779 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 780 void wil_disable_irq(struct wil6210_priv *wil); 781 void wil_enable_irq(struct wil6210_priv *wil); 782 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 783 struct cfg80211_mgmt_tx_params *params, 784 u64 *cookie); 785 786 int wil6210_debugfs_init(struct wil6210_priv *wil); 787 void wil6210_debugfs_remove(struct wil6210_priv *wil); 788 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid, 789 struct station_info *sinfo); 790 791 struct wireless_dev *wil_cfg80211_init(struct device *dev); 792 void wil_wdev_free(struct wil6210_priv *wil); 793 794 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 795 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, 796 u8 chan, u8 hidden_ssid); 797 int wmi_pcp_stop(struct wil6210_priv *wil); 798 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, 799 u16 reason_code, bool from_event); 800 void wil_probe_client_flush(struct wil6210_priv *wil); 801 void wil_probe_client_worker(struct work_struct *work); 802 803 int wil_rx_init(struct wil6210_priv *wil, u16 size); 804 void wil_rx_fini(struct wil6210_priv *wil); 805 806 /* TX API */ 807 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 808 int cid, int tid); 809 void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 810 int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size); 811 int wil_bcast_init(struct wil6210_priv *wil); 812 void wil_bcast_fini(struct wil6210_priv *wil); 813 814 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 815 int wil_tx_complete(struct wil6210_priv *wil, int ringid); 816 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 817 818 /* RX API */ 819 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 820 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 821 822 int wil_iftype_nl2wmi(enum nl80211_iftype type); 823 824 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd); 825 int wil_request_firmware(struct wil6210_priv *wil, const char *name); 826 827 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 828 int wil_suspend(struct wil6210_priv *wil, bool is_runtime); 829 int wil_resume(struct wil6210_priv *wil, bool is_runtime); 830 831 void wil_fw_core_dump(struct wil6210_priv *wil); 832 833 #endif /* __WIL6210_H__ */ 834