1 /* 2 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WIL6210_H__ 18 #define __WIL6210_H__ 19 20 #include <linux/etherdevice.h> 21 #include <linux/netdevice.h> 22 #include <linux/wireless.h> 23 #include <net/cfg80211.h> 24 #include <linux/timex.h> 25 #include <linux/types.h> 26 #include "wmi.h" 27 #include "wil_platform.h" 28 29 extern bool no_fw_recovery; 30 extern unsigned int mtu_max; 31 extern unsigned short rx_ring_overflow_thrsh; 32 extern int agg_wsize; 33 extern u32 vring_idle_trsh; 34 extern bool rx_align_2; 35 extern bool debug_fw; 36 37 #define WIL_NAME "wil6210" 38 #define WIL_FW_NAME "wil6210.fw" /* code */ 39 #define WIL_FW2_NAME "wil6210.brd" /* board & radio parameters */ 40 41 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 42 43 /** 44 * extract bits [@b0:@b1] (inclusive) from the value @x 45 * it should be @b0 <= @b1, or result is incorrect 46 */ 47 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 48 { 49 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 50 } 51 52 #define WIL6210_MEM_SIZE (2*1024*1024UL) 53 54 #define WIL_TX_Q_LEN_DEFAULT (4000) 55 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 56 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 57 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 58 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 59 /* limit ring size in range [32..32k] */ 60 #define WIL_RING_SIZE_ORDER_MIN (5) 61 #define WIL_RING_SIZE_ORDER_MAX (15) 62 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 63 #define WIL6210_MAX_CID (8) /* HW limit */ 64 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 65 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 66 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 67 /* Hardware offload block adds the following: 68 * 26 bytes - 3-address QoS data header 69 * 8 bytes - IV + EIV (for GCMP) 70 * 8 bytes - SNAP 71 * 16 bytes - MIC (for GCMP) 72 * 4 bytes - CRC 73 */ 74 #define WIL_MAX_MPDU_OVERHEAD (62) 75 76 /* Calculate MAC buffer size for the firmware. It includes all overhead, 77 * as it will go over the air, and need to be 8 byte aligned 78 */ 79 static inline u32 wil_mtu2macbuf(u32 mtu) 80 { 81 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 82 } 83 84 /* MTU for Ethernet need to take into account 8-byte SNAP header 85 * to be added when encapsulating Ethernet frame into 802.11 86 */ 87 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 88 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 89 #define WIL6210_ITR_TRSH_MAX (5000000) 90 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 91 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 92 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 93 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 94 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 95 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 96 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 97 #define WIL6210_DISCONNECT_TO_MS (2000) 98 #define WIL6210_RX_HIGH_TRSH_INIT (0) 99 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 100 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 101 /* Hardware definitions begin */ 102 103 /* 104 * Mapping 105 * RGF File | Host addr | FW addr 106 * | | 107 * user_rgf | 0x000000 | 0x880000 108 * dma_rgf | 0x001000 | 0x881000 109 * pcie_rgf | 0x002000 | 0x882000 110 * | | 111 */ 112 113 /* Where various structures placed in host address space */ 114 #define WIL6210_FW_HOST_OFF (0x880000UL) 115 116 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 117 118 /* 119 * Interrupt control registers block 120 * 121 * each interrupt controlled by the same bit in all registers 122 */ 123 struct RGF_ICR { 124 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 125 u32 ICR; /* Cause, W1C/COR depending on ICC */ 126 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 127 u32 ICS; /* Cause Set, WO */ 128 u32 IMV; /* Mask, RW+S/C */ 129 u32 IMS; /* Mask Set, write 1 to set */ 130 u32 IMC; /* Mask Clear, write 1 to clear */ 131 } __packed; 132 133 /* registers - FW addresses */ 134 #define RGF_USER_USAGE_1 (0x880004) 135 #define RGF_USER_USAGE_6 (0x880018) 136 #define BIT_USER_OOB_MODE BIT(31) 137 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 138 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 139 #define RGF_USER_USER_CPU_0 (0x8801e0) 140 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 141 #define RGF_USER_MAC_CPU_0 (0x8801fc) 142 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 143 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 144 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 145 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 146 #define RGF_USER_CLKS_CTL_0 (0x880abc) 147 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 148 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 149 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 150 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 151 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 152 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 153 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 154 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 155 #define BIT_CAR_PERST_RST BIT(7) 156 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 157 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 158 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 159 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 160 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 161 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 162 163 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 164 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 165 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 166 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 167 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 168 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 169 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 170 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 171 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 172 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 173 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 174 175 /* Legacy interrupt moderation control (before Sparrow v2)*/ 176 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 177 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 178 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 179 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 180 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 181 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 182 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 183 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 184 185 /* Offload control (Sparrow B0+) */ 186 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 187 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 188 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 189 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 190 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 191 192 /* New (sparrow v2+) interrupt moderation control */ 193 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 194 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 195 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 196 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 197 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 198 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 199 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 200 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 201 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 202 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 203 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 204 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 205 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 206 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 207 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 208 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 209 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 210 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 211 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 212 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 213 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 214 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 215 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 216 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 217 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 218 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 219 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 220 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 221 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 222 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 223 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 224 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 225 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 226 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 227 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 228 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 229 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 230 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 231 232 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 233 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 234 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 235 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 236 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 237 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 238 239 #define RGF_HP_CTRL (0x88265c) 240 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 241 242 /* MAC timer, usec, for packet lifetime */ 243 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 244 245 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 246 #define RGF_CAF_OSC_CONTROL (0x88afa4) 247 #define BIT_CAF_OSC_XTAL_EN BIT(0) 248 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 249 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 250 251 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 252 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f) 253 254 /* crash codes for FW/Ucode stored here */ 255 #define RGF_FW_ASSERT_CODE (0x91f020) 256 #define RGF_UCODE_ASSERT_CODE (0x91f028) 257 258 enum { 259 HW_VER_UNKNOWN, 260 HW_VER_SPARROW_B0, /* JTAG_DEV_ID_SPARROW_B0 */ 261 }; 262 263 /* popular locations */ 264 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 265 #define HOST_MBOX HOSTADDR(RGF_MBOX) 266 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 267 268 /* ISR register bits */ 269 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 270 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 271 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 272 273 /* Hardware definitions end */ 274 struct fw_map { 275 u32 from; /* linker address - from, inclusive */ 276 u32 to; /* linker address - to, exclusive */ 277 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 278 const char *name; /* for debugfs */ 279 bool fw; /* true if FW mapping, false if UCODE mapping */ 280 }; 281 282 /* array size should be in sync with actual definition in the wmi.c */ 283 extern const struct fw_map fw_mapping[10]; 284 285 /** 286 * mk_cidxtid - construct @cidxtid field 287 * @cid: CID value 288 * @tid: TID value 289 * 290 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 291 */ 292 static inline u8 mk_cidxtid(u8 cid, u8 tid) 293 { 294 return ((tid & 0xf) << 4) | (cid & 0xf); 295 } 296 297 /** 298 * parse_cidxtid - parse @cidxtid field 299 * @cid: store CID value here 300 * @tid: store TID value here 301 * 302 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 303 */ 304 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 305 { 306 *cid = cidxtid & 0xf; 307 *tid = (cidxtid >> 4) & 0xf; 308 } 309 310 struct wil6210_mbox_ring { 311 u32 base; 312 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 313 u16 size; 314 u32 tail; 315 u32 head; 316 } __packed; 317 318 struct wil6210_mbox_ring_desc { 319 __le32 sync; 320 __le32 addr; 321 } __packed; 322 323 /* at HOST_OFF_WIL6210_MBOX_CTL */ 324 struct wil6210_mbox_ctl { 325 struct wil6210_mbox_ring tx; 326 struct wil6210_mbox_ring rx; 327 } __packed; 328 329 struct wil6210_mbox_hdr { 330 __le16 seq; 331 __le16 len; /* payload, bytes after this header */ 332 __le16 type; 333 u8 flags; 334 u8 reserved; 335 } __packed; 336 337 #define WIL_MBOX_HDR_TYPE_WMI (0) 338 339 /* max. value for wil6210_mbox_hdr.len */ 340 #define MAX_MBOXITEM_SIZE (240) 341 342 struct pending_wmi_event { 343 struct list_head list; 344 struct { 345 struct wil6210_mbox_hdr hdr; 346 struct wmi_cmd_hdr wmi; 347 u8 data[0]; 348 } __packed event; 349 }; 350 351 enum { /* for wil_ctx.mapped_as */ 352 wil_mapped_as_none = 0, 353 wil_mapped_as_single = 1, 354 wil_mapped_as_page = 2, 355 }; 356 357 /** 358 * struct wil_ctx - software context for Vring descriptor 359 */ 360 struct wil_ctx { 361 struct sk_buff *skb; 362 u8 nr_frags; 363 u8 mapped_as; 364 }; 365 366 union vring_desc; 367 368 struct vring { 369 dma_addr_t pa; 370 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 371 u16 size; /* number of vring_desc elements */ 372 u32 swtail; 373 u32 swhead; 374 u32 hwtail; /* write here to inform hw */ 375 struct wil_ctx *ctx; /* ctx[size] - software context */ 376 }; 377 378 /** 379 * Additional data for Tx Vring 380 */ 381 struct vring_tx_data { 382 bool dot1x_open; 383 int enabled; 384 cycles_t idle, last_idle, begin; 385 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 386 u16 agg_timeout; 387 u8 agg_amsdu; 388 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 389 spinlock_t lock; 390 }; 391 392 enum { /* for wil6210_priv.status */ 393 wil_status_fwready = 0, /* FW operational */ 394 wil_status_fwconnecting, 395 wil_status_fwconnected, 396 wil_status_dontscan, 397 wil_status_mbox_ready, /* MBOX structures ready */ 398 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 399 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 400 wil_status_resetting, /* reset in progress */ 401 wil_status_last /* keep last */ 402 }; 403 404 struct pci_dev; 405 406 /** 407 * struct tid_ampdu_rx - TID aggregation information (Rx). 408 * 409 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 410 * @reorder_time: jiffies when skb was added 411 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 412 * @reorder_timer: releases expired frames from the reorder buffer. 413 * @last_rx: jiffies of last rx activity 414 * @head_seq_num: head sequence number in reordering buffer. 415 * @stored_mpdu_num: number of MPDUs in reordering buffer 416 * @ssn: Starting Sequence Number expected to be aggregated. 417 * @buf_size: buffer size for incoming A-MPDUs 418 * @timeout: reset timer value (in TUs). 419 * @ssn_last_drop: SSN of the last dropped frame 420 * @total: total number of processed incoming frames 421 * @drop_dup: duplicate frames dropped for this reorder buffer 422 * @drop_old: old frames dropped for this reorder buffer 423 * @dialog_token: dialog token for aggregation session 424 * @first_time: true when this buffer used 1-st time 425 */ 426 struct wil_tid_ampdu_rx { 427 struct sk_buff **reorder_buf; 428 unsigned long *reorder_time; 429 struct timer_list session_timer; 430 struct timer_list reorder_timer; 431 unsigned long last_rx; 432 u16 head_seq_num; 433 u16 stored_mpdu_num; 434 u16 ssn; 435 u16 buf_size; 436 u16 timeout; 437 u16 ssn_last_drop; 438 unsigned long long total; /* frames processed */ 439 unsigned long long drop_dup; 440 unsigned long long drop_old; 441 u8 dialog_token; 442 bool first_time; /* is it 1-st time this buffer used? */ 443 }; 444 445 /** 446 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 447 * 448 * @pn: GCMP PN for the session 449 * @key_set: valid key present 450 */ 451 struct wil_tid_crypto_rx_single { 452 u8 pn[IEEE80211_GCMP_PN_LEN]; 453 bool key_set; 454 }; 455 456 struct wil_tid_crypto_rx { 457 struct wil_tid_crypto_rx_single key_id[4]; 458 }; 459 460 struct wil_p2p_info { 461 struct ieee80211_channel listen_chan; 462 u8 discovery_started; 463 u8 p2p_dev_started; 464 u64 cookie; 465 struct wireless_dev *pending_listen_wdev; 466 unsigned int listen_duration; 467 struct timer_list discovery_timer; /* listen/search duration */ 468 struct work_struct discovery_expired_work; /* listen/search expire */ 469 struct work_struct delayed_listen_work; /* listen after scan done */ 470 }; 471 472 enum wil_sta_status { 473 wil_sta_unused = 0, 474 wil_sta_conn_pending = 1, 475 wil_sta_connected = 2, 476 }; 477 478 #define WIL_STA_TID_NUM (16) 479 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 480 481 struct wil_net_stats { 482 unsigned long rx_packets; 483 unsigned long tx_packets; 484 unsigned long rx_bytes; 485 unsigned long tx_bytes; 486 unsigned long tx_errors; 487 unsigned long rx_dropped; 488 unsigned long rx_non_data_frame; 489 unsigned long rx_short_frame; 490 unsigned long rx_large_frame; 491 unsigned long rx_replay; 492 u16 last_mcs_rx; 493 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 494 }; 495 496 /** 497 * struct wil_sta_info - data for peer 498 * 499 * Peer identified by its CID (connection ID) 500 * NIC performs beam forming for each peer; 501 * if no beam forming done, frame exchange is not 502 * possible. 503 */ 504 struct wil_sta_info { 505 u8 addr[ETH_ALEN]; 506 enum wil_sta_status status; 507 struct wil_net_stats stats; 508 /* Rx BACK */ 509 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 510 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 511 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 512 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 513 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 514 struct wil_tid_crypto_rx group_crypto_rx; 515 }; 516 517 enum { 518 fw_recovery_idle = 0, 519 fw_recovery_pending = 1, 520 fw_recovery_running = 2, 521 }; 522 523 enum { 524 hw_capability_last 525 }; 526 527 struct wil_probe_client_req { 528 struct list_head list; 529 u64 cookie; 530 u8 cid; 531 }; 532 533 struct pmc_ctx { 534 /* alloc, free, and read operations must own the lock */ 535 struct mutex lock; 536 struct vring_tx_desc *pring_va; 537 dma_addr_t pring_pa; 538 struct desc_alloc_info *descriptors; 539 int last_cmd_status; 540 int num_descriptors; 541 int descriptor_size; 542 }; 543 544 struct wil_halp { 545 struct mutex lock; /* protect halp ref_cnt */ 546 unsigned int ref_cnt; 547 struct completion comp; 548 }; 549 550 struct wil_blob_wrapper { 551 struct wil6210_priv *wil; 552 struct debugfs_blob_wrapper blob; 553 }; 554 555 #define WIL_LED_MAX_ID (2) 556 #define WIL_LED_INVALID_ID (0xF) 557 #define WIL_LED_BLINK_ON_SLOW_MS (300) 558 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 559 #define WIL_LED_BLINK_ON_MED_MS (200) 560 #define WIL_LED_BLINK_OFF_MED_MS (200) 561 #define WIL_LED_BLINK_ON_FAST_MS (100) 562 #define WIL_LED_BLINK_OFF_FAST_MS (100) 563 enum { 564 WIL_LED_TIME_SLOW = 0, 565 WIL_LED_TIME_MED, 566 WIL_LED_TIME_FAST, 567 WIL_LED_TIME_LAST, 568 }; 569 570 struct blink_on_off_time { 571 u32 on_ms; 572 u32 off_ms; 573 }; 574 575 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 576 extern u8 led_id; 577 extern u8 led_polarity; 578 579 struct wil6210_priv { 580 struct pci_dev *pdev; 581 struct wireless_dev *wdev; 582 void __iomem *csr; 583 DECLARE_BITMAP(status, wil_status_last); 584 u8 fw_version[ETHTOOL_FWVERS_LEN]; 585 u32 hw_version; 586 const char *hw_name; 587 DECLARE_BITMAP(hw_capabilities, hw_capability_last); 588 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 589 u8 n_mids; /* number of additional MIDs as reported by FW */ 590 u32 recovery_count; /* num of FW recovery attempts in a short time */ 591 u32 recovery_state; /* FW recovery state machine */ 592 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 593 wait_queue_head_t wq; /* for all wait_event() use */ 594 /* profile */ 595 u32 monitor_flags; 596 u32 privacy; /* secure connection? */ 597 u8 hidden_ssid; /* relevant in AP mode */ 598 u16 channel; /* relevant in AP mode */ 599 int sinfo_gen; 600 u32 ap_isolate; /* no intra-BSS communication */ 601 /* interrupt moderation */ 602 u32 tx_max_burst_duration; 603 u32 tx_interframe_timeout; 604 u32 rx_max_burst_duration; 605 u32 rx_interframe_timeout; 606 /* cached ISR registers */ 607 u32 isr_misc; 608 /* mailbox related */ 609 struct mutex wmi_mutex; 610 struct wil6210_mbox_ctl mbox_ctl; 611 struct completion wmi_ready; 612 struct completion wmi_call; 613 u16 wmi_seq; 614 u16 reply_id; /**< wait for this WMI event */ 615 void *reply_buf; 616 u16 reply_size; 617 struct workqueue_struct *wmi_wq; /* for deferred calls */ 618 struct work_struct wmi_event_worker; 619 struct workqueue_struct *wq_service; 620 struct work_struct disconnect_worker; 621 struct work_struct fw_error_worker; /* for FW error recovery */ 622 struct timer_list connect_timer; 623 struct timer_list scan_timer; /* detect scan timeout */ 624 struct list_head pending_wmi_ev; 625 /* 626 * protect pending_wmi_ev 627 * - fill in IRQ from wil6210_irq_misc, 628 * - consumed in thread by wmi_event_worker 629 */ 630 spinlock_t wmi_ev_lock; 631 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 632 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 633 struct napi_struct napi_rx; 634 struct napi_struct napi_tx; 635 /* keep alive */ 636 struct list_head probe_client_pending; 637 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 638 struct work_struct probe_client_worker; 639 /* DMA related */ 640 struct vring vring_rx; 641 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 642 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 643 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 644 struct wil_sta_info sta[WIL6210_MAX_CID]; 645 int bcast_vring; 646 /* scan */ 647 struct cfg80211_scan_request *scan_request; 648 649 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 650 /* statistics */ 651 atomic_t isr_count_rx, isr_count_tx; 652 /* debugfs */ 653 struct dentry *debug; 654 struct wil_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)]; 655 u8 discovery_mode; 656 657 void *platform_handle; 658 struct wil_platform_ops platform_ops; 659 660 struct pmc_ctx pmc; 661 662 bool pbss; 663 664 struct wil_p2p_info p2p; 665 666 /* P2P_DEVICE vif */ 667 struct wireless_dev *p2p_wdev; 668 struct mutex p2p_wdev_mutex; /* protect @p2p_wdev and @scan_request */ 669 struct wireless_dev *radio_wdev; 670 671 /* High Access Latency Policy voting */ 672 struct wil_halp halp; 673 674 #ifdef CONFIG_PM 675 #ifdef CONFIG_PM_SLEEP 676 struct notifier_block pm_notify; 677 #endif /* CONFIG_PM_SLEEP */ 678 #endif /* CONFIG_PM */ 679 }; 680 681 #define wil_to_wiphy(i) (i->wdev->wiphy) 682 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 683 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 684 #define wil_to_wdev(i) (i->wdev) 685 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 686 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 687 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 688 689 __printf(2, 3) 690 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 691 __printf(2, 3) 692 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 693 __printf(2, 3) 694 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 695 __printf(2, 3) 696 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 697 __printf(2, 3) 698 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 699 #define wil_dbg(wil, fmt, arg...) do { \ 700 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 701 wil_dbg_trace(wil, fmt, ##arg); \ 702 } while (0) 703 704 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 705 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 706 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 707 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 708 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 709 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 710 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 711 #define wil_err_ratelimited(wil, fmt, arg...) \ 712 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 713 714 /* target operations */ 715 /* register read */ 716 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 717 { 718 return readl(wil->csr + HOSTADDR(reg)); 719 } 720 721 /* register write. wmb() to make sure it is completed */ 722 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 723 { 724 writel(val, wil->csr + HOSTADDR(reg)); 725 wmb(); /* wait for write to propagate to the HW */ 726 } 727 728 /* register set = read, OR, write */ 729 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 730 { 731 wil_w(wil, reg, wil_r(wil, reg) | val); 732 } 733 734 /* register clear = read, AND with inverted, write */ 735 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 736 { 737 wil_w(wil, reg, wil_r(wil, reg) & ~val); 738 } 739 740 #if defined(CONFIG_DYNAMIC_DEBUG) 741 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 742 groupsize, buf, len, ascii) \ 743 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 744 prefix_type, rowsize, \ 745 groupsize, buf, len, ascii) 746 747 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 748 groupsize, buf, len, ascii) \ 749 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 750 prefix_type, rowsize, \ 751 groupsize, buf, len, ascii) 752 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 753 static inline 754 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 755 int groupsize, const void *buf, size_t len, bool ascii) 756 { 757 } 758 759 static inline 760 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 761 int groupsize, const void *buf, size_t len, bool ascii) 762 { 763 } 764 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 765 766 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 767 size_t count); 768 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 769 size_t count); 770 void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst, 771 const volatile void __iomem *src, 772 size_t count); 773 void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil, 774 volatile void __iomem *dst, 775 const void *src, size_t count); 776 777 void *wil_if_alloc(struct device *dev); 778 void wil_if_free(struct wil6210_priv *wil); 779 int wil_if_add(struct wil6210_priv *wil); 780 void wil_if_remove(struct wil6210_priv *wil); 781 int wil_priv_init(struct wil6210_priv *wil); 782 void wil_priv_deinit(struct wil6210_priv *wil); 783 int wil_reset(struct wil6210_priv *wil, bool no_fw); 784 void wil_fw_error_recovery(struct wil6210_priv *wil); 785 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 786 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 787 int wil_up(struct wil6210_priv *wil); 788 int __wil_up(struct wil6210_priv *wil); 789 int wil_down(struct wil6210_priv *wil); 790 int __wil_down(struct wil6210_priv *wil); 791 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 792 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 793 void wil_set_ethtoolops(struct net_device *ndev); 794 795 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 796 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 797 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 798 struct wil6210_mbox_hdr *hdr); 799 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 800 void wmi_recv_cmd(struct wil6210_priv *wil); 801 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 802 u16 reply_id, void *reply, u8 reply_size, int to_msec); 803 void wmi_event_worker(struct work_struct *work); 804 void wmi_event_flush(struct wil6210_priv *wil); 805 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 806 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 807 int wmi_set_channel(struct wil6210_priv *wil, int channel); 808 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 809 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 810 const void *mac_addr, int key_usage); 811 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 812 const void *mac_addr, int key_len, const void *key, 813 int key_usage); 814 int wmi_echo(struct wil6210_priv *wil); 815 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 816 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 817 int wmi_rxon(struct wil6210_priv *wil, bool on); 818 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 819 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason, 820 bool full_disconnect); 821 int wmi_addba(struct wil6210_priv *wil, u8 ringid, u8 size, u16 timeout); 822 int wmi_delba_tx(struct wil6210_priv *wil, u8 ringid, u16 reason); 823 int wmi_delba_rx(struct wil6210_priv *wil, u8 cidxtid, u16 reason); 824 int wmi_addba_rx_resp(struct wil6210_priv *wil, u8 cid, u8 tid, u8 token, 825 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 826 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 827 enum wmi_ps_profile_type ps_profile); 828 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 829 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 830 int wil_addba_rx_request(struct wil6210_priv *wil, u8 cidxtid, 831 u8 dialog_token, __le16 ba_param_set, 832 __le16 ba_timeout, __le16 ba_seq_ctrl); 833 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 834 835 void wil6210_clear_irq(struct wil6210_priv *wil); 836 int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi); 837 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 838 void wil_mask_irq(struct wil6210_priv *wil); 839 void wil_unmask_irq(struct wil6210_priv *wil); 840 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 841 void wil_disable_irq(struct wil6210_priv *wil); 842 void wil_enable_irq(struct wil6210_priv *wil); 843 void wil6210_mask_halp(struct wil6210_priv *wil); 844 845 /* P2P */ 846 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 847 void wil_p2p_discovery_timer_fn(ulong x); 848 int wil_p2p_search(struct wil6210_priv *wil, 849 struct cfg80211_scan_request *request); 850 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 851 unsigned int duration, struct ieee80211_channel *chan, 852 u64 *cookie); 853 u8 wil_p2p_stop_discovery(struct wil6210_priv *wil); 854 int wil_p2p_cancel_listen(struct wil6210_priv *wil, u64 cookie); 855 void wil_p2p_listen_expired(struct work_struct *work); 856 void wil_p2p_search_expired(struct work_struct *work); 857 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 858 void wil_p2p_delayed_listen_work(struct work_struct *work); 859 860 /* WMI for P2P */ 861 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel, int bi); 862 int wmi_start_listen(struct wil6210_priv *wil); 863 int wmi_start_search(struct wil6210_priv *wil); 864 int wmi_stop_discovery(struct wil6210_priv *wil); 865 866 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 867 struct cfg80211_mgmt_tx_params *params, 868 u64 *cookie); 869 870 int wil6210_debugfs_init(struct wil6210_priv *wil); 871 void wil6210_debugfs_remove(struct wil6210_priv *wil); 872 int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid, 873 struct station_info *sinfo); 874 875 struct wireless_dev *wil_cfg80211_init(struct device *dev); 876 void wil_wdev_free(struct wil6210_priv *wil); 877 void wil_p2p_wdev_free(struct wil6210_priv *wil); 878 879 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 880 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, 881 u8 chan, u8 hidden_ssid, u8 is_go); 882 int wmi_pcp_stop(struct wil6210_priv *wil); 883 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 884 int wmi_abort_scan(struct wil6210_priv *wil); 885 void wil_abort_scan(struct wil6210_priv *wil, bool sync); 886 887 void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid, 888 u16 reason_code, bool from_event); 889 void wil_probe_client_flush(struct wil6210_priv *wil); 890 void wil_probe_client_worker(struct work_struct *work); 891 892 int wil_rx_init(struct wil6210_priv *wil, u16 size); 893 void wil_rx_fini(struct wil6210_priv *wil); 894 895 /* TX API */ 896 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 897 int cid, int tid); 898 void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 899 int wil_tx_init(struct wil6210_priv *wil, int cid); 900 int wil_vring_init_bcast(struct wil6210_priv *wil, int id, int size); 901 int wil_bcast_init(struct wil6210_priv *wil); 902 void wil_bcast_fini(struct wil6210_priv *wil); 903 904 void wil_update_net_queues(struct wil6210_priv *wil, struct vring *vring, 905 bool should_stop); 906 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct vring *vring, 907 bool check_stop); 908 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 909 int wil_tx_complete(struct wil6210_priv *wil, int ringid); 910 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 911 912 /* RX API */ 913 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 914 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 915 916 int wil_iftype_nl2wmi(enum nl80211_iftype type); 917 918 int wil_ioctl(struct wil6210_priv *wil, void __user *data, int cmd); 919 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 920 bool load); 921 922 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 923 int wil_suspend(struct wil6210_priv *wil, bool is_runtime); 924 int wil_resume(struct wil6210_priv *wil, bool is_runtime); 925 926 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 927 void wil_fw_core_dump(struct wil6210_priv *wil); 928 929 void wil_halp_vote(struct wil6210_priv *wil); 930 void wil_halp_unvote(struct wil6210_priv *wil); 931 void wil6210_set_halp(struct wil6210_priv *wil); 932 void wil6210_clear_halp(struct wil6210_priv *wil); 933 934 #endif /* __WIL6210_H__ */ 935