1 /* 2 * Copyright (c) 2012 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WIL6210_H__ 18 #define __WIL6210_H__ 19 20 #include <linux/netdevice.h> 21 #include <linux/wireless.h> 22 #include <net/cfg80211.h> 23 24 #define WIL_NAME "wil6210" 25 26 /** 27 * extract bits [@b0:@b1] (inclusive) from the value @x 28 * it should be @b0 <= @b1, or result is incorrect 29 */ 30 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 31 { 32 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 33 } 34 35 #define WIL6210_MEM_SIZE (2*1024*1024UL) 36 37 #define WIL6210_RX_RING_SIZE (128) 38 #define WIL6210_TX_RING_SIZE (128) 39 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 40 #define WIL6210_MAX_CID (8) /* HW limit */ 41 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 42 #define WIL6210_ITR_TRSH (10000) /* arbitrary - about 15 IRQs/msec */ 43 44 /* Hardware definitions begin */ 45 46 /* 47 * Mapping 48 * RGF File | Host addr | FW addr 49 * | | 50 * user_rgf | 0x000000 | 0x880000 51 * dma_rgf | 0x001000 | 0x881000 52 * pcie_rgf | 0x002000 | 0x882000 53 * | | 54 */ 55 56 /* Where various structures placed in host address space */ 57 #define WIL6210_FW_HOST_OFF (0x880000UL) 58 59 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 60 61 /* 62 * Interrupt control registers block 63 * 64 * each interrupt controlled by the same bit in all registers 65 */ 66 struct RGF_ICR { 67 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 68 u32 ICR; /* Cause, W1C/COR depending on ICC */ 69 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 70 u32 ICS; /* Cause Set, WO */ 71 u32 IMV; /* Mask, RW+S/C */ 72 u32 IMS; /* Mask Set, write 1 to set */ 73 u32 IMC; /* Mask Clear, write 1 to clear */ 74 } __packed; 75 76 /* registers - FW addresses */ 77 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 78 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 79 #define RGF_USER_USER_CPU_0 (0x8801e0) 80 #define RGF_USER_MAC_CPU_0 (0x8801fc) 81 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 82 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 83 #define RGF_USER_CLKS_CTL_0 (0x880abc) 84 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 85 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 86 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 87 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 88 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 89 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 90 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 91 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 92 93 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 94 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 95 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 96 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 97 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 98 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 99 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 100 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 101 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 102 103 /* Interrupt moderation control */ 104 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 105 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 106 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 107 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 108 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 109 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 110 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 111 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 112 113 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 114 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 115 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 116 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 117 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 118 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 119 120 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 121 122 /* popular locations */ 123 #define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD) 124 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \ 125 offsetof(struct RGF_ICR, ICS)) 126 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 127 128 /* ISR register bits */ 129 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 130 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 131 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 132 133 /* Hardware definitions end */ 134 135 /** 136 * mk_cidxtid - construct @cidxtid field 137 * @cid: CID value 138 * @tid: TID value 139 * 140 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 141 */ 142 static inline u8 mk_cidxtid(u8 cid, u8 tid) 143 { 144 return ((tid & 0xf) << 4) | (cid & 0xf); 145 } 146 147 /** 148 * parse_cidxtid - parse @cidxtid field 149 * @cid: store CID value here 150 * @tid: store TID value here 151 * 152 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 153 */ 154 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 155 { 156 *cid = cidxtid & 0xf; 157 *tid = (cidxtid >> 4) & 0xf; 158 } 159 160 struct wil6210_mbox_ring { 161 u32 base; 162 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 163 u16 size; 164 u32 tail; 165 u32 head; 166 } __packed; 167 168 struct wil6210_mbox_ring_desc { 169 __le32 sync; 170 __le32 addr; 171 } __packed; 172 173 /* at HOST_OFF_WIL6210_MBOX_CTL */ 174 struct wil6210_mbox_ctl { 175 struct wil6210_mbox_ring tx; 176 struct wil6210_mbox_ring rx; 177 } __packed; 178 179 struct wil6210_mbox_hdr { 180 __le16 seq; 181 __le16 len; /* payload, bytes after this header */ 182 __le16 type; 183 u8 flags; 184 u8 reserved; 185 } __packed; 186 187 #define WIL_MBOX_HDR_TYPE_WMI (0) 188 189 /* max. value for wil6210_mbox_hdr.len */ 190 #define MAX_MBOXITEM_SIZE (240) 191 192 /** 193 * struct wil6210_mbox_hdr_wmi - WMI header 194 * 195 * @mid: MAC ID 196 * 00 - default, created by FW 197 * 01..0f - WiFi ports, driver to create 198 * 10..fe - debug 199 * ff - broadcast 200 * @id: command/event ID 201 * @timestamp: FW fills for events, free-running msec timer 202 */ 203 struct wil6210_mbox_hdr_wmi { 204 u8 mid; 205 u8 reserved; 206 __le16 id; 207 __le32 timestamp; 208 } __packed; 209 210 struct pending_wmi_event { 211 struct list_head list; 212 struct { 213 struct wil6210_mbox_hdr hdr; 214 struct wil6210_mbox_hdr_wmi wmi; 215 u8 data[0]; 216 } __packed event; 217 }; 218 219 enum { /* for wil_ctx.mapped_as */ 220 wil_mapped_as_none = 0, 221 wil_mapped_as_single = 1, 222 wil_mapped_as_page = 2, 223 }; 224 225 /** 226 * struct wil_ctx - software context for Vring descriptor 227 */ 228 struct wil_ctx { 229 struct sk_buff *skb; 230 u8 nr_frags; 231 u8 mapped_as; 232 }; 233 234 union vring_desc; 235 236 struct vring { 237 dma_addr_t pa; 238 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */ 239 u16 size; /* number of vring_desc elements */ 240 u32 swtail; 241 u32 swhead; 242 u32 hwtail; /* write here to inform hw */ 243 struct wil_ctx *ctx; /* ctx[size] - software context */ 244 }; 245 246 /** 247 * Additional data for Tx Vring 248 */ 249 struct vring_tx_data { 250 int enabled; 251 252 }; 253 254 enum { /* for wil6210_priv.status */ 255 wil_status_fwready = 0, 256 wil_status_fwconnecting, 257 wil_status_fwconnected, 258 wil_status_dontscan, 259 wil_status_reset_done, 260 wil_status_irqen, /* FIXME: interrupts enabled - for debug */ 261 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 262 }; 263 264 struct pci_dev; 265 266 /** 267 * struct tid_ampdu_rx - TID aggregation information (Rx). 268 * 269 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 270 * @reorder_time: jiffies when skb was added 271 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value) 272 * @reorder_timer: releases expired frames from the reorder buffer. 273 * @last_rx: jiffies of last rx activity 274 * @head_seq_num: head sequence number in reordering buffer. 275 * @stored_mpdu_num: number of MPDUs in reordering buffer 276 * @ssn: Starting Sequence Number expected to be aggregated. 277 * @buf_size: buffer size for incoming A-MPDUs 278 * @timeout: reset timer value (in TUs). 279 * @dialog_token: dialog token for aggregation session 280 * @rcu_head: RCU head used for freeing this struct 281 * @reorder_lock: serializes access to reorder buffer, see below. 282 * 283 * This structure's lifetime is managed by RCU, assignments to 284 * the array holding it must hold the aggregation mutex. 285 * 286 * The @reorder_lock is used to protect the members of this 287 * struct, except for @timeout, @buf_size and @dialog_token, 288 * which are constant across the lifetime of the struct (the 289 * dialog token being used only for debugging). 290 */ 291 struct wil_tid_ampdu_rx { 292 spinlock_t reorder_lock; /* see above */ 293 struct sk_buff **reorder_buf; 294 unsigned long *reorder_time; 295 struct timer_list session_timer; 296 struct timer_list reorder_timer; 297 unsigned long last_rx; 298 u16 head_seq_num; 299 u16 stored_mpdu_num; 300 u16 ssn; 301 u16 buf_size; 302 u16 timeout; 303 u8 dialog_token; 304 }; 305 306 struct wil6210_stats { 307 u64 tsf; 308 u32 snr; 309 u16 last_mcs_rx; 310 u16 bf_mcs; /* last BF, used for Tx */ 311 u16 my_rx_sector; 312 u16 my_tx_sector; 313 u16 peer_rx_sector; 314 u16 peer_tx_sector; 315 }; 316 317 enum wil_sta_status { 318 wil_sta_unused = 0, 319 wil_sta_conn_pending = 1, 320 wil_sta_connected = 2, 321 }; 322 323 #define WIL_STA_TID_NUM (16) 324 325 struct wil_net_stats { 326 unsigned long rx_packets; 327 unsigned long tx_packets; 328 unsigned long rx_bytes; 329 unsigned long tx_bytes; 330 unsigned long tx_errors; 331 unsigned long rx_dropped; 332 u16 last_mcs_rx; 333 }; 334 335 /** 336 * struct wil_sta_info - data for peer 337 * 338 * Peer identified by its CID (connection ID) 339 * NIC performs beam forming for each peer; 340 * if no beam forming done, frame exchange is not 341 * possible. 342 */ 343 struct wil_sta_info { 344 u8 addr[ETH_ALEN]; 345 enum wil_sta_status status; 346 struct wil_net_stats stats; 347 bool data_port_open; /* can send any data, not only EAPOL */ 348 /* Rx BACK */ 349 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 350 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 351 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 352 }; 353 354 struct wil6210_priv { 355 struct pci_dev *pdev; 356 int n_msi; 357 struct wireless_dev *wdev; 358 void __iomem *csr; 359 ulong status; 360 u32 fw_version; 361 u32 hw_version; 362 u8 n_mids; /* number of additional MIDs as reported by FW */ 363 /* profile */ 364 u32 monitor_flags; 365 u32 secure_pcp; /* create secure PCP? */ 366 int sinfo_gen; 367 /* cached ISR registers */ 368 u32 isr_misc; 369 /* mailbox related */ 370 struct mutex wmi_mutex; 371 struct wil6210_mbox_ctl mbox_ctl; 372 struct completion wmi_ready; 373 u16 wmi_seq; 374 u16 reply_id; /**< wait for this WMI event */ 375 void *reply_buf; 376 u16 reply_size; 377 struct workqueue_struct *wmi_wq; /* for deferred calls */ 378 struct work_struct wmi_event_worker; 379 struct workqueue_struct *wmi_wq_conn; /* for connect worker */ 380 struct work_struct connect_worker; 381 struct work_struct disconnect_worker; 382 struct work_struct fw_error_worker; /* for FW error recovery */ 383 struct timer_list connect_timer; 384 int pending_connect_cid; 385 struct list_head pending_wmi_ev; 386 /* 387 * protect pending_wmi_ev 388 * - fill in IRQ from wil6210_irq_misc, 389 * - consumed in thread by wmi_event_worker 390 */ 391 spinlock_t wmi_ev_lock; 392 struct napi_struct napi_rx; 393 struct napi_struct napi_tx; 394 /* DMA related */ 395 struct vring vring_rx; 396 struct vring vring_tx[WIL6210_MAX_TX_RINGS]; 397 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS]; 398 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 399 struct wil_sta_info sta[WIL6210_MAX_CID]; 400 /* scan */ 401 struct cfg80211_scan_request *scan_request; 402 403 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 404 /* statistics */ 405 struct wil6210_stats stats; 406 /* debugfs */ 407 struct dentry *debug; 408 struct debugfs_blob_wrapper fw_code_blob; 409 struct debugfs_blob_wrapper fw_data_blob; 410 struct debugfs_blob_wrapper fw_peri_blob; 411 struct debugfs_blob_wrapper uc_code_blob; 412 struct debugfs_blob_wrapper uc_data_blob; 413 struct debugfs_blob_wrapper rgf_blob; 414 }; 415 416 #define wil_to_wiphy(i) (i->wdev->wiphy) 417 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 418 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 419 #define wil_to_wdev(i) (i->wdev) 420 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 421 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev) 422 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 423 424 int wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 425 int wil_err(struct wil6210_priv *wil, const char *fmt, ...); 426 int wil_info(struct wil6210_priv *wil, const char *fmt, ...); 427 #define wil_dbg(wil, fmt, arg...) do { \ 428 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \ 429 wil_dbg_trace(wil, fmt, ##arg); \ 430 } while (0) 431 432 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 433 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 434 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 435 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 436 437 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 438 groupsize, buf, len, ascii) \ 439 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 440 prefix_type, rowsize, \ 441 groupsize, buf, len, ascii) 442 443 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 444 groupsize, buf, len, ascii) \ 445 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 446 prefix_type, rowsize, \ 447 groupsize, buf, len, ascii) 448 449 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 450 size_t count); 451 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 452 size_t count); 453 454 void *wil_if_alloc(struct device *dev, void __iomem *csr); 455 void wil_if_free(struct wil6210_priv *wil); 456 int wil_if_add(struct wil6210_priv *wil); 457 void wil_if_remove(struct wil6210_priv *wil); 458 int wil_priv_init(struct wil6210_priv *wil); 459 void wil_priv_deinit(struct wil6210_priv *wil); 460 int wil_reset(struct wil6210_priv *wil); 461 void wil_fw_error_recovery(struct wil6210_priv *wil); 462 void wil_link_on(struct wil6210_priv *wil); 463 void wil_link_off(struct wil6210_priv *wil); 464 int wil_up(struct wil6210_priv *wil); 465 int wil_down(struct wil6210_priv *wil); 466 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 467 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac); 468 469 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 470 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 471 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 472 struct wil6210_mbox_hdr *hdr); 473 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len); 474 void wmi_recv_cmd(struct wil6210_priv *wil); 475 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len, 476 u16 reply_id, void *reply, u8 reply_size, int to_msec); 477 void wmi_event_worker(struct work_struct *work); 478 void wmi_event_flush(struct wil6210_priv *wil); 479 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid); 480 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid); 481 int wmi_set_channel(struct wil6210_priv *wil, int channel); 482 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 483 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index, 484 const void *mac_addr); 485 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index, 486 const void *mac_addr, int key_len, const void *key); 487 int wmi_echo(struct wil6210_priv *wil); 488 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie); 489 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring); 490 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel); 491 int wmi_rxon(struct wil6210_priv *wil, bool on); 492 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 493 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason); 494 495 void wil6210_clear_irq(struct wil6210_priv *wil); 496 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 497 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 498 void wil6210_disable_irq(struct wil6210_priv *wil); 499 void wil6210_enable_irq(struct wil6210_priv *wil); 500 501 int wil6210_debugfs_init(struct wil6210_priv *wil); 502 void wil6210_debugfs_remove(struct wil6210_priv *wil); 503 504 struct wireless_dev *wil_cfg80211_init(struct device *dev); 505 void wil_wdev_free(struct wil6210_priv *wil); 506 507 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 508 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan); 509 int wmi_pcp_stop(struct wil6210_priv *wil); 510 void wil6210_disconnect(struct wil6210_priv *wil, void *bssid); 511 512 int wil_rx_init(struct wil6210_priv *wil); 513 void wil_rx_fini(struct wil6210_priv *wil); 514 515 /* TX API */ 516 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size, 517 int cid, int tid); 518 void wil_vring_fini_tx(struct wil6210_priv *wil, int id); 519 520 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 521 int wil_tx_complete(struct wil6210_priv *wil, int ringid); 522 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 523 524 /* RX API */ 525 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 526 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 527 528 int wil_iftype_nl2wmi(enum nl80211_iftype type); 529 530 #endif /* __WIL6210_H__ */ 531