1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef __WIL6210_H__
8 #define __WIL6210_H__
9 
10 #include <linux/etherdevice.h>
11 #include <linux/netdevice.h>
12 #include <linux/wireless.h>
13 #include <net/cfg80211.h>
14 #include <linux/timex.h>
15 #include <linux/types.h>
16 #include <linux/irqreturn.h>
17 #include "wmi.h"
18 #include "wil_platform.h"
19 #include "fw.h"
20 
21 extern bool no_fw_recovery;
22 extern unsigned int mtu_max;
23 extern unsigned short rx_ring_overflow_thrsh;
24 extern int agg_wsize;
25 extern bool rx_align_2;
26 extern bool rx_large_buf;
27 extern bool debug_fw;
28 extern bool disable_ap_sme;
29 extern bool ftm_mode;
30 extern bool drop_if_ring_full;
31 extern uint max_assoc_sta;
32 
33 struct wil6210_priv;
34 struct wil6210_vif;
35 union wil_tx_desc;
36 
37 #define WIL_NAME "wil6210"
38 
39 #define WIL_FW_NAME_DEFAULT "wil6210.fw"
40 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw"
41 
42 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw"
43 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw"
44 
45 #define WIL_FW_NAME_TALYN "wil6436.fw"
46 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw"
47 #define WIL_BRD_NAME_TALYN "wil6436.brd"
48 
49 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */
50 
51 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */
52 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
53 
54 #define WIL_NUM_LATENCY_BINS 200
55 
56 /* maximum number of virtual interfaces the driver supports
57  * (including the main interface)
58  */
59 #define WIL_MAX_VIFS 4
60 
61 /**
62  * extract bits [@b0:@b1] (inclusive) from the value @x
63  * it should be @b0 <= @b1, or result is incorrect
64  */
65 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
66 {
67 	return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
68 }
69 
70 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL)
71 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL)
72 
73 #define WIL_TX_Q_LEN_DEFAULT		(4000)
74 #define WIL_RX_RING_SIZE_ORDER_DEFAULT	(10)
75 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT	(11)
76 #define WIL_TX_RING_SIZE_ORDER_DEFAULT	(12)
77 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT	(7)
78 #define WIL_BCAST_MCS0_LIMIT		(1024) /* limit for MCS0 frame size */
79 /* limit ring size in range [32..32k] */
80 #define WIL_RING_SIZE_ORDER_MIN	(5)
81 #define WIL_RING_SIZE_ORDER_MAX	(15)
82 #define WIL6210_MAX_TX_RINGS	(24) /* HW limit */
83 #define WIL6210_MAX_CID		(20) /* max number of stations */
84 #define WIL6210_RX_DESC_MAX_CID	(8)  /* HW limit */
85 #define WIL_MAX_AMPDU_SIZE	(64 * 1024) /* FW/HW limit */
86 #define WIL_MAX_AGG_WSIZE	(32) /* FW/HW limit */
87 #define WIL_MAX_AMPDU_SIZE_128	(128 * 1024) /* FW/HW limit */
88 #define WIL_MAX_AGG_WSIZE_64	(64) /* FW/HW limit */
89 #define WIL6210_MAX_STATUS_RINGS	(8)
90 #define WIL_WMI_CALL_GENERAL_TO_MS 100
91 #define WIL_EXTENDED_MCS_26 (26) /* FW reports MCS 12.1 to driver as "26" */
92 #define WIL_BASE_MCS_FOR_EXTENDED_26 (7) /* MCS 7 is base MCS for MCS 12.1 */
93 #define WIL_EXTENDED_MCS_CHECK(x) (((x) == WIL_EXTENDED_MCS_26) ? "12.1" : #x)
94 
95 /* Hardware offload block adds the following:
96  * 26 bytes - 3-address QoS data header
97  *  8 bytes - IV + EIV (for GCMP)
98  *  8 bytes - SNAP
99  * 16 bytes - MIC (for GCMP)
100  *  4 bytes - CRC
101  */
102 #define WIL_MAX_MPDU_OVERHEAD	(62)
103 
104 struct wil_suspend_count_stats {
105 	unsigned long successful_suspends;
106 	unsigned long successful_resumes;
107 	unsigned long failed_suspends;
108 	unsigned long failed_resumes;
109 };
110 
111 struct wil_suspend_stats {
112 	struct wil_suspend_count_stats r_off;
113 	struct wil_suspend_count_stats r_on;
114 	unsigned long rejected_by_device; /* only radio on */
115 	unsigned long rejected_by_host;
116 };
117 
118 /* Calculate MAC buffer size for the firmware. It includes all overhead,
119  * as it will go over the air, and need to be 8 byte aligned
120  */
121 static inline u32 wil_mtu2macbuf(u32 mtu)
122 {
123 	return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8);
124 }
125 
126 /* MTU for Ethernet need to take into account 8-byte SNAP header
127  * to be added when encapsulating Ethernet frame into 802.11
128  */
129 #define WIL_MAX_ETH_MTU		(IEEE80211_MAX_DATA_LEN_DMG - 8)
130 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
131 #define WIL6210_ITR_TRSH_MAX (5000000)
132 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
133 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
134 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
135 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
136 #define WIL6210_FW_RECOVERY_RETRIES	(5) /* try to recover this many times */
137 #define WIL6210_FW_RECOVERY_TO	msecs_to_jiffies(5000)
138 #define WIL6210_SCAN_TO		msecs_to_jiffies(10000)
139 #define WIL6210_DISCONNECT_TO_MS (2000)
140 #define WIL6210_RX_HIGH_TRSH_INIT		(0)
141 #define WIL6210_RX_HIGH_TRSH_DEFAULT \
142 				(1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
143 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see
144 			     * 802.11REVmc/D5.0, section 9.4.1.8)
145 			     */
146 /* Hardware definitions begin */
147 
148 /*
149  * Mapping
150  * RGF File      | Host addr    |  FW addr
151  *               |              |
152  * user_rgf      | 0x000000     | 0x880000
153  *  dma_rgf      | 0x001000     | 0x881000
154  * pcie_rgf      | 0x002000     | 0x882000
155  *               |              |
156  */
157 
158 /* Where various structures placed in host address space */
159 #define WIL6210_FW_HOST_OFF      (0x880000UL)
160 
161 #define HOSTADDR(fwaddr)        (fwaddr - WIL6210_FW_HOST_OFF)
162 
163 /*
164  * Interrupt control registers block
165  *
166  * each interrupt controlled by the same bit in all registers
167  */
168 struct RGF_ICR {
169 	u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
170 	u32 ICR; /* Cause, W1C/COR depending on ICC */
171 	u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
172 	u32 ICS; /* Cause Set, WO */
173 	u32 IMV; /* Mask, RW+S/C */
174 	u32 IMS; /* Mask Set, write 1 to set */
175 	u32 IMC; /* Mask Clear, write 1 to clear */
176 } __packed;
177 
178 /* registers - FW addresses */
179 #define RGF_USER_USAGE_1		(0x880004)
180 #define RGF_USER_USAGE_2		(0x880008)
181 #define RGF_USER_USAGE_6		(0x880018)
182 	#define BIT_USER_OOB_MODE		BIT(31)
183 	#define BIT_USER_OOB_R2_MODE		BIT(30)
184 #define RGF_USER_USAGE_8		(0x880020)
185 	#define BIT_USER_PREVENT_DEEP_SLEEP	BIT(0)
186 	#define BIT_USER_SUPPORT_T_POWER_ON_0	BIT(1)
187 	#define BIT_USER_EXT_CLK		BIT(2)
188 #define RGF_USER_HW_MACHINE_STATE	(0x8801dc)
189 	#define HW_MACHINE_BOOT_DONE	(0x3fffffd)
190 #define RGF_USER_USER_CPU_0		(0x8801e0)
191 	#define BIT_USER_USER_CPU_MAN_RST	BIT(1) /* user_cpu_man_rst */
192 #define RGF_USER_CPU_PC			(0x8801e8)
193 #define RGF_USER_MAC_CPU_0		(0x8801fc)
194 	#define BIT_USER_MAC_CPU_MAN_RST	BIT(1) /* mac_cpu_man_rst */
195 #define RGF_USER_USER_SCRATCH_PAD	(0x8802bc)
196 #define RGF_USER_BL			(0x880A3C) /* Boot Loader */
197 #define RGF_USER_FW_REV_ID		(0x880a8c) /* chip revision */
198 #define RGF_USER_FW_CALIB_RESULT	(0x880a90) /* b0-7:result
199 						    * b8-15:signature
200 						    */
201 	#define CALIB_RESULT_SIGNATURE	(0x11)
202 #define RGF_USER_CLKS_CTL_0		(0x880abc)
203 	#define BIT_USER_CLKS_CAR_AHB_SW_SEL	BIT(1) /* ref clk/PLL */
204 	#define BIT_USER_CLKS_RST_PWGD	BIT(11) /* reset on "power good" */
205 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0	(0x880b04)
206 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1	(0x880b08)
207 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2	(0x880b0c)
208 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3	(0x880b10)
209 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0	(0x880b14)
210 	#define BIT_HPAL_PERST_FROM_PAD	BIT(6)
211 	#define BIT_CAR_PERST_RST	BIT(7)
212 #define RGF_USER_USER_ICR		(0x880b4c) /* struct RGF_ICR */
213 	#define BIT_USER_USER_ICR_SW_INT_2	BIT(18)
214 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0	(0x880c18)
215 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1	(0x880c2c)
216 #define RGF_USER_SPARROW_M_4			(0x880c50) /* Sparrow */
217 	#define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF	BIT(2)
218 #define RGF_USER_OTP_HW_RD_MACHINE_1	(0x880ce0)
219 	#define BIT_OTP_SIGNATURE_ERR_TALYN_MB		BIT(0)
220 	#define BIT_OTP_HW_SECTION_DONE_TALYN_MB	BIT(2)
221 	#define BIT_NO_FLASH_INDICATION			BIT(8)
222 #define RGF_USER_XPM_IFC_RD_TIME1	(0x880cec)
223 #define RGF_USER_XPM_IFC_RD_TIME2	(0x880cf0)
224 #define RGF_USER_XPM_IFC_RD_TIME3	(0x880cf4)
225 #define RGF_USER_XPM_IFC_RD_TIME4	(0x880cf8)
226 #define RGF_USER_XPM_IFC_RD_TIME5	(0x880cfc)
227 #define RGF_USER_XPM_IFC_RD_TIME6	(0x880d00)
228 #define RGF_USER_XPM_IFC_RD_TIME7	(0x880d04)
229 #define RGF_USER_XPM_IFC_RD_TIME8	(0x880d08)
230 #define RGF_USER_XPM_IFC_RD_TIME9	(0x880d0c)
231 #define RGF_USER_XPM_IFC_RD_TIME10	(0x880d10)
232 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64)
233 
234 #define RGF_DMA_EP_TX_ICR		(0x881bb4) /* struct RGF_ICR */
235 	#define BIT_DMA_EP_TX_ICR_TX_DONE	BIT(0)
236 	#define BIT_DMA_EP_TX_ICR_TX_DONE_N(n)	BIT(n+1) /* n = [0..23] */
237 #define RGF_DMA_EP_RX_ICR		(0x881bd0) /* struct RGF_ICR */
238 	#define BIT_DMA_EP_RX_ICR_RX_DONE	BIT(0)
239 	#define BIT_DMA_EP_RX_ICR_RX_HTRSH	BIT(1)
240 #define RGF_DMA_EP_MISC_ICR		(0x881bec) /* struct RGF_ICR */
241 	#define BIT_DMA_EP_MISC_ICR_RX_HTRSH	BIT(0)
242 	#define BIT_DMA_EP_MISC_ICR_TX_NO_ACT	BIT(1)
243 	#define BIT_DMA_EP_MISC_ICR_HALP	BIT(27)
244 	#define BIT_DMA_EP_MISC_ICR_FW_INT(n)	BIT(28+n) /* n = [0..3] */
245 
246 /* Legacy interrupt moderation control (before Sparrow v2)*/
247 #define RGF_DMA_ITR_CNT_TRSH		(0x881c5c)
248 #define RGF_DMA_ITR_CNT_DATA		(0x881c60)
249 #define RGF_DMA_ITR_CNT_CRL		(0x881c64)
250 	#define BIT_DMA_ITR_CNT_CRL_EN		BIT(0)
251 	#define BIT_DMA_ITR_CNT_CRL_EXT_TICK	BIT(1)
252 	#define BIT_DMA_ITR_CNT_CRL_FOREVER	BIT(2)
253 	#define BIT_DMA_ITR_CNT_CRL_CLR		BIT(3)
254 	#define BIT_DMA_ITR_CNT_CRL_REACH_TRSH	BIT(4)
255 
256 /* Offload control (Sparrow B0+) */
257 #define RGF_DMA_OFUL_NID_0		(0x881cd4)
258 	#define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN		BIT(0)
259 	#define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN		BIT(1)
260 	#define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC	BIT(2)
261 	#define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC	BIT(3)
262 
263 /* New (sparrow v2+) interrupt moderation control */
264 #define RGF_DMA_ITR_TX_DESQ_NO_MOD		(0x881d40)
265 #define RGF_DMA_ITR_TX_CNT_TRSH			(0x881d34)
266 #define RGF_DMA_ITR_TX_CNT_DATA			(0x881d38)
267 #define RGF_DMA_ITR_TX_CNT_CTL			(0x881d3c)
268 	#define BIT_DMA_ITR_TX_CNT_CTL_EN		BIT(0)
269 	#define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL	BIT(1)
270 	#define BIT_DMA_ITR_TX_CNT_CTL_FOREVER		BIT(2)
271 	#define BIT_DMA_ITR_TX_CNT_CTL_CLR		BIT(3)
272 	#define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH	BIT(4)
273 	#define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN		BIT(5)
274 	#define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG	BIT(6)
275 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH			(0x881d60)
276 #define RGF_DMA_ITR_TX_IDL_CNT_DATA			(0x881d64)
277 #define RGF_DMA_ITR_TX_IDL_CNT_CTL			(0x881d68)
278 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN			BIT(0)
279 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
280 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER		BIT(2)
281 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR			BIT(3)
282 	#define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
283 #define RGF_DMA_ITR_RX_DESQ_NO_MOD		(0x881d50)
284 #define RGF_DMA_ITR_RX_CNT_TRSH			(0x881d44)
285 #define RGF_DMA_ITR_RX_CNT_DATA			(0x881d48)
286 #define RGF_DMA_ITR_RX_CNT_CTL			(0x881d4c)
287 	#define BIT_DMA_ITR_RX_CNT_CTL_EN		BIT(0)
288 	#define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL	BIT(1)
289 	#define BIT_DMA_ITR_RX_CNT_CTL_FOREVER		BIT(2)
290 	#define BIT_DMA_ITR_RX_CNT_CTL_CLR		BIT(3)
291 	#define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH	BIT(4)
292 	#define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN		BIT(5)
293 	#define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG	BIT(6)
294 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH			(0x881d54)
295 #define RGF_DMA_ITR_RX_IDL_CNT_DATA			(0x881d58)
296 #define RGF_DMA_ITR_RX_IDL_CNT_CTL			(0x881d5c)
297 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN			BIT(0)
298 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL		BIT(1)
299 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER		BIT(2)
300 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR			BIT(3)
301 	#define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH	BIT(4)
302 #define RGF_DMA_MISC_CTL				(0x881d6c)
303 	#define BIT_OFUL34_RDY_VALID_BUG_FIX_EN			BIT(7)
304 
305 #define RGF_DMA_PSEUDO_CAUSE		(0x881c68)
306 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW	(0x881c6c)
307 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW	(0x881c70)
308 	#define BIT_DMA_PSEUDO_CAUSE_RX		BIT(0)
309 	#define BIT_DMA_PSEUDO_CAUSE_TX		BIT(1)
310 	#define BIT_DMA_PSEUDO_CAUSE_MISC	BIT(2)
311 
312 #define RGF_HP_CTRL			(0x88265c)
313 #define RGF_PAL_UNIT_ICR		(0x88266c) /* struct RGF_ICR */
314 #define RGF_PCIE_LOS_COUNTER_CTL	(0x882dc4)
315 
316 /* MAC timer, usec, for packet lifetime */
317 #define RGF_MAC_MTRL_COUNTER_0		(0x886aa8)
318 
319 #define RGF_CAF_ICR_TALYN_MB		(0x8893d4) /* struct RGF_ICR */
320 #define RGF_CAF_ICR			(0x88946c) /* struct RGF_ICR */
321 #define RGF_CAF_OSC_CONTROL		(0x88afa4)
322 	#define BIT_CAF_OSC_XTAL_EN		BIT(0)
323 #define RGF_CAF_PLL_LOCK_STATUS		(0x88afec)
324 	#define BIT_CAF_OSC_DIG_XTAL_STABLE	BIT(0)
325 
326 #define RGF_OTP_QC_SECURED		(0x8a0038)
327 	#define BIT_BOOT_FROM_ROM		BIT(31)
328 
329 /* eDMA */
330 #define RGF_SCM_PTRS_SUBQ_RD_PTR	(0x8b4000)
331 #define RGF_SCM_PTRS_COMPQ_RD_PTR	(0x8b4100)
332 #define RGF_DMA_SCM_SUBQ_CONS		(0x8b60ec)
333 #define RGF_DMA_SCM_COMPQ_PROD		(0x8b616c)
334 
335 #define RGF_INT_COUNT_ON_SPECIAL_EVT	(0x8b62d8)
336 
337 #define RGF_INT_CTRL_INT_GEN_CFG_0	(0x8bc000)
338 #define RGF_INT_CTRL_INT_GEN_CFG_1	(0x8bc004)
339 #define RGF_INT_GEN_TIME_UNIT_LIMIT	(0x8bc0c8)
340 
341 #define RGF_INT_GEN_CTRL		(0x8bc0ec)
342 	#define BIT_CONTROL_0			BIT(0)
343 
344 /* eDMA status interrupts */
345 #define RGF_INT_GEN_RX_ICR		(0x8bc0f4)
346 	#define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX)
347 #define RGF_INT_GEN_TX_ICR		(0x8bc110)
348 	#define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX)
349 #define RGF_INT_CTRL_RX_INT_MASK	(0x8bc12c)
350 #define RGF_INT_CTRL_TX_INT_MASK	(0x8bc130)
351 
352 #define RGF_INT_GEN_IDLE_TIME_LIMIT	(0x8bc134)
353 
354 #define USER_EXT_USER_PMU_3		(0x88d00c)
355 	#define BIT_PMU_DEVICE_RDY		BIT(0)
356 
357 #define RGF_USER_JTAG_DEV_ID	(0x880b34) /* device ID */
358 	#define JTAG_DEV_ID_SPARROW	(0x2632072f)
359 	#define JTAG_DEV_ID_TALYN	(0x7e0e1)
360 	#define JTAG_DEV_ID_TALYN_MB	(0x1007e0e1)
361 
362 #define RGF_USER_REVISION_ID		(0x88afe4)
363 #define RGF_USER_REVISION_ID_MASK	(3)
364 	#define REVISION_ID_SPARROW_B0	(0x0)
365 	#define REVISION_ID_SPARROW_D0	(0x3)
366 
367 #define RGF_OTP_MAC_TALYN_MB		(0x8a0304)
368 #define RGF_OTP_OEM_MAC			(0x8a0334)
369 #define RGF_OTP_MAC			(0x8a0620)
370 
371 /* Talyn-MB */
372 #define RGF_USER_USER_CPU_0_TALYN_MB	(0x8c0138)
373 #define RGF_USER_MAC_CPU_0_TALYN_MB	(0x8c0154)
374 
375 /* crash codes for FW/Ucode stored here */
376 
377 /* ASSERT RGFs */
378 #define SPARROW_RGF_FW_ASSERT_CODE	(0x91f020)
379 #define SPARROW_RGF_UCODE_ASSERT_CODE	(0x91f028)
380 #define TALYN_RGF_FW_ASSERT_CODE	(0xa37020)
381 #define TALYN_RGF_UCODE_ASSERT_CODE	(0xa37028)
382 
383 enum {
384 	HW_VER_UNKNOWN,
385 	HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */
386 	HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */
387 	HW_VER_TALYN,	/* JTAG_DEV_ID_TALYN */
388 	HW_VER_TALYN_MB	/* JTAG_DEV_ID_TALYN_MB */
389 };
390 
391 /* popular locations */
392 #define RGF_MBOX   RGF_USER_USER_SCRATCH_PAD
393 #define HOST_MBOX   HOSTADDR(RGF_MBOX)
394 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
395 
396 /* ISR register bits */
397 #define ISR_MISC_FW_READY	BIT_DMA_EP_MISC_ICR_FW_INT(0)
398 #define ISR_MISC_MBOX_EVT	BIT_DMA_EP_MISC_ICR_FW_INT(1)
399 #define ISR_MISC_FW_ERROR	BIT_DMA_EP_MISC_ICR_FW_INT(3)
400 
401 #define WIL_DATA_COMPLETION_TO_MS 200
402 
403 /* Hardware definitions end */
404 #define SPARROW_FW_MAPPING_TABLE_SIZE 10
405 #define TALYN_FW_MAPPING_TABLE_SIZE 13
406 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19
407 #define MAX_FW_MAPPING_TABLE_SIZE 19
408 
409 /* Common representation of physical address in wil ring */
410 struct wil_ring_dma_addr {
411 	__le32 addr_low;
412 	__le16 addr_high;
413 } __packed;
414 
415 struct fw_map {
416 	u32 from; /* linker address - from, inclusive */
417 	u32 to;   /* linker address - to, exclusive */
418 	u32 host; /* PCI/Host address - BAR0 + 0x880000 */
419 	const char *name; /* for debugfs */
420 	bool fw; /* true if FW mapping, false if UCODE mapping */
421 	bool crash_dump; /* true if should be dumped during crash dump */
422 };
423 
424 /* array size should be in sync with actual definition in the wmi.c */
425 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE];
426 extern const struct fw_map sparrow_d0_mac_rgf_ext;
427 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE];
428 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE];
429 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE];
430 
431 /**
432  * mk_cidxtid - construct @cidxtid field
433  * @cid: CID value
434  * @tid: TID value
435  *
436  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
437  */
438 static inline u8 mk_cidxtid(u8 cid, u8 tid)
439 {
440 	return ((tid & 0xf) << 4) | (cid & 0xf);
441 }
442 
443 /**
444  * parse_cidxtid - parse @cidxtid field
445  * @cid: store CID value here
446  * @tid: store TID value here
447  *
448  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
449  */
450 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
451 {
452 	*cid = cidxtid & 0xf;
453 	*tid = (cidxtid >> 4) & 0xf;
454 }
455 
456 struct wil6210_mbox_ring {
457 	u32 base;
458 	u16 entry_size; /* max. size of mbox entry, incl. all headers */
459 	u16 size;
460 	u32 tail;
461 	u32 head;
462 } __packed;
463 
464 struct wil6210_mbox_ring_desc {
465 	__le32 sync;
466 	__le32 addr;
467 } __packed;
468 
469 /* at HOST_OFF_WIL6210_MBOX_CTL */
470 struct wil6210_mbox_ctl {
471 	struct wil6210_mbox_ring tx;
472 	struct wil6210_mbox_ring rx;
473 } __packed;
474 
475 struct wil6210_mbox_hdr {
476 	__le16 seq;
477 	__le16 len; /* payload, bytes after this header */
478 	__le16 type;
479 	u8 flags;
480 	u8 reserved;
481 } __packed;
482 
483 #define WIL_MBOX_HDR_TYPE_WMI (0)
484 
485 /* max. value for wil6210_mbox_hdr.len */
486 #define MAX_MBOXITEM_SIZE   (240)
487 
488 struct pending_wmi_event {
489 	struct list_head list;
490 	struct {
491 		struct wil6210_mbox_hdr hdr;
492 		struct wmi_cmd_hdr wmi;
493 		u8 data[0];
494 	} __packed event;
495 };
496 
497 enum { /* for wil_ctx.mapped_as */
498 	wil_mapped_as_none = 0,
499 	wil_mapped_as_single = 1,
500 	wil_mapped_as_page = 2,
501 };
502 
503 /**
504  * struct wil_ctx - software context for ring descriptor
505  */
506 struct wil_ctx {
507 	struct sk_buff *skb;
508 	u8 nr_frags;
509 	u8 mapped_as;
510 };
511 
512 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */
513 	u32 *va;
514 	dma_addr_t pa;
515 };
516 
517 /**
518  * A general ring structure, used for RX and TX.
519  * In legacy DMA it represents the vring,
520  * In enahnced DMA it represents the descriptor ring (vrings are handled by FW)
521  */
522 struct wil_ring {
523 	dma_addr_t pa;
524 	volatile union wil_ring_desc *va;
525 	u16 size; /* number of wil_ring_desc elements */
526 	u32 swtail;
527 	u32 swhead;
528 	u32 hwtail; /* write here to inform hw */
529 	struct wil_ctx *ctx; /* ctx[size] - software context */
530 	struct wil_desc_ring_rx_swtail edma_rx_swtail;
531 	bool is_rx;
532 };
533 
534 /**
535  * Additional data for Rx ring.
536  * Used for enhanced DMA RX chaining.
537  */
538 struct wil_ring_rx_data {
539 	/* the skb being assembled */
540 	struct sk_buff *skb;
541 	/* true if we are skipping a bad fragmented packet */
542 	bool skipping;
543 	u16 buff_size;
544 };
545 
546 /**
547  * Status ring structure, used for enhanced DMA completions for RX and TX.
548  */
549 struct wil_status_ring {
550 	dma_addr_t pa;
551 	void *va; /* pointer to ring_[tr]x_status elements */
552 	u16 size; /* number of status elements */
553 	size_t elem_size; /* status element size in bytes */
554 	u32 swhead;
555 	u32 hwtail; /* write here to inform hw */
556 	bool is_rx;
557 	u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */
558 	struct wil_ring_rx_data rx_data;
559 	u32 invalid_buff_id_cnt; /* relevant only for RX */
560 };
561 
562 #define WIL_STA_TID_NUM (16)
563 #define WIL_MCS_MAX (15) /* Maximum MCS supported */
564 
565 struct wil_net_stats {
566 	unsigned long	rx_packets;
567 	unsigned long	tx_packets;
568 	unsigned long	rx_bytes;
569 	unsigned long	tx_bytes;
570 	unsigned long	tx_errors;
571 	u32 tx_latency_min_us;
572 	u32 tx_latency_max_us;
573 	u64 tx_latency_total_us;
574 	unsigned long	rx_dropped;
575 	unsigned long	rx_non_data_frame;
576 	unsigned long	rx_short_frame;
577 	unsigned long	rx_large_frame;
578 	unsigned long	rx_replay;
579 	unsigned long	rx_mic_error;
580 	unsigned long	rx_key_error; /* eDMA specific */
581 	unsigned long	rx_amsdu_error; /* eDMA specific */
582 	unsigned long	rx_csum_err;
583 	u16 last_mcs_rx;
584 	u8 last_cb_mode_rx;
585 	u64 rx_per_mcs[WIL_MCS_MAX + 1];
586 	u32 ft_roams; /* relevant in STA mode */
587 };
588 
589 /**
590  * struct tx_rx_ops - different TX/RX ops for legacy and enhanced
591  * DMA flow
592  */
593 struct wil_txrx_ops {
594 	void (*configure_interrupt_moderation)(struct wil6210_priv *wil);
595 	/* TX ops */
596 	int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id,
597 			    int size, int cid, int tid);
598 	void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring);
599 	int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size);
600 	int (*tx_init)(struct wil6210_priv *wil);
601 	void (*tx_fini)(struct wil6210_priv *wil);
602 	int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa,
603 			   u32 len, int ring_index);
604 	void (*tx_desc_unmap)(struct device *dev,
605 			      union wil_tx_desc *desc,
606 			      struct wil_ctx *ctx);
607 	int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif,
608 			   struct wil_ring *ring, struct sk_buff *skb);
609 	int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id,
610 			      int cid, int tid);
611 	irqreturn_t (*irq_tx)(int irq, void *cookie);
612 	/* RX ops */
613 	int (*rx_init)(struct wil6210_priv *wil, uint ring_order);
614 	void (*rx_fini)(struct wil6210_priv *wil);
615 	int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid,
616 				 u8 tid, u8 token, u16 status, bool amsdu,
617 				 u16 agg_wsize, u16 timeout);
618 	void (*get_reorder_params)(struct wil6210_priv *wil,
619 				   struct sk_buff *skb, int *tid, int *cid,
620 				   int *mid, u16 *seq, int *mcast, int *retry);
621 	void (*get_netif_rx_params)(struct sk_buff *skb,
622 				    int *cid, int *security);
623 	int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb);
624 	int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb,
625 			      struct wil_net_stats *stats);
626 	bool (*is_rx_idle)(struct wil6210_priv *wil);
627 	irqreturn_t (*irq_rx)(int irq, void *cookie);
628 };
629 
630 /**
631  * Additional data for Tx ring
632  */
633 struct wil_ring_tx_data {
634 	bool dot1x_open;
635 	int enabled;
636 	cycles_t idle, last_idle, begin;
637 	u8 agg_wsize; /* agreed aggregation window, 0 - no agg */
638 	u16 agg_timeout;
639 	u8 agg_amsdu;
640 	bool addba_in_progress; /* if set, agg_xxx is for request in progress */
641 	u8 mid;
642 	spinlock_t lock;
643 };
644 
645 enum { /* for wil6210_priv.status */
646 	wil_status_fwready = 0, /* FW operational */
647 	wil_status_dontscan,
648 	wil_status_mbox_ready, /* MBOX structures ready */
649 	wil_status_irqen, /* interrupts enabled - for debug */
650 	wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
651 	wil_status_resetting, /* reset in progress */
652 	wil_status_suspending, /* suspend in progress */
653 	wil_status_suspended, /* suspend completed, device is suspended */
654 	wil_status_resuming, /* resume in progress */
655 	wil_status_last /* keep last */
656 };
657 
658 struct pci_dev;
659 
660 /**
661  * struct tid_ampdu_rx - TID aggregation information (Rx).
662  *
663  * @reorder_buf: buffer to reorder incoming aggregated MPDUs
664  * @last_rx: jiffies of last rx activity
665  * @head_seq_num: head sequence number in reordering buffer.
666  * @stored_mpdu_num: number of MPDUs in reordering buffer
667  * @ssn: Starting Sequence Number expected to be aggregated.
668  * @buf_size: buffer size for incoming A-MPDUs
669  * @ssn_last_drop: SSN of the last dropped frame
670  * @total: total number of processed incoming frames
671  * @drop_dup: duplicate frames dropped for this reorder buffer
672  * @drop_old: old frames dropped for this reorder buffer
673  * @first_time: true when this buffer used 1-st time
674  * @mcast_last_seq: sequence number (SN) of last received multicast packet
675  * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer
676  */
677 struct wil_tid_ampdu_rx {
678 	struct sk_buff **reorder_buf;
679 	unsigned long last_rx;
680 	u16 head_seq_num;
681 	u16 stored_mpdu_num;
682 	u16 ssn;
683 	u16 buf_size;
684 	u16 ssn_last_drop;
685 	unsigned long long total; /* frames processed */
686 	unsigned long long drop_dup;
687 	unsigned long long drop_old;
688 	bool first_time; /* is it 1-st time this buffer used? */
689 	u16 mcast_last_seq; /* multicast dup detection */
690 	unsigned long long drop_dup_mcast;
691 };
692 
693 /**
694  * struct wil_tid_crypto_rx_single - TID crypto information (Rx).
695  *
696  * @pn: GCMP PN for the session
697  * @key_set: valid key present
698  */
699 struct wil_tid_crypto_rx_single {
700 	u8 pn[IEEE80211_GCMP_PN_LEN];
701 	bool key_set;
702 };
703 
704 struct wil_tid_crypto_rx {
705 	struct wil_tid_crypto_rx_single key_id[4];
706 };
707 
708 struct wil_p2p_info {
709 	struct ieee80211_channel listen_chan;
710 	u8 discovery_started;
711 	u64 cookie;
712 	struct wireless_dev *pending_listen_wdev;
713 	unsigned int listen_duration;
714 	struct timer_list discovery_timer; /* listen/search duration */
715 	struct work_struct discovery_expired_work; /* listen/search expire */
716 	struct work_struct delayed_listen_work; /* listen after scan done */
717 };
718 
719 enum wil_sta_status {
720 	wil_sta_unused = 0,
721 	wil_sta_conn_pending = 1,
722 	wil_sta_connected = 2,
723 };
724 
725 enum wil_rekey_state {
726 	WIL_REKEY_IDLE = 0,
727 	WIL_REKEY_M3_RECEIVED = 1,
728 	WIL_REKEY_WAIT_M4_SENT = 2,
729 };
730 
731 /**
732  * struct wil_sta_info - data for peer
733  *
734  * Peer identified by its CID (connection ID)
735  * NIC performs beam forming for each peer;
736  * if no beam forming done, frame exchange is not
737  * possible.
738  */
739 struct wil_sta_info {
740 	u8 addr[ETH_ALEN];
741 	u8 mid;
742 	enum wil_sta_status status;
743 	struct wil_net_stats stats;
744 	/**
745 	 * 20 latency bins. 1st bin counts packets with latency
746 	 * of 0..tx_latency_res, last bin counts packets with latency
747 	 * of 19*tx_latency_res and above.
748 	 * tx_latency_res is configured from "tx_latency" debug-fs.
749 	 */
750 	u64 *tx_latency_bins;
751 	struct wmi_link_stats_basic fw_stats_basic;
752 	/* Rx BACK */
753 	struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
754 	spinlock_t tid_rx_lock; /* guarding tid_rx array */
755 	unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
756 	unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
757 	struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM];
758 	struct wil_tid_crypto_rx group_crypto_rx;
759 	u8 aid; /* 1-254; 0 if unknown/not reported */
760 };
761 
762 enum {
763 	fw_recovery_idle = 0,
764 	fw_recovery_pending = 1,
765 	fw_recovery_running = 2,
766 };
767 
768 enum {
769 	hw_capa_no_flash,
770 	hw_capa_last
771 };
772 
773 struct wil_probe_client_req {
774 	struct list_head list;
775 	u64 cookie;
776 	u8 cid;
777 };
778 
779 struct pmc_ctx {
780 	/* alloc, free, and read operations must own the lock */
781 	struct mutex		lock;
782 	struct vring_tx_desc	*pring_va;
783 	dma_addr_t		pring_pa;
784 	struct desc_alloc_info  *descriptors;
785 	int			last_cmd_status;
786 	int			num_descriptors;
787 	int			descriptor_size;
788 };
789 
790 struct wil_halp {
791 	struct mutex		lock; /* protect halp ref_cnt */
792 	unsigned int		ref_cnt;
793 	struct completion	comp;
794 	u8			handle_icr;
795 };
796 
797 struct wil_blob_wrapper {
798 	struct wil6210_priv *wil;
799 	struct debugfs_blob_wrapper blob;
800 };
801 
802 #define WIL_LED_MAX_ID			(2)
803 #define WIL_LED_INVALID_ID		(0xF)
804 #define WIL_LED_BLINK_ON_SLOW_MS	(300)
805 #define WIL_LED_BLINK_OFF_SLOW_MS	(300)
806 #define WIL_LED_BLINK_ON_MED_MS		(200)
807 #define WIL_LED_BLINK_OFF_MED_MS	(200)
808 #define WIL_LED_BLINK_ON_FAST_MS	(100)
809 #define WIL_LED_BLINK_OFF_FAST_MS	(100)
810 enum {
811 	WIL_LED_TIME_SLOW = 0,
812 	WIL_LED_TIME_MED,
813 	WIL_LED_TIME_FAST,
814 	WIL_LED_TIME_LAST,
815 };
816 
817 struct blink_on_off_time {
818 	u32 on_ms;
819 	u32 off_ms;
820 };
821 
822 struct wil_debugfs_iomem_data {
823 	void *offset;
824 	struct wil6210_priv *wil;
825 };
826 
827 struct wil_debugfs_data {
828 	struct wil_debugfs_iomem_data *data_arr;
829 	int iomem_data_count;
830 };
831 
832 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST];
833 extern u8 led_id;
834 extern u8 led_polarity;
835 
836 enum wil6210_vif_status {
837 	wil_vif_fwconnecting,
838 	wil_vif_fwconnected,
839 	wil_vif_ft_roam,
840 	wil_vif_status_last /* keep last */
841 };
842 
843 struct wil6210_vif {
844 	struct wireless_dev wdev;
845 	struct net_device *ndev;
846 	struct wil6210_priv *wil;
847 	u8 mid;
848 	DECLARE_BITMAP(status, wil_vif_status_last);
849 	u32 privacy; /* secure connection? */
850 	u16 channel; /* relevant in AP mode */
851 	u8 wmi_edmg_channel; /* relevant in AP mode */
852 	u8 hidden_ssid; /* relevant in AP mode */
853 	u32 ap_isolate; /* no intra-BSS communication */
854 	bool pbss;
855 	int bi;
856 	u8 *proberesp, *proberesp_ies, *assocresp_ies;
857 	size_t proberesp_len, proberesp_ies_len, assocresp_ies_len;
858 	u8 ssid[IEEE80211_MAX_SSID_LEN];
859 	size_t ssid_len;
860 	u8 gtk_index;
861 	u8 gtk[WMI_MAX_KEY_LEN];
862 	size_t gtk_len;
863 	int bcast_ring;
864 	struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */
865 	int locally_generated_disc; /* relevant in STA mode */
866 	struct timer_list connect_timer;
867 	struct work_struct disconnect_worker;
868 	/* scan */
869 	struct cfg80211_scan_request *scan_request;
870 	struct timer_list scan_timer; /* detect scan timeout */
871 	struct wil_p2p_info p2p;
872 	/* keep alive */
873 	struct list_head probe_client_pending;
874 	struct mutex probe_client_mutex; /* protect @probe_client_pending */
875 	struct work_struct probe_client_worker;
876 	int net_queue_stopped; /* netif_tx_stop_all_queues invoked */
877 	bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */
878 	u64 fw_stats_tsf; /* measurement timestamp */
879 
880 	/* PTK rekey race prevention, this is relevant to station mode only */
881 	enum wil_rekey_state ptk_rekey_state;
882 	struct work_struct enable_tx_key_worker;
883 };
884 
885 /**
886  * RX buffer allocated for enhanced DMA RX descriptors
887  */
888 struct wil_rx_buff {
889 	struct sk_buff *skb;
890 	struct list_head list;
891 	int id;
892 };
893 
894 /**
895  * During Rx completion processing, the driver extracts a buffer ID which
896  * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB
897  * is given to the network stack and the buffer is moved from the 'active'
898  * list to the 'free' list.
899  * During Rx refill, SKBs are attached to free buffers and moved to the
900  * 'active' list.
901  */
902 struct wil_rx_buff_mgmt {
903 	struct wil_rx_buff *buff_arr;
904 	size_t size; /* number of items in buff_arr */
905 	struct list_head active;
906 	struct list_head free;
907 	unsigned long free_list_empty_cnt; /* statistics */
908 };
909 
910 struct wil_fw_stats_global {
911 	bool ready;
912 	u64 tsf; /* measurement timestamp */
913 	struct wmi_link_stats_global stats;
914 };
915 
916 struct wil_brd_info {
917 	u32 file_addr;
918 	u32 file_max_size;
919 };
920 
921 struct wil6210_priv {
922 	struct pci_dev *pdev;
923 	u32 bar_size;
924 	struct wiphy *wiphy;
925 	struct net_device *main_ndev;
926 	int n_msi;
927 	void __iomem *csr;
928 	DECLARE_BITMAP(status, wil_status_last);
929 	u8 fw_version[ETHTOOL_FWVERS_LEN];
930 	u32 hw_version;
931 	u8 chip_revision;
932 	const char *hw_name;
933 	const char *wil_fw_name;
934 	char *board_file;
935 	u32 num_of_brd_entries;
936 	struct wil_brd_info *brd_info;
937 	DECLARE_BITMAP(hw_capa, hw_capa_last);
938 	DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX);
939 	DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX);
940 	u32 recovery_count; /* num of FW recovery attempts in a short time */
941 	u32 recovery_state; /* FW recovery state machine */
942 	unsigned long last_fw_recovery; /* jiffies of last fw recovery */
943 	wait_queue_head_t wq; /* for all wait_event() use */
944 	u8 max_vifs; /* maximum number of interfaces, including main */
945 	struct wil6210_vif *vifs[WIL_MAX_VIFS];
946 	struct mutex vif_mutex; /* protects access to VIF entries */
947 	atomic_t connected_vifs;
948 	u32 max_assoc_sta; /* max sta's supported by the driver and the FW */
949 
950 	/* profile */
951 	struct cfg80211_chan_def monitor_chandef;
952 	u32 monitor_flags;
953 	int sinfo_gen;
954 	/* interrupt moderation */
955 	u32 tx_max_burst_duration;
956 	u32 tx_interframe_timeout;
957 	u32 rx_max_burst_duration;
958 	u32 rx_interframe_timeout;
959 	/* cached ISR registers */
960 	u32 isr_misc;
961 	/* mailbox related */
962 	struct mutex wmi_mutex;
963 	struct wil6210_mbox_ctl mbox_ctl;
964 	struct completion wmi_ready;
965 	struct completion wmi_call;
966 	u16 wmi_seq;
967 	u16 reply_id; /**< wait for this WMI event */
968 	u8 reply_mid;
969 	void *reply_buf;
970 	u16 reply_size;
971 	struct workqueue_struct *wmi_wq; /* for deferred calls */
972 	struct work_struct wmi_event_worker;
973 	struct workqueue_struct *wq_service;
974 	struct work_struct fw_error_worker;	/* for FW error recovery */
975 	struct list_head pending_wmi_ev;
976 	/*
977 	 * protect pending_wmi_ev
978 	 * - fill in IRQ from wil6210_irq_misc,
979 	 * - consumed in thread by wmi_event_worker
980 	 */
981 	spinlock_t wmi_ev_lock;
982 	spinlock_t net_queue_lock; /* guarding stop/wake netif queue */
983 	spinlock_t eap_lock; /* guarding access to eap rekey fields */
984 	struct napi_struct napi_rx;
985 	struct napi_struct napi_tx;
986 	struct net_device napi_ndev; /* dummy net_device serving all VIFs */
987 
988 	/* DMA related */
989 	struct wil_ring ring_rx;
990 	unsigned int rx_buf_len;
991 	struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS];
992 	struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS];
993 	struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS];
994 	u8 num_rx_status_rings;
995 	int tx_sring_idx;
996 	u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
997 	struct wil_sta_info sta[WIL6210_MAX_CID];
998 	u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once  */
999 	u32 dma_addr_size; /* indicates dma addr size */
1000 	struct wil_rx_buff_mgmt rx_buff_mgmt;
1001 	bool use_enhanced_dma_hw;
1002 	struct wil_txrx_ops txrx_ops;
1003 
1004 	struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
1005 	/* for synchronizing device memory access while reset or suspend */
1006 	struct rw_semaphore mem_lock;
1007 	/* statistics */
1008 	atomic_t isr_count_rx, isr_count_tx;
1009 	/* debugfs */
1010 	struct dentry *debug;
1011 	struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE];
1012 	u8 discovery_mode;
1013 	u8 abft_len;
1014 	u8 wakeup_trigger;
1015 	struct wil_suspend_stats suspend_stats;
1016 	struct wil_debugfs_data dbg_data;
1017 	bool tx_latency; /* collect TX latency measurements */
1018 	size_t tx_latency_res; /* bin resolution in usec */
1019 
1020 	void *platform_handle;
1021 	struct wil_platform_ops platform_ops;
1022 	bool keep_radio_on_during_sleep;
1023 
1024 	struct pmc_ctx pmc;
1025 
1026 	u8 p2p_dev_started;
1027 
1028 	/* P2P_DEVICE vif */
1029 	struct wireless_dev *p2p_wdev;
1030 	struct wireless_dev *radio_wdev;
1031 
1032 	/* High Access Latency Policy voting */
1033 	struct wil_halp halp;
1034 
1035 	enum wmi_ps_profile_type ps_profile;
1036 
1037 	int fw_calib_result;
1038 
1039 	struct notifier_block pm_notify;
1040 
1041 	bool suspend_resp_rcvd;
1042 	bool suspend_resp_comp;
1043 	u32 bus_request_kbps;
1044 	u32 bus_request_kbps_pre_suspend;
1045 
1046 	u32 rgf_fw_assert_code_addr;
1047 	u32 rgf_ucode_assert_code_addr;
1048 	u32 iccm_base;
1049 
1050 	/* relevant only for eDMA */
1051 	bool use_compressed_rx_status;
1052 	u32 rx_status_ring_order;
1053 	u32 tx_status_ring_order;
1054 	u32 rx_buff_id_count;
1055 	bool amsdu_en;
1056 	bool use_rx_hw_reordering;
1057 	bool secured_boot;
1058 	u8 boot_config;
1059 
1060 	struct wil_fw_stats_global fw_stats_global;
1061 
1062 	u32 max_agg_wsize;
1063 	u32 max_ampdu_size;
1064 	u8 multicast_to_unicast;
1065 	s32 cqm_rssi_thold;
1066 };
1067 
1068 #define wil_to_wiphy(i) (i->wiphy)
1069 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
1070 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
1071 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
1072 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
1073 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n))
1074 #define vif_to_wil(v) (v->wil)
1075 #define vif_to_ndev(v) (v->ndev)
1076 #define vif_to_wdev(v) (&v->wdev)
1077 #define GET_MAX_VIFS(wil) min_t(int, (wil)->max_vifs, WIL_MAX_VIFS)
1078 
1079 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil,
1080 					      struct wireless_dev *wdev)
1081 {
1082 	/* main interface is shared with P2P device */
1083 	if (wdev == wil->p2p_wdev)
1084 		return ndev_to_vif(wil->main_ndev);
1085 	else
1086 		return container_of(wdev, struct wil6210_vif, wdev);
1087 }
1088 
1089 static inline struct wireless_dev *
1090 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif)
1091 {
1092 	/* main interface is shared with P2P device */
1093 	if (vif->mid)
1094 		return vif_to_wdev(vif);
1095 	else
1096 		return wil->radio_wdev;
1097 }
1098 
1099 __printf(2, 3)
1100 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
1101 __printf(2, 3)
1102 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...);
1103 __printf(2, 3)
1104 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...);
1105 __printf(2, 3)
1106 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...);
1107 __printf(2, 3)
1108 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...);
1109 #define wil_dbg(wil, fmt, arg...) do { \
1110 	netdev_dbg(wil->main_ndev, fmt, ##arg); \
1111 	wil_dbg_trace(wil, fmt, ##arg); \
1112 } while (0)
1113 
1114 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
1115 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
1116 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
1117 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
1118 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg)
1119 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg)
1120 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg)
1121 #define wil_err_ratelimited(wil, fmt, arg...) \
1122 	__wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg)
1123 
1124 /* target operations */
1125 /* register read */
1126 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg)
1127 {
1128 	return readl(wil->csr + HOSTADDR(reg));
1129 }
1130 
1131 /* register write. wmb() to make sure it is completed */
1132 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val)
1133 {
1134 	writel(val, wil->csr + HOSTADDR(reg));
1135 	wmb(); /* wait for write to propagate to the HW */
1136 }
1137 
1138 /* register set = read, OR, write */
1139 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val)
1140 {
1141 	wil_w(wil, reg, wil_r(wil, reg) | val);
1142 }
1143 
1144 /* register clear = read, AND with inverted, write */
1145 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val)
1146 {
1147 	wil_w(wil, reg, wil_r(wil, reg) & ~val);
1148 }
1149 
1150 /**
1151  * wil_cid_valid - check cid is valid
1152  */
1153 static inline bool wil_cid_valid(struct wil6210_priv *wil, int cid)
1154 {
1155 	return (cid >= 0 && cid < wil->max_assoc_sta && cid < WIL6210_MAX_CID);
1156 }
1157 
1158 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len);
1159 
1160 #if defined(CONFIG_DYNAMIC_DEBUG)
1161 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize,	\
1162 			  groupsize, buf, len, ascii)		\
1163 			  print_hex_dump_debug("DBG[TXRX]" prefix_str,\
1164 					 prefix_type, rowsize,	\
1165 					 groupsize, buf, len, ascii)
1166 
1167 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize,	\
1168 			 groupsize, buf, len, ascii)		\
1169 			 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
1170 					prefix_type, rowsize,	\
1171 					groupsize, buf, len, ascii)
1172 
1173 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize,	\
1174 			  groupsize, buf, len, ascii)		\
1175 			  print_hex_dump_debug("DBG[MISC]" prefix_str,\
1176 					prefix_type, rowsize,	\
1177 					groupsize, buf, len, ascii)
1178 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
1179 static inline
1180 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize,
1181 		       int groupsize, const void *buf, size_t len, bool ascii)
1182 {
1183 }
1184 
1185 static inline
1186 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize,
1187 		      int groupsize, const void *buf, size_t len, bool ascii)
1188 {
1189 }
1190 
1191 static inline
1192 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize,
1193 		       int groupsize, const void *buf, size_t len, bool ascii)
1194 {
1195 }
1196 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
1197 
1198 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
1199 			  size_t count);
1200 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
1201 			size_t count);
1202 int wil_mem_access_lock(struct wil6210_priv *wil);
1203 void wil_mem_access_unlock(struct wil6210_priv *wil);
1204 
1205 struct wil6210_vif *
1206 wil_vif_alloc(struct wil6210_priv *wil, const char *name,
1207 	      unsigned char name_assign_type, enum nl80211_iftype iftype);
1208 void wil_vif_free(struct wil6210_vif *vif);
1209 void *wil_if_alloc(struct device *dev);
1210 bool wil_has_other_active_ifaces(struct wil6210_priv *wil,
1211 				 struct net_device *ndev, bool up, bool ok);
1212 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok);
1213 void wil_if_free(struct wil6210_priv *wil);
1214 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif);
1215 int wil_if_add(struct wil6210_priv *wil);
1216 void wil_vif_remove(struct wil6210_priv *wil, u8 mid);
1217 void wil_if_remove(struct wil6210_priv *wil);
1218 int wil_priv_init(struct wil6210_priv *wil);
1219 void wil_priv_deinit(struct wil6210_priv *wil);
1220 int wil_ps_update(struct wil6210_priv *wil,
1221 		  enum wmi_ps_profile_type ps_profile);
1222 int wil_reset(struct wil6210_priv *wil, bool no_fw);
1223 void wil_fw_error_recovery(struct wil6210_priv *wil);
1224 void wil_set_recovery_state(struct wil6210_priv *wil, int state);
1225 bool wil_is_recovery_blocked(struct wil6210_priv *wil);
1226 int wil_up(struct wil6210_priv *wil);
1227 int __wil_up(struct wil6210_priv *wil);
1228 int wil_down(struct wil6210_priv *wil);
1229 int __wil_down(struct wil6210_priv *wil);
1230 void wil_refresh_fw_capabilities(struct wil6210_priv *wil);
1231 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
1232 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac);
1233 int wil_find_cid_by_idx(struct wil6210_priv *wil, u8 mid, int idx);
1234 void wil_set_ethtoolops(struct net_device *ndev);
1235 
1236 struct fw_map *wil_find_fw_mapping(const char *section);
1237 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size);
1238 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
1239 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
1240 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
1241 		 struct wil6210_mbox_hdr *hdr);
1242 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len);
1243 void wmi_recv_cmd(struct wil6210_priv *wil);
1244 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len,
1245 	     u16 reply_id, void *reply, u16 reply_size, int to_msec);
1246 void wmi_event_worker(struct work_struct *work);
1247 void wmi_event_flush(struct wil6210_priv *wil);
1248 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid);
1249 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid);
1250 int wmi_set_channel(struct wil6210_priv *wil, int channel);
1251 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
1252 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index,
1253 		       const void *mac_addr, int key_usage);
1254 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index,
1255 		       const void *mac_addr, int key_len, const void *key,
1256 		       int key_usage);
1257 int wmi_echo(struct wil6210_priv *wil);
1258 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie);
1259 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring);
1260 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie);
1261 int wmi_rxon(struct wil6210_priv *wil, bool on);
1262 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
1263 int wmi_get_all_temperatures(struct wil6210_priv *wil,
1264 			     struct wmi_temp_sense_all_done_event
1265 			     *sense_all_evt);
1266 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason,
1267 		       bool del_sta);
1268 int wmi_addba(struct wil6210_priv *wil, u8 mid,
1269 	      u8 ringid, u8 size, u16 timeout);
1270 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason);
1271 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason);
1272 int wmi_addba_rx_resp(struct wil6210_priv *wil,
1273 		      u8 mid, u8 cid, u8 tid, u8 token,
1274 		      u16 status, bool amsdu, u16 agg_wsize, u16 timeout);
1275 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil,
1276 			   enum wmi_ps_profile_type ps_profile);
1277 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short);
1278 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short);
1279 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid);
1280 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid,
1281 		      const u8 *mac, enum nl80211_iftype iftype);
1282 int wmi_port_delete(struct wil6210_priv *wil, u8 mid);
1283 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval);
1284 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid,
1285 			 u8 dialog_token, __le16 ba_param_set,
1286 			 __le16 ba_timeout, __le16 ba_seq_ctrl);
1287 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize);
1288 
1289 void wil6210_clear_irq(struct wil6210_priv *wil);
1290 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
1291 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
1292 void wil_mask_irq(struct wil6210_priv *wil);
1293 void wil_unmask_irq(struct wil6210_priv *wil);
1294 void wil_configure_interrupt_moderation(struct wil6210_priv *wil);
1295 void wil_disable_irq(struct wil6210_priv *wil);
1296 void wil_enable_irq(struct wil6210_priv *wil);
1297 void wil6210_mask_halp(struct wil6210_priv *wil);
1298 
1299 /* P2P */
1300 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request);
1301 int wil_p2p_search(struct wil6210_vif *vif,
1302 		   struct cfg80211_scan_request *request);
1303 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev,
1304 		   unsigned int duration, struct ieee80211_channel *chan,
1305 		   u64 *cookie);
1306 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif);
1307 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie);
1308 void wil_p2p_listen_expired(struct work_struct *work);
1309 void wil_p2p_search_expired(struct work_struct *work);
1310 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil);
1311 void wil_p2p_delayed_listen_work(struct work_struct *work);
1312 
1313 /* WMI for P2P */
1314 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi);
1315 int wmi_start_listen(struct wil6210_vif *vif);
1316 int wmi_start_search(struct wil6210_vif *vif);
1317 int wmi_stop_discovery(struct wil6210_vif *vif);
1318 
1319 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
1320 			 struct cfg80211_mgmt_tx_params *params,
1321 			 u64 *cookie);
1322 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil);
1323 int wil_cfg80211_iface_combinations_from_fw(
1324 	struct wil6210_priv *wil,
1325 	const struct wil_fw_record_concurrency *conc);
1326 int wil_vif_prepare_stop(struct wil6210_vif *vif);
1327 
1328 #if defined(CONFIG_WIL6210_DEBUGFS)
1329 int wil6210_debugfs_init(struct wil6210_priv *wil);
1330 void wil6210_debugfs_remove(struct wil6210_priv *wil);
1331 #else
1332 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; }
1333 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {}
1334 #endif
1335 
1336 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid,
1337 		       struct station_info *sinfo);
1338 
1339 struct wil6210_priv *wil_cfg80211_init(struct device *dev);
1340 void wil_cfg80211_deinit(struct wil6210_priv *wil);
1341 void wil_p2p_wdev_free(struct wil6210_priv *wil);
1342 
1343 int wmi_set_mac_address(struct wil6210_priv *wil, const void *addr);
1344 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan,
1345 		  u8 edmg_chan, u8 hidden_ssid, u8 is_go);
1346 int wmi_pcp_stop(struct wil6210_vif *vif);
1347 int wmi_led_cfg(struct wil6210_priv *wil, bool enable);
1348 int wmi_abort_scan(struct wil6210_vif *vif);
1349 void wil_abort_scan(struct wil6210_vif *vif, bool sync);
1350 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync);
1351 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps);
1352 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid,
1353 			u16 reason_code);
1354 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid,
1355 				 u16 reason_code);
1356 void wil_probe_client_flush(struct wil6210_vif *vif);
1357 void wil_probe_client_worker(struct work_struct *work);
1358 void wil_disconnect_worker(struct work_struct *work);
1359 void wil_enable_tx_key_worker(struct work_struct *work);
1360 
1361 void wil_init_txrx_ops(struct wil6210_priv *wil);
1362 
1363 /* TX API */
1364 int wil_ring_init_tx(struct wil6210_vif *vif, int cid);
1365 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size);
1366 int wil_bcast_init(struct wil6210_vif *vif);
1367 void wil_bcast_fini(struct wil6210_vif *vif);
1368 void wil_bcast_fini_all(struct wil6210_priv *wil);
1369 
1370 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif,
1371 			   struct wil_ring *ring, bool should_stop);
1372 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif,
1373 			      struct wil_ring *ring, bool check_stop);
1374 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
1375 int wil_tx_complete(struct wil6210_vif *vif, int ringid);
1376 void wil_tx_complete_handle_eapol(struct wil6210_vif *vif,
1377 				  struct sk_buff *skb);
1378 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
1379 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil);
1380 
1381 /* RX API */
1382 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
1383 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
1384 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil);
1385 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage,
1386 		       struct wil_sta_info *cs,
1387 		       struct key_params *params);
1388 
1389 int wil_iftype_nl2wmi(enum nl80211_iftype type);
1390 
1391 int wil_request_firmware(struct wil6210_priv *wil, const char *name,
1392 			 bool load);
1393 int wil_request_board(struct wil6210_priv *wil, const char *name);
1394 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name);
1395 
1396 void wil_pm_runtime_allow(struct wil6210_priv *wil);
1397 void wil_pm_runtime_forbid(struct wil6210_priv *wil);
1398 int wil_pm_runtime_get(struct wil6210_priv *wil);
1399 void wil_pm_runtime_put(struct wil6210_priv *wil);
1400 
1401 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime);
1402 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on);
1403 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on);
1404 bool wil_is_wmi_idle(struct wil6210_priv *wil);
1405 int wmi_resume(struct wil6210_priv *wil);
1406 int wmi_suspend(struct wil6210_priv *wil);
1407 bool wil_is_tx_idle(struct wil6210_priv *wil);
1408 
1409 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size);
1410 void wil_fw_core_dump(struct wil6210_priv *wil);
1411 
1412 void wil_halp_vote(struct wil6210_priv *wil);
1413 void wil_halp_unvote(struct wil6210_priv *wil);
1414 void wil6210_set_halp(struct wil6210_priv *wil);
1415 void wil6210_clear_halp(struct wil6210_priv *wil);
1416 
1417 int wmi_start_sched_scan(struct wil6210_priv *wil,
1418 			 struct cfg80211_sched_scan_request *request);
1419 int wmi_stop_sched_scan(struct wil6210_priv *wil);
1420 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len);
1421 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len,
1422 		    u8 channel, u16 duration_ms);
1423 int wmi_rbufcap_cfg(struct wil6210_priv *wil, bool enable, u16 threshold);
1424 
1425 int wil_wmi2spec_ch(u8 wmi_ch, u8 *spec_ch);
1426 int wil_spec2wmi_ch(u8 spec_ch, u8 *wmi_ch);
1427 void wil_update_supported_bands(struct wil6210_priv *wil);
1428 
1429 int reverse_memcmp(const void *cs, const void *ct, size_t count);
1430 
1431 /* WMI for enhanced DMA */
1432 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id);
1433 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil,
1434 			       u16 max_rx_pl_per_desc);
1435 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id);
1436 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id);
1437 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid,
1438 			     int tid);
1439 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id);
1440 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid,
1441 			   u8 tid, u8 token, u16 status, bool amsdu,
1442 			   u16 agg_wsize, u16 timeout);
1443 
1444 void update_supported_bands(struct wil6210_priv *wil);
1445 
1446 void wil_clear_fw_log_addr(struct wil6210_priv *wil);
1447 int wmi_set_cqm_rssi_config(struct wil6210_priv *wil,
1448 			    s32 rssi_thold, u32 rssi_hyst);
1449 #endif /* __WIL6210_H__ */
1450