1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 extern bool ftm_mode; 41 42 struct wil6210_priv; 43 struct wil6210_vif; 44 union wil_tx_desc; 45 46 #define WIL_NAME "wil6210" 47 48 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 49 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 50 51 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 52 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 53 54 #define WIL_FW_NAME_TALYN "wil6436.fw" 55 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 56 #define WIL_BRD_NAME_TALYN "wil6436.brd" 57 58 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 59 60 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 61 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 62 63 #define WIL_NUM_LATENCY_BINS 200 64 65 /* maximum number of virtual interfaces the driver supports 66 * (including the main interface) 67 */ 68 #define WIL_MAX_VIFS 4 69 70 /** 71 * extract bits [@b0:@b1] (inclusive) from the value @x 72 * it should be @b0 <= @b1, or result is incorrect 73 */ 74 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 75 { 76 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 77 } 78 79 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 80 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 81 82 #define WIL_TX_Q_LEN_DEFAULT (4000) 83 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 84 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 85 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 86 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 87 /* limit ring size in range [32..32k] */ 88 #define WIL_RING_SIZE_ORDER_MIN (5) 89 #define WIL_RING_SIZE_ORDER_MAX (15) 90 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 91 #define WIL6210_MAX_CID (8) /* HW limit */ 92 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 93 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 94 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 95 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 96 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 97 #define WIL6210_MAX_STATUS_RINGS (8) 98 99 /* Hardware offload block adds the following: 100 * 26 bytes - 3-address QoS data header 101 * 8 bytes - IV + EIV (for GCMP) 102 * 8 bytes - SNAP 103 * 16 bytes - MIC (for GCMP) 104 * 4 bytes - CRC 105 */ 106 #define WIL_MAX_MPDU_OVERHEAD (62) 107 108 struct wil_suspend_count_stats { 109 unsigned long successful_suspends; 110 unsigned long successful_resumes; 111 unsigned long failed_suspends; 112 unsigned long failed_resumes; 113 }; 114 115 struct wil_suspend_stats { 116 struct wil_suspend_count_stats r_off; 117 struct wil_suspend_count_stats r_on; 118 unsigned long rejected_by_device; /* only radio on */ 119 unsigned long rejected_by_host; 120 }; 121 122 /* Calculate MAC buffer size for the firmware. It includes all overhead, 123 * as it will go over the air, and need to be 8 byte aligned 124 */ 125 static inline u32 wil_mtu2macbuf(u32 mtu) 126 { 127 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 128 } 129 130 /* MTU for Ethernet need to take into account 8-byte SNAP header 131 * to be added when encapsulating Ethernet frame into 802.11 132 */ 133 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 134 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 135 #define WIL6210_ITR_TRSH_MAX (5000000) 136 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 137 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 138 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 139 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 140 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 141 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 142 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 143 #define WIL6210_DISCONNECT_TO_MS (2000) 144 #define WIL6210_RX_HIGH_TRSH_INIT (0) 145 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 146 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 147 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 148 * 802.11REVmc/D5.0, section 9.4.1.8) 149 */ 150 /* Hardware definitions begin */ 151 152 /* 153 * Mapping 154 * RGF File | Host addr | FW addr 155 * | | 156 * user_rgf | 0x000000 | 0x880000 157 * dma_rgf | 0x001000 | 0x881000 158 * pcie_rgf | 0x002000 | 0x882000 159 * | | 160 */ 161 162 /* Where various structures placed in host address space */ 163 #define WIL6210_FW_HOST_OFF (0x880000UL) 164 165 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 166 167 /* 168 * Interrupt control registers block 169 * 170 * each interrupt controlled by the same bit in all registers 171 */ 172 struct RGF_ICR { 173 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 174 u32 ICR; /* Cause, W1C/COR depending on ICC */ 175 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 176 u32 ICS; /* Cause Set, WO */ 177 u32 IMV; /* Mask, RW+S/C */ 178 u32 IMS; /* Mask Set, write 1 to set */ 179 u32 IMC; /* Mask Clear, write 1 to clear */ 180 } __packed; 181 182 /* registers - FW addresses */ 183 #define RGF_USER_USAGE_1 (0x880004) 184 #define RGF_USER_USAGE_6 (0x880018) 185 #define BIT_USER_OOB_MODE BIT(31) 186 #define BIT_USER_OOB_R2_MODE BIT(30) 187 #define RGF_USER_USAGE_8 (0x880020) 188 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 189 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 190 #define BIT_USER_EXT_CLK BIT(2) 191 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 192 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 193 #define RGF_USER_USER_CPU_0 (0x8801e0) 194 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 195 #define RGF_USER_CPU_PC (0x8801e8) 196 #define RGF_USER_MAC_CPU_0 (0x8801fc) 197 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 198 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 199 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 200 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 201 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 202 * b8-15:signature 203 */ 204 #define CALIB_RESULT_SIGNATURE (0x11) 205 #define RGF_USER_CLKS_CTL_0 (0x880abc) 206 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 207 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 208 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 209 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 210 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 211 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 212 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 213 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 214 #define BIT_CAR_PERST_RST BIT(7) 215 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 216 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 217 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 218 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 219 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 220 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 221 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 222 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 223 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 224 #define BIT_NO_FLASH_INDICATION BIT(8) 225 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 226 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 227 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 228 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 229 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 230 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 231 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 232 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 233 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 234 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 235 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 236 237 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 238 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 239 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 240 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 241 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 242 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 243 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 244 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 245 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 246 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 247 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 248 249 /* Legacy interrupt moderation control (before Sparrow v2)*/ 250 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 251 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 252 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 253 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 254 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 255 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 256 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 257 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 258 259 /* Offload control (Sparrow B0+) */ 260 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 261 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 262 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 263 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 264 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 265 266 /* New (sparrow v2+) interrupt moderation control */ 267 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 268 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 269 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 270 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 271 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 272 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 273 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 274 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 275 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 276 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 277 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 278 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 279 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 280 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 281 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 282 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 283 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 284 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 285 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 286 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 287 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 288 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 289 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 290 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 291 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 292 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 293 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 294 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 295 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 296 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 297 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 298 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 299 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 300 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 301 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 302 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 303 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 304 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 305 #define RGF_DMA_MISC_CTL (0x881d6c) 306 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 307 308 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 309 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 310 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 311 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 312 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 313 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 314 315 #define RGF_HP_CTRL (0x88265c) 316 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 317 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 318 319 /* MAC timer, usec, for packet lifetime */ 320 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 321 322 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 323 #define RGF_CAF_OSC_CONTROL (0x88afa4) 324 #define BIT_CAF_OSC_XTAL_EN BIT(0) 325 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 326 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 327 328 #define RGF_OTP_QC_SECURED (0x8a0038) 329 #define BIT_BOOT_FROM_ROM BIT(31) 330 331 /* eDMA */ 332 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 333 334 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 335 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 336 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 337 338 #define RGF_INT_GEN_CTRL (0x8bc0ec) 339 #define BIT_CONTROL_0 BIT(0) 340 341 /* eDMA status interrupts */ 342 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 343 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 344 #define RGF_INT_GEN_TX_ICR (0x8bc110) 345 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 346 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 347 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 348 349 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 350 351 #define USER_EXT_USER_PMU_3 (0x88d00c) 352 #define BIT_PMU_DEVICE_RDY BIT(0) 353 354 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 355 #define JTAG_DEV_ID_SPARROW (0x2632072f) 356 #define JTAG_DEV_ID_TALYN (0x7e0e1) 357 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 358 359 #define RGF_USER_REVISION_ID (0x88afe4) 360 #define RGF_USER_REVISION_ID_MASK (3) 361 #define REVISION_ID_SPARROW_B0 (0x0) 362 #define REVISION_ID_SPARROW_D0 (0x3) 363 364 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 365 #define RGF_OTP_MAC (0x8a0620) 366 367 /* Talyn-MB */ 368 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 369 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 370 371 /* crash codes for FW/Ucode stored here */ 372 373 /* ASSERT RGFs */ 374 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 375 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 376 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 377 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 378 379 enum { 380 HW_VER_UNKNOWN, 381 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 382 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 383 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 384 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 385 }; 386 387 /* popular locations */ 388 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 389 #define HOST_MBOX HOSTADDR(RGF_MBOX) 390 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 391 392 /* ISR register bits */ 393 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 394 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 395 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 396 397 #define WIL_DATA_COMPLETION_TO_MS 200 398 399 /* Hardware definitions end */ 400 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 401 #define TALYN_FW_MAPPING_TABLE_SIZE 13 402 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 403 #define MAX_FW_MAPPING_TABLE_SIZE 19 404 405 /* Common representation of physical address in wil ring */ 406 struct wil_ring_dma_addr { 407 __le32 addr_low; 408 __le16 addr_high; 409 } __packed; 410 411 struct fw_map { 412 u32 from; /* linker address - from, inclusive */ 413 u32 to; /* linker address - to, exclusive */ 414 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 415 const char *name; /* for debugfs */ 416 bool fw; /* true if FW mapping, false if UCODE mapping */ 417 bool crash_dump; /* true if should be dumped during crash dump */ 418 }; 419 420 /* array size should be in sync with actual definition in the wmi.c */ 421 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 422 extern const struct fw_map sparrow_d0_mac_rgf_ext; 423 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 424 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 425 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 426 427 /** 428 * mk_cidxtid - construct @cidxtid field 429 * @cid: CID value 430 * @tid: TID value 431 * 432 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 433 */ 434 static inline u8 mk_cidxtid(u8 cid, u8 tid) 435 { 436 return ((tid & 0xf) << 4) | (cid & 0xf); 437 } 438 439 /** 440 * parse_cidxtid - parse @cidxtid field 441 * @cid: store CID value here 442 * @tid: store TID value here 443 * 444 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 445 */ 446 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 447 { 448 *cid = cidxtid & 0xf; 449 *tid = (cidxtid >> 4) & 0xf; 450 } 451 452 struct wil6210_mbox_ring { 453 u32 base; 454 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 455 u16 size; 456 u32 tail; 457 u32 head; 458 } __packed; 459 460 struct wil6210_mbox_ring_desc { 461 __le32 sync; 462 __le32 addr; 463 } __packed; 464 465 /* at HOST_OFF_WIL6210_MBOX_CTL */ 466 struct wil6210_mbox_ctl { 467 struct wil6210_mbox_ring tx; 468 struct wil6210_mbox_ring rx; 469 } __packed; 470 471 struct wil6210_mbox_hdr { 472 __le16 seq; 473 __le16 len; /* payload, bytes after this header */ 474 __le16 type; 475 u8 flags; 476 u8 reserved; 477 } __packed; 478 479 #define WIL_MBOX_HDR_TYPE_WMI (0) 480 481 /* max. value for wil6210_mbox_hdr.len */ 482 #define MAX_MBOXITEM_SIZE (240) 483 484 struct pending_wmi_event { 485 struct list_head list; 486 struct { 487 struct wil6210_mbox_hdr hdr; 488 struct wmi_cmd_hdr wmi; 489 u8 data[0]; 490 } __packed event; 491 }; 492 493 enum { /* for wil_ctx.mapped_as */ 494 wil_mapped_as_none = 0, 495 wil_mapped_as_single = 1, 496 wil_mapped_as_page = 2, 497 }; 498 499 /** 500 * struct wil_ctx - software context for ring descriptor 501 */ 502 struct wil_ctx { 503 struct sk_buff *skb; 504 u8 nr_frags; 505 u8 mapped_as; 506 }; 507 508 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 509 u32 *va; 510 dma_addr_t pa; 511 }; 512 513 /** 514 * A general ring structure, used for RX and TX. 515 * In legacy DMA it represents the vring, 516 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 517 */ 518 struct wil_ring { 519 dma_addr_t pa; 520 volatile union wil_ring_desc *va; 521 u16 size; /* number of wil_ring_desc elements */ 522 u32 swtail; 523 u32 swhead; 524 u32 hwtail; /* write here to inform hw */ 525 struct wil_ctx *ctx; /* ctx[size] - software context */ 526 struct wil_desc_ring_rx_swtail edma_rx_swtail; 527 bool is_rx; 528 }; 529 530 /** 531 * Additional data for Rx ring. 532 * Used for enhanced DMA RX chaining. 533 */ 534 struct wil_ring_rx_data { 535 /* the skb being assembled */ 536 struct sk_buff *skb; 537 /* true if we are skipping a bad fragmented packet */ 538 bool skipping; 539 u16 buff_size; 540 }; 541 542 /** 543 * Status ring structure, used for enhanced DMA completions for RX and TX. 544 */ 545 struct wil_status_ring { 546 dma_addr_t pa; 547 void *va; /* pointer to ring_[tr]x_status elements */ 548 u16 size; /* number of status elements */ 549 size_t elem_size; /* status element size in bytes */ 550 u32 swhead; 551 u32 hwtail; /* write here to inform hw */ 552 bool is_rx; 553 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 554 struct wil_ring_rx_data rx_data; 555 }; 556 557 #define WIL_STA_TID_NUM (16) 558 #define WIL_MCS_MAX (12) /* Maximum MCS supported */ 559 560 struct wil_net_stats { 561 unsigned long rx_packets; 562 unsigned long tx_packets; 563 unsigned long rx_bytes; 564 unsigned long tx_bytes; 565 unsigned long tx_errors; 566 u32 tx_latency_min_us; 567 u32 tx_latency_max_us; 568 u64 tx_latency_total_us; 569 unsigned long rx_dropped; 570 unsigned long rx_non_data_frame; 571 unsigned long rx_short_frame; 572 unsigned long rx_large_frame; 573 unsigned long rx_replay; 574 unsigned long rx_mic_error; 575 unsigned long rx_key_error; /* eDMA specific */ 576 unsigned long rx_amsdu_error; /* eDMA specific */ 577 unsigned long rx_csum_err; 578 u16 last_mcs_rx; 579 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 580 }; 581 582 /** 583 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 584 * DMA flow 585 */ 586 struct wil_txrx_ops { 587 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 588 /* TX ops */ 589 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 590 int size, int cid, int tid); 591 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 592 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 593 int (*tx_init)(struct wil6210_priv *wil); 594 void (*tx_fini)(struct wil6210_priv *wil); 595 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 596 u32 len, int ring_index); 597 void (*tx_desc_unmap)(struct device *dev, 598 union wil_tx_desc *desc, 599 struct wil_ctx *ctx); 600 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 601 struct wil_ring *ring, struct sk_buff *skb); 602 irqreturn_t (*irq_tx)(int irq, void *cookie); 603 /* RX ops */ 604 int (*rx_init)(struct wil6210_priv *wil, u16 ring_size); 605 void (*rx_fini)(struct wil6210_priv *wil); 606 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 607 u8 tid, u8 token, u16 status, bool amsdu, 608 u16 agg_wsize, u16 timeout); 609 void (*get_reorder_params)(struct wil6210_priv *wil, 610 struct sk_buff *skb, int *tid, int *cid, 611 int *mid, u16 *seq, int *mcast, int *retry); 612 void (*get_netif_rx_params)(struct sk_buff *skb, 613 int *cid, int *security); 614 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 615 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 616 struct wil_net_stats *stats); 617 bool (*is_rx_idle)(struct wil6210_priv *wil); 618 irqreturn_t (*irq_rx)(int irq, void *cookie); 619 }; 620 621 /** 622 * Additional data for Tx ring 623 */ 624 struct wil_ring_tx_data { 625 bool dot1x_open; 626 int enabled; 627 cycles_t idle, last_idle, begin; 628 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 629 u16 agg_timeout; 630 u8 agg_amsdu; 631 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 632 u8 mid; 633 spinlock_t lock; 634 }; 635 636 enum { /* for wil6210_priv.status */ 637 wil_status_fwready = 0, /* FW operational */ 638 wil_status_dontscan, 639 wil_status_mbox_ready, /* MBOX structures ready */ 640 wil_status_irqen, /* interrupts enabled - for debug */ 641 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 642 wil_status_resetting, /* reset in progress */ 643 wil_status_suspending, /* suspend in progress */ 644 wil_status_suspended, /* suspend completed, device is suspended */ 645 wil_status_resuming, /* resume in progress */ 646 wil_status_collecting_dumps, /* crashdump collection in progress */ 647 wil_status_last /* keep last */ 648 }; 649 650 struct pci_dev; 651 652 /** 653 * struct tid_ampdu_rx - TID aggregation information (Rx). 654 * 655 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 656 * @last_rx: jiffies of last rx activity 657 * @head_seq_num: head sequence number in reordering buffer. 658 * @stored_mpdu_num: number of MPDUs in reordering buffer 659 * @ssn: Starting Sequence Number expected to be aggregated. 660 * @buf_size: buffer size for incoming A-MPDUs 661 * @ssn_last_drop: SSN of the last dropped frame 662 * @total: total number of processed incoming frames 663 * @drop_dup: duplicate frames dropped for this reorder buffer 664 * @drop_old: old frames dropped for this reorder buffer 665 * @first_time: true when this buffer used 1-st time 666 * @mcast_last_seq: sequence number (SN) of last received multicast packet 667 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 668 */ 669 struct wil_tid_ampdu_rx { 670 struct sk_buff **reorder_buf; 671 unsigned long last_rx; 672 u16 head_seq_num; 673 u16 stored_mpdu_num; 674 u16 ssn; 675 u16 buf_size; 676 u16 ssn_last_drop; 677 unsigned long long total; /* frames processed */ 678 unsigned long long drop_dup; 679 unsigned long long drop_old; 680 bool first_time; /* is it 1-st time this buffer used? */ 681 u16 mcast_last_seq; /* multicast dup detection */ 682 unsigned long long drop_dup_mcast; 683 }; 684 685 /** 686 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 687 * 688 * @pn: GCMP PN for the session 689 * @key_set: valid key present 690 */ 691 struct wil_tid_crypto_rx_single { 692 u8 pn[IEEE80211_GCMP_PN_LEN]; 693 bool key_set; 694 }; 695 696 struct wil_tid_crypto_rx { 697 struct wil_tid_crypto_rx_single key_id[4]; 698 }; 699 700 struct wil_p2p_info { 701 struct ieee80211_channel listen_chan; 702 u8 discovery_started; 703 u64 cookie; 704 struct wireless_dev *pending_listen_wdev; 705 unsigned int listen_duration; 706 struct timer_list discovery_timer; /* listen/search duration */ 707 struct work_struct discovery_expired_work; /* listen/search expire */ 708 struct work_struct delayed_listen_work; /* listen after scan done */ 709 }; 710 711 enum wil_sta_status { 712 wil_sta_unused = 0, 713 wil_sta_conn_pending = 1, 714 wil_sta_connected = 2, 715 }; 716 717 /** 718 * struct wil_sta_info - data for peer 719 * 720 * Peer identified by its CID (connection ID) 721 * NIC performs beam forming for each peer; 722 * if no beam forming done, frame exchange is not 723 * possible. 724 */ 725 struct wil_sta_info { 726 u8 addr[ETH_ALEN]; 727 u8 mid; 728 enum wil_sta_status status; 729 struct wil_net_stats stats; 730 /** 731 * 20 latency bins. 1st bin counts packets with latency 732 * of 0..tx_latency_res, last bin counts packets with latency 733 * of 19*tx_latency_res and above. 734 * tx_latency_res is configured from "tx_latency" debug-fs. 735 */ 736 u64 *tx_latency_bins; 737 struct wmi_link_stats_basic fw_stats_basic; 738 /* Rx BACK */ 739 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 740 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 741 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 742 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 743 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 744 struct wil_tid_crypto_rx group_crypto_rx; 745 u8 aid; /* 1-254; 0 if unknown/not reported */ 746 }; 747 748 enum { 749 fw_recovery_idle = 0, 750 fw_recovery_pending = 1, 751 fw_recovery_running = 2, 752 }; 753 754 enum { 755 hw_capa_no_flash, 756 hw_capa_last 757 }; 758 759 struct wil_probe_client_req { 760 struct list_head list; 761 u64 cookie; 762 u8 cid; 763 }; 764 765 struct pmc_ctx { 766 /* alloc, free, and read operations must own the lock */ 767 struct mutex lock; 768 struct vring_tx_desc *pring_va; 769 dma_addr_t pring_pa; 770 struct desc_alloc_info *descriptors; 771 int last_cmd_status; 772 int num_descriptors; 773 int descriptor_size; 774 }; 775 776 struct wil_halp { 777 struct mutex lock; /* protect halp ref_cnt */ 778 unsigned int ref_cnt; 779 struct completion comp; 780 }; 781 782 struct wil_blob_wrapper { 783 struct wil6210_priv *wil; 784 struct debugfs_blob_wrapper blob; 785 }; 786 787 #define WIL_LED_MAX_ID (2) 788 #define WIL_LED_INVALID_ID (0xF) 789 #define WIL_LED_BLINK_ON_SLOW_MS (300) 790 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 791 #define WIL_LED_BLINK_ON_MED_MS (200) 792 #define WIL_LED_BLINK_OFF_MED_MS (200) 793 #define WIL_LED_BLINK_ON_FAST_MS (100) 794 #define WIL_LED_BLINK_OFF_FAST_MS (100) 795 enum { 796 WIL_LED_TIME_SLOW = 0, 797 WIL_LED_TIME_MED, 798 WIL_LED_TIME_FAST, 799 WIL_LED_TIME_LAST, 800 }; 801 802 struct blink_on_off_time { 803 u32 on_ms; 804 u32 off_ms; 805 }; 806 807 struct wil_debugfs_iomem_data { 808 void *offset; 809 struct wil6210_priv *wil; 810 }; 811 812 struct wil_debugfs_data { 813 struct wil_debugfs_iomem_data *data_arr; 814 int iomem_data_count; 815 }; 816 817 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 818 extern u8 led_id; 819 extern u8 led_polarity; 820 821 enum wil6210_vif_status { 822 wil_vif_fwconnecting, 823 wil_vif_fwconnected, 824 wil_vif_status_last /* keep last */ 825 }; 826 827 struct wil6210_vif { 828 struct wireless_dev wdev; 829 struct net_device *ndev; 830 struct wil6210_priv *wil; 831 u8 mid; 832 DECLARE_BITMAP(status, wil_vif_status_last); 833 u32 privacy; /* secure connection? */ 834 u16 channel; /* relevant in AP mode */ 835 u8 hidden_ssid; /* relevant in AP mode */ 836 u32 ap_isolate; /* no intra-BSS communication */ 837 bool pbss; 838 int bcast_ring; 839 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 840 int locally_generated_disc; /* relevant in STA mode */ 841 struct timer_list connect_timer; 842 struct work_struct disconnect_worker; 843 /* scan */ 844 struct cfg80211_scan_request *scan_request; 845 struct timer_list scan_timer; /* detect scan timeout */ 846 struct wil_p2p_info p2p; 847 /* keep alive */ 848 struct list_head probe_client_pending; 849 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 850 struct work_struct probe_client_worker; 851 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 852 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 853 u64 fw_stats_tsf; /* measurement timestamp */ 854 }; 855 856 /** 857 * RX buffer allocated for enhanced DMA RX descriptors 858 */ 859 struct wil_rx_buff { 860 struct sk_buff *skb; 861 struct list_head list; 862 int id; 863 }; 864 865 /** 866 * During Rx completion processing, the driver extracts a buffer ID which 867 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 868 * is given to the network stack and the buffer is moved from the 'active' 869 * list to the 'free' list. 870 * During Rx refill, SKBs are attached to free buffers and moved to the 871 * 'active' list. 872 */ 873 struct wil_rx_buff_mgmt { 874 struct wil_rx_buff *buff_arr; 875 size_t size; /* number of items in buff_arr */ 876 struct list_head active; 877 struct list_head free; 878 unsigned long free_list_empty_cnt; /* statistics */ 879 }; 880 881 struct wil_fw_stats_global { 882 bool ready; 883 u64 tsf; /* measurement timestamp */ 884 struct wmi_link_stats_global stats; 885 }; 886 887 struct wil6210_priv { 888 struct pci_dev *pdev; 889 u32 bar_size; 890 struct wiphy *wiphy; 891 struct net_device *main_ndev; 892 int n_msi; 893 void __iomem *csr; 894 DECLARE_BITMAP(status, wil_status_last); 895 u8 fw_version[ETHTOOL_FWVERS_LEN]; 896 u32 hw_version; 897 u8 chip_revision; 898 const char *hw_name; 899 const char *wil_fw_name; 900 char *board_file; 901 u32 brd_file_addr; 902 u32 brd_file_max_size; 903 DECLARE_BITMAP(hw_capa, hw_capa_last); 904 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 905 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 906 u32 recovery_count; /* num of FW recovery attempts in a short time */ 907 u32 recovery_state; /* FW recovery state machine */ 908 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 909 wait_queue_head_t wq; /* for all wait_event() use */ 910 u8 max_vifs; /* maximum number of interfaces, including main */ 911 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 912 struct mutex vif_mutex; /* protects access to VIF entries */ 913 atomic_t connected_vifs; 914 /* profile */ 915 struct cfg80211_chan_def monitor_chandef; 916 u32 monitor_flags; 917 int sinfo_gen; 918 /* interrupt moderation */ 919 u32 tx_max_burst_duration; 920 u32 tx_interframe_timeout; 921 u32 rx_max_burst_duration; 922 u32 rx_interframe_timeout; 923 /* cached ISR registers */ 924 u32 isr_misc; 925 /* mailbox related */ 926 struct mutex wmi_mutex; 927 struct wil6210_mbox_ctl mbox_ctl; 928 struct completion wmi_ready; 929 struct completion wmi_call; 930 u16 wmi_seq; 931 u16 reply_id; /**< wait for this WMI event */ 932 u8 reply_mid; 933 void *reply_buf; 934 u16 reply_size; 935 struct workqueue_struct *wmi_wq; /* for deferred calls */ 936 struct work_struct wmi_event_worker; 937 struct workqueue_struct *wq_service; 938 struct work_struct fw_error_worker; /* for FW error recovery */ 939 struct list_head pending_wmi_ev; 940 /* 941 * protect pending_wmi_ev 942 * - fill in IRQ from wil6210_irq_misc, 943 * - consumed in thread by wmi_event_worker 944 */ 945 spinlock_t wmi_ev_lock; 946 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 947 struct napi_struct napi_rx; 948 struct napi_struct napi_tx; 949 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 950 951 /* DMA related */ 952 struct wil_ring ring_rx; 953 unsigned int rx_buf_len; 954 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 955 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 956 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 957 u8 num_rx_status_rings; 958 int tx_sring_idx; 959 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 960 struct wil_sta_info sta[WIL6210_MAX_CID]; 961 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 962 u32 dma_addr_size; /* indicates dma addr size */ 963 struct wil_rx_buff_mgmt rx_buff_mgmt; 964 bool use_enhanced_dma_hw; 965 struct wil_txrx_ops txrx_ops; 966 967 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 968 /* statistics */ 969 atomic_t isr_count_rx, isr_count_tx; 970 /* debugfs */ 971 struct dentry *debug; 972 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 973 u8 discovery_mode; 974 u8 abft_len; 975 u8 wakeup_trigger; 976 struct wil_suspend_stats suspend_stats; 977 struct wil_debugfs_data dbg_data; 978 bool tx_latency; /* collect TX latency measurements */ 979 size_t tx_latency_res; /* bin resolution in usec */ 980 981 void *platform_handle; 982 struct wil_platform_ops platform_ops; 983 bool keep_radio_on_during_sleep; 984 985 struct pmc_ctx pmc; 986 987 u8 p2p_dev_started; 988 989 /* P2P_DEVICE vif */ 990 struct wireless_dev *p2p_wdev; 991 struct wireless_dev *radio_wdev; 992 993 /* High Access Latency Policy voting */ 994 struct wil_halp halp; 995 996 enum wmi_ps_profile_type ps_profile; 997 998 int fw_calib_result; 999 1000 struct notifier_block pm_notify; 1001 1002 bool suspend_resp_rcvd; 1003 bool suspend_resp_comp; 1004 u32 bus_request_kbps; 1005 u32 bus_request_kbps_pre_suspend; 1006 1007 u32 rgf_fw_assert_code_addr; 1008 u32 rgf_ucode_assert_code_addr; 1009 u32 iccm_base; 1010 1011 /* relevant only for eDMA */ 1012 bool use_compressed_rx_status; 1013 u32 rx_status_ring_order; 1014 u32 tx_status_ring_order; 1015 u32 rx_buff_id_count; 1016 bool amsdu_en; 1017 bool use_rx_hw_reordering; 1018 bool secured_boot; 1019 u8 boot_config; 1020 1021 struct wil_fw_stats_global fw_stats_global; 1022 1023 u32 max_agg_wsize; 1024 u32 max_ampdu_size; 1025 }; 1026 1027 #define wil_to_wiphy(i) (i->wiphy) 1028 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1029 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1030 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1031 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1032 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1033 #define vif_to_wil(v) (v->wil) 1034 #define vif_to_ndev(v) (v->ndev) 1035 #define vif_to_wdev(v) (&v->wdev) 1036 1037 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1038 struct wireless_dev *wdev) 1039 { 1040 /* main interface is shared with P2P device */ 1041 if (wdev == wil->p2p_wdev) 1042 return ndev_to_vif(wil->main_ndev); 1043 else 1044 return container_of(wdev, struct wil6210_vif, wdev); 1045 } 1046 1047 static inline struct wireless_dev * 1048 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1049 { 1050 /* main interface is shared with P2P device */ 1051 if (vif->mid) 1052 return vif_to_wdev(vif); 1053 else 1054 return wil->radio_wdev; 1055 } 1056 1057 __printf(2, 3) 1058 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1059 __printf(2, 3) 1060 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1061 __printf(2, 3) 1062 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1063 __printf(2, 3) 1064 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1065 __printf(2, 3) 1066 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1067 #define wil_dbg(wil, fmt, arg...) do { \ 1068 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1069 wil_dbg_trace(wil, fmt, ##arg); \ 1070 } while (0) 1071 1072 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1073 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1074 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1075 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1076 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1077 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1078 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1079 #define wil_err_ratelimited(wil, fmt, arg...) \ 1080 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1081 1082 /* target operations */ 1083 /* register read */ 1084 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1085 { 1086 return readl(wil->csr + HOSTADDR(reg)); 1087 } 1088 1089 /* register write. wmb() to make sure it is completed */ 1090 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1091 { 1092 writel(val, wil->csr + HOSTADDR(reg)); 1093 wmb(); /* wait for write to propagate to the HW */ 1094 } 1095 1096 /* register set = read, OR, write */ 1097 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1098 { 1099 wil_w(wil, reg, wil_r(wil, reg) | val); 1100 } 1101 1102 /* register clear = read, AND with inverted, write */ 1103 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1104 { 1105 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1106 } 1107 1108 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1109 1110 #if defined(CONFIG_DYNAMIC_DEBUG) 1111 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1112 groupsize, buf, len, ascii) \ 1113 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1114 prefix_type, rowsize, \ 1115 groupsize, buf, len, ascii) 1116 1117 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1118 groupsize, buf, len, ascii) \ 1119 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1120 prefix_type, rowsize, \ 1121 groupsize, buf, len, ascii) 1122 1123 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1124 groupsize, buf, len, ascii) \ 1125 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1126 prefix_type, rowsize, \ 1127 groupsize, buf, len, ascii) 1128 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1129 static inline 1130 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1131 int groupsize, const void *buf, size_t len, bool ascii) 1132 { 1133 } 1134 1135 static inline 1136 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1137 int groupsize, const void *buf, size_t len, bool ascii) 1138 { 1139 } 1140 1141 static inline 1142 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1143 int groupsize, const void *buf, size_t len, bool ascii) 1144 { 1145 } 1146 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1147 1148 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1149 size_t count); 1150 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1151 size_t count); 1152 1153 struct wil6210_vif * 1154 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1155 unsigned char name_assign_type, enum nl80211_iftype iftype); 1156 void wil_vif_free(struct wil6210_vif *vif); 1157 void *wil_if_alloc(struct device *dev); 1158 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1159 struct net_device *ndev, bool up, bool ok); 1160 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1161 void wil_if_free(struct wil6210_priv *wil); 1162 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1163 int wil_if_add(struct wil6210_priv *wil); 1164 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1165 void wil_if_remove(struct wil6210_priv *wil); 1166 int wil_priv_init(struct wil6210_priv *wil); 1167 void wil_priv_deinit(struct wil6210_priv *wil); 1168 int wil_ps_update(struct wil6210_priv *wil, 1169 enum wmi_ps_profile_type ps_profile); 1170 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1171 void wil_fw_error_recovery(struct wil6210_priv *wil); 1172 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1173 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1174 int wil_up(struct wil6210_priv *wil); 1175 int __wil_up(struct wil6210_priv *wil); 1176 int wil_down(struct wil6210_priv *wil); 1177 int __wil_down(struct wil6210_priv *wil); 1178 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1179 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1180 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1181 void wil_set_ethtoolops(struct net_device *ndev); 1182 1183 struct fw_map *wil_find_fw_mapping(const char *section); 1184 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1185 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1186 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1187 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1188 struct wil6210_mbox_hdr *hdr); 1189 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1190 void wmi_recv_cmd(struct wil6210_priv *wil); 1191 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1192 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1193 void wmi_event_worker(struct work_struct *work); 1194 void wmi_event_flush(struct wil6210_priv *wil); 1195 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1196 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1197 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1198 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1199 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1200 const void *mac_addr, int key_usage); 1201 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1202 const void *mac_addr, int key_len, const void *key, 1203 int key_usage); 1204 int wmi_echo(struct wil6210_priv *wil); 1205 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1206 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1207 int wmi_rxon(struct wil6210_priv *wil, bool on); 1208 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1209 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, 1210 u16 reason, bool full_disconnect, bool del_sta); 1211 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1212 u8 ringid, u8 size, u16 timeout); 1213 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1214 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cidxtid, u16 reason); 1215 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1216 u8 mid, u8 cid, u8 tid, u8 token, 1217 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1218 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1219 enum wmi_ps_profile_type ps_profile); 1220 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1221 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1222 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1223 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1224 const u8 *mac, enum nl80211_iftype iftype); 1225 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1226 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1227 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, 1228 u8 cidxtid, u8 dialog_token, __le16 ba_param_set, 1229 __le16 ba_timeout, __le16 ba_seq_ctrl); 1230 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1231 1232 void wil6210_clear_irq(struct wil6210_priv *wil); 1233 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1234 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1235 void wil_mask_irq(struct wil6210_priv *wil); 1236 void wil_unmask_irq(struct wil6210_priv *wil); 1237 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1238 void wil_disable_irq(struct wil6210_priv *wil); 1239 void wil_enable_irq(struct wil6210_priv *wil); 1240 void wil6210_mask_halp(struct wil6210_priv *wil); 1241 1242 /* P2P */ 1243 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1244 int wil_p2p_search(struct wil6210_vif *vif, 1245 struct cfg80211_scan_request *request); 1246 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1247 unsigned int duration, struct ieee80211_channel *chan, 1248 u64 *cookie); 1249 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1250 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1251 void wil_p2p_listen_expired(struct work_struct *work); 1252 void wil_p2p_search_expired(struct work_struct *work); 1253 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1254 void wil_p2p_delayed_listen_work(struct work_struct *work); 1255 1256 /* WMI for P2P */ 1257 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1258 int wmi_start_listen(struct wil6210_vif *vif); 1259 int wmi_start_search(struct wil6210_vif *vif); 1260 int wmi_stop_discovery(struct wil6210_vif *vif); 1261 1262 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1263 struct cfg80211_mgmt_tx_params *params, 1264 u64 *cookie); 1265 int wil_cfg80211_iface_combinations_from_fw( 1266 struct wil6210_priv *wil, 1267 const struct wil_fw_record_concurrency *conc); 1268 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1269 1270 #if defined(CONFIG_WIL6210_DEBUGFS) 1271 int wil6210_debugfs_init(struct wil6210_priv *wil); 1272 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1273 #else 1274 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1275 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1276 #endif 1277 1278 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1279 struct station_info *sinfo); 1280 1281 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1282 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1283 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1284 1285 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1286 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1287 u8 hidden_ssid, u8 is_go); 1288 int wmi_pcp_stop(struct wil6210_vif *vif); 1289 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1290 int wmi_abort_scan(struct wil6210_vif *vif); 1291 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1292 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1293 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1294 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1295 u16 reason_code, bool from_event); 1296 void wil_probe_client_flush(struct wil6210_vif *vif); 1297 void wil_probe_client_worker(struct work_struct *work); 1298 void wil_disconnect_worker(struct work_struct *work); 1299 1300 void wil_init_txrx_ops(struct wil6210_priv *wil); 1301 1302 /* TX API */ 1303 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1304 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1305 int wil_bcast_init(struct wil6210_vif *vif); 1306 void wil_bcast_fini(struct wil6210_vif *vif); 1307 void wil_bcast_fini_all(struct wil6210_priv *wil); 1308 1309 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1310 struct wil_ring *ring, bool should_stop); 1311 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1312 struct wil_ring *ring, bool check_stop); 1313 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1314 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1315 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1316 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1317 1318 /* RX API */ 1319 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1320 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1321 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1322 1323 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1324 1325 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1326 bool load); 1327 int wil_request_board(struct wil6210_priv *wil, const char *name); 1328 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1329 1330 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1331 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1332 int wil_pm_runtime_get(struct wil6210_priv *wil); 1333 void wil_pm_runtime_put(struct wil6210_priv *wil); 1334 1335 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1336 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1337 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1338 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1339 int wmi_resume(struct wil6210_priv *wil); 1340 int wmi_suspend(struct wil6210_priv *wil); 1341 bool wil_is_tx_idle(struct wil6210_priv *wil); 1342 1343 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1344 void wil_fw_core_dump(struct wil6210_priv *wil); 1345 1346 void wil_halp_vote(struct wil6210_priv *wil); 1347 void wil_halp_unvote(struct wil6210_priv *wil); 1348 void wil6210_set_halp(struct wil6210_priv *wil); 1349 void wil6210_clear_halp(struct wil6210_priv *wil); 1350 1351 int wmi_start_sched_scan(struct wil6210_priv *wil, 1352 struct cfg80211_sched_scan_request *request); 1353 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1354 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1355 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1356 u8 channel, u16 duration_ms); 1357 1358 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1359 1360 /* WMI for enhanced DMA */ 1361 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1362 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1363 u16 max_rx_pl_per_desc); 1364 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1365 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1366 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1367 int tid); 1368 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1369 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1370 u8 tid, u8 token, u16 status, bool amsdu, 1371 u16 agg_wsize, u16 timeout); 1372 1373 #endif /* __WIL6210_H__ */ 1374