1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef __WIL6210_H__ 19 #define __WIL6210_H__ 20 21 #include <linux/etherdevice.h> 22 #include <linux/netdevice.h> 23 #include <linux/wireless.h> 24 #include <net/cfg80211.h> 25 #include <linux/timex.h> 26 #include <linux/types.h> 27 #include <linux/irqreturn.h> 28 #include "wmi.h" 29 #include "wil_platform.h" 30 #include "fw.h" 31 32 extern bool no_fw_recovery; 33 extern unsigned int mtu_max; 34 extern unsigned short rx_ring_overflow_thrsh; 35 extern int agg_wsize; 36 extern bool rx_align_2; 37 extern bool rx_large_buf; 38 extern bool debug_fw; 39 extern bool disable_ap_sme; 40 extern bool ftm_mode; 41 extern bool drop_if_ring_full; 42 extern uint max_assoc_sta; 43 44 struct wil6210_priv; 45 struct wil6210_vif; 46 union wil_tx_desc; 47 48 #define WIL_NAME "wil6210" 49 50 #define WIL_FW_NAME_DEFAULT "wil6210.fw" 51 #define WIL_FW_NAME_FTM_DEFAULT "wil6210_ftm.fw" 52 53 #define WIL_FW_NAME_SPARROW_PLUS "wil6210_sparrow_plus.fw" 54 #define WIL_FW_NAME_FTM_SPARROW_PLUS "wil6210_sparrow_plus_ftm.fw" 55 56 #define WIL_FW_NAME_TALYN "wil6436.fw" 57 #define WIL_FW_NAME_FTM_TALYN "wil6436_ftm.fw" 58 #define WIL_BRD_NAME_TALYN "wil6436.brd" 59 60 #define WIL_BOARD_FILE_NAME "wil6210.brd" /* board & radio parameters */ 61 62 #define WIL_DEFAULT_BUS_REQUEST_KBPS 128000 /* ~1Gbps */ 63 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */ 64 65 #define WIL_NUM_LATENCY_BINS 200 66 67 /* maximum number of virtual interfaces the driver supports 68 * (including the main interface) 69 */ 70 #define WIL_MAX_VIFS 4 71 72 /** 73 * extract bits [@b0:@b1] (inclusive) from the value @x 74 * it should be @b0 <= @b1, or result is incorrect 75 */ 76 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1) 77 { 78 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1); 79 } 80 81 #define WIL6210_MIN_MEM_SIZE (2 * 1024 * 1024UL) 82 #define WIL6210_MAX_MEM_SIZE (4 * 1024 * 1024UL) 83 84 #define WIL_TX_Q_LEN_DEFAULT (4000) 85 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10) 86 #define WIL_RX_RING_SIZE_ORDER_TALYN_DEFAULT (11) 87 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12) 88 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7) 89 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */ 90 /* limit ring size in range [32..32k] */ 91 #define WIL_RING_SIZE_ORDER_MIN (5) 92 #define WIL_RING_SIZE_ORDER_MAX (15) 93 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */ 94 #define WIL6210_MAX_CID (20) /* max number of stations */ 95 #define WIL6210_RX_DESC_MAX_CID (8) /* HW limit */ 96 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */ 97 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */ 98 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */ 99 #define WIL_MAX_AMPDU_SIZE_128 (128 * 1024) /* FW/HW limit */ 100 #define WIL_MAX_AGG_WSIZE_64 (64) /* FW/HW limit */ 101 #define WIL6210_MAX_STATUS_RINGS (8) 102 #define WIL_WMI_CALL_GENERAL_TO_MS 100 103 104 /* Hardware offload block adds the following: 105 * 26 bytes - 3-address QoS data header 106 * 8 bytes - IV + EIV (for GCMP) 107 * 8 bytes - SNAP 108 * 16 bytes - MIC (for GCMP) 109 * 4 bytes - CRC 110 */ 111 #define WIL_MAX_MPDU_OVERHEAD (62) 112 113 struct wil_suspend_count_stats { 114 unsigned long successful_suspends; 115 unsigned long successful_resumes; 116 unsigned long failed_suspends; 117 unsigned long failed_resumes; 118 }; 119 120 struct wil_suspend_stats { 121 struct wil_suspend_count_stats r_off; 122 struct wil_suspend_count_stats r_on; 123 unsigned long rejected_by_device; /* only radio on */ 124 unsigned long rejected_by_host; 125 }; 126 127 /* Calculate MAC buffer size for the firmware. It includes all overhead, 128 * as it will go over the air, and need to be 8 byte aligned 129 */ 130 static inline u32 wil_mtu2macbuf(u32 mtu) 131 { 132 return ALIGN(mtu + WIL_MAX_MPDU_OVERHEAD, 8); 133 } 134 135 /* MTU for Ethernet need to take into account 8-byte SNAP header 136 * to be added when encapsulating Ethernet frame into 802.11 137 */ 138 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8) 139 /* Max supported by wil6210 value for interrupt threshold is 5sec. */ 140 #define WIL6210_ITR_TRSH_MAX (5000000) 141 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 142 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */ 143 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 144 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */ 145 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */ 146 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000) 147 #define WIL6210_SCAN_TO msecs_to_jiffies(10000) 148 #define WIL6210_DISCONNECT_TO_MS (2000) 149 #define WIL6210_RX_HIGH_TRSH_INIT (0) 150 #define WIL6210_RX_HIGH_TRSH_DEFAULT \ 151 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3)) 152 #define WIL_MAX_DMG_AID 254 /* for DMG only 1-254 allowed (see 153 * 802.11REVmc/D5.0, section 9.4.1.8) 154 */ 155 /* Hardware definitions begin */ 156 157 /* 158 * Mapping 159 * RGF File | Host addr | FW addr 160 * | | 161 * user_rgf | 0x000000 | 0x880000 162 * dma_rgf | 0x001000 | 0x881000 163 * pcie_rgf | 0x002000 | 0x882000 164 * | | 165 */ 166 167 /* Where various structures placed in host address space */ 168 #define WIL6210_FW_HOST_OFF (0x880000UL) 169 170 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF) 171 172 /* 173 * Interrupt control registers block 174 * 175 * each interrupt controlled by the same bit in all registers 176 */ 177 struct RGF_ICR { 178 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */ 179 u32 ICR; /* Cause, W1C/COR depending on ICC */ 180 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */ 181 u32 ICS; /* Cause Set, WO */ 182 u32 IMV; /* Mask, RW+S/C */ 183 u32 IMS; /* Mask Set, write 1 to set */ 184 u32 IMC; /* Mask Clear, write 1 to clear */ 185 } __packed; 186 187 /* registers - FW addresses */ 188 #define RGF_USER_USAGE_1 (0x880004) 189 #define RGF_USER_USAGE_2 (0x880008) 190 #define RGF_USER_USAGE_6 (0x880018) 191 #define BIT_USER_OOB_MODE BIT(31) 192 #define BIT_USER_OOB_R2_MODE BIT(30) 193 #define RGF_USER_USAGE_8 (0x880020) 194 #define BIT_USER_PREVENT_DEEP_SLEEP BIT(0) 195 #define BIT_USER_SUPPORT_T_POWER_ON_0 BIT(1) 196 #define BIT_USER_EXT_CLK BIT(2) 197 #define RGF_USER_HW_MACHINE_STATE (0x8801dc) 198 #define HW_MACHINE_BOOT_DONE (0x3fffffd) 199 #define RGF_USER_USER_CPU_0 (0x8801e0) 200 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */ 201 #define RGF_USER_CPU_PC (0x8801e8) 202 #define RGF_USER_MAC_CPU_0 (0x8801fc) 203 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */ 204 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc) 205 #define RGF_USER_BL (0x880A3C) /* Boot Loader */ 206 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */ 207 #define RGF_USER_FW_CALIB_RESULT (0x880a90) /* b0-7:result 208 * b8-15:signature 209 */ 210 #define CALIB_RESULT_SIGNATURE (0x11) 211 #define RGF_USER_CLKS_CTL_0 (0x880abc) 212 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */ 213 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */ 214 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04) 215 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08) 216 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c) 217 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10) 218 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14) 219 #define BIT_HPAL_PERST_FROM_PAD BIT(6) 220 #define BIT_CAR_PERST_RST BIT(7) 221 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */ 222 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18) 223 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18) 224 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c) 225 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */ 226 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2) 227 #define RGF_USER_OTP_HW_RD_MACHINE_1 (0x880ce0) 228 #define BIT_OTP_SIGNATURE_ERR_TALYN_MB BIT(0) 229 #define BIT_OTP_HW_SECTION_DONE_TALYN_MB BIT(2) 230 #define BIT_NO_FLASH_INDICATION BIT(8) 231 #define RGF_USER_XPM_IFC_RD_TIME1 (0x880cec) 232 #define RGF_USER_XPM_IFC_RD_TIME2 (0x880cf0) 233 #define RGF_USER_XPM_IFC_RD_TIME3 (0x880cf4) 234 #define RGF_USER_XPM_IFC_RD_TIME4 (0x880cf8) 235 #define RGF_USER_XPM_IFC_RD_TIME5 (0x880cfc) 236 #define RGF_USER_XPM_IFC_RD_TIME6 (0x880d00) 237 #define RGF_USER_XPM_IFC_RD_TIME7 (0x880d04) 238 #define RGF_USER_XPM_IFC_RD_TIME8 (0x880d08) 239 #define RGF_USER_XPM_IFC_RD_TIME9 (0x880d0c) 240 #define RGF_USER_XPM_IFC_RD_TIME10 (0x880d10) 241 #define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64) 242 243 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */ 244 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0) 245 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */ 246 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */ 247 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0) 248 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1) 249 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */ 250 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0) 251 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1) 252 #define BIT_DMA_EP_MISC_ICR_HALP BIT(27) 253 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */ 254 255 /* Legacy interrupt moderation control (before Sparrow v2)*/ 256 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c) 257 #define RGF_DMA_ITR_CNT_DATA (0x881c60) 258 #define RGF_DMA_ITR_CNT_CRL (0x881c64) 259 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0) 260 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1) 261 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2) 262 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3) 263 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4) 264 265 /* Offload control (Sparrow B0+) */ 266 #define RGF_DMA_OFUL_NID_0 (0x881cd4) 267 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0) 268 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1) 269 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2) 270 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3) 271 272 /* New (sparrow v2+) interrupt moderation control */ 273 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40) 274 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34) 275 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38) 276 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c) 277 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0) 278 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1) 279 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2) 280 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3) 281 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4) 282 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5) 283 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6) 284 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60) 285 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64) 286 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68) 287 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0) 288 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 289 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2) 290 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3) 291 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 292 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50) 293 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44) 294 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48) 295 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c) 296 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0) 297 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1) 298 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2) 299 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3) 300 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4) 301 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5) 302 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6) 303 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54) 304 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58) 305 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c) 306 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0) 307 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1) 308 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2) 309 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3) 310 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4) 311 #define RGF_DMA_MISC_CTL (0x881d6c) 312 #define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7) 313 314 #define RGF_DMA_PSEUDO_CAUSE (0x881c68) 315 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c) 316 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70) 317 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0) 318 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1) 319 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2) 320 321 #define RGF_HP_CTRL (0x88265c) 322 #define RGF_PAL_UNIT_ICR (0x88266c) /* struct RGF_ICR */ 323 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4) 324 325 /* MAC timer, usec, for packet lifetime */ 326 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8) 327 328 #define RGF_CAF_ICR_TALYN_MB (0x8893d4) /* struct RGF_ICR */ 329 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */ 330 #define RGF_CAF_OSC_CONTROL (0x88afa4) 331 #define BIT_CAF_OSC_XTAL_EN BIT(0) 332 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec) 333 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0) 334 335 #define RGF_OTP_QC_SECURED (0x8a0038) 336 #define BIT_BOOT_FROM_ROM BIT(31) 337 338 /* eDMA */ 339 #define RGF_SCM_PTRS_SUBQ_RD_PTR (0x8b4000) 340 #define RGF_SCM_PTRS_COMPQ_RD_PTR (0x8b4100) 341 #define RGF_DMA_SCM_SUBQ_CONS (0x8b60ec) 342 #define RGF_DMA_SCM_COMPQ_PROD (0x8b616c) 343 344 #define RGF_INT_COUNT_ON_SPECIAL_EVT (0x8b62d8) 345 346 #define RGF_INT_CTRL_INT_GEN_CFG_0 (0x8bc000) 347 #define RGF_INT_CTRL_INT_GEN_CFG_1 (0x8bc004) 348 #define RGF_INT_GEN_TIME_UNIT_LIMIT (0x8bc0c8) 349 350 #define RGF_INT_GEN_CTRL (0x8bc0ec) 351 #define BIT_CONTROL_0 BIT(0) 352 353 /* eDMA status interrupts */ 354 #define RGF_INT_GEN_RX_ICR (0x8bc0f4) 355 #define BIT_RX_STATUS_IRQ BIT(WIL_RX_STATUS_IRQ_IDX) 356 #define RGF_INT_GEN_TX_ICR (0x8bc110) 357 #define BIT_TX_STATUS_IRQ BIT(WIL_TX_STATUS_IRQ_IDX) 358 #define RGF_INT_CTRL_RX_INT_MASK (0x8bc12c) 359 #define RGF_INT_CTRL_TX_INT_MASK (0x8bc130) 360 361 #define RGF_INT_GEN_IDLE_TIME_LIMIT (0x8bc134) 362 363 #define USER_EXT_USER_PMU_3 (0x88d00c) 364 #define BIT_PMU_DEVICE_RDY BIT(0) 365 366 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */ 367 #define JTAG_DEV_ID_SPARROW (0x2632072f) 368 #define JTAG_DEV_ID_TALYN (0x7e0e1) 369 #define JTAG_DEV_ID_TALYN_MB (0x1007e0e1) 370 371 #define RGF_USER_REVISION_ID (0x88afe4) 372 #define RGF_USER_REVISION_ID_MASK (3) 373 #define REVISION_ID_SPARROW_B0 (0x0) 374 #define REVISION_ID_SPARROW_D0 (0x3) 375 376 #define RGF_OTP_MAC_TALYN_MB (0x8a0304) 377 #define RGF_OTP_OEM_MAC (0x8a0334) 378 #define RGF_OTP_MAC (0x8a0620) 379 380 /* Talyn-MB */ 381 #define RGF_USER_USER_CPU_0_TALYN_MB (0x8c0138) 382 #define RGF_USER_MAC_CPU_0_TALYN_MB (0x8c0154) 383 384 /* crash codes for FW/Ucode stored here */ 385 386 /* ASSERT RGFs */ 387 #define SPARROW_RGF_FW_ASSERT_CODE (0x91f020) 388 #define SPARROW_RGF_UCODE_ASSERT_CODE (0x91f028) 389 #define TALYN_RGF_FW_ASSERT_CODE (0xa37020) 390 #define TALYN_RGF_UCODE_ASSERT_CODE (0xa37028) 391 392 enum { 393 HW_VER_UNKNOWN, 394 HW_VER_SPARROW_B0, /* REVISION_ID_SPARROW_B0 */ 395 HW_VER_SPARROW_D0, /* REVISION_ID_SPARROW_D0 */ 396 HW_VER_TALYN, /* JTAG_DEV_ID_TALYN */ 397 HW_VER_TALYN_MB /* JTAG_DEV_ID_TALYN_MB */ 398 }; 399 400 /* popular locations */ 401 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD 402 #define HOST_MBOX HOSTADDR(RGF_MBOX) 403 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 404 405 /* ISR register bits */ 406 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0) 407 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1) 408 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3) 409 410 #define WIL_DATA_COMPLETION_TO_MS 200 411 412 /* Hardware definitions end */ 413 #define SPARROW_FW_MAPPING_TABLE_SIZE 10 414 #define TALYN_FW_MAPPING_TABLE_SIZE 13 415 #define TALYN_MB_FW_MAPPING_TABLE_SIZE 19 416 #define MAX_FW_MAPPING_TABLE_SIZE 19 417 418 /* Common representation of physical address in wil ring */ 419 struct wil_ring_dma_addr { 420 __le32 addr_low; 421 __le16 addr_high; 422 } __packed; 423 424 struct fw_map { 425 u32 from; /* linker address - from, inclusive */ 426 u32 to; /* linker address - to, exclusive */ 427 u32 host; /* PCI/Host address - BAR0 + 0x880000 */ 428 const char *name; /* for debugfs */ 429 bool fw; /* true if FW mapping, false if UCODE mapping */ 430 bool crash_dump; /* true if should be dumped during crash dump */ 431 }; 432 433 /* array size should be in sync with actual definition in the wmi.c */ 434 extern const struct fw_map sparrow_fw_mapping[SPARROW_FW_MAPPING_TABLE_SIZE]; 435 extern const struct fw_map sparrow_d0_mac_rgf_ext; 436 extern const struct fw_map talyn_fw_mapping[TALYN_FW_MAPPING_TABLE_SIZE]; 437 extern const struct fw_map talyn_mb_fw_mapping[TALYN_MB_FW_MAPPING_TABLE_SIZE]; 438 extern struct fw_map fw_mapping[MAX_FW_MAPPING_TABLE_SIZE]; 439 440 /** 441 * mk_cidxtid - construct @cidxtid field 442 * @cid: CID value 443 * @tid: TID value 444 * 445 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 446 */ 447 static inline u8 mk_cidxtid(u8 cid, u8 tid) 448 { 449 return ((tid & 0xf) << 4) | (cid & 0xf); 450 } 451 452 /** 453 * parse_cidxtid - parse @cidxtid field 454 * @cid: store CID value here 455 * @tid: store TID value here 456 * 457 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID 458 */ 459 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid) 460 { 461 *cid = cidxtid & 0xf; 462 *tid = (cidxtid >> 4) & 0xf; 463 } 464 465 struct wil6210_mbox_ring { 466 u32 base; 467 u16 entry_size; /* max. size of mbox entry, incl. all headers */ 468 u16 size; 469 u32 tail; 470 u32 head; 471 } __packed; 472 473 struct wil6210_mbox_ring_desc { 474 __le32 sync; 475 __le32 addr; 476 } __packed; 477 478 /* at HOST_OFF_WIL6210_MBOX_CTL */ 479 struct wil6210_mbox_ctl { 480 struct wil6210_mbox_ring tx; 481 struct wil6210_mbox_ring rx; 482 } __packed; 483 484 struct wil6210_mbox_hdr { 485 __le16 seq; 486 __le16 len; /* payload, bytes after this header */ 487 __le16 type; 488 u8 flags; 489 u8 reserved; 490 } __packed; 491 492 #define WIL_MBOX_HDR_TYPE_WMI (0) 493 494 /* max. value for wil6210_mbox_hdr.len */ 495 #define MAX_MBOXITEM_SIZE (240) 496 497 struct pending_wmi_event { 498 struct list_head list; 499 struct { 500 struct wil6210_mbox_hdr hdr; 501 struct wmi_cmd_hdr wmi; 502 u8 data[0]; 503 } __packed event; 504 }; 505 506 enum { /* for wil_ctx.mapped_as */ 507 wil_mapped_as_none = 0, 508 wil_mapped_as_single = 1, 509 wil_mapped_as_page = 2, 510 }; 511 512 /** 513 * struct wil_ctx - software context for ring descriptor 514 */ 515 struct wil_ctx { 516 struct sk_buff *skb; 517 u8 nr_frags; 518 u8 mapped_as; 519 }; 520 521 struct wil_desc_ring_rx_swtail { /* relevant for enhanced DMA only */ 522 u32 *va; 523 dma_addr_t pa; 524 }; 525 526 /** 527 * A general ring structure, used for RX and TX. 528 * In legacy DMA it represents the vring, 529 * In enahnced DMA it represents the descriptor ring (vrings are handled by FW) 530 */ 531 struct wil_ring { 532 dma_addr_t pa; 533 volatile union wil_ring_desc *va; 534 u16 size; /* number of wil_ring_desc elements */ 535 u32 swtail; 536 u32 swhead; 537 u32 hwtail; /* write here to inform hw */ 538 struct wil_ctx *ctx; /* ctx[size] - software context */ 539 struct wil_desc_ring_rx_swtail edma_rx_swtail; 540 bool is_rx; 541 }; 542 543 /** 544 * Additional data for Rx ring. 545 * Used for enhanced DMA RX chaining. 546 */ 547 struct wil_ring_rx_data { 548 /* the skb being assembled */ 549 struct sk_buff *skb; 550 /* true if we are skipping a bad fragmented packet */ 551 bool skipping; 552 u16 buff_size; 553 }; 554 555 /** 556 * Status ring structure, used for enhanced DMA completions for RX and TX. 557 */ 558 struct wil_status_ring { 559 dma_addr_t pa; 560 void *va; /* pointer to ring_[tr]x_status elements */ 561 u16 size; /* number of status elements */ 562 size_t elem_size; /* status element size in bytes */ 563 u32 swhead; 564 u32 hwtail; /* write here to inform hw */ 565 bool is_rx; 566 u8 desc_rdy_pol; /* Expected descriptor ready bit polarity */ 567 struct wil_ring_rx_data rx_data; 568 u32 invalid_buff_id_cnt; /* relevant only for RX */ 569 }; 570 571 #define WIL_STA_TID_NUM (16) 572 #define WIL_MCS_MAX (15) /* Maximum MCS supported */ 573 574 struct wil_net_stats { 575 unsigned long rx_packets; 576 unsigned long tx_packets; 577 unsigned long rx_bytes; 578 unsigned long tx_bytes; 579 unsigned long tx_errors; 580 u32 tx_latency_min_us; 581 u32 tx_latency_max_us; 582 u64 tx_latency_total_us; 583 unsigned long rx_dropped; 584 unsigned long rx_non_data_frame; 585 unsigned long rx_short_frame; 586 unsigned long rx_large_frame; 587 unsigned long rx_replay; 588 unsigned long rx_mic_error; 589 unsigned long rx_key_error; /* eDMA specific */ 590 unsigned long rx_amsdu_error; /* eDMA specific */ 591 unsigned long rx_csum_err; 592 u16 last_mcs_rx; 593 u8 last_cb_mode_rx; 594 u64 rx_per_mcs[WIL_MCS_MAX + 1]; 595 u32 ft_roams; /* relevant in STA mode */ 596 }; 597 598 /** 599 * struct tx_rx_ops - different TX/RX ops for legacy and enhanced 600 * DMA flow 601 */ 602 struct wil_txrx_ops { 603 void (*configure_interrupt_moderation)(struct wil6210_priv *wil); 604 /* TX ops */ 605 int (*ring_init_tx)(struct wil6210_vif *vif, int ring_id, 606 int size, int cid, int tid); 607 void (*ring_fini_tx)(struct wil6210_priv *wil, struct wil_ring *ring); 608 int (*ring_init_bcast)(struct wil6210_vif *vif, int id, int size); 609 int (*tx_init)(struct wil6210_priv *wil); 610 void (*tx_fini)(struct wil6210_priv *wil); 611 int (*tx_desc_map)(union wil_tx_desc *desc, dma_addr_t pa, 612 u32 len, int ring_index); 613 void (*tx_desc_unmap)(struct device *dev, 614 union wil_tx_desc *desc, 615 struct wil_ctx *ctx); 616 int (*tx_ring_tso)(struct wil6210_priv *wil, struct wil6210_vif *vif, 617 struct wil_ring *ring, struct sk_buff *skb); 618 int (*tx_ring_modify)(struct wil6210_vif *vif, int ring_id, 619 int cid, int tid); 620 irqreturn_t (*irq_tx)(int irq, void *cookie); 621 /* RX ops */ 622 int (*rx_init)(struct wil6210_priv *wil, uint ring_order); 623 void (*rx_fini)(struct wil6210_priv *wil); 624 int (*wmi_addba_rx_resp)(struct wil6210_priv *wil, u8 mid, u8 cid, 625 u8 tid, u8 token, u16 status, bool amsdu, 626 u16 agg_wsize, u16 timeout); 627 void (*get_reorder_params)(struct wil6210_priv *wil, 628 struct sk_buff *skb, int *tid, int *cid, 629 int *mid, u16 *seq, int *mcast, int *retry); 630 void (*get_netif_rx_params)(struct sk_buff *skb, 631 int *cid, int *security); 632 int (*rx_crypto_check)(struct wil6210_priv *wil, struct sk_buff *skb); 633 int (*rx_error_check)(struct wil6210_priv *wil, struct sk_buff *skb, 634 struct wil_net_stats *stats); 635 bool (*is_rx_idle)(struct wil6210_priv *wil); 636 irqreturn_t (*irq_rx)(int irq, void *cookie); 637 }; 638 639 /** 640 * Additional data for Tx ring 641 */ 642 struct wil_ring_tx_data { 643 bool dot1x_open; 644 int enabled; 645 cycles_t idle, last_idle, begin; 646 u8 agg_wsize; /* agreed aggregation window, 0 - no agg */ 647 u16 agg_timeout; 648 u8 agg_amsdu; 649 bool addba_in_progress; /* if set, agg_xxx is for request in progress */ 650 u8 mid; 651 spinlock_t lock; 652 }; 653 654 enum { /* for wil6210_priv.status */ 655 wil_status_fwready = 0, /* FW operational */ 656 wil_status_dontscan, 657 wil_status_mbox_ready, /* MBOX structures ready */ 658 wil_status_irqen, /* interrupts enabled - for debug */ 659 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */ 660 wil_status_resetting, /* reset in progress */ 661 wil_status_suspending, /* suspend in progress */ 662 wil_status_suspended, /* suspend completed, device is suspended */ 663 wil_status_resuming, /* resume in progress */ 664 wil_status_last /* keep last */ 665 }; 666 667 struct pci_dev; 668 669 /** 670 * struct tid_ampdu_rx - TID aggregation information (Rx). 671 * 672 * @reorder_buf: buffer to reorder incoming aggregated MPDUs 673 * @last_rx: jiffies of last rx activity 674 * @head_seq_num: head sequence number in reordering buffer. 675 * @stored_mpdu_num: number of MPDUs in reordering buffer 676 * @ssn: Starting Sequence Number expected to be aggregated. 677 * @buf_size: buffer size for incoming A-MPDUs 678 * @ssn_last_drop: SSN of the last dropped frame 679 * @total: total number of processed incoming frames 680 * @drop_dup: duplicate frames dropped for this reorder buffer 681 * @drop_old: old frames dropped for this reorder buffer 682 * @first_time: true when this buffer used 1-st time 683 * @mcast_last_seq: sequence number (SN) of last received multicast packet 684 * @drop_dup_mcast: duplicate multicast frames dropped for this reorder buffer 685 */ 686 struct wil_tid_ampdu_rx { 687 struct sk_buff **reorder_buf; 688 unsigned long last_rx; 689 u16 head_seq_num; 690 u16 stored_mpdu_num; 691 u16 ssn; 692 u16 buf_size; 693 u16 ssn_last_drop; 694 unsigned long long total; /* frames processed */ 695 unsigned long long drop_dup; 696 unsigned long long drop_old; 697 bool first_time; /* is it 1-st time this buffer used? */ 698 u16 mcast_last_seq; /* multicast dup detection */ 699 unsigned long long drop_dup_mcast; 700 }; 701 702 /** 703 * struct wil_tid_crypto_rx_single - TID crypto information (Rx). 704 * 705 * @pn: GCMP PN for the session 706 * @key_set: valid key present 707 */ 708 struct wil_tid_crypto_rx_single { 709 u8 pn[IEEE80211_GCMP_PN_LEN]; 710 bool key_set; 711 }; 712 713 struct wil_tid_crypto_rx { 714 struct wil_tid_crypto_rx_single key_id[4]; 715 }; 716 717 struct wil_p2p_info { 718 struct ieee80211_channel listen_chan; 719 u8 discovery_started; 720 u64 cookie; 721 struct wireless_dev *pending_listen_wdev; 722 unsigned int listen_duration; 723 struct timer_list discovery_timer; /* listen/search duration */ 724 struct work_struct discovery_expired_work; /* listen/search expire */ 725 struct work_struct delayed_listen_work; /* listen after scan done */ 726 }; 727 728 enum wil_sta_status { 729 wil_sta_unused = 0, 730 wil_sta_conn_pending = 1, 731 wil_sta_connected = 2, 732 }; 733 734 enum wil_rekey_state { 735 WIL_REKEY_IDLE = 0, 736 WIL_REKEY_M3_RECEIVED = 1, 737 WIL_REKEY_WAIT_M4_SENT = 2, 738 }; 739 740 /** 741 * struct wil_sta_info - data for peer 742 * 743 * Peer identified by its CID (connection ID) 744 * NIC performs beam forming for each peer; 745 * if no beam forming done, frame exchange is not 746 * possible. 747 */ 748 struct wil_sta_info { 749 u8 addr[ETH_ALEN]; 750 u8 mid; 751 enum wil_sta_status status; 752 struct wil_net_stats stats; 753 /** 754 * 20 latency bins. 1st bin counts packets with latency 755 * of 0..tx_latency_res, last bin counts packets with latency 756 * of 19*tx_latency_res and above. 757 * tx_latency_res is configured from "tx_latency" debug-fs. 758 */ 759 u64 *tx_latency_bins; 760 struct wmi_link_stats_basic fw_stats_basic; 761 /* Rx BACK */ 762 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM]; 763 spinlock_t tid_rx_lock; /* guarding tid_rx array */ 764 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 765 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)]; 766 struct wil_tid_crypto_rx tid_crypto_rx[WIL_STA_TID_NUM]; 767 struct wil_tid_crypto_rx group_crypto_rx; 768 u8 aid; /* 1-254; 0 if unknown/not reported */ 769 }; 770 771 enum { 772 fw_recovery_idle = 0, 773 fw_recovery_pending = 1, 774 fw_recovery_running = 2, 775 }; 776 777 enum { 778 hw_capa_no_flash, 779 hw_capa_last 780 }; 781 782 struct wil_probe_client_req { 783 struct list_head list; 784 u64 cookie; 785 u8 cid; 786 }; 787 788 struct pmc_ctx { 789 /* alloc, free, and read operations must own the lock */ 790 struct mutex lock; 791 struct vring_tx_desc *pring_va; 792 dma_addr_t pring_pa; 793 struct desc_alloc_info *descriptors; 794 int last_cmd_status; 795 int num_descriptors; 796 int descriptor_size; 797 }; 798 799 struct wil_halp { 800 struct mutex lock; /* protect halp ref_cnt */ 801 unsigned int ref_cnt; 802 struct completion comp; 803 u8 handle_icr; 804 }; 805 806 struct wil_blob_wrapper { 807 struct wil6210_priv *wil; 808 struct debugfs_blob_wrapper blob; 809 }; 810 811 #define WIL_LED_MAX_ID (2) 812 #define WIL_LED_INVALID_ID (0xF) 813 #define WIL_LED_BLINK_ON_SLOW_MS (300) 814 #define WIL_LED_BLINK_OFF_SLOW_MS (300) 815 #define WIL_LED_BLINK_ON_MED_MS (200) 816 #define WIL_LED_BLINK_OFF_MED_MS (200) 817 #define WIL_LED_BLINK_ON_FAST_MS (100) 818 #define WIL_LED_BLINK_OFF_FAST_MS (100) 819 enum { 820 WIL_LED_TIME_SLOW = 0, 821 WIL_LED_TIME_MED, 822 WIL_LED_TIME_FAST, 823 WIL_LED_TIME_LAST, 824 }; 825 826 struct blink_on_off_time { 827 u32 on_ms; 828 u32 off_ms; 829 }; 830 831 struct wil_debugfs_iomem_data { 832 void *offset; 833 struct wil6210_priv *wil; 834 }; 835 836 struct wil_debugfs_data { 837 struct wil_debugfs_iomem_data *data_arr; 838 int iomem_data_count; 839 }; 840 841 extern struct blink_on_off_time led_blink_time[WIL_LED_TIME_LAST]; 842 extern u8 led_id; 843 extern u8 led_polarity; 844 845 enum wil6210_vif_status { 846 wil_vif_fwconnecting, 847 wil_vif_fwconnected, 848 wil_vif_ft_roam, 849 wil_vif_status_last /* keep last */ 850 }; 851 852 struct wil6210_vif { 853 struct wireless_dev wdev; 854 struct net_device *ndev; 855 struct wil6210_priv *wil; 856 u8 mid; 857 DECLARE_BITMAP(status, wil_vif_status_last); 858 u32 privacy; /* secure connection? */ 859 u16 channel; /* relevant in AP mode */ 860 u8 wmi_edmg_channel; /* relevant in AP mode */ 861 u8 hidden_ssid; /* relevant in AP mode */ 862 u32 ap_isolate; /* no intra-BSS communication */ 863 bool pbss; 864 int bi; 865 u8 *proberesp, *proberesp_ies, *assocresp_ies; 866 size_t proberesp_len, proberesp_ies_len, assocresp_ies_len; 867 u8 ssid[IEEE80211_MAX_SSID_LEN]; 868 size_t ssid_len; 869 u8 gtk_index; 870 u8 gtk[WMI_MAX_KEY_LEN]; 871 size_t gtk_len; 872 int bcast_ring; 873 struct cfg80211_bss *bss; /* connected bss, relevant in STA mode */ 874 int locally_generated_disc; /* relevant in STA mode */ 875 struct timer_list connect_timer; 876 struct work_struct disconnect_worker; 877 /* scan */ 878 struct cfg80211_scan_request *scan_request; 879 struct timer_list scan_timer; /* detect scan timeout */ 880 struct wil_p2p_info p2p; 881 /* keep alive */ 882 struct list_head probe_client_pending; 883 struct mutex probe_client_mutex; /* protect @probe_client_pending */ 884 struct work_struct probe_client_worker; 885 int net_queue_stopped; /* netif_tx_stop_all_queues invoked */ 886 bool fw_stats_ready; /* per-cid statistics are ready inside sta_info */ 887 u64 fw_stats_tsf; /* measurement timestamp */ 888 889 /* PTK rekey race prevention, this is relevant to station mode only */ 890 enum wil_rekey_state ptk_rekey_state; 891 struct work_struct enable_tx_key_worker; 892 }; 893 894 /** 895 * RX buffer allocated for enhanced DMA RX descriptors 896 */ 897 struct wil_rx_buff { 898 struct sk_buff *skb; 899 struct list_head list; 900 int id; 901 }; 902 903 /** 904 * During Rx completion processing, the driver extracts a buffer ID which 905 * is used as an index to the rx_buff_mgmt.buff_arr array and then the SKB 906 * is given to the network stack and the buffer is moved from the 'active' 907 * list to the 'free' list. 908 * During Rx refill, SKBs are attached to free buffers and moved to the 909 * 'active' list. 910 */ 911 struct wil_rx_buff_mgmt { 912 struct wil_rx_buff *buff_arr; 913 size_t size; /* number of items in buff_arr */ 914 struct list_head active; 915 struct list_head free; 916 unsigned long free_list_empty_cnt; /* statistics */ 917 }; 918 919 struct wil_fw_stats_global { 920 bool ready; 921 u64 tsf; /* measurement timestamp */ 922 struct wmi_link_stats_global stats; 923 }; 924 925 struct wil_brd_info { 926 u32 file_addr; 927 u32 file_max_size; 928 }; 929 930 struct wil6210_priv { 931 struct pci_dev *pdev; 932 u32 bar_size; 933 struct wiphy *wiphy; 934 struct net_device *main_ndev; 935 int n_msi; 936 void __iomem *csr; 937 DECLARE_BITMAP(status, wil_status_last); 938 u8 fw_version[ETHTOOL_FWVERS_LEN]; 939 u32 hw_version; 940 u8 chip_revision; 941 const char *hw_name; 942 const char *wil_fw_name; 943 char *board_file; 944 u32 num_of_brd_entries; 945 struct wil_brd_info *brd_info; 946 DECLARE_BITMAP(hw_capa, hw_capa_last); 947 DECLARE_BITMAP(fw_capabilities, WMI_FW_CAPABILITY_MAX); 948 DECLARE_BITMAP(platform_capa, WIL_PLATFORM_CAPA_MAX); 949 u32 recovery_count; /* num of FW recovery attempts in a short time */ 950 u32 recovery_state; /* FW recovery state machine */ 951 unsigned long last_fw_recovery; /* jiffies of last fw recovery */ 952 wait_queue_head_t wq; /* for all wait_event() use */ 953 u8 max_vifs; /* maximum number of interfaces, including main */ 954 struct wil6210_vif *vifs[WIL_MAX_VIFS]; 955 struct mutex vif_mutex; /* protects access to VIF entries */ 956 atomic_t connected_vifs; 957 u32 max_assoc_sta; /* max sta's supported by the driver and the FW */ 958 959 /* profile */ 960 struct cfg80211_chan_def monitor_chandef; 961 u32 monitor_flags; 962 int sinfo_gen; 963 /* interrupt moderation */ 964 u32 tx_max_burst_duration; 965 u32 tx_interframe_timeout; 966 u32 rx_max_burst_duration; 967 u32 rx_interframe_timeout; 968 /* cached ISR registers */ 969 u32 isr_misc; 970 /* mailbox related */ 971 struct mutex wmi_mutex; 972 struct wil6210_mbox_ctl mbox_ctl; 973 struct completion wmi_ready; 974 struct completion wmi_call; 975 u16 wmi_seq; 976 u16 reply_id; /**< wait for this WMI event */ 977 u8 reply_mid; 978 void *reply_buf; 979 u16 reply_size; 980 struct workqueue_struct *wmi_wq; /* for deferred calls */ 981 struct work_struct wmi_event_worker; 982 struct workqueue_struct *wq_service; 983 struct work_struct fw_error_worker; /* for FW error recovery */ 984 struct list_head pending_wmi_ev; 985 /* 986 * protect pending_wmi_ev 987 * - fill in IRQ from wil6210_irq_misc, 988 * - consumed in thread by wmi_event_worker 989 */ 990 spinlock_t wmi_ev_lock; 991 spinlock_t net_queue_lock; /* guarding stop/wake netif queue */ 992 spinlock_t eap_lock; /* guarding access to eap rekey fields */ 993 struct napi_struct napi_rx; 994 struct napi_struct napi_tx; 995 struct net_device napi_ndev; /* dummy net_device serving all VIFs */ 996 997 /* DMA related */ 998 struct wil_ring ring_rx; 999 unsigned int rx_buf_len; 1000 struct wil_ring ring_tx[WIL6210_MAX_TX_RINGS]; 1001 struct wil_ring_tx_data ring_tx_data[WIL6210_MAX_TX_RINGS]; 1002 struct wil_status_ring srings[WIL6210_MAX_STATUS_RINGS]; 1003 u8 num_rx_status_rings; 1004 int tx_sring_idx; 1005 u8 ring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */ 1006 struct wil_sta_info sta[WIL6210_MAX_CID]; 1007 u32 ring_idle_trsh; /* HW fetches up to 16 descriptors at once */ 1008 u32 dma_addr_size; /* indicates dma addr size */ 1009 struct wil_rx_buff_mgmt rx_buff_mgmt; 1010 bool use_enhanced_dma_hw; 1011 struct wil_txrx_ops txrx_ops; 1012 1013 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */ 1014 /* for synchronizing device memory access while reset or suspend */ 1015 struct rw_semaphore mem_lock; 1016 /* statistics */ 1017 atomic_t isr_count_rx, isr_count_tx; 1018 /* debugfs */ 1019 struct dentry *debug; 1020 struct wil_blob_wrapper blobs[MAX_FW_MAPPING_TABLE_SIZE]; 1021 u8 discovery_mode; 1022 u8 abft_len; 1023 u8 wakeup_trigger; 1024 struct wil_suspend_stats suspend_stats; 1025 struct wil_debugfs_data dbg_data; 1026 bool tx_latency; /* collect TX latency measurements */ 1027 size_t tx_latency_res; /* bin resolution in usec */ 1028 1029 void *platform_handle; 1030 struct wil_platform_ops platform_ops; 1031 bool keep_radio_on_during_sleep; 1032 1033 struct pmc_ctx pmc; 1034 1035 u8 p2p_dev_started; 1036 1037 /* P2P_DEVICE vif */ 1038 struct wireless_dev *p2p_wdev; 1039 struct wireless_dev *radio_wdev; 1040 1041 /* High Access Latency Policy voting */ 1042 struct wil_halp halp; 1043 1044 enum wmi_ps_profile_type ps_profile; 1045 1046 int fw_calib_result; 1047 1048 struct notifier_block pm_notify; 1049 1050 bool suspend_resp_rcvd; 1051 bool suspend_resp_comp; 1052 u32 bus_request_kbps; 1053 u32 bus_request_kbps_pre_suspend; 1054 1055 u32 rgf_fw_assert_code_addr; 1056 u32 rgf_ucode_assert_code_addr; 1057 u32 iccm_base; 1058 1059 /* relevant only for eDMA */ 1060 bool use_compressed_rx_status; 1061 u32 rx_status_ring_order; 1062 u32 tx_status_ring_order; 1063 u32 rx_buff_id_count; 1064 bool amsdu_en; 1065 bool use_rx_hw_reordering; 1066 bool secured_boot; 1067 u8 boot_config; 1068 1069 struct wil_fw_stats_global fw_stats_global; 1070 1071 u32 max_agg_wsize; 1072 u32 max_ampdu_size; 1073 }; 1074 1075 #define wil_to_wiphy(i) (i->wiphy) 1076 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i))) 1077 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w)) 1078 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w)) 1079 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr)) 1080 #define ndev_to_vif(n) (struct wil6210_vif *)(netdev_priv(n)) 1081 #define vif_to_wil(v) (v->wil) 1082 #define vif_to_ndev(v) (v->ndev) 1083 #define vif_to_wdev(v) (&v->wdev) 1084 #define GET_MAX_VIFS(wil) min_t(int, (wil)->max_vifs, WIL_MAX_VIFS) 1085 1086 static inline struct wil6210_vif *wdev_to_vif(struct wil6210_priv *wil, 1087 struct wireless_dev *wdev) 1088 { 1089 /* main interface is shared with P2P device */ 1090 if (wdev == wil->p2p_wdev) 1091 return ndev_to_vif(wil->main_ndev); 1092 else 1093 return container_of(wdev, struct wil6210_vif, wdev); 1094 } 1095 1096 static inline struct wireless_dev * 1097 vif_to_radio_wdev(struct wil6210_priv *wil, struct wil6210_vif *vif) 1098 { 1099 /* main interface is shared with P2P device */ 1100 if (vif->mid) 1101 return vif_to_wdev(vif); 1102 else 1103 return wil->radio_wdev; 1104 } 1105 1106 __printf(2, 3) 1107 void wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...); 1108 __printf(2, 3) 1109 void __wil_err(struct wil6210_priv *wil, const char *fmt, ...); 1110 __printf(2, 3) 1111 void __wil_err_ratelimited(struct wil6210_priv *wil, const char *fmt, ...); 1112 __printf(2, 3) 1113 void __wil_info(struct wil6210_priv *wil, const char *fmt, ...); 1114 __printf(2, 3) 1115 void wil_dbg_ratelimited(const struct wil6210_priv *wil, const char *fmt, ...); 1116 #define wil_dbg(wil, fmt, arg...) do { \ 1117 netdev_dbg(wil->main_ndev, fmt, ##arg); \ 1118 wil_dbg_trace(wil, fmt, ##arg); \ 1119 } while (0) 1120 1121 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg) 1122 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg) 1123 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) 1124 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) 1125 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg) 1126 #define wil_err(wil, fmt, arg...) __wil_err(wil, "%s: " fmt, __func__, ##arg) 1127 #define wil_info(wil, fmt, arg...) __wil_info(wil, "%s: " fmt, __func__, ##arg) 1128 #define wil_err_ratelimited(wil, fmt, arg...) \ 1129 __wil_err_ratelimited(wil, "%s: " fmt, __func__, ##arg) 1130 1131 /* target operations */ 1132 /* register read */ 1133 static inline u32 wil_r(struct wil6210_priv *wil, u32 reg) 1134 { 1135 return readl(wil->csr + HOSTADDR(reg)); 1136 } 1137 1138 /* register write. wmb() to make sure it is completed */ 1139 static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val) 1140 { 1141 writel(val, wil->csr + HOSTADDR(reg)); 1142 wmb(); /* wait for write to propagate to the HW */ 1143 } 1144 1145 /* register set = read, OR, write */ 1146 static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val) 1147 { 1148 wil_w(wil, reg, wil_r(wil, reg) | val); 1149 } 1150 1151 /* register clear = read, AND with inverted, write */ 1152 static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val) 1153 { 1154 wil_w(wil, reg, wil_r(wil, reg) & ~val); 1155 } 1156 1157 /** 1158 * wil_cid_valid - check cid is valid 1159 */ 1160 static inline bool wil_cid_valid(struct wil6210_priv *wil, int cid) 1161 { 1162 return (cid >= 0 && cid < wil->max_assoc_sta); 1163 } 1164 1165 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len); 1166 1167 #if defined(CONFIG_DYNAMIC_DEBUG) 1168 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ 1169 groupsize, buf, len, ascii) \ 1170 print_hex_dump_debug("DBG[TXRX]" prefix_str,\ 1171 prefix_type, rowsize, \ 1172 groupsize, buf, len, ascii) 1173 1174 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \ 1175 groupsize, buf, len, ascii) \ 1176 print_hex_dump_debug("DBG[ WMI]" prefix_str,\ 1177 prefix_type, rowsize, \ 1178 groupsize, buf, len, ascii) 1179 1180 #define wil_hex_dump_misc(prefix_str, prefix_type, rowsize, \ 1181 groupsize, buf, len, ascii) \ 1182 print_hex_dump_debug("DBG[MISC]" prefix_str,\ 1183 prefix_type, rowsize, \ 1184 groupsize, buf, len, ascii) 1185 #else /* defined(CONFIG_DYNAMIC_DEBUG) */ 1186 static inline 1187 void wil_hex_dump_txrx(const char *prefix_str, int prefix_type, int rowsize, 1188 int groupsize, const void *buf, size_t len, bool ascii) 1189 { 1190 } 1191 1192 static inline 1193 void wil_hex_dump_wmi(const char *prefix_str, int prefix_type, int rowsize, 1194 int groupsize, const void *buf, size_t len, bool ascii) 1195 { 1196 } 1197 1198 static inline 1199 void wil_hex_dump_misc(const char *prefix_str, int prefix_type, int rowsize, 1200 int groupsize, const void *buf, size_t len, bool ascii) 1201 { 1202 } 1203 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */ 1204 1205 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 1206 size_t count); 1207 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 1208 size_t count); 1209 int wil_mem_access_lock(struct wil6210_priv *wil); 1210 void wil_mem_access_unlock(struct wil6210_priv *wil); 1211 1212 struct wil6210_vif * 1213 wil_vif_alloc(struct wil6210_priv *wil, const char *name, 1214 unsigned char name_assign_type, enum nl80211_iftype iftype); 1215 void wil_vif_free(struct wil6210_vif *vif); 1216 void *wil_if_alloc(struct device *dev); 1217 bool wil_has_other_active_ifaces(struct wil6210_priv *wil, 1218 struct net_device *ndev, bool up, bool ok); 1219 bool wil_has_active_ifaces(struct wil6210_priv *wil, bool up, bool ok); 1220 void wil_if_free(struct wil6210_priv *wil); 1221 int wil_vif_add(struct wil6210_priv *wil, struct wil6210_vif *vif); 1222 int wil_if_add(struct wil6210_priv *wil); 1223 void wil_vif_remove(struct wil6210_priv *wil, u8 mid); 1224 void wil_if_remove(struct wil6210_priv *wil); 1225 int wil_priv_init(struct wil6210_priv *wil); 1226 void wil_priv_deinit(struct wil6210_priv *wil); 1227 int wil_ps_update(struct wil6210_priv *wil, 1228 enum wmi_ps_profile_type ps_profile); 1229 int wil_reset(struct wil6210_priv *wil, bool no_fw); 1230 void wil_fw_error_recovery(struct wil6210_priv *wil); 1231 void wil_set_recovery_state(struct wil6210_priv *wil, int state); 1232 bool wil_is_recovery_blocked(struct wil6210_priv *wil); 1233 int wil_up(struct wil6210_priv *wil); 1234 int __wil_up(struct wil6210_priv *wil); 1235 int wil_down(struct wil6210_priv *wil); 1236 int __wil_down(struct wil6210_priv *wil); 1237 void wil_refresh_fw_capabilities(struct wil6210_priv *wil); 1238 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r); 1239 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac); 1240 int wil_find_cid_by_idx(struct wil6210_priv *wil, u8 mid, int idx); 1241 void wil_set_ethtoolops(struct net_device *ndev); 1242 1243 struct fw_map *wil_find_fw_mapping(const char *section); 1244 void __iomem *wmi_buffer_block(struct wil6210_priv *wil, __le32 ptr, u32 size); 1245 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr); 1246 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr); 1247 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr, 1248 struct wil6210_mbox_hdr *hdr); 1249 int wmi_send(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len); 1250 void wmi_recv_cmd(struct wil6210_priv *wil); 1251 int wmi_call(struct wil6210_priv *wil, u16 cmdid, u8 mid, void *buf, u16 len, 1252 u16 reply_id, void *reply, u16 reply_size, int to_msec); 1253 void wmi_event_worker(struct work_struct *work); 1254 void wmi_event_flush(struct wil6210_priv *wil); 1255 int wmi_set_ssid(struct wil6210_vif *vif, u8 ssid_len, const void *ssid); 1256 int wmi_get_ssid(struct wil6210_vif *vif, u8 *ssid_len, void *ssid); 1257 int wmi_set_channel(struct wil6210_priv *wil, int channel); 1258 int wmi_get_channel(struct wil6210_priv *wil, int *channel); 1259 int wmi_del_cipher_key(struct wil6210_vif *vif, u8 key_index, 1260 const void *mac_addr, int key_usage); 1261 int wmi_add_cipher_key(struct wil6210_vif *vif, u8 key_index, 1262 const void *mac_addr, int key_len, const void *key, 1263 int key_usage); 1264 int wmi_echo(struct wil6210_priv *wil); 1265 int wmi_set_ie(struct wil6210_vif *vif, u8 type, u16 ie_len, const void *ie); 1266 int wmi_rx_chain_add(struct wil6210_priv *wil, struct wil_ring *vring); 1267 int wmi_update_ft_ies(struct wil6210_vif *vif, u16 ie_len, const void *ie); 1268 int wmi_rxon(struct wil6210_priv *wil, bool on); 1269 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r); 1270 int wmi_get_all_temperatures(struct wil6210_priv *wil, 1271 struct wmi_temp_sense_all_done_event 1272 *sense_all_evt); 1273 int wmi_disconnect_sta(struct wil6210_vif *vif, const u8 *mac, u16 reason, 1274 bool del_sta); 1275 int wmi_addba(struct wil6210_priv *wil, u8 mid, 1276 u8 ringid, u8 size, u16 timeout); 1277 int wmi_delba_tx(struct wil6210_priv *wil, u8 mid, u8 ringid, u16 reason); 1278 int wmi_delba_rx(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, u16 reason); 1279 int wmi_addba_rx_resp(struct wil6210_priv *wil, 1280 u8 mid, u8 cid, u8 tid, u8 token, 1281 u16 status, bool amsdu, u16 agg_wsize, u16 timeout); 1282 int wmi_ps_dev_profile_cfg(struct wil6210_priv *wil, 1283 enum wmi_ps_profile_type ps_profile); 1284 int wmi_set_mgmt_retry(struct wil6210_priv *wil, u8 retry_short); 1285 int wmi_get_mgmt_retry(struct wil6210_priv *wil, u8 *retry_short); 1286 int wmi_new_sta(struct wil6210_vif *vif, const u8 *mac, u8 aid); 1287 int wmi_port_allocate(struct wil6210_priv *wil, u8 mid, 1288 const u8 *mac, enum nl80211_iftype iftype); 1289 int wmi_port_delete(struct wil6210_priv *wil, u8 mid); 1290 int wmi_link_stats_cfg(struct wil6210_vif *vif, u32 type, u8 cid, u32 interval); 1291 int wil_addba_rx_request(struct wil6210_priv *wil, u8 mid, u8 cid, u8 tid, 1292 u8 dialog_token, __le16 ba_param_set, 1293 __le16 ba_timeout, __le16 ba_seq_ctrl); 1294 int wil_addba_tx_request(struct wil6210_priv *wil, u8 ringid, u16 wsize); 1295 1296 void wil6210_clear_irq(struct wil6210_priv *wil); 1297 int wil6210_init_irq(struct wil6210_priv *wil, int irq); 1298 void wil6210_fini_irq(struct wil6210_priv *wil, int irq); 1299 void wil_mask_irq(struct wil6210_priv *wil); 1300 void wil_unmask_irq(struct wil6210_priv *wil); 1301 void wil_configure_interrupt_moderation(struct wil6210_priv *wil); 1302 void wil_disable_irq(struct wil6210_priv *wil); 1303 void wil_enable_irq(struct wil6210_priv *wil); 1304 void wil6210_mask_halp(struct wil6210_priv *wil); 1305 1306 /* P2P */ 1307 bool wil_p2p_is_social_scan(struct cfg80211_scan_request *request); 1308 int wil_p2p_search(struct wil6210_vif *vif, 1309 struct cfg80211_scan_request *request); 1310 int wil_p2p_listen(struct wil6210_priv *wil, struct wireless_dev *wdev, 1311 unsigned int duration, struct ieee80211_channel *chan, 1312 u64 *cookie); 1313 u8 wil_p2p_stop_discovery(struct wil6210_vif *vif); 1314 int wil_p2p_cancel_listen(struct wil6210_vif *vif, u64 cookie); 1315 void wil_p2p_listen_expired(struct work_struct *work); 1316 void wil_p2p_search_expired(struct work_struct *work); 1317 void wil_p2p_stop_radio_operations(struct wil6210_priv *wil); 1318 void wil_p2p_delayed_listen_work(struct work_struct *work); 1319 1320 /* WMI for P2P */ 1321 int wmi_p2p_cfg(struct wil6210_vif *vif, int channel, int bi); 1322 int wmi_start_listen(struct wil6210_vif *vif); 1323 int wmi_start_search(struct wil6210_vif *vif); 1324 int wmi_stop_discovery(struct wil6210_vif *vif); 1325 1326 int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev, 1327 struct cfg80211_mgmt_tx_params *params, 1328 u64 *cookie); 1329 void wil_cfg80211_ap_recovery(struct wil6210_priv *wil); 1330 int wil_cfg80211_iface_combinations_from_fw( 1331 struct wil6210_priv *wil, 1332 const struct wil_fw_record_concurrency *conc); 1333 int wil_vif_prepare_stop(struct wil6210_vif *vif); 1334 1335 #if defined(CONFIG_WIL6210_DEBUGFS) 1336 int wil6210_debugfs_init(struct wil6210_priv *wil); 1337 void wil6210_debugfs_remove(struct wil6210_priv *wil); 1338 #else 1339 static inline int wil6210_debugfs_init(struct wil6210_priv *wil) { return 0; } 1340 static inline void wil6210_debugfs_remove(struct wil6210_priv *wil) {} 1341 #endif 1342 1343 int wil_cid_fill_sinfo(struct wil6210_vif *vif, int cid, 1344 struct station_info *sinfo); 1345 1346 struct wil6210_priv *wil_cfg80211_init(struct device *dev); 1347 void wil_cfg80211_deinit(struct wil6210_priv *wil); 1348 void wil_p2p_wdev_free(struct wil6210_priv *wil); 1349 1350 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr); 1351 int wmi_pcp_start(struct wil6210_vif *vif, int bi, u8 wmi_nettype, u8 chan, 1352 u8 edmg_chan, u8 hidden_ssid, u8 is_go); 1353 int wmi_pcp_stop(struct wil6210_vif *vif); 1354 int wmi_led_cfg(struct wil6210_priv *wil, bool enable); 1355 int wmi_abort_scan(struct wil6210_vif *vif); 1356 void wil_abort_scan(struct wil6210_vif *vif, bool sync); 1357 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync); 1358 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps); 1359 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 1360 u16 reason_code); 1361 void wil6210_disconnect_complete(struct wil6210_vif *vif, const u8 *bssid, 1362 u16 reason_code); 1363 void wil_probe_client_flush(struct wil6210_vif *vif); 1364 void wil_probe_client_worker(struct work_struct *work); 1365 void wil_disconnect_worker(struct work_struct *work); 1366 void wil_enable_tx_key_worker(struct work_struct *work); 1367 1368 void wil_init_txrx_ops(struct wil6210_priv *wil); 1369 1370 /* TX API */ 1371 int wil_ring_init_tx(struct wil6210_vif *vif, int cid); 1372 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size); 1373 int wil_bcast_init(struct wil6210_vif *vif); 1374 void wil_bcast_fini(struct wil6210_vif *vif); 1375 void wil_bcast_fini_all(struct wil6210_priv *wil); 1376 1377 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 1378 struct wil_ring *ring, bool should_stop); 1379 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 1380 struct wil_ring *ring, bool check_stop); 1381 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev); 1382 int wil_tx_complete(struct wil6210_vif *vif, int ringid); 1383 void wil_tx_complete_handle_eapol(struct wil6210_vif *vif, 1384 struct sk_buff *skb); 1385 void wil6210_unmask_irq_tx(struct wil6210_priv *wil); 1386 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil); 1387 1388 /* RX API */ 1389 void wil_rx_handle(struct wil6210_priv *wil, int *quota); 1390 void wil6210_unmask_irq_rx(struct wil6210_priv *wil); 1391 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil); 1392 void wil_set_crypto_rx(u8 key_index, enum wmi_key_usage key_usage, 1393 struct wil_sta_info *cs, 1394 struct key_params *params); 1395 1396 int wil_iftype_nl2wmi(enum nl80211_iftype type); 1397 1398 int wil_request_firmware(struct wil6210_priv *wil, const char *name, 1399 bool load); 1400 int wil_request_board(struct wil6210_priv *wil, const char *name); 1401 bool wil_fw_verify_file_exists(struct wil6210_priv *wil, const char *name); 1402 1403 void wil_pm_runtime_allow(struct wil6210_priv *wil); 1404 void wil_pm_runtime_forbid(struct wil6210_priv *wil); 1405 int wil_pm_runtime_get(struct wil6210_priv *wil); 1406 void wil_pm_runtime_put(struct wil6210_priv *wil); 1407 1408 int wil_can_suspend(struct wil6210_priv *wil, bool is_runtime); 1409 int wil_suspend(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1410 int wil_resume(struct wil6210_priv *wil, bool is_runtime, bool keep_radio_on); 1411 bool wil_is_wmi_idle(struct wil6210_priv *wil); 1412 int wmi_resume(struct wil6210_priv *wil); 1413 int wmi_suspend(struct wil6210_priv *wil); 1414 bool wil_is_tx_idle(struct wil6210_priv *wil); 1415 1416 int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size); 1417 void wil_fw_core_dump(struct wil6210_priv *wil); 1418 1419 void wil_halp_vote(struct wil6210_priv *wil); 1420 void wil_halp_unvote(struct wil6210_priv *wil); 1421 void wil6210_set_halp(struct wil6210_priv *wil); 1422 void wil6210_clear_halp(struct wil6210_priv *wil); 1423 1424 int wmi_start_sched_scan(struct wil6210_priv *wil, 1425 struct cfg80211_sched_scan_request *request); 1426 int wmi_stop_sched_scan(struct wil6210_priv *wil); 1427 int wmi_mgmt_tx(struct wil6210_vif *vif, const u8 *buf, size_t len); 1428 int wmi_mgmt_tx_ext(struct wil6210_vif *vif, const u8 *buf, size_t len, 1429 u8 channel, u16 duration_ms); 1430 int wmi_rbufcap_cfg(struct wil6210_priv *wil, bool enable, u16 threshold); 1431 1432 int wil_wmi2spec_ch(u8 wmi_ch, u8 *spec_ch); 1433 int wil_spec2wmi_ch(u8 spec_ch, u8 *wmi_ch); 1434 void wil_update_supported_bands(struct wil6210_priv *wil); 1435 1436 int reverse_memcmp(const void *cs, const void *ct, size_t count); 1437 1438 /* WMI for enhanced DMA */ 1439 int wil_wmi_tx_sring_cfg(struct wil6210_priv *wil, int ring_id); 1440 int wil_wmi_cfg_def_rx_offload(struct wil6210_priv *wil, 1441 u16 max_rx_pl_per_desc); 1442 int wil_wmi_rx_sring_add(struct wil6210_priv *wil, u16 ring_id); 1443 int wil_wmi_rx_desc_ring_add(struct wil6210_priv *wil, int status_ring_id); 1444 int wil_wmi_tx_desc_ring_add(struct wil6210_vif *vif, int ring_id, int cid, 1445 int tid); 1446 int wil_wmi_bcast_desc_ring_add(struct wil6210_vif *vif, int ring_id); 1447 int wmi_addba_rx_resp_edma(struct wil6210_priv *wil, u8 mid, u8 cid, 1448 u8 tid, u8 token, u16 status, bool amsdu, 1449 u16 agg_wsize, u16 timeout); 1450 1451 void update_supported_bands(struct wil6210_priv *wil); 1452 1453 void wil_clear_fw_log_addr(struct wil6210_priv *wil); 1454 #endif /* __WIL6210_H__ */ 1455