1 /* 2 * Copyright (c) 2012-2016,2018, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef WIL6210_TXRX_EDMA_H 18 #define WIL6210_TXRX_EDMA_H 19 20 #include "wil6210.h" 21 22 /* limit status ring size in range [ring size..max ring size] */ 23 #define WIL_SRING_SIZE_ORDER_MIN (WIL_RING_SIZE_ORDER_MIN) 24 #define WIL_SRING_SIZE_ORDER_MAX (WIL_RING_SIZE_ORDER_MAX) 25 /* RX sring order should be bigger than RX ring order */ 26 #define WIL_RX_SRING_SIZE_ORDER_DEFAULT (11) 27 #define WIL_TX_SRING_SIZE_ORDER_DEFAULT (12) 28 #define WIL_RX_BUFF_ARR_SIZE_DEFAULT (1536) 29 30 #define WIL_DEFAULT_RX_STATUS_RING_ID 0 31 #define WIL_RX_DESC_RING_ID 0 32 #define WIL_RX_STATUS_IRQ_IDX 0 33 #define WIL_TX_STATUS_IRQ_IDX 1 34 35 #define WIL_EDMA_AGG_WATERMARK (0xffff) 36 #define WIL_EDMA_AGG_WATERMARK_POS (16) 37 38 #define WIL_EDMA_IDLE_TIME_LIMIT_USEC (50) 39 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */ 40 41 /* Error field */ 42 #define WIL_RX_EDMA_ERROR_MIC (1) 43 #define WIL_RX_EDMA_ERROR_KEY (2) /* Key missing */ 44 #define WIL_RX_EDMA_ERROR_REPLAY (3) 45 #define WIL_RX_EDMA_ERROR_AMSDU (4) 46 #define WIL_RX_EDMA_ERROR_FCS (7) 47 48 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1)) 49 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1)) 50 51 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11) 52 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK 0x7 53 #define WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK 0xf 54 55 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2 56 #define WIL_RX_EDMA_DLPF_LU_HIT_CID_POS 4 57 58 #define WIL_RX_EDMA_DLPF_LU_MISS_TID_POS 5 59 60 #define WIL_RX_EDMA_MID_VALID_BIT BIT(22) 61 62 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS 16 63 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_LEN 6 64 65 #define WIL_EDMA_DESC_TX_CFG_EOP_POS 0 66 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1 67 68 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS 3 69 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2 70 71 #define WIL_EDMA_DESC_TX_CFG_SEG_EN_POS 5 72 #define WIL_EDMA_DESC_TX_CFG_SEG_EN_LEN 1 73 74 #define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS 6 75 #define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_LEN 1 76 77 #define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS 7 78 #define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_LEN 1 79 80 #define WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS 15 81 #define WIL_EDMA_DESC_TX_CFG_L4_TYPE_LEN 1 82 83 #define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS 5 84 #define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_LEN 1 85 86 /* Enhanced Rx descriptor - MAC part 87 * [dword 0] : Reserved 88 * [dword 1] : Reserved 89 * [dword 2] : Reserved 90 * [dword 3] 91 * bit 0..15 : Buffer ID 92 * bit 16..31 : Reserved 93 */ 94 struct wil_ring_rx_enhanced_mac { 95 u32 d[3]; 96 __le16 buff_id; 97 u16 reserved; 98 } __packed; 99 100 /* Enhanced Rx descriptor - DMA part 101 * [dword 0] - Reserved 102 * [dword 1] 103 * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31 104 * [dword 2] 105 * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47 106 * bit 16..31 : Reserved 107 * [dword 3] 108 * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63 109 * bit 16..31 : length 110 */ 111 struct wil_ring_rx_enhanced_dma { 112 u32 d0; 113 struct wil_ring_dma_addr addr; 114 u16 w5; 115 __le16 addr_high_high; 116 __le16 length; 117 } __packed; 118 119 struct wil_rx_enhanced_desc { 120 struct wil_ring_rx_enhanced_mac mac; 121 struct wil_ring_rx_enhanced_dma dma; 122 } __packed; 123 124 /* Enhanced Tx descriptor - DMA part 125 * [dword 0] 126 * Same as legacy 127 * [dword 1] 128 * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31 129 * [dword 2] 130 * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47 131 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum 132 * offload feature 133 * bit 24..30 : mac_length:7 134 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 135 * [dword 3] 136 * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63 137 * bit 16..31 : length 138 */ 139 struct wil_ring_tx_enhanced_dma { 140 u8 l4_hdr_len; 141 u8 cmd; 142 u16 w1; 143 struct wil_ring_dma_addr addr; 144 u8 ip_length; 145 u8 b11; /* 0..6: mac_length; 7:ip_version */ 146 __le16 addr_high_high; 147 __le16 length; 148 } __packed; 149 150 /* Enhanced Tx descriptor - MAC part 151 * [dword 0] 152 * bit 0.. 9 : lifetime_expiry_value:10 153 * bit 10 : interrupt_en:1 154 * bit 11 : status_en:1 155 * bit 12..13 : txss_override:2 156 * bit 14 : timestamp_insertion:1 157 * bit 15 : duration_preserve:1 158 * bit 16..21 : reserved0:6 159 * bit 22..26 : mcs_index:5 160 * bit 27 : mcs_en:1 161 * bit 28..30 : reserved1:3 162 * bit 31 : sn_preserved:1 163 * [dword 1] 164 * bit 0.. 3 : pkt_mode:4 165 * bit 4 : pkt_mode_en:1 166 * bit 5..14 : reserved0:10 167 * bit 15 : ack_policy_en:1 168 * bit 16..19 : dst_index:4 169 * bit 20 : dst_index_en:1 170 * bit 21..22 : ack_policy:2 171 * bit 23 : lifetime_en:1 172 * bit 24..30 : max_retry:7 173 * bit 31 : max_retry_en:1 174 * [dword 2] 175 * bit 0.. 7 : num_of_descriptors:8 176 * bit 8..17 : reserved:10 177 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11 178 * bit 20 : snap_hdr_insertion_en:1 179 * bit 21 : vlan_removal_en:1 180 * bit 22..23 : reserved0:2 181 * bit 24 : Dest ID extension:1 182 * bit 25..31 : reserved0:7 183 * [dword 3] 184 * bit 0..15 : tso_mss:16 185 * bit 16..31 : descriptor_scratchpad:16 - mailbox between driver and ucode 186 */ 187 struct wil_ring_tx_enhanced_mac { 188 u32 d[3]; 189 __le16 tso_mss; 190 u16 scratchpad; 191 } __packed; 192 193 struct wil_tx_enhanced_desc { 194 struct wil_ring_tx_enhanced_mac mac; 195 struct wil_ring_tx_enhanced_dma dma; 196 } __packed; 197 198 #define TX_STATUS_DESC_READY_POS 7 199 200 /* Enhanced TX status message 201 * [dword 0] 202 * bit 0.. 7 : Number of Descriptor:8 - The number of descriptors that 203 * are used to form the packets. It is needed for WB when 204 * releasing the packet 205 * bit 8..15 : tx_ring_id:8 The transmission ring ID that is related to 206 * the message 207 * bit 16..23 : Status:8 - The TX status Code 208 * 0x0 - A successful transmission 209 * 0x1 - Retry expired 210 * 0x2 - Lifetime Expired 211 * 0x3 - Released 212 * 0x4-0xFF - Reserved 213 * bit 24..30 : Reserved:7 214 * bit 31 : Descriptor Ready bit:1 - It is initiated to 215 * zero by the driver when the ring is created. It is set by the HW 216 * to one for each completed status message. Each wrap around, 217 * the DR bit value is flipped. 218 * [dword 1] 219 * bit 0..31 : timestamp:32 - Set when MPDU is transmitted. 220 * [dword 2] 221 * bit 0.. 4 : MCS:5 - The transmitted MCS value 222 * bit 5 : Reserved:1 223 * bit 6.. 7 : CB mode:2 - 0-DMG 1-EDMG 2-Wide 224 * bit 8..12 : QID:5 - The QID that was used for the transmission 225 * bit 13..15 : Reserved:3 226 * bit 16..20 : Num of MSDUs:5 - Number of MSDUs in the aggregation 227 * bit 21..22 : Reserved:2 228 * bit 23 : Retry:1 - An indication that the transmission was retried 229 * bit 24..31 : TX-Sector:8 - the antenna sector that was used for 230 * transmission 231 * [dword 3] 232 * bit 0..11 : Sequence number:12 - The Sequence Number that was used 233 * for the MPDU transmission 234 * bit 12..31 : Reserved:20 235 */ 236 struct wil_ring_tx_status { 237 u8 num_descriptors; 238 u8 ring_id; 239 u8 status; 240 u8 desc_ready; /* Only the last bit should be set */ 241 u32 timestamp; 242 u32 d2; 243 u16 seq_number; /* Only the first 12 bits */ 244 u16 w7; 245 } __packed; 246 247 /* Enhanced Rx status message - compressed part 248 * [dword 0] 249 * bit 0.. 2 : L2 Rx Status:3 - The L2 packet reception Status 250 * 0-Success, 1-MIC Error, 2-Key Error, 3-Replay Error, 251 * 4-A-MSDU Error, 5-Reserved, 6-Reserved, 7-FCS Error 252 * bit 3.. 4 : L3 Rx Status:2 - Bit0 - L3I - L3 identified and checksum 253 * calculated, Bit1- L3Err - IPv4 Checksum Error 254 * bit 5.. 6 : L4 Rx Status:2 - Bit0 - L4I - L4 identified and checksum 255 * calculated, Bit1- L4Err - TCP/UDP Checksum Error 256 * bit 7 : Reserved:1 257 * bit 8..19 : Flow ID:12 - MSDU flow ID 258 * bit 20..21 : MID:2 - The MAC ID 259 * bit 22 : MID_V:1 - The MAC ID field is valid 260 * bit 23 : L3T:1 - IP types: 0-IPv6, 1-IPv4 261 * bit 24 : L4T:1 - Layer 4 Type: 0-UDP, 1-TCP 262 * bit 25 : BC:1 - The received MPDU is broadcast 263 * bit 26 : MC:1 - The received MPDU is multicast 264 * bit 27 : Raw:1 - The MPDU received with no translation 265 * bit 28 : Sec:1 - The FC control (b14) - Frame Protected 266 * bit 29 : Error:1 - An error is set when (L2 status != 0) || 267 * (L3 status == 3) || (L4 status == 3) 268 * bit 30 : EOP:1 - End of MSDU signaling. It is set to mark the end 269 * of the transfer, otherwise the status indicates buffer 270 * only completion. 271 * bit 31 : Descriptor Ready bit:1 - It is initiated to 272 * zero by the driver when the ring is created. It is set 273 * by the HW to one for each completed status message. 274 * Each wrap around, the DR bit value is flipped. 275 * [dword 1] 276 * bit 0.. 5 : MAC Len:6 - The number of bytes that are used for L2 header 277 * bit 6..11 : IPLEN:6 - The number of DW that are used for L3 header 278 * bit 12..15 : I4Len:4 - The number of DW that are used for L4 header 279 * bit 16..21 : MCS:6 - The received MCS field from the PLCP Header 280 * bit 22..23 : CB mode:2 - The CB Mode: 0-DMG, 1-EDMG, 2-Wide 281 * bit 24..27 : Data Offset:4 - The data offset, a code that describe the 282 * payload shift from the beginning of the buffer: 283 * 0 - 0 Bytes, 3 - 2 Bytes 284 * bit 28 : A-MSDU Present:1 - The QoS (b7) A-MSDU present field 285 * bit 29 : A-MSDU Type:1 The QoS (b8) A-MSDU Type field 286 * bit 30 : A-MPDU:1 - Packet is part of aggregated MPDU 287 * bit 31 : Key ID:1 - The extracted Key ID from the encryption header 288 * [dword 2] 289 * bit 0..15 : Buffer ID:16 - The Buffer Identifier 290 * bit 16..31 : Length:16 - It indicates the valid bytes that are stored 291 * in the current descriptor buffer. For multiple buffer 292 * descriptor, SW need to sum the total descriptor length 293 * in all buffers to produce the packet length 294 * [dword 3] 295 * bit 0..31 : timestamp:32 - The MPDU Timestamp. 296 */ 297 struct wil_rx_status_compressed { 298 u32 d0; 299 u32 d1; 300 __le16 buff_id; 301 __le16 length; 302 u32 timestamp; 303 } __packed; 304 305 /* Enhanced Rx status message - extension part 306 * [dword 0] 307 * bit 0.. 4 : QID:5 - The Queue Identifier that the packet is received 308 * from 309 * bit 5.. 7 : Reserved:3 310 * bit 8..11 : TID:4 - The QoS (b3-0) TID Field 311 * bit 12..15 Source index:4 - The Source index that was found 312 during Parsing the TA. This field is used to define the 313 source of the packet 314 * bit 16..18 : Destination index:3 - The Destination index that 315 was found during Parsing the RA. 316 * bit 19..20 : DS Type:2 - The FC Control (b9-8) - From / To DS 317 * bit 21..22 : MIC ICR:2 - this signal tells the DMA to assert an 318 interrupt after it writes the packet 319 * bit 23 : ESOP:1 - The QoS (b4) ESOP field 320 * bit 24 : RDG:1 321 * bit 25..31 : Reserved:7 322 * [dword 1] 323 * bit 0.. 1 : Frame Type:2 - The FC Control (b3-2) - MPDU Type 324 (management, data, control and extension) 325 * bit 2.. 5 : Syb type:4 - The FC Control (b7-4) - Frame Subtype 326 * bit 6..11 : Ext sub type:6 - The FC Control (b11-8) - Frame Extended 327 * Subtype 328 * bit 12..13 : ACK Policy:2 - The QoS (b6-5) ACK Policy fields 329 * bit 14 : DECRYPT_BYP:1 - The MPDU is bypass by the decryption unit 330 * bit 15..23 : Reserved:9 331 * bit 24..31 : RSSI/SNR:8 - The RSSI / SNR measurement for the received 332 * MPDU 333 * [dword 2] 334 * bit 0..11 : SN:12 - The received Sequence number field 335 * bit 12..15 : Reserved:4 336 * bit 16..31 : PN bits [15:0]:16 337 * [dword 3] 338 * bit 0..31 : PN bits [47:16]:32 339 */ 340 struct wil_rx_status_extension { 341 u32 d0; 342 u32 d1; 343 __le16 seq_num; /* only lower 12 bits */ 344 u16 pn_15_0; 345 u32 pn_47_16; 346 } __packed; 347 348 struct wil_rx_status_extended { 349 struct wil_rx_status_compressed comp; 350 struct wil_rx_status_extension ext; 351 } __packed; 352 353 static inline void *wil_skb_rxstatus(struct sk_buff *skb) 354 { 355 return (void *)skb->cb; 356 } 357 358 static inline __le16 wil_rx_status_get_length(void *msg) 359 { 360 return ((struct wil_rx_status_compressed *)msg)->length; 361 } 362 363 static inline u8 wil_rx_status_get_mcs(void *msg) 364 { 365 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1, 366 16, 21); 367 } 368 369 static inline u16 wil_rx_status_get_flow_id(void *msg) 370 { 371 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 372 8, 19); 373 } 374 375 static inline u8 wil_rx_status_get_mcast(void *msg) 376 { 377 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 378 26, 26); 379 } 380 381 /** 382 * In case of DLPF miss the parsing of flow Id should be as follows: 383 * dest_id:2 384 * src_id :3 - cid 385 * tid:3 386 * Otherwise: 387 * tid:4 388 * cid:4 389 */ 390 391 static inline u8 wil_rx_status_get_cid(void *msg) 392 { 393 u16 val = wil_rx_status_get_flow_id(msg); 394 395 if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT) 396 /* CID is in bits 2..4 */ 397 return (val >> WIL_RX_EDMA_DLPF_LU_MISS_CID_POS) & 398 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK; 399 else 400 /* CID is in bits 4..7 */ 401 return (val >> WIL_RX_EDMA_DLPF_LU_HIT_CID_POS) & 402 WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK; 403 } 404 405 static inline u8 wil_rx_status_get_tid(void *msg) 406 { 407 u16 val = wil_rx_status_get_flow_id(msg); 408 409 if (val & WIL_RX_EDMA_DLPF_LU_MISS_BIT) 410 /* TID is in bits 5..7 */ 411 return (val >> WIL_RX_EDMA_DLPF_LU_MISS_TID_POS) & 412 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK; 413 else 414 /* TID is in bits 0..3 */ 415 return val & WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK; 416 } 417 418 static inline int wil_rx_status_get_desc_rdy_bit(void *msg) 419 { 420 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 421 31, 31); 422 } 423 424 static inline int wil_rx_status_get_eop(void *msg) /* EoP = End of Packet */ 425 { 426 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 427 30, 30); 428 } 429 430 static inline __le16 wil_rx_status_get_buff_id(void *msg) 431 { 432 return ((struct wil_rx_status_compressed *)msg)->buff_id; 433 } 434 435 static inline u8 wil_rx_status_get_data_offset(void *msg) 436 { 437 u8 val = WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1, 438 24, 27); 439 440 switch (val) { 441 case 0: return 0; 442 case 3: return 2; 443 default: return 0xFF; 444 } 445 } 446 447 static inline int wil_rx_status_get_frame_type(struct wil6210_priv *wil, 448 void *msg) 449 { 450 if (wil->use_compressed_rx_status) 451 return IEEE80211_FTYPE_DATA; 452 453 return WIL_GET_BITS(((struct wil_rx_status_extended *)msg)->ext.d1, 454 0, 1) << 2; 455 } 456 457 static inline int wil_rx_status_get_fc1(struct wil6210_priv *wil, void *msg) 458 { 459 if (wil->use_compressed_rx_status) 460 return 0; 461 462 return WIL_GET_BITS(((struct wil_rx_status_extended *)msg)->ext.d1, 463 0, 5) << 2; 464 } 465 466 static inline __le16 wil_rx_status_get_seq(struct wil6210_priv *wil, void *msg) 467 { 468 if (wil->use_compressed_rx_status) 469 return 0; 470 471 return ((struct wil_rx_status_extended *)msg)->ext.seq_num; 472 } 473 474 static inline u8 wil_rx_status_get_retry(void *msg) 475 { 476 /* retry bit is missing in EDMA HW. return 1 to be on the safe side */ 477 return 1; 478 } 479 480 static inline int wil_rx_status_get_mid(void *msg) 481 { 482 if (!(((struct wil_rx_status_compressed *)msg)->d0 & 483 WIL_RX_EDMA_MID_VALID_BIT)) 484 return 0; /* use the default MID */ 485 486 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 487 20, 21); 488 } 489 490 static inline int wil_rx_status_get_error(void *msg) 491 { 492 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 493 29, 29); 494 } 495 496 static inline int wil_rx_status_get_l2_rx_status(void *msg) 497 { 498 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 499 0, 2); 500 } 501 502 static inline int wil_rx_status_get_l3_rx_status(void *msg) 503 { 504 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 505 3, 4); 506 } 507 508 static inline int wil_rx_status_get_l4_rx_status(void *msg) 509 { 510 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 511 5, 6); 512 } 513 514 static inline int wil_rx_status_get_security(void *msg) 515 { 516 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d0, 517 28, 28); 518 } 519 520 static inline u8 wil_rx_status_get_key_id(void *msg) 521 { 522 return WIL_GET_BITS(((struct wil_rx_status_compressed *)msg)->d1, 523 31, 31); 524 } 525 526 static inline u8 wil_tx_status_get_mcs(struct wil_ring_tx_status *msg) 527 { 528 return WIL_GET_BITS(msg->d2, 0, 4); 529 } 530 531 static inline u32 wil_ring_next_head(struct wil_ring *ring) 532 { 533 return (ring->swhead + 1) % ring->size; 534 } 535 536 static inline void wil_desc_set_addr_edma(struct wil_ring_dma_addr *addr, 537 __le16 *addr_high_high, 538 dma_addr_t pa) 539 { 540 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); 541 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); 542 *addr_high_high = cpu_to_le16((u16)(upper_32_bits(pa) >> 16)); 543 } 544 545 static inline 546 dma_addr_t wil_tx_desc_get_addr_edma(struct wil_ring_tx_enhanced_dma *dma) 547 { 548 return le32_to_cpu(dma->addr.addr_low) | 549 ((u64)le16_to_cpu(dma->addr.addr_high) << 32) | 550 ((u64)le16_to_cpu(dma->addr_high_high) << 48); 551 } 552 553 static inline 554 dma_addr_t wil_rx_desc_get_addr_edma(struct wil_ring_rx_enhanced_dma *dma) 555 { 556 return le32_to_cpu(dma->addr.addr_low) | 557 ((u64)le16_to_cpu(dma->addr.addr_high) << 32) | 558 ((u64)le16_to_cpu(dma->addr_high_high) << 48); 559 } 560 561 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil); 562 int wil_tx_sring_handler(struct wil6210_priv *wil, 563 struct wil_status_ring *sring); 564 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota); 565 void wil_init_txrx_ops_edma(struct wil6210_priv *wil); 566 567 #endif /* WIL6210_TXRX_EDMA_H */ 568 569