110590c6aSGidon Studinski /* 210590c6aSGidon Studinski * Copyright (c) 2012-2016,2018, The Linux Foundation. All rights reserved. 310590c6aSGidon Studinski * 410590c6aSGidon Studinski * Permission to use, copy, modify, and/or distribute this software for any 510590c6aSGidon Studinski * purpose with or without fee is hereby granted, provided that the above 610590c6aSGidon Studinski * copyright notice and this permission notice appear in all copies. 710590c6aSGidon Studinski * 810590c6aSGidon Studinski * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 910590c6aSGidon Studinski * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1010590c6aSGidon Studinski * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1110590c6aSGidon Studinski * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1210590c6aSGidon Studinski * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1310590c6aSGidon Studinski * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1410590c6aSGidon Studinski * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1510590c6aSGidon Studinski */ 1610590c6aSGidon Studinski 1710590c6aSGidon Studinski #ifndef WIL6210_TXRX_EDMA_H 1810590c6aSGidon Studinski #define WIL6210_TXRX_EDMA_H 1910590c6aSGidon Studinski 2010590c6aSGidon Studinski #include "wil6210.h" 2110590c6aSGidon Studinski 2296c93589SGidon Studinski /* limit status ring size in range [ring size..max ring size] */ 2396c93589SGidon Studinski #define WIL_SRING_SIZE_ORDER_MIN (WIL_RING_SIZE_ORDER_MIN) 2496c93589SGidon Studinski #define WIL_SRING_SIZE_ORDER_MAX (WIL_RING_SIZE_ORDER_MAX) 2596c93589SGidon Studinski /* RX sring order should be bigger than RX ring order */ 2696c93589SGidon Studinski #define WIL_RX_SRING_SIZE_ORDER_DEFAULT (11) 2796c93589SGidon Studinski #define WIL_TX_SRING_SIZE_ORDER_DEFAULT (12) 2896c93589SGidon Studinski #define WIL_RX_BUFF_ARR_SIZE_DEFAULT (1536) 2996c93589SGidon Studinski 3096c93589SGidon Studinski #define WIL_DEFAULT_RX_STATUS_RING_ID 0 3196c93589SGidon Studinski #define WIL_RX_DESC_RING_ID 0 3296c93589SGidon Studinski #define WIL_RX_STATUS_IRQ_IDX 0 3396c93589SGidon Studinski #define WIL_TX_STATUS_IRQ_IDX 1 3496c93589SGidon Studinski 3596c93589SGidon Studinski #define WIL_EDMA_AGG_WATERMARK (0xffff) 3696c93589SGidon Studinski #define WIL_EDMA_AGG_WATERMARK_POS (16) 3796c93589SGidon Studinski 3896c93589SGidon Studinski #define WIL_EDMA_IDLE_TIME_LIMIT_USEC (50) 3996c93589SGidon Studinski #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */ 4096c93589SGidon Studinski 4110590c6aSGidon Studinski /* Enhanced Rx descriptor - MAC part 4210590c6aSGidon Studinski * [dword 0] : Reserved 4310590c6aSGidon Studinski * [dword 1] : Reserved 4410590c6aSGidon Studinski * [dword 2] : Reserved 4510590c6aSGidon Studinski * [dword 3] 4610590c6aSGidon Studinski * bit 0..15 : Buffer ID 4710590c6aSGidon Studinski * bit 16..31 : Reserved 4810590c6aSGidon Studinski */ 4910590c6aSGidon Studinski struct wil_ring_rx_enhanced_mac { 5010590c6aSGidon Studinski u32 d[3]; 5110590c6aSGidon Studinski __le16 buff_id; 5210590c6aSGidon Studinski u16 reserved; 5310590c6aSGidon Studinski } __packed; 5410590c6aSGidon Studinski 5510590c6aSGidon Studinski /* Enhanced Rx descriptor - DMA part 5610590c6aSGidon Studinski * [dword 0] - Reserved 5710590c6aSGidon Studinski * [dword 1] 5810590c6aSGidon Studinski * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31 5910590c6aSGidon Studinski * [dword 2] 6010590c6aSGidon Studinski * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47 6110590c6aSGidon Studinski * bit 16..31 : Reserved 6210590c6aSGidon Studinski * [dword 3] 6310590c6aSGidon Studinski * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63 6410590c6aSGidon Studinski * bit 16..31 : length 6510590c6aSGidon Studinski */ 6610590c6aSGidon Studinski struct wil_ring_rx_enhanced_dma { 6710590c6aSGidon Studinski u32 d0; 6810590c6aSGidon Studinski struct wil_ring_dma_addr addr; 6910590c6aSGidon Studinski u16 w5; 7010590c6aSGidon Studinski __le16 addr_high_high; 7110590c6aSGidon Studinski __le16 length; 7210590c6aSGidon Studinski } __packed; 7310590c6aSGidon Studinski 7410590c6aSGidon Studinski struct wil_rx_enhanced_desc { 7510590c6aSGidon Studinski struct wil_ring_rx_enhanced_mac mac; 7610590c6aSGidon Studinski struct wil_ring_rx_enhanced_dma dma; 7710590c6aSGidon Studinski } __packed; 7810590c6aSGidon Studinski 7910590c6aSGidon Studinski /* Enhanced Tx descriptor - DMA part 8010590c6aSGidon Studinski * [dword 0] 8110590c6aSGidon Studinski * Same as legacy 8210590c6aSGidon Studinski * [dword 1] 8310590c6aSGidon Studinski * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31 8410590c6aSGidon Studinski * [dword 2] 8510590c6aSGidon Studinski * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47 8610590c6aSGidon Studinski * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum 8710590c6aSGidon Studinski * offload feature 8810590c6aSGidon Studinski * bit 24..30 : mac_length:7 8910590c6aSGidon Studinski * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6 9010590c6aSGidon Studinski * [dword 3] 9110590c6aSGidon Studinski * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63 9210590c6aSGidon Studinski * bit 16..31 : length 9310590c6aSGidon Studinski */ 9410590c6aSGidon Studinski struct wil_ring_tx_enhanced_dma { 9510590c6aSGidon Studinski u8 l4_hdr_len; 9610590c6aSGidon Studinski u8 cmd; 9710590c6aSGidon Studinski u16 w1; 9810590c6aSGidon Studinski struct wil_ring_dma_addr addr; 9910590c6aSGidon Studinski u8 ip_length; 10010590c6aSGidon Studinski u8 b11; /* 0..6: mac_length; 7:ip_version */ 10110590c6aSGidon Studinski __le16 addr_high_high; 10210590c6aSGidon Studinski __le16 length; 10310590c6aSGidon Studinski } __packed; 10410590c6aSGidon Studinski 10510590c6aSGidon Studinski /* Enhanced Tx descriptor - MAC part 10610590c6aSGidon Studinski * [dword 0] 10710590c6aSGidon Studinski * bit 0.. 9 : lifetime_expiry_value:10 10810590c6aSGidon Studinski * bit 10 : interrupt_en:1 10910590c6aSGidon Studinski * bit 11 : status_en:1 11010590c6aSGidon Studinski * bit 12..13 : txss_override:2 11110590c6aSGidon Studinski * bit 14 : timestamp_insertion:1 11210590c6aSGidon Studinski * bit 15 : duration_preserve:1 11310590c6aSGidon Studinski * bit 16..21 : reserved0:6 11410590c6aSGidon Studinski * bit 22..26 : mcs_index:5 11510590c6aSGidon Studinski * bit 27 : mcs_en:1 11610590c6aSGidon Studinski * bit 28..30 : reserved1:3 11710590c6aSGidon Studinski * bit 31 : sn_preserved:1 11810590c6aSGidon Studinski * [dword 1] 11910590c6aSGidon Studinski * bit 0.. 3 : pkt_mode:4 12010590c6aSGidon Studinski * bit 4 : pkt_mode_en:1 12110590c6aSGidon Studinski * bit 5..14 : reserved0:10 12210590c6aSGidon Studinski * bit 15 : ack_policy_en:1 12310590c6aSGidon Studinski * bit 16..19 : dst_index:4 12410590c6aSGidon Studinski * bit 20 : dst_index_en:1 12510590c6aSGidon Studinski * bit 21..22 : ack_policy:2 12610590c6aSGidon Studinski * bit 23 : lifetime_en:1 12710590c6aSGidon Studinski * bit 24..30 : max_retry:7 12810590c6aSGidon Studinski * bit 31 : max_retry_en:1 12910590c6aSGidon Studinski * [dword 2] 13010590c6aSGidon Studinski * bit 0.. 7 : num_of_descriptors:8 13110590c6aSGidon Studinski * bit 8..17 : reserved:10 13210590c6aSGidon Studinski * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11 13310590c6aSGidon Studinski * bit 20 : snap_hdr_insertion_en:1 13410590c6aSGidon Studinski * bit 21 : vlan_removal_en:1 13510590c6aSGidon Studinski * bit 22..23 : reserved0:2 13610590c6aSGidon Studinski * bit 24 : Dest ID extension:1 13710590c6aSGidon Studinski * bit 25..31 : reserved0:7 13810590c6aSGidon Studinski * [dword 3] 13910590c6aSGidon Studinski * bit 0..15 : tso_mss:16 14010590c6aSGidon Studinski * bit 16..31 : descriptor_scratchpad:16 - mailbox between driver and ucode 14110590c6aSGidon Studinski */ 14210590c6aSGidon Studinski struct wil_ring_tx_enhanced_mac { 14310590c6aSGidon Studinski u32 d[3]; 14410590c6aSGidon Studinski __le16 tso_mss; 14510590c6aSGidon Studinski u16 scratchpad; 14610590c6aSGidon Studinski } __packed; 14710590c6aSGidon Studinski 14810590c6aSGidon Studinski struct wil_tx_enhanced_desc { 14910590c6aSGidon Studinski struct wil_ring_tx_enhanced_mac mac; 15010590c6aSGidon Studinski struct wil_ring_tx_enhanced_dma dma; 15110590c6aSGidon Studinski } __packed; 15210590c6aSGidon Studinski 15310590c6aSGidon Studinski #define TX_STATUS_DESC_READY_POS 7 15410590c6aSGidon Studinski 15510590c6aSGidon Studinski /* Enhanced TX status message 15610590c6aSGidon Studinski * [dword 0] 15710590c6aSGidon Studinski * bit 0.. 7 : Number of Descriptor:8 - The number of descriptors that 15810590c6aSGidon Studinski * are used to form the packets. It is needed for WB when 15910590c6aSGidon Studinski * releasing the packet 16010590c6aSGidon Studinski * bit 8..15 : tx_ring_id:8 The transmission ring ID that is related to 16110590c6aSGidon Studinski * the message 16210590c6aSGidon Studinski * bit 16..23 : Status:8 - The TX status Code 16310590c6aSGidon Studinski * 0x0 - A successful transmission 16410590c6aSGidon Studinski * 0x1 - Retry expired 16510590c6aSGidon Studinski * 0x2 - Lifetime Expired 16610590c6aSGidon Studinski * 0x3 - Released 16710590c6aSGidon Studinski * 0x4-0xFF - Reserved 16810590c6aSGidon Studinski * bit 24..30 : Reserved:7 16910590c6aSGidon Studinski * bit 31 : Descriptor Ready bit:1 - It is initiated to 17010590c6aSGidon Studinski * zero by the driver when the ring is created. It is set by the HW 17110590c6aSGidon Studinski * to one for each completed status message. Each wrap around, 17210590c6aSGidon Studinski * the DR bit value is flipped. 17310590c6aSGidon Studinski * [dword 1] 17410590c6aSGidon Studinski * bit 0..31 : timestamp:32 - Set when MPDU is transmitted. 17510590c6aSGidon Studinski * [dword 2] 17610590c6aSGidon Studinski * bit 0.. 4 : MCS:5 - The transmitted MCS value 17710590c6aSGidon Studinski * bit 5 : Reserved:1 17810590c6aSGidon Studinski * bit 6.. 7 : CB mode:2 - 0-DMG 1-EDMG 2-Wide 17910590c6aSGidon Studinski * bit 8..12 : QID:5 - The QID that was used for the transmission 18010590c6aSGidon Studinski * bit 13..15 : Reserved:3 18110590c6aSGidon Studinski * bit 16..20 : Num of MSDUs:5 - Number of MSDUs in the aggregation 18210590c6aSGidon Studinski * bit 21..22 : Reserved:2 18310590c6aSGidon Studinski * bit 23 : Retry:1 - An indication that the transmission was retried 18410590c6aSGidon Studinski * bit 24..31 : TX-Sector:8 - the antenna sector that was used for 18510590c6aSGidon Studinski * transmission 18610590c6aSGidon Studinski * [dword 3] 18710590c6aSGidon Studinski * bit 0..11 : Sequence number:12 - The Sequence Number that was used 18810590c6aSGidon Studinski * for the MPDU transmission 18910590c6aSGidon Studinski * bit 12..31 : Reserved:20 19010590c6aSGidon Studinski */ 19110590c6aSGidon Studinski struct wil_ring_tx_status { 19210590c6aSGidon Studinski u8 num_descriptors; 19310590c6aSGidon Studinski u8 ring_id; 19410590c6aSGidon Studinski u8 status; 19510590c6aSGidon Studinski u8 desc_ready; /* Only the last bit should be set */ 19610590c6aSGidon Studinski u32 timestamp; 19710590c6aSGidon Studinski u32 d2; 19810590c6aSGidon Studinski u16 seq_number; /* Only the first 12 bits */ 19910590c6aSGidon Studinski u16 w7; 20010590c6aSGidon Studinski } __packed; 20110590c6aSGidon Studinski 20210590c6aSGidon Studinski /* Enhanced Rx status message - compressed part 20310590c6aSGidon Studinski * [dword 0] 20410590c6aSGidon Studinski * bit 0.. 2 : L2 Rx Status:3 - The L2 packet reception Status 20510590c6aSGidon Studinski * 0-Success, 1-MIC Error, 2-Key Error, 3-Replay Error, 20610590c6aSGidon Studinski * 4-A-MSDU Error, 5-Reserved, 6-Reserved, 7-FCS Error 20710590c6aSGidon Studinski * bit 3.. 4 : L3 Rx Status:2 - Bit0 - L3I - L3 identified and checksum 20810590c6aSGidon Studinski * calculated, Bit1- L3Err - IPv4 Checksum Error 20910590c6aSGidon Studinski * bit 5.. 6 : L4 Rx Status:2 - Bit0 - L4I - L4 identified and checksum 21010590c6aSGidon Studinski * calculated, Bit1- L4Err - TCP/UDP Checksum Error 21110590c6aSGidon Studinski * bit 7 : Reserved:1 21210590c6aSGidon Studinski * bit 8..19 : Flow ID:12 - MSDU flow ID 21310590c6aSGidon Studinski * bit 20..21 : MID:2 - The MAC ID 21410590c6aSGidon Studinski * bit 22 : MID_V:1 - The MAC ID field is valid 21510590c6aSGidon Studinski * bit 23 : L3T:1 - IP types: 0-IPv6, 1-IPv4 21610590c6aSGidon Studinski * bit 24 : L4T:1 - Layer 4 Type: 0-UDP, 1-TCP 21710590c6aSGidon Studinski * bit 25 : BC:1 - The received MPDU is broadcast 21810590c6aSGidon Studinski * bit 26 : MC:1 - The received MPDU is multicast 21910590c6aSGidon Studinski * bit 27 : Raw:1 - The MPDU received with no translation 22010590c6aSGidon Studinski * bit 28 : Sec:1 - The FC control (b14) - Frame Protected 22110590c6aSGidon Studinski * bit 29 : Error:1 - An error is set when (L2 status != 0) || 22210590c6aSGidon Studinski * (L3 status == 3) || (L4 status == 3) 22310590c6aSGidon Studinski * bit 30 : EOP:1 - End of MSDU signaling. It is set to mark the end 22410590c6aSGidon Studinski * of the transfer, otherwise the status indicates buffer 22510590c6aSGidon Studinski * only completion. 22610590c6aSGidon Studinski * bit 31 : Descriptor Ready bit:1 - It is initiated to 22710590c6aSGidon Studinski * zero by the driver when the ring is created. It is set 22810590c6aSGidon Studinski * by the HW to one for each completed status message. 22910590c6aSGidon Studinski * Each wrap around, the DR bit value is flipped. 23010590c6aSGidon Studinski * [dword 1] 23110590c6aSGidon Studinski * bit 0.. 5 : MAC Len:6 - The number of bytes that are used for L2 header 23210590c6aSGidon Studinski * bit 6..11 : IPLEN:6 - The number of DW that are used for L3 header 23310590c6aSGidon Studinski * bit 12..15 : I4Len:4 - The number of DW that are used for L4 header 23410590c6aSGidon Studinski * bit 16..21 : MCS:6 - The received MCS field from the PLCP Header 23510590c6aSGidon Studinski * bit 22..23 : CB mode:2 - The CB Mode: 0-DMG, 1-EDMG, 2-Wide 23610590c6aSGidon Studinski * bit 24..27 : Data Offset:4 - The data offset, a code that describe the 23710590c6aSGidon Studinski * payload shift from the beginning of the buffer: 23896c93589SGidon Studinski * 0 - 0 Bytes, 3 - 2 Bytes 23910590c6aSGidon Studinski * bit 28 : A-MSDU Present:1 - The QoS (b7) A-MSDU present field 24010590c6aSGidon Studinski * bit 29 : A-MSDU Type:1 The QoS (b8) A-MSDU Type field 24110590c6aSGidon Studinski * bit 30 : A-MPDU:1 - Packet is part of aggregated MPDU 24210590c6aSGidon Studinski * bit 31 : Key ID:1 - The extracted Key ID from the encryption header 24310590c6aSGidon Studinski * [dword 2] 24410590c6aSGidon Studinski * bit 0..15 : Buffer ID:16 - The Buffer Identifier 24510590c6aSGidon Studinski * bit 16..31 : Length:16 - It indicates the valid bytes that are stored 24610590c6aSGidon Studinski * in the current descriptor buffer. For multiple buffer 24710590c6aSGidon Studinski * descriptor, SW need to sum the total descriptor length 24810590c6aSGidon Studinski * in all buffers to produce the packet length 24910590c6aSGidon Studinski * [dword 3] 25010590c6aSGidon Studinski * bit 0..31 : timestamp:32 - The MPDU Timestamp. 25110590c6aSGidon Studinski */ 25210590c6aSGidon Studinski struct wil_rx_status_compressed { 25310590c6aSGidon Studinski u32 d0; 25410590c6aSGidon Studinski u32 d1; 25510590c6aSGidon Studinski __le16 buff_id; 25610590c6aSGidon Studinski __le16 length; 25710590c6aSGidon Studinski u32 timestamp; 25810590c6aSGidon Studinski } __packed; 25910590c6aSGidon Studinski 26010590c6aSGidon Studinski /* Enhanced Rx status message - extension part 26110590c6aSGidon Studinski * [dword 0] 26210590c6aSGidon Studinski * bit 0.. 4 : QID:5 - The Queue Identifier that the packet is received 26310590c6aSGidon Studinski * from 26410590c6aSGidon Studinski * bit 5.. 7 : Reserved:3 26510590c6aSGidon Studinski * bit 8..11 : TID:4 - The QoS (b3-0) TID Field 26610590c6aSGidon Studinski * bit 12..15 Source index:4 - The Source index that was found 26710590c6aSGidon Studinski during Parsing the TA. This field is used to define the 26810590c6aSGidon Studinski source of the packet 26910590c6aSGidon Studinski * bit 16..18 : Destination index:3 - The Destination index that 27010590c6aSGidon Studinski was found during Parsing the RA. 27110590c6aSGidon Studinski * bit 19..20 : DS Type:2 - The FC Control (b9-8) - From / To DS 27210590c6aSGidon Studinski * bit 21..22 : MIC ICR:2 - this signal tells the DMA to assert an 27310590c6aSGidon Studinski interrupt after it writes the packet 27410590c6aSGidon Studinski * bit 23 : ESOP:1 - The QoS (b4) ESOP field 27510590c6aSGidon Studinski * bit 24 : RDG:1 27610590c6aSGidon Studinski * bit 25..31 : Reserved:7 27710590c6aSGidon Studinski * [dword 1] 27810590c6aSGidon Studinski * bit 0.. 1 : Frame Type:2 - The FC Control (b3-2) - MPDU Type 27910590c6aSGidon Studinski (management, data, control and extension) 28010590c6aSGidon Studinski * bit 2.. 5 : Syb type:4 - The FC Control (b7-4) - Frame Subtype 28110590c6aSGidon Studinski * bit 6..11 : Ext sub type:6 - The FC Control (b11-8) - Frame Extended 28210590c6aSGidon Studinski * Subtype 28310590c6aSGidon Studinski * bit 12..13 : ACK Policy:2 - The QoS (b6-5) ACK Policy fields 28410590c6aSGidon Studinski * bit 14 : DECRYPT_BYP:1 - The MPDU is bypass by the decryption unit 28510590c6aSGidon Studinski * bit 15..23 : Reserved:9 28610590c6aSGidon Studinski * bit 24..31 : RSSI/SNR:8 - The RSSI / SNR measurement for the received 28710590c6aSGidon Studinski * MPDU 28810590c6aSGidon Studinski * [dword 2] 28910590c6aSGidon Studinski * bit 0..11 : SN:12 - The received Sequence number field 29010590c6aSGidon Studinski * bit 12..15 : Reserved:4 29110590c6aSGidon Studinski * bit 16..31 : PN bits [15:0]:16 29210590c6aSGidon Studinski * [dword 3] 29310590c6aSGidon Studinski * bit 0..31 : PN bits [47:16]:32 29410590c6aSGidon Studinski */ 29510590c6aSGidon Studinski struct wil_rx_status_extension { 29610590c6aSGidon Studinski u32 d0; 29710590c6aSGidon Studinski u32 d1; 29810590c6aSGidon Studinski __le16 seq_num; /* only lower 12 bits */ 29910590c6aSGidon Studinski u16 pn_15_0; 30010590c6aSGidon Studinski u32 pn_47_16; 30110590c6aSGidon Studinski } __packed; 30210590c6aSGidon Studinski 30310590c6aSGidon Studinski struct wil_rx_status_extended { 30410590c6aSGidon Studinski struct wil_rx_status_compressed comp; 30510590c6aSGidon Studinski struct wil_rx_status_extension ext; 30610590c6aSGidon Studinski }; 30710590c6aSGidon Studinski 30896c93589SGidon Studinski static inline u32 wil_ring_next_head(struct wil_ring *ring) 30996c93589SGidon Studinski { 31096c93589SGidon Studinski return (ring->swhead + 1) % ring->size; 31196c93589SGidon Studinski } 31296c93589SGidon Studinski 31396c93589SGidon Studinski static inline void wil_desc_set_addr_edma(struct wil_ring_dma_addr *addr, 31496c93589SGidon Studinski __le16 *addr_high_high, 31596c93589SGidon Studinski dma_addr_t pa) 31696c93589SGidon Studinski { 31796c93589SGidon Studinski addr->addr_low = cpu_to_le32(lower_32_bits(pa)); 31896c93589SGidon Studinski addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); 31996c93589SGidon Studinski *addr_high_high = cpu_to_le16((u16)(upper_32_bits(pa) >> 16)); 32096c93589SGidon Studinski } 32196c93589SGidon Studinski 32296c93589SGidon Studinski static inline 32396c93589SGidon Studinski dma_addr_t wil_tx_desc_get_addr_edma(struct wil_ring_tx_enhanced_dma *dma) 32496c93589SGidon Studinski { 32596c93589SGidon Studinski return le32_to_cpu(dma->addr.addr_low) | 32696c93589SGidon Studinski ((u64)le16_to_cpu(dma->addr.addr_high) << 32) | 32796c93589SGidon Studinski ((u64)le16_to_cpu(dma->addr_high_high) << 48); 32896c93589SGidon Studinski } 32996c93589SGidon Studinski 33096c93589SGidon Studinski static inline 33196c93589SGidon Studinski dma_addr_t wil_rx_desc_get_addr_edma(struct wil_ring_rx_enhanced_dma *dma) 33296c93589SGidon Studinski { 33396c93589SGidon Studinski return le32_to_cpu(dma->addr.addr_low) | 33496c93589SGidon Studinski ((u64)le16_to_cpu(dma->addr.addr_high) << 32) | 33596c93589SGidon Studinski ((u64)le16_to_cpu(dma->addr_high_high) << 48); 33696c93589SGidon Studinski } 33796c93589SGidon Studinski 33896c93589SGidon Studinski void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil); 33996c93589SGidon Studinski void wil_init_txrx_ops_edma(struct wil6210_priv *wil); 34096c93589SGidon Studinski 34110590c6aSGidon Studinski #endif /* WIL6210_TXRX_EDMA_H */ 34210590c6aSGidon Studinski 343