1 /* 2 * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/etherdevice.h> 18 #include <linux/moduleparam.h> 19 #include <linux/prefetch.h> 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include "wil6210.h" 25 #include "txrx_edma.h" 26 #include "txrx.h" 27 #include "trace.h" 28 29 #define WIL_EDMA_MAX_DATA_OFFSET (2) 30 /* RX buffer size must be aligned to 4 bytes */ 31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 32 33 static void wil_tx_desc_unmap_edma(struct device *dev, 34 union wil_tx_desc *desc, 35 struct wil_ctx *ctx) 36 { 37 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 38 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 39 u16 dmalen = le16_to_cpu(d->dma.length); 40 41 switch (ctx->mapped_as) { 42 case wil_mapped_as_single: 43 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 44 break; 45 case wil_mapped_as_page: 46 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 47 break; 48 default: 49 break; 50 } 51 } 52 53 static int wil_find_free_sring(struct wil6210_priv *wil) 54 { 55 int i; 56 57 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 58 if (!wil->srings[i].va) 59 return i; 60 } 61 62 return -EINVAL; 63 } 64 65 static void wil_sring_free(struct wil6210_priv *wil, 66 struct wil_status_ring *sring) 67 { 68 struct device *dev = wil_to_dev(wil); 69 size_t sz; 70 71 if (!sring || !sring->va) 72 return; 73 74 sz = sring->elem_size * sring->size; 75 76 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 77 sz, sring->va, &sring->pa); 78 79 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 80 sring->pa = 0; 81 sring->va = NULL; 82 } 83 84 static int wil_sring_alloc(struct wil6210_priv *wil, 85 struct wil_status_ring *sring) 86 { 87 struct device *dev = wil_to_dev(wil); 88 size_t sz = sring->elem_size * sring->size; 89 90 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 91 92 if (sz == 0) { 93 wil_err(wil, "Cannot allocate a zero size status ring\n"); 94 return -EINVAL; 95 } 96 97 sring->swhead = 0; 98 99 /* Status messages are allocated and initialized to 0. This is necessary 100 * since DR bit should be initialized to 0. 101 */ 102 sring->va = dma_zalloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 103 if (!sring->va) 104 return -ENOMEM; 105 106 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 107 &sring->pa); 108 109 return 0; 110 } 111 112 static int wil_tx_init_edma(struct wil6210_priv *wil) 113 { 114 int ring_id = wil_find_free_sring(wil); 115 struct wil_status_ring *sring; 116 int rc; 117 u16 status_ring_size; 118 119 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 120 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 121 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 122 123 status_ring_size = 1 << wil->tx_status_ring_order; 124 125 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 126 status_ring_size, ring_id); 127 128 if (ring_id < 0) 129 return ring_id; 130 131 /* Allocate Tx status ring. Tx descriptor rings will be 132 * allocated on WMI connect event 133 */ 134 sring = &wil->srings[ring_id]; 135 136 sring->is_rx = false; 137 sring->size = status_ring_size; 138 sring->elem_size = sizeof(struct wil_ring_tx_status); 139 rc = wil_sring_alloc(wil, sring); 140 if (rc) 141 return rc; 142 143 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 144 if (rc) 145 goto out_free; 146 147 sring->desc_rdy_pol = 1; 148 wil->tx_sring_idx = ring_id; 149 150 return 0; 151 out_free: 152 wil_sring_free(wil, sring); 153 return rc; 154 } 155 156 /** 157 * Allocate one skb for Rx descriptor RING 158 */ 159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 160 struct wil_ring *ring, u32 i) 161 { 162 struct device *dev = wil_to_dev(wil); 163 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 164 dma_addr_t pa; 165 u16 buff_id; 166 struct list_head *active = &wil->rx_buff_mgmt.active; 167 struct list_head *free = &wil->rx_buff_mgmt.free; 168 struct wil_rx_buff *rx_buff; 169 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 170 struct sk_buff *skb; 171 struct wil_rx_enhanced_desc dd, *d = ⅆ 172 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 173 &ring->va[i].rx.enhanced; 174 175 if (unlikely(list_empty(free))) { 176 wil->rx_buff_mgmt.free_list_empty_cnt++; 177 return -EAGAIN; 178 } 179 180 skb = dev_alloc_skb(sz); 181 if (unlikely(!skb)) 182 return -ENOMEM; 183 184 skb_put(skb, sz); 185 186 /** 187 * Make sure that the network stack calculates checksum for packets 188 * which failed the HW checksum calculation 189 */ 190 skb->ip_summed = CHECKSUM_NONE; 191 192 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 193 if (unlikely(dma_mapping_error(dev, pa))) { 194 kfree_skb(skb); 195 return -ENOMEM; 196 } 197 198 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 199 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 200 buff_id = rx_buff->id; 201 202 /* Move a buffer from the free list to the active list */ 203 list_move(&rx_buff->list, active); 204 205 buff_arr[buff_id].skb = skb; 206 207 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 208 d->dma.length = cpu_to_le16(sz); 209 d->mac.buff_id = cpu_to_le16(buff_id); 210 *_d = *d; 211 212 /* Save the physical address in skb->cb for later use in dma_unmap */ 213 memcpy(skb->cb, &pa, sizeof(pa)); 214 215 return 0; 216 } 217 218 static inline 219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg) 220 { 221 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)), 222 sring->elem_size); 223 } 224 225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 226 { 227 sring->swhead = (sring->swhead + 1) % sring->size; 228 if (sring->swhead == 0) 229 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 230 } 231 232 static int wil_rx_refill_edma(struct wil6210_priv *wil) 233 { 234 struct wil_ring *ring = &wil->ring_rx; 235 u32 next_head; 236 int rc = 0; 237 u32 swtail = *ring->edma_rx_swtail.va; 238 239 for (; next_head = wil_ring_next_head(ring), (next_head != swtail); 240 ring->swhead = next_head) { 241 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 242 if (unlikely(rc)) { 243 if (rc == -EAGAIN) 244 wil_dbg_txrx(wil, "No free buffer ID found\n"); 245 else 246 wil_err_ratelimited(wil, 247 "Error %d in refill desc[%d]\n", 248 rc, ring->swhead); 249 break; 250 } 251 } 252 253 /* make sure all writes to descriptors (shared memory) are done before 254 * committing them to HW 255 */ 256 wmb(); 257 258 wil_w(wil, ring->hwtail, ring->swhead); 259 260 return rc; 261 } 262 263 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 264 struct wil_ring *ring) 265 { 266 struct device *dev = wil_to_dev(wil); 267 u32 next_tail; 268 u32 swhead = (ring->swhead + 1) % ring->size; 269 dma_addr_t pa; 270 u16 dmalen; 271 272 for (; next_tail = wil_ring_next_tail(ring), (next_tail != swhead); 273 ring->swtail = next_tail) { 274 struct wil_rx_enhanced_desc dd, *d = ⅆ 275 struct wil_rx_enhanced_desc *_d = 276 (struct wil_rx_enhanced_desc *) 277 &ring->va[ring->swtail].rx.enhanced; 278 struct sk_buff *skb; 279 u16 buff_id; 280 281 *d = *_d; 282 pa = wil_rx_desc_get_addr_edma(&d->dma); 283 dmalen = le16_to_cpu(d->dma.length); 284 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE); 285 286 /* Extract the SKB from the rx_buff management array */ 287 buff_id = __le16_to_cpu(d->mac.buff_id); 288 if (buff_id >= wil->rx_buff_mgmt.size) { 289 wil_err(wil, "invalid buff_id %d\n", buff_id); 290 continue; 291 } 292 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 293 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 294 if (unlikely(!skb)) 295 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 296 else 297 kfree_skb(skb); 298 299 /* Move the buffer from the active to the free list */ 300 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 301 &wil->rx_buff_mgmt.free); 302 } 303 } 304 305 static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 306 { 307 struct wil_ring *ring = &wil->ring_rx; 308 309 if (!wil->rx_buff_mgmt.buff_arr) 310 return; 311 312 /* Move all the buffers to the free list in case active list is 313 * not empty in order to release all SKBs before deleting the array 314 */ 315 wil_move_all_rx_buff_to_free_list(wil, ring); 316 317 kfree(wil->rx_buff_mgmt.buff_arr); 318 wil->rx_buff_mgmt.buff_arr = NULL; 319 } 320 321 static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 322 size_t size) 323 { 324 struct wil_rx_buff *buff_arr; 325 struct list_head *active = &wil->rx_buff_mgmt.active; 326 struct list_head *free = &wil->rx_buff_mgmt.free; 327 int i; 328 329 wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff), 330 GFP_KERNEL); 331 if (!wil->rx_buff_mgmt.buff_arr) 332 return -ENOMEM; 333 334 /* Set list heads */ 335 INIT_LIST_HEAD(active); 336 INIT_LIST_HEAD(free); 337 338 /* Linkify the list */ 339 buff_arr = wil->rx_buff_mgmt.buff_arr; 340 for (i = 0; i < size; i++) { 341 list_add(&buff_arr[i].list, free); 342 buff_arr[i].id = i; 343 } 344 345 wil->rx_buff_mgmt.size = size; 346 347 return 0; 348 } 349 350 static int wil_init_rx_sring(struct wil6210_priv *wil, 351 u16 status_ring_size, 352 size_t elem_size, 353 u16 ring_id) 354 { 355 struct wil_status_ring *sring = &wil->srings[ring_id]; 356 int rc; 357 358 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", sring->size, 359 ring_id); 360 361 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 362 363 sring->is_rx = true; 364 sring->size = status_ring_size; 365 sring->elem_size = elem_size; 366 rc = wil_sring_alloc(wil, sring); 367 if (rc) 368 return rc; 369 370 rc = wil_wmi_rx_sring_add(wil, ring_id); 371 if (rc) 372 goto out_free; 373 374 sring->desc_rdy_pol = 1; 375 376 return 0; 377 out_free: 378 wil_sring_free(wil, sring); 379 return rc; 380 } 381 382 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 383 struct wil_ring *ring) 384 { 385 struct device *dev = wil_to_dev(wil); 386 size_t sz = ring->size * sizeof(ring->va[0]); 387 388 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 389 390 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 391 392 ring->swhead = 0; 393 ring->swtail = 0; 394 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 395 if (!ring->ctx) 396 goto err; 397 398 ring->va = dma_zalloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 399 if (!ring->va) 400 goto err_free_ctx; 401 402 if (ring->is_rx) { 403 sz = sizeof(*ring->edma_rx_swtail.va); 404 ring->edma_rx_swtail.va = 405 dma_zalloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 406 GFP_KERNEL); 407 if (!ring->edma_rx_swtail.va) 408 goto err_free_va; 409 } 410 411 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 412 ring->is_rx ? "RX" : "TX", 413 ring->size, ring->va, &ring->pa, ring->ctx); 414 415 return 0; 416 err_free_va: 417 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 418 (void *)ring->va, ring->pa); 419 ring->va = NULL; 420 err_free_ctx: 421 kfree(ring->ctx); 422 ring->ctx = NULL; 423 err: 424 return -ENOMEM; 425 } 426 427 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 428 { 429 struct device *dev = wil_to_dev(wil); 430 size_t sz; 431 int ring_index = 0; 432 433 if (!ring->va) 434 return; 435 436 sz = ring->size * sizeof(ring->va[0]); 437 438 lockdep_assert_held(&wil->mutex); 439 if (ring->is_rx) { 440 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 441 ring->size, ring->va, 442 &ring->pa, ring->ctx); 443 444 wil_move_all_rx_buff_to_free_list(wil, ring); 445 goto out; 446 } 447 448 /* TX ring */ 449 ring_index = ring - wil->ring_tx; 450 451 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 452 ring_index, ring->size, ring->va, 453 &ring->pa, ring->ctx); 454 455 while (!wil_ring_is_empty(ring)) { 456 struct wil_ctx *ctx; 457 458 struct wil_tx_enhanced_desc dd, *d = ⅆ 459 struct wil_tx_enhanced_desc *_d = 460 (struct wil_tx_enhanced_desc *) 461 &ring->va[ring->swtail].tx.enhanced; 462 463 ctx = &ring->ctx[ring->swtail]; 464 if (!ctx) { 465 wil_dbg_txrx(wil, 466 "ctx(%d) was already completed\n", 467 ring->swtail); 468 ring->swtail = wil_ring_next_tail(ring); 469 continue; 470 } 471 *d = *_d; 472 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 473 if (ctx->skb) 474 dev_kfree_skb_any(ctx->skb); 475 ring->swtail = wil_ring_next_tail(ring); 476 } 477 478 out: 479 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 480 kfree(ring->ctx); 481 ring->pa = 0; 482 ring->va = NULL; 483 ring->ctx = NULL; 484 } 485 486 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 487 int status_ring_id) 488 { 489 struct wil_ring *ring = &wil->ring_rx; 490 int rc; 491 492 wil_dbg_misc(wil, "init RX desc ring\n"); 493 494 ring->size = desc_ring_size; 495 ring->is_rx = true; 496 rc = wil_ring_alloc_desc_ring(wil, ring); 497 if (rc) 498 return rc; 499 500 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 501 if (rc) 502 goto out_free; 503 504 return 0; 505 out_free: 506 wil_ring_free_edma(wil, ring); 507 return rc; 508 } 509 510 static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 511 struct sk_buff *skb, int *tid, 512 int *cid, int *mid, u16 *seq, 513 int *mcast, int *retry) 514 { 515 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 516 517 *tid = wil_rx_status_get_tid(s); 518 *cid = wil_rx_status_get_cid(s); 519 *mid = wil_rx_status_get_mid(s); 520 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 521 *mcast = wil_rx_status_get_mcast(s); 522 *retry = wil_rx_status_get_retry(s); 523 } 524 525 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 526 int *security) 527 { 528 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 529 530 *cid = wil_rx_status_get_cid(s); 531 *security = wil_rx_status_get_security(s); 532 } 533 534 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 535 struct sk_buff *skb) 536 { 537 struct wil_rx_status_extended *st; 538 int cid, tid, key_id, mc; 539 struct wil_sta_info *s; 540 struct wil_tid_crypto_rx *c; 541 struct wil_tid_crypto_rx_single *cc; 542 const u8 *pn; 543 544 /* In HW reorder, HW is responsible for crypto check */ 545 if (wil->use_rx_hw_reordering) 546 return 0; 547 548 st = wil_skb_rxstatus(skb); 549 550 cid = wil_rx_status_get_cid(st); 551 tid = wil_rx_status_get_tid(st); 552 key_id = wil_rx_status_get_key_id(st); 553 mc = wil_rx_status_get_mcast(st); 554 s = &wil->sta[cid]; 555 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 556 cc = &c->key_id[key_id]; 557 pn = (u8 *)&st->ext.pn_15_0; 558 559 if (!cc->key_set) { 560 wil_err_ratelimited(wil, 561 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 562 cid, tid, mc, key_id); 563 return -EINVAL; 564 } 565 566 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 567 wil_err_ratelimited(wil, 568 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 569 cid, tid, mc, key_id, pn, cc->pn); 570 return -EINVAL; 571 } 572 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 573 574 return 0; 575 } 576 577 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 578 { 579 struct wil_status_ring *sring; 580 struct wil_rx_status_extended msg1; 581 void *msg = &msg1; 582 u8 dr_bit; 583 int i; 584 585 for (i = 0; i < wil->num_rx_status_rings; i++) { 586 sring = &wil->srings[i]; 587 if (!sring->va) 588 continue; 589 590 wil_get_next_rx_status_msg(sring, msg); 591 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 592 593 /* Check if there are unhandled RX status messages */ 594 if (dr_bit == sring->desc_rdy_pol) 595 return false; 596 } 597 598 return true; 599 } 600 601 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 602 { 603 wil->rx_buf_len = rx_large_buf ? 604 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 605 } 606 607 static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size) 608 { 609 u16 status_ring_size; 610 struct wil_ring *ring = &wil->ring_rx; 611 int rc; 612 size_t elem_size = wil->use_compressed_rx_status ? 613 sizeof(struct wil_rx_status_compressed) : 614 sizeof(struct wil_rx_status_extended); 615 int i; 616 u16 max_rx_pl_per_desc; 617 618 /* In SW reorder one must use extended status messages */ 619 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 620 wil_err(wil, 621 "compressed RX status cannot be used with SW reorder\n"); 622 return -EINVAL; 623 } 624 625 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 626 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 627 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 628 629 status_ring_size = 1 << wil->rx_status_ring_order; 630 631 wil_dbg_misc(wil, 632 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 633 desc_ring_size, status_ring_size, elem_size); 634 635 wil_rx_buf_len_init_edma(wil); 636 637 max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4); 638 639 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 640 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 641 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 642 643 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 644 wil->num_rx_status_rings); 645 646 rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc); 647 if (rc) 648 return rc; 649 650 /* Allocate status ring */ 651 for (i = 0; i < wil->num_rx_status_rings; i++) { 652 int sring_id = wil_find_free_sring(wil); 653 654 if (sring_id < 0) { 655 rc = -EFAULT; 656 goto err_free_status; 657 } 658 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 659 sring_id); 660 if (rc) 661 goto err_free_status; 662 } 663 664 /* Allocate descriptor ring */ 665 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 666 WIL_DEFAULT_RX_STATUS_RING_ID); 667 if (rc) 668 goto err_free_status; 669 670 if (wil->rx_buff_id_count >= status_ring_size) { 671 wil_info(wil, 672 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 673 wil->rx_buff_id_count, status_ring_size, 674 status_ring_size - 1); 675 wil->rx_buff_id_count = status_ring_size - 1; 676 } 677 678 /* Allocate Rx buffer array */ 679 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 680 if (rc) 681 goto err_free_desc; 682 683 /* Fill descriptor ring with credits */ 684 rc = wil_rx_refill_edma(wil); 685 if (rc) 686 goto err_free_rx_buff_arr; 687 688 return 0; 689 err_free_rx_buff_arr: 690 wil_free_rx_buff_arr(wil); 691 err_free_desc: 692 wil_ring_free_edma(wil, ring); 693 err_free_status: 694 for (i = 0; i < wil->num_rx_status_rings; i++) 695 wil_sring_free(wil, &wil->srings[i]); 696 697 return rc; 698 } 699 700 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 701 int size, int cid, int tid) 702 { 703 struct wil6210_priv *wil = vif_to_wil(vif); 704 int rc; 705 struct wil_ring *ring = &wil->ring_tx[ring_id]; 706 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 707 708 lockdep_assert_held(&wil->mutex); 709 710 wil_dbg_misc(wil, 711 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 712 ring_id, cid, tid, wil->tx_sring_idx); 713 714 wil_tx_data_init(txdata); 715 ring->size = size; 716 rc = wil_ring_alloc_desc_ring(wil, ring); 717 if (rc) 718 goto out; 719 720 wil->ring2cid_tid[ring_id][0] = cid; 721 wil->ring2cid_tid[ring_id][1] = tid; 722 if (!vif->privacy) 723 txdata->dot1x_open = true; 724 725 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 726 if (rc) { 727 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 728 goto out_free; 729 } 730 731 if (txdata->dot1x_open && agg_wsize >= 0) 732 wil_addba_tx_request(wil, ring_id, agg_wsize); 733 734 return 0; 735 out_free: 736 spin_lock_bh(&txdata->lock); 737 txdata->dot1x_open = false; 738 txdata->enabled = 0; 739 spin_unlock_bh(&txdata->lock); 740 wil_ring_free_edma(wil, ring); 741 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; 742 wil->ring2cid_tid[ring_id][1] = 0; 743 744 out: 745 return rc; 746 } 747 748 /* This function is used only for RX SW reorder */ 749 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 750 struct sk_buff *skb, struct wil_net_stats *stats) 751 { 752 u8 ftype; 753 u8 fc1; 754 int mid; 755 int tid; 756 u16 seq; 757 struct wil6210_vif *vif; 758 759 ftype = wil_rx_status_get_frame_type(wil, msg); 760 if (ftype == IEEE80211_FTYPE_DATA) 761 return 0; 762 763 fc1 = wil_rx_status_get_fc1(wil, msg); 764 mid = wil_rx_status_get_mid(msg); 765 tid = wil_rx_status_get_tid(msg); 766 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 767 vif = wil->vifs[mid]; 768 769 if (unlikely(!vif)) { 770 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 771 return -EAGAIN; 772 } 773 774 wil_dbg_txrx(wil, 775 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 776 fc1, mid, cid, tid, seq); 777 if (stats) 778 stats->rx_non_data_frame++; 779 if (wil_is_back_req(fc1)) { 780 wil_dbg_txrx(wil, 781 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 782 mid, cid, tid, seq); 783 wil_rx_bar(wil, vif, cid, tid, seq); 784 } else { 785 u32 sz = wil->use_compressed_rx_status ? 786 sizeof(struct wil_rx_status_compressed) : 787 sizeof(struct wil_rx_status_extended); 788 789 /* print again all info. One can enable only this 790 * without overhead for printing every Rx frame 791 */ 792 wil_dbg_txrx(wil, 793 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 794 fc1, mid, cid, tid, seq); 795 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 796 (const void *)msg, sz, false); 797 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 798 skb->data, skb_headlen(skb), false); 799 } 800 801 return -EAGAIN; 802 } 803 804 static int wil_rx_error_check_edma(struct wil6210_priv *wil, 805 struct sk_buff *skb, 806 struct wil_net_stats *stats) 807 { 808 int error; 809 int l2_rx_status; 810 int l3_rx_status; 811 int l4_rx_status; 812 void *msg = wil_skb_rxstatus(skb); 813 814 error = wil_rx_status_get_error(msg); 815 if (!error) { 816 skb->ip_summed = CHECKSUM_UNNECESSARY; 817 return 0; 818 } 819 820 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 821 if (l2_rx_status != 0) { 822 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 823 l2_rx_status); 824 /* Due to HW issue, KEY error will trigger a MIC error */ 825 if (l2_rx_status & WIL_RX_EDMA_ERROR_MIC) { 826 wil_dbg_txrx(wil, 827 "L2 MIC/KEY error, dropping packet\n"); 828 stats->rx_mic_error++; 829 } 830 if (l2_rx_status & WIL_RX_EDMA_ERROR_KEY) { 831 wil_dbg_txrx(wil, "L2 KEY error, dropping packet\n"); 832 stats->rx_key_error++; 833 } 834 if (l2_rx_status & WIL_RX_EDMA_ERROR_REPLAY) { 835 wil_dbg_txrx(wil, 836 "L2 REPLAY error, dropping packet\n"); 837 stats->rx_replay++; 838 } 839 if (l2_rx_status & WIL_RX_EDMA_ERROR_AMSDU) { 840 wil_dbg_txrx(wil, 841 "L2 AMSDU error, dropping packet\n"); 842 stats->rx_amsdu_error++; 843 } 844 return -EFAULT; 845 } 846 847 l3_rx_status = wil_rx_status_get_l3_rx_status(msg); 848 l4_rx_status = wil_rx_status_get_l4_rx_status(msg); 849 if (!l3_rx_status && !l4_rx_status) 850 skb->ip_summed = CHECKSUM_UNNECESSARY; 851 /* If HW reports bad checksum, let IP stack re-check it 852 * For example, HW don't understand Microsoft IP stack that 853 * mis-calculates TCP checksum - if it should be 0x0, 854 * it writes 0xffff in violation of RFC 1624 855 */ 856 else 857 stats->rx_csum_err++; 858 859 return 0; 860 } 861 862 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 863 struct wil_status_ring *sring) 864 { 865 struct device *dev = wil_to_dev(wil); 866 struct wil_rx_status_extended msg1; 867 void *msg = &msg1; 868 u16 buff_id; 869 struct sk_buff *skb; 870 dma_addr_t pa; 871 struct wil_ring_rx_data *rxdata = &sring->rx_data; 872 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 873 struct wil_net_stats *stats = NULL; 874 u16 dmalen; 875 int cid; 876 bool eop, headstolen; 877 int delta; 878 u8 dr_bit; 879 u8 data_offset; 880 struct wil_rx_status_extended *s; 881 u16 sring_idx = sring - wil->srings; 882 883 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 884 885 again: 886 wil_get_next_rx_status_msg(sring, msg); 887 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 888 889 /* Completed handling all the ready status messages */ 890 if (dr_bit != sring->desc_rdy_pol) 891 return NULL; 892 893 /* Extract the buffer ID from the status message */ 894 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 895 if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) { 896 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 897 buff_id, sring->swhead); 898 wil_sring_advance_swhead(sring); 899 goto again; 900 } 901 902 wil_sring_advance_swhead(sring); 903 904 /* Extract the SKB from the rx_buff management array */ 905 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 906 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 907 if (!skb) { 908 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 909 goto again; 910 } 911 912 memcpy(&pa, skb->cb, sizeof(pa)); 913 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 914 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 915 916 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 917 msg); 918 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 919 buff_id, sring_idx, dmalen); 920 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 921 (const void *)msg, wil->use_compressed_rx_status ? 922 sizeof(struct wil_rx_status_compressed) : 923 sizeof(struct wil_rx_status_extended), false); 924 925 /* Move the buffer from the active list to the free list */ 926 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 927 &wil->rx_buff_mgmt.free); 928 929 eop = wil_rx_status_get_eop(msg); 930 931 cid = wil_rx_status_get_cid(msg); 932 if (unlikely(!wil_val_in_range(cid, 0, WIL6210_MAX_CID))) { 933 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 934 cid, sring->swhead); 935 rxdata->skipping = true; 936 goto skipping; 937 } 938 stats = &wil->sta[cid].stats; 939 940 if (unlikely(skb->len < ETH_HLEN)) { 941 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len); 942 stats->rx_short_frame++; 943 rxdata->skipping = true; 944 goto skipping; 945 } 946 947 if (unlikely(dmalen > sz)) { 948 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 949 stats->rx_large_frame++; 950 rxdata->skipping = true; 951 } 952 953 skipping: 954 /* skipping indicates if a certain SKB should be dropped. 955 * It is set in case there is an error on the current SKB or in case 956 * of RX chaining: as long as we manage to merge the SKBs it will 957 * be false. once we have a bad SKB or we don't manage to merge SKBs 958 * it will be set to the !EOP value of the current SKB. 959 * This guarantees that all the following SKBs until EOP will also 960 * get dropped. 961 */ 962 if (unlikely(rxdata->skipping)) { 963 kfree_skb(skb); 964 if (rxdata->skb) { 965 kfree_skb(rxdata->skb); 966 rxdata->skb = NULL; 967 } 968 rxdata->skipping = !eop; 969 goto again; 970 } 971 972 skb_trim(skb, dmalen); 973 974 prefetch(skb->data); 975 976 if (!rxdata->skb) { 977 rxdata->skb = skb; 978 } else { 979 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 980 &delta))) { 981 kfree_skb_partial(skb, headstolen); 982 } else { 983 wil_err(wil, "failed to merge skbs!\n"); 984 kfree_skb(skb); 985 kfree_skb(rxdata->skb); 986 rxdata->skb = NULL; 987 rxdata->skipping = !eop; 988 goto again; 989 } 990 } 991 992 if (!eop) 993 goto again; 994 995 /* reaching here rxdata->skb always contains a full packet */ 996 skb = rxdata->skb; 997 rxdata->skb = NULL; 998 rxdata->skipping = false; 999 1000 if (stats) { 1001 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1002 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1003 stats->rx_per_mcs[stats->last_mcs_rx]++; 1004 } 1005 1006 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1007 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1008 kfree_skb(skb); 1009 goto again; 1010 } 1011 1012 /* Compensate for the HW data alignment according to the status 1013 * message 1014 */ 1015 data_offset = wil_rx_status_get_data_offset(msg); 1016 if (data_offset == 0xFF || 1017 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1018 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1019 kfree_skb(skb); 1020 goto again; 1021 } 1022 1023 skb_pull(skb, data_offset); 1024 1025 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1026 skb->data, skb_headlen(skb), false); 1027 1028 /* Has to be done after dma_unmap_single as skb->cb is also 1029 * used for holding the pa 1030 */ 1031 s = wil_skb_rxstatus(skb); 1032 memcpy(s, msg, sring->elem_size); 1033 1034 return skb; 1035 } 1036 1037 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1038 { 1039 struct net_device *ndev; 1040 struct wil_ring *ring = &wil->ring_rx; 1041 struct wil_status_ring *sring; 1042 struct sk_buff *skb; 1043 int i; 1044 1045 if (unlikely(!ring->va)) { 1046 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1047 return; 1048 } 1049 wil_dbg_txrx(wil, "rx_handle\n"); 1050 1051 for (i = 0; i < wil->num_rx_status_rings; i++) { 1052 sring = &wil->srings[i]; 1053 if (unlikely(!sring->va)) { 1054 wil_err(wil, 1055 "Rx IRQ while Rx status ring %d not yet initialized\n", 1056 i); 1057 continue; 1058 } 1059 1060 while ((*quota > 0) && 1061 (NULL != (skb = 1062 wil_sring_reap_rx_edma(wil, sring)))) { 1063 (*quota)--; 1064 if (wil->use_rx_hw_reordering) { 1065 void *msg = wil_skb_rxstatus(skb); 1066 int mid = wil_rx_status_get_mid(msg); 1067 struct wil6210_vif *vif = wil->vifs[mid]; 1068 1069 if (unlikely(!vif)) { 1070 wil_dbg_txrx(wil, 1071 "RX desc invalid mid %d", 1072 mid); 1073 kfree_skb(skb); 1074 continue; 1075 } 1076 ndev = vif_to_ndev(vif); 1077 wil_netif_rx_any(skb, ndev); 1078 } else { 1079 wil_rx_reorder(wil, skb); 1080 } 1081 } 1082 1083 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1084 } 1085 1086 wil_rx_refill_edma(wil); 1087 } 1088 1089 static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1090 dma_addr_t pa, 1091 u32 len, 1092 int ring_index) 1093 { 1094 struct wil_tx_enhanced_desc *d = 1095 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1096 1097 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1098 1099 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1100 1101 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1102 d->dma.length = cpu_to_le16((u16)len); 1103 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1104 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1105 * 3 - eth mode 1106 */ 1107 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1108 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1109 1110 return 0; 1111 } 1112 1113 static inline void 1114 wil_get_next_tx_status_msg(struct wil_status_ring *sring, 1115 struct wil_ring_tx_status *msg) 1116 { 1117 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1118 (sring->va + (sring->elem_size * sring->swhead)); 1119 1120 *msg = *_msg; 1121 } 1122 1123 /** 1124 * Clean up transmitted skb's from the Tx descriptor RING. 1125 * Return number of descriptors cleared. 1126 */ 1127 int wil_tx_sring_handler(struct wil6210_priv *wil, 1128 struct wil_status_ring *sring) 1129 { 1130 struct net_device *ndev; 1131 struct device *dev = wil_to_dev(wil); 1132 struct wil_ring *ring = NULL; 1133 struct wil_ring_tx_data *txdata; 1134 /* Total number of completed descriptors in all descriptor rings */ 1135 int desc_cnt = 0; 1136 int cid; 1137 struct wil_net_stats *stats = NULL; 1138 struct wil_tx_enhanced_desc *_d; 1139 unsigned int ring_id; 1140 unsigned int num_descs; 1141 int i; 1142 u8 dr_bit; /* Descriptor Ready bit */ 1143 struct wil_ring_tx_status msg; 1144 struct wil6210_vif *vif; 1145 int used_before_complete; 1146 int used_new; 1147 1148 wil_get_next_tx_status_msg(sring, &msg); 1149 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1150 1151 /* Process completion messages while DR bit has the expected polarity */ 1152 while (dr_bit == sring->desc_rdy_pol) { 1153 num_descs = msg.num_descriptors; 1154 if (!num_descs) { 1155 wil_err(wil, "invalid num_descs 0\n"); 1156 goto again; 1157 } 1158 1159 /* Find the corresponding descriptor ring */ 1160 ring_id = msg.ring_id; 1161 1162 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1163 wil_err(wil, "invalid ring id %d\n", ring_id); 1164 goto again; 1165 } 1166 ring = &wil->ring_tx[ring_id]; 1167 if (unlikely(!ring->va)) { 1168 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1169 ring_id); 1170 goto again; 1171 } 1172 txdata = &wil->ring_tx_data[ring_id]; 1173 if (unlikely(!txdata->enabled)) { 1174 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1175 goto again; 1176 } 1177 vif = wil->vifs[txdata->mid]; 1178 if (unlikely(!vif)) { 1179 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1180 txdata->mid, ring_id); 1181 goto again; 1182 } 1183 1184 ndev = vif_to_ndev(vif); 1185 1186 cid = wil->ring2cid_tid[ring_id][0]; 1187 if (cid < WIL6210_MAX_CID) 1188 stats = &wil->sta[cid].stats; 1189 1190 wil_dbg_txrx(wil, 1191 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1192 ring_id, num_descs); 1193 1194 used_before_complete = wil_ring_used_tx(ring); 1195 1196 for (i = 0 ; i < num_descs; ++i) { 1197 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1198 struct wil_tx_enhanced_desc dd, *d = ⅆ 1199 u16 dmalen; 1200 struct sk_buff *skb = ctx->skb; 1201 1202 _d = (struct wil_tx_enhanced_desc *) 1203 &ring->va[ring->swtail].tx.enhanced; 1204 *d = *_d; 1205 1206 dmalen = le16_to_cpu(d->dma.length); 1207 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1208 wil_dbg_txrx(wil, 1209 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1210 ring_id, ring->swtail, dmalen, 1211 msg.status); 1212 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1213 (const void *)&msg, sizeof(msg), 1214 false); 1215 1216 wil_tx_desc_unmap_edma(dev, 1217 (union wil_tx_desc *)d, 1218 ctx); 1219 1220 if (skb) { 1221 if (likely(msg.status == 0)) { 1222 ndev->stats.tx_packets++; 1223 ndev->stats.tx_bytes += skb->len; 1224 if (stats) { 1225 stats->tx_packets++; 1226 stats->tx_bytes += skb->len; 1227 1228 wil_tx_latency_calc(wil, skb, 1229 &wil->sta[cid]); 1230 } 1231 } else { 1232 ndev->stats.tx_errors++; 1233 if (stats) 1234 stats->tx_errors++; 1235 } 1236 wil_consume_skb(skb, msg.status == 0); 1237 } 1238 memset(ctx, 0, sizeof(*ctx)); 1239 /* Make sure the ctx is zeroed before updating the tail 1240 * to prevent a case where wil_tx_ring will see 1241 * this descriptor as used and handle it before ctx zero 1242 * is completed. 1243 */ 1244 wmb(); 1245 1246 ring->swtail = wil_ring_next_tail(ring); 1247 1248 desc_cnt++; 1249 } 1250 1251 /* performance monitoring */ 1252 used_new = wil_ring_used_tx(ring); 1253 if (wil_val_in_range(wil->ring_idle_trsh, 1254 used_new, used_before_complete)) { 1255 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1256 ring_id, used_before_complete, used_new); 1257 txdata->last_idle = get_cycles(); 1258 } 1259 1260 again: 1261 wil_sring_advance_swhead(sring); 1262 1263 wil_get_next_tx_status_msg(sring, &msg); 1264 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1265 } 1266 1267 /* shall we wake net queues? */ 1268 if (desc_cnt) 1269 wil_update_net_queues(wil, vif, NULL, false); 1270 1271 /* Update the HW tail ptr (RD ptr) */ 1272 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1273 1274 return desc_cnt; 1275 } 1276 1277 /** 1278 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1279 * @skb is used to obtain the protocol and headers length. 1280 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1281 * 2 - middle, 3 - last descriptor. 1282 */ 1283 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1284 int tso_desc_type, bool is_ipv4, 1285 int tcp_hdr_len, 1286 int skb_net_hdr_len, 1287 int mss) 1288 { 1289 /* Number of descriptors */ 1290 d->mac.d[2] |= 1; 1291 /* Maximum Segment Size */ 1292 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1293 /* L4 header len: TCP header length */ 1294 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1295 /* EOP, TSO desc type, Segmentation enable, 1296 * Insert IPv4 and TCP / UDP Checksum 1297 */ 1298 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1299 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1300 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1301 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1302 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1303 /* Calculate pseudo-header */ 1304 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1305 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1306 /* IP Header Length */ 1307 d->dma.ip_length |= skb_net_hdr_len; 1308 /* MAC header length and IP address family*/ 1309 d->dma.b11 |= ETH_HLEN | 1310 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1311 } 1312 1313 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1314 int len, uint i, int tso_desc_type, 1315 skb_frag_t *frag, struct wil_ring *ring, 1316 struct sk_buff *skb, bool is_ipv4, 1317 int tcp_hdr_len, int skb_net_hdr_len, 1318 int mss, int *descs_used) 1319 { 1320 struct device *dev = wil_to_dev(wil); 1321 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1322 &ring->va[i].tx.enhanced; 1323 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1324 int ring_index = ring - wil->ring_tx; 1325 dma_addr_t pa; 1326 1327 if (len == 0) 1328 return 0; 1329 1330 if (!frag) { 1331 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1332 ring->ctx[i].mapped_as = wil_mapped_as_single; 1333 } else { 1334 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1335 ring->ctx[i].mapped_as = wil_mapped_as_page; 1336 } 1337 if (unlikely(dma_mapping_error(dev, pa))) { 1338 wil_err(wil, "TSO: Skb DMA map error\n"); 1339 return -EINVAL; 1340 } 1341 1342 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1343 len, ring_index); 1344 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1345 tcp_hdr_len, 1346 skb_net_hdr_len, mss); 1347 1348 /* hold reference to skb 1349 * to prevent skb release before accounting 1350 * in case of immediate "tx done" 1351 */ 1352 if (tso_desc_type == wil_tso_type_lst) 1353 ring->ctx[i].skb = skb_get(skb); 1354 1355 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1356 (const void *)d, sizeof(*d), false); 1357 1358 *_desc = *d; 1359 (*descs_used)++; 1360 1361 return 0; 1362 } 1363 1364 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1365 struct wil6210_vif *vif, 1366 struct wil_ring *ring, 1367 struct sk_buff *skb) 1368 { 1369 int ring_index = ring - wil->ring_tx; 1370 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1371 int nr_frags = skb_shinfo(skb)->nr_frags; 1372 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1373 int used, avail = wil_ring_avail_tx(ring); 1374 int f, hdrlen, headlen; 1375 int gso_type; 1376 bool is_ipv4; 1377 u32 swhead = ring->swhead; 1378 int descs_used = 0; /* total number of used descriptors */ 1379 int rc = -EINVAL; 1380 int tcp_hdr_len; 1381 int skb_net_hdr_len; 1382 int mss = skb_shinfo(skb)->gso_size; 1383 1384 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1385 ring_index); 1386 1387 if (unlikely(!txdata->enabled)) 1388 return -EINVAL; 1389 1390 if (unlikely(avail < min_desc_required)) { 1391 wil_err_ratelimited(wil, 1392 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1393 ring_index, min_desc_required); 1394 return -ENOMEM; 1395 } 1396 1397 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1398 switch (gso_type) { 1399 case SKB_GSO_TCPV4: 1400 is_ipv4 = true; 1401 break; 1402 case SKB_GSO_TCPV6: 1403 is_ipv4 = false; 1404 break; 1405 default: 1406 return -EINVAL; 1407 } 1408 1409 if (skb->ip_summed != CHECKSUM_PARTIAL) 1410 return -EINVAL; 1411 1412 /* tcp header length and skb network header length are fixed for all 1413 * packet's descriptors - read them once here 1414 */ 1415 tcp_hdr_len = tcp_hdrlen(skb); 1416 skb_net_hdr_len = skb_network_header_len(skb); 1417 1418 /* First descriptor must contain the header only 1419 * Header Length = MAC header len + IP header len + TCP header len 1420 */ 1421 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1422 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1423 hdrlen); 1424 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1425 wil_tso_type_hdr, NULL, ring, skb, 1426 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1427 mss, &descs_used); 1428 if (rc) 1429 return -EINVAL; 1430 1431 /* Second descriptor contains the head */ 1432 headlen = skb_headlen(skb) - hdrlen; 1433 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1434 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1435 (swhead + descs_used) % ring->size, 1436 (nr_frags != 0) ? wil_tso_type_first : 1437 wil_tso_type_lst, NULL, ring, skb, 1438 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1439 mss, &descs_used); 1440 if (rc) 1441 goto mem_error; 1442 1443 /* Rest of the descriptors are from the SKB fragments */ 1444 for (f = 0; f < nr_frags; f++) { 1445 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1446 int len = frag->size; 1447 1448 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1449 len, descs_used); 1450 1451 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1452 (swhead + descs_used) % ring->size, 1453 (f != nr_frags - 1) ? 1454 wil_tso_type_mid : wil_tso_type_lst, 1455 frag, ring, skb, is_ipv4, 1456 tcp_hdr_len, skb_net_hdr_len, 1457 mss, &descs_used); 1458 if (rc) 1459 goto mem_error; 1460 } 1461 1462 /* performance monitoring */ 1463 used = wil_ring_used_tx(ring); 1464 if (wil_val_in_range(wil->ring_idle_trsh, 1465 used, used + descs_used)) { 1466 txdata->idle += get_cycles() - txdata->last_idle; 1467 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1468 ring_index, used, used + descs_used); 1469 } 1470 1471 /* advance swhead */ 1472 wil_ring_advance_head(ring, descs_used); 1473 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1474 1475 /* make sure all writes to descriptors (shared memory) are done before 1476 * committing them to HW 1477 */ 1478 wmb(); 1479 1480 if (wil->tx_latency) 1481 *(ktime_t *)&skb->cb = ktime_get(); 1482 else 1483 memset(skb->cb, 0, sizeof(ktime_t)); 1484 1485 wil_w(wil, ring->hwtail, ring->swhead); 1486 1487 return 0; 1488 1489 mem_error: 1490 while (descs_used > 0) { 1491 struct device *dev = wil_to_dev(wil); 1492 struct wil_ctx *ctx; 1493 int i = (swhead + descs_used - 1) % ring->size; 1494 struct wil_tx_enhanced_desc dd, *d = ⅆ 1495 struct wil_tx_enhanced_desc *_desc = 1496 (struct wil_tx_enhanced_desc *) 1497 &ring->va[i].tx.enhanced; 1498 1499 *d = *_desc; 1500 ctx = &ring->ctx[i]; 1501 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1502 memset(ctx, 0, sizeof(*ctx)); 1503 descs_used--; 1504 } 1505 return rc; 1506 } 1507 1508 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1509 int size) 1510 { 1511 struct wil6210_priv *wil = vif_to_wil(vif); 1512 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1513 int rc; 1514 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1515 1516 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1517 ring_id, wil->tx_sring_idx); 1518 1519 lockdep_assert_held(&wil->mutex); 1520 1521 wil_tx_data_init(txdata); 1522 ring->size = size; 1523 ring->is_rx = false; 1524 rc = wil_ring_alloc_desc_ring(wil, ring); 1525 if (rc) 1526 goto out; 1527 1528 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1529 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1530 if (!vif->privacy) 1531 txdata->dot1x_open = true; 1532 1533 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1534 if (rc) 1535 goto out_free; 1536 1537 return 0; 1538 1539 out_free: 1540 spin_lock_bh(&txdata->lock); 1541 txdata->enabled = 0; 1542 txdata->dot1x_open = false; 1543 spin_unlock_bh(&txdata->lock); 1544 wil_ring_free_edma(wil, ring); 1545 1546 out: 1547 return rc; 1548 } 1549 1550 static void wil_tx_fini_edma(struct wil6210_priv *wil) 1551 { 1552 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1553 1554 wil_dbg_misc(wil, "free TX sring\n"); 1555 1556 wil_sring_free(wil, sring); 1557 } 1558 1559 static void wil_rx_data_free(struct wil_status_ring *sring) 1560 { 1561 if (!sring) 1562 return; 1563 1564 kfree_skb(sring->rx_data.skb); 1565 sring->rx_data.skb = NULL; 1566 } 1567 1568 static void wil_rx_fini_edma(struct wil6210_priv *wil) 1569 { 1570 struct wil_ring *ring = &wil->ring_rx; 1571 int i; 1572 1573 wil_dbg_misc(wil, "rx_fini_edma\n"); 1574 1575 wil_ring_free_edma(wil, ring); 1576 1577 for (i = 0; i < wil->num_rx_status_rings; i++) { 1578 wil_rx_data_free(&wil->srings[i]); 1579 wil_sring_free(wil, &wil->srings[i]); 1580 } 1581 1582 wil_free_rx_buff_arr(wil); 1583 } 1584 1585 void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1586 { 1587 wil->txrx_ops.configure_interrupt_moderation = 1588 wil_configure_interrupt_moderation_edma; 1589 /* TX ops */ 1590 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1591 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1592 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1593 wil->txrx_ops.tx_init = wil_tx_init_edma; 1594 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1595 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1596 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1597 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1598 /* RX ops */ 1599 wil->txrx_ops.rx_init = wil_rx_init_edma; 1600 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1601 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1602 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1603 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1604 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1605 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1606 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1607 } 1608 1609