1 /*
2  * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/etherdevice.h>
18 #include <linux/moduleparam.h>
19 #include <linux/prefetch.h>
20 #include <linux/types.h>
21 #include <linux/list.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include "wil6210.h"
25 #include "txrx_edma.h"
26 #include "txrx.h"
27 #include "trace.h"
28 
29 #define WIL_EDMA_MAX_DATA_OFFSET (2)
30 /* RX buffer size must be aligned to 4 bytes */
31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
32 
33 static void wil_tx_desc_unmap_edma(struct device *dev,
34 				   union wil_tx_desc *desc,
35 				   struct wil_ctx *ctx)
36 {
37 	struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc;
38 	dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma);
39 	u16 dmalen = le16_to_cpu(d->dma.length);
40 
41 	switch (ctx->mapped_as) {
42 	case wil_mapped_as_single:
43 		dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
44 		break;
45 	case wil_mapped_as_page:
46 		dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
47 		break;
48 	default:
49 		break;
50 	}
51 }
52 
53 static int wil_find_free_sring(struct wil6210_priv *wil)
54 {
55 	int i;
56 
57 	for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) {
58 		if (!wil->srings[i].va)
59 			return i;
60 	}
61 
62 	return -EINVAL;
63 }
64 
65 static void wil_sring_free(struct wil6210_priv *wil,
66 			   struct wil_status_ring *sring)
67 {
68 	struct device *dev = wil_to_dev(wil);
69 	size_t sz;
70 
71 	if (!sring || !sring->va)
72 		return;
73 
74 	sz = sring->elem_size * sring->size;
75 
76 	wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n",
77 		     sz, sring->va, &sring->pa);
78 
79 	dma_free_coherent(dev, sz, (void *)sring->va, sring->pa);
80 	sring->pa = 0;
81 	sring->va = NULL;
82 }
83 
84 static int wil_sring_alloc(struct wil6210_priv *wil,
85 			   struct wil_status_ring *sring)
86 {
87 	struct device *dev = wil_to_dev(wil);
88 	size_t sz = sring->elem_size * sring->size;
89 
90 	wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz);
91 
92 	if (sz == 0) {
93 		wil_err(wil, "Cannot allocate a zero size status ring\n");
94 		return -EINVAL;
95 	}
96 
97 	sring->swhead = 0;
98 
99 	/* Status messages are allocated and initialized to 0. This is necessary
100 	 * since DR bit should be initialized to 0.
101 	 */
102 	sring->va = dma_alloc_coherent(dev, sz, &sring->pa, GFP_KERNEL);
103 	if (!sring->va)
104 		return -ENOMEM;
105 
106 	wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va,
107 		     &sring->pa);
108 
109 	return 0;
110 }
111 
112 static int wil_tx_init_edma(struct wil6210_priv *wil)
113 {
114 	int ring_id = wil_find_free_sring(wil);
115 	struct wil_status_ring *sring;
116 	int rc;
117 	u16 status_ring_size;
118 
119 	if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
120 	    wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
121 		wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
122 
123 	status_ring_size = 1 << wil->tx_status_ring_order;
124 
125 	wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n",
126 		     status_ring_size, ring_id);
127 
128 	if (ring_id < 0)
129 		return ring_id;
130 
131 	/* Allocate Tx status ring. Tx descriptor rings will be
132 	 * allocated on WMI connect event
133 	 */
134 	sring = &wil->srings[ring_id];
135 
136 	sring->is_rx = false;
137 	sring->size = status_ring_size;
138 	sring->elem_size = sizeof(struct wil_ring_tx_status);
139 	rc = wil_sring_alloc(wil, sring);
140 	if (rc)
141 		return rc;
142 
143 	rc = wil_wmi_tx_sring_cfg(wil, ring_id);
144 	if (rc)
145 		goto out_free;
146 
147 	sring->desc_rdy_pol = 1;
148 	wil->tx_sring_idx = ring_id;
149 
150 	return 0;
151 out_free:
152 	wil_sring_free(wil, sring);
153 	return rc;
154 }
155 
156 /**
157  * Allocate one skb for Rx descriptor RING
158  */
159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
160 				   struct wil_ring *ring, u32 i)
161 {
162 	struct device *dev = wil_to_dev(wil);
163 	unsigned int sz = wil->rx_buf_len;
164 	dma_addr_t pa;
165 	u16 buff_id;
166 	struct list_head *active = &wil->rx_buff_mgmt.active;
167 	struct list_head *free = &wil->rx_buff_mgmt.free;
168 	struct wil_rx_buff *rx_buff;
169 	struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr;
170 	struct sk_buff *skb;
171 	struct wil_rx_enhanced_desc dd, *d = &dd;
172 	struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *)
173 		&ring->va[i].rx.enhanced;
174 
175 	if (unlikely(list_empty(free))) {
176 		wil->rx_buff_mgmt.free_list_empty_cnt++;
177 		return -EAGAIN;
178 	}
179 
180 	skb = dev_alloc_skb(sz);
181 	if (unlikely(!skb))
182 		return -ENOMEM;
183 
184 	skb_put(skb, sz);
185 
186 	/**
187 	 * Make sure that the network stack calculates checksum for packets
188 	 * which failed the HW checksum calculation
189 	 */
190 	skb->ip_summed = CHECKSUM_NONE;
191 
192 	pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
193 	if (unlikely(dma_mapping_error(dev, pa))) {
194 		kfree_skb(skb);
195 		return -ENOMEM;
196 	}
197 
198 	/* Get the buffer ID - the index of the rx buffer in the buff_arr */
199 	rx_buff = list_first_entry(free, struct wil_rx_buff, list);
200 	buff_id = rx_buff->id;
201 
202 	/* Move a buffer from the free list to the active list */
203 	list_move(&rx_buff->list, active);
204 
205 	buff_arr[buff_id].skb = skb;
206 
207 	wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
208 	d->dma.length = cpu_to_le16(sz);
209 	d->mac.buff_id = cpu_to_le16(buff_id);
210 	*_d = *d;
211 
212 	/* Save the physical address in skb->cb for later use in dma_unmap */
213 	memcpy(skb->cb, &pa, sizeof(pa));
214 
215 	return 0;
216 }
217 
218 static inline
219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg)
220 {
221 	memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)),
222 	       sring->elem_size);
223 }
224 
225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring)
226 {
227 	sring->swhead = (sring->swhead + 1) % sring->size;
228 	if (sring->swhead == 0)
229 		sring->desc_rdy_pol = 1 - sring->desc_rdy_pol;
230 }
231 
232 static int wil_rx_refill_edma(struct wil6210_priv *wil)
233 {
234 	struct wil_ring *ring = &wil->ring_rx;
235 	u32 next_head;
236 	int rc = 0;
237 	ring->swtail = *ring->edma_rx_swtail.va;
238 
239 	for (; next_head = wil_ring_next_head(ring),
240 	     (next_head != ring->swtail);
241 	     ring->swhead = next_head) {
242 		rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead);
243 		if (unlikely(rc)) {
244 			if (rc == -EAGAIN)
245 				wil_dbg_txrx(wil, "No free buffer ID found\n");
246 			else
247 				wil_err_ratelimited(wil,
248 						    "Error %d in refill desc[%d]\n",
249 						    rc, ring->swhead);
250 			break;
251 		}
252 	}
253 
254 	/* make sure all writes to descriptors (shared memory) are done before
255 	 * committing them to HW
256 	 */
257 	wmb();
258 
259 	wil_w(wil, ring->hwtail, ring->swhead);
260 
261 	return rc;
262 }
263 
264 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil,
265 					      struct wil_ring *ring)
266 {
267 	struct device *dev = wil_to_dev(wil);
268 	struct list_head *active = &wil->rx_buff_mgmt.active;
269 	dma_addr_t pa;
270 
271 	while (!list_empty(active)) {
272 		struct wil_rx_buff *rx_buff =
273 			list_first_entry(active, struct wil_rx_buff, list);
274 		struct sk_buff *skb = rx_buff->skb;
275 
276 		if (unlikely(!skb)) {
277 			wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id);
278 		} else {
279 			rx_buff->skb = NULL;
280 			memcpy(&pa, skb->cb, sizeof(pa));
281 			dma_unmap_single(dev, pa, wil->rx_buf_len,
282 					 DMA_FROM_DEVICE);
283 			kfree_skb(skb);
284 		}
285 
286 		/* Move the buffer from the active to the free list */
287 		list_move(&rx_buff->list, &wil->rx_buff_mgmt.free);
288 	}
289 }
290 
291 static void wil_free_rx_buff_arr(struct wil6210_priv *wil)
292 {
293 	struct wil_ring *ring = &wil->ring_rx;
294 
295 	if (!wil->rx_buff_mgmt.buff_arr)
296 		return;
297 
298 	/* Move all the buffers to the free list in case active list is
299 	 * not empty in order to release all SKBs before deleting the array
300 	 */
301 	wil_move_all_rx_buff_to_free_list(wil, ring);
302 
303 	kfree(wil->rx_buff_mgmt.buff_arr);
304 	wil->rx_buff_mgmt.buff_arr = NULL;
305 }
306 
307 static int wil_init_rx_buff_arr(struct wil6210_priv *wil,
308 				size_t size)
309 {
310 	struct wil_rx_buff *buff_arr;
311 	struct list_head *active = &wil->rx_buff_mgmt.active;
312 	struct list_head *free = &wil->rx_buff_mgmt.free;
313 	int i;
314 
315 	wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff),
316 					     GFP_KERNEL);
317 	if (!wil->rx_buff_mgmt.buff_arr)
318 		return -ENOMEM;
319 
320 	/* Set list heads */
321 	INIT_LIST_HEAD(active);
322 	INIT_LIST_HEAD(free);
323 
324 	/* Linkify the list */
325 	buff_arr = wil->rx_buff_mgmt.buff_arr;
326 	for (i = 0; i < size; i++) {
327 		list_add(&buff_arr[i].list, free);
328 		buff_arr[i].id = i;
329 	}
330 
331 	wil->rx_buff_mgmt.size = size;
332 
333 	return 0;
334 }
335 
336 static int wil_init_rx_sring(struct wil6210_priv *wil,
337 			     u16 status_ring_size,
338 			     size_t elem_size,
339 			     u16 ring_id)
340 {
341 	struct wil_status_ring *sring = &wil->srings[ring_id];
342 	int rc;
343 
344 	wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n",
345 		     status_ring_size, ring_id);
346 
347 	memset(&sring->rx_data, 0, sizeof(sring->rx_data));
348 
349 	sring->is_rx = true;
350 	sring->size = status_ring_size;
351 	sring->elem_size = elem_size;
352 	rc = wil_sring_alloc(wil, sring);
353 	if (rc)
354 		return rc;
355 
356 	rc = wil_wmi_rx_sring_add(wil, ring_id);
357 	if (rc)
358 		goto out_free;
359 
360 	sring->desc_rdy_pol = 1;
361 
362 	return 0;
363 out_free:
364 	wil_sring_free(wil, sring);
365 	return rc;
366 }
367 
368 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil,
369 				    struct wil_ring *ring)
370 {
371 	struct device *dev = wil_to_dev(wil);
372 	size_t sz = ring->size * sizeof(ring->va[0]);
373 
374 	wil_dbg_misc(wil, "alloc_desc_ring:\n");
375 
376 	BUILD_BUG_ON(sizeof(ring->va[0]) != 32);
377 
378 	ring->swhead = 0;
379 	ring->swtail = 0;
380 	ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL);
381 	if (!ring->ctx)
382 		goto err;
383 
384 	ring->va = dma_alloc_coherent(dev, sz, &ring->pa, GFP_KERNEL);
385 	if (!ring->va)
386 		goto err_free_ctx;
387 
388 	if (ring->is_rx) {
389 		sz = sizeof(*ring->edma_rx_swtail.va);
390 		ring->edma_rx_swtail.va =
391 			dma_alloc_coherent(dev, sz, &ring->edma_rx_swtail.pa,
392 					   GFP_KERNEL);
393 		if (!ring->edma_rx_swtail.va)
394 			goto err_free_va;
395 	}
396 
397 	wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n",
398 		     ring->is_rx ? "RX" : "TX",
399 		     ring->size, ring->va, &ring->pa, ring->ctx);
400 
401 	return 0;
402 err_free_va:
403 	dma_free_coherent(dev, ring->size * sizeof(ring->va[0]),
404 			  (void *)ring->va, ring->pa);
405 	ring->va = NULL;
406 err_free_ctx:
407 	kfree(ring->ctx);
408 	ring->ctx = NULL;
409 err:
410 	return -ENOMEM;
411 }
412 
413 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring)
414 {
415 	struct device *dev = wil_to_dev(wil);
416 	size_t sz;
417 	int ring_index = 0;
418 
419 	if (!ring->va)
420 		return;
421 
422 	sz = ring->size * sizeof(ring->va[0]);
423 
424 	lockdep_assert_held(&wil->mutex);
425 	if (ring->is_rx) {
426 		wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n",
427 			     ring->size, ring->va,
428 			     &ring->pa, ring->ctx);
429 
430 		wil_move_all_rx_buff_to_free_list(wil, ring);
431 		goto out;
432 	}
433 
434 	/* TX ring */
435 	ring_index = ring - wil->ring_tx;
436 
437 	wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n",
438 		     ring_index, ring->size, ring->va,
439 		     &ring->pa, ring->ctx);
440 
441 	while (!wil_ring_is_empty(ring)) {
442 		struct wil_ctx *ctx;
443 
444 		struct wil_tx_enhanced_desc dd, *d = &dd;
445 		struct wil_tx_enhanced_desc *_d =
446 			(struct wil_tx_enhanced_desc *)
447 			&ring->va[ring->swtail].tx.enhanced;
448 
449 		ctx = &ring->ctx[ring->swtail];
450 		if (!ctx) {
451 			wil_dbg_txrx(wil,
452 				     "ctx(%d) was already completed\n",
453 				     ring->swtail);
454 			ring->swtail = wil_ring_next_tail(ring);
455 			continue;
456 		}
457 		*d = *_d;
458 		wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
459 		if (ctx->skb)
460 			dev_kfree_skb_any(ctx->skb);
461 		ring->swtail = wil_ring_next_tail(ring);
462 	}
463 
464 out:
465 	dma_free_coherent(dev, sz, (void *)ring->va, ring->pa);
466 	kfree(ring->ctx);
467 	ring->pa = 0;
468 	ring->va = NULL;
469 	ring->ctx = NULL;
470 }
471 
472 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size,
473 				 int status_ring_id)
474 {
475 	struct wil_ring *ring = &wil->ring_rx;
476 	int rc;
477 
478 	wil_dbg_misc(wil, "init RX desc ring\n");
479 
480 	ring->size = desc_ring_size;
481 	ring->is_rx = true;
482 	rc = wil_ring_alloc_desc_ring(wil, ring);
483 	if (rc)
484 		return rc;
485 
486 	rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id);
487 	if (rc)
488 		goto out_free;
489 
490 	return 0;
491 out_free:
492 	wil_ring_free_edma(wil, ring);
493 	return rc;
494 }
495 
496 static void wil_get_reorder_params_edma(struct wil6210_priv *wil,
497 					struct sk_buff *skb, int *tid,
498 					int *cid, int *mid, u16 *seq,
499 					int *mcast, int *retry)
500 {
501 	struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
502 
503 	*tid = wil_rx_status_get_tid(s);
504 	*cid = wil_rx_status_get_cid(s);
505 	*mid = wil_rx_status_get_mid(s);
506 	*seq = le16_to_cpu(wil_rx_status_get_seq(wil, s));
507 	*mcast = wil_rx_status_get_mcast(s);
508 	*retry = wil_rx_status_get_retry(s);
509 }
510 
511 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid,
512 					 int *security)
513 {
514 	struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
515 
516 	*cid = wil_rx_status_get_cid(s);
517 	*security = wil_rx_status_get_security(s);
518 }
519 
520 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil,
521 				    struct sk_buff *skb)
522 {
523 	struct wil_rx_status_extended *st;
524 	int cid, tid, key_id, mc;
525 	struct wil_sta_info *s;
526 	struct wil_tid_crypto_rx *c;
527 	struct wil_tid_crypto_rx_single *cc;
528 	const u8 *pn;
529 
530 	/* In HW reorder, HW is responsible for crypto check */
531 	if (wil->use_rx_hw_reordering)
532 		return 0;
533 
534 	st = wil_skb_rxstatus(skb);
535 
536 	cid = wil_rx_status_get_cid(st);
537 	tid = wil_rx_status_get_tid(st);
538 	key_id = wil_rx_status_get_key_id(st);
539 	mc = wil_rx_status_get_mcast(st);
540 	s = &wil->sta[cid];
541 	c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid];
542 	cc = &c->key_id[key_id];
543 	pn = (u8 *)&st->ext.pn_15_0;
544 
545 	if (!cc->key_set) {
546 		wil_err_ratelimited(wil,
547 				    "Key missing. CID %d TID %d MCast %d KEY_ID %d\n",
548 				    cid, tid, mc, key_id);
549 		return -EINVAL;
550 	}
551 
552 	if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) {
553 		wil_err_ratelimited(wil,
554 				    "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n",
555 				    cid, tid, mc, key_id, pn, cc->pn);
556 		return -EINVAL;
557 	}
558 	memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN);
559 
560 	return 0;
561 }
562 
563 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
564 {
565 	struct wil_status_ring *sring;
566 	struct wil_rx_status_extended msg1;
567 	void *msg = &msg1;
568 	u8 dr_bit;
569 	int i;
570 
571 	for (i = 0; i < wil->num_rx_status_rings; i++) {
572 		sring = &wil->srings[i];
573 		if (!sring->va)
574 			continue;
575 
576 		wil_get_next_rx_status_msg(sring, msg);
577 		dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
578 
579 		/* Check if there are unhandled RX status messages */
580 		if (dr_bit == sring->desc_rdy_pol)
581 			return false;
582 	}
583 
584 	return true;
585 }
586 
587 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
588 {
589 	/* RX buffer size must be aligned to 4 bytes */
590 	wil->rx_buf_len = rx_large_buf ?
591 		WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
592 }
593 
594 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order)
595 {
596 	u16 status_ring_size, desc_ring_size = 1 << desc_ring_order;
597 	struct wil_ring *ring = &wil->ring_rx;
598 	int rc;
599 	size_t elem_size = wil->use_compressed_rx_status ?
600 		sizeof(struct wil_rx_status_compressed) :
601 		sizeof(struct wil_rx_status_extended);
602 	int i;
603 
604 	/* In SW reorder one must use extended status messages */
605 	if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) {
606 		wil_err(wil,
607 			"compressed RX status cannot be used with SW reorder\n");
608 		return -EINVAL;
609 	}
610 	if (wil->rx_status_ring_order <= desc_ring_order)
611 		/* make sure sring is larger than desc ring */
612 		wil->rx_status_ring_order = desc_ring_order + 1;
613 	if (wil->rx_buff_id_count <= desc_ring_size)
614 		/* make sure we will not run out of buff_ids */
615 		wil->rx_buff_id_count = desc_ring_size + 512;
616 	if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
617 	    wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
618 		wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
619 
620 	status_ring_size = 1 << wil->rx_status_ring_order;
621 
622 	wil_dbg_misc(wil,
623 		     "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n",
624 		     desc_ring_size, status_ring_size, elem_size);
625 
626 	wil_rx_buf_len_init_edma(wil);
627 
628 	/* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
629 	if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
630 		wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1;
631 
632 	wil_dbg_misc(wil, "rx_init: allocate %d status rings\n",
633 		     wil->num_rx_status_rings);
634 
635 	rc = wil_wmi_cfg_def_rx_offload(wil, wil->rx_buf_len);
636 	if (rc)
637 		return rc;
638 
639 	/* Allocate status ring */
640 	for (i = 0; i < wil->num_rx_status_rings; i++) {
641 		int sring_id = wil_find_free_sring(wil);
642 
643 		if (sring_id < 0) {
644 			rc = -EFAULT;
645 			goto err_free_status;
646 		}
647 		rc = wil_init_rx_sring(wil, status_ring_size, elem_size,
648 				       sring_id);
649 		if (rc)
650 			goto err_free_status;
651 	}
652 
653 	/* Allocate descriptor ring */
654 	rc = wil_init_rx_desc_ring(wil, desc_ring_size,
655 				   WIL_DEFAULT_RX_STATUS_RING_ID);
656 	if (rc)
657 		goto err_free_status;
658 
659 	if (wil->rx_buff_id_count >= status_ring_size) {
660 		wil_info(wil,
661 			 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n",
662 			 wil->rx_buff_id_count, status_ring_size,
663 			 status_ring_size - 1);
664 		wil->rx_buff_id_count = status_ring_size - 1;
665 	}
666 
667 	/* Allocate Rx buffer array */
668 	rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count);
669 	if (rc)
670 		goto err_free_desc;
671 
672 	/* Fill descriptor ring with credits */
673 	rc = wil_rx_refill_edma(wil);
674 	if (rc)
675 		goto err_free_rx_buff_arr;
676 
677 	return 0;
678 err_free_rx_buff_arr:
679 	wil_free_rx_buff_arr(wil);
680 err_free_desc:
681 	wil_ring_free_edma(wil, ring);
682 err_free_status:
683 	for (i = 0; i < wil->num_rx_status_rings; i++)
684 		wil_sring_free(wil, &wil->srings[i]);
685 
686 	return rc;
687 }
688 
689 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id,
690 				 int size, int cid, int tid)
691 {
692 	struct wil6210_priv *wil = vif_to_wil(vif);
693 	int rc;
694 	struct wil_ring *ring = &wil->ring_tx[ring_id];
695 	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
696 
697 	lockdep_assert_held(&wil->mutex);
698 
699 	wil_dbg_misc(wil,
700 		     "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n",
701 		     ring_id, cid, tid, wil->tx_sring_idx);
702 
703 	wil_tx_data_init(txdata);
704 	ring->size = size;
705 	rc = wil_ring_alloc_desc_ring(wil, ring);
706 	if (rc)
707 		goto out;
708 
709 	wil->ring2cid_tid[ring_id][0] = cid;
710 	wil->ring2cid_tid[ring_id][1] = tid;
711 	if (!vif->privacy)
712 		txdata->dot1x_open = true;
713 
714 	rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid);
715 	if (rc) {
716 		wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n");
717 		goto out_free;
718 	}
719 
720 	if (txdata->dot1x_open && agg_wsize >= 0)
721 		wil_addba_tx_request(wil, ring_id, agg_wsize);
722 
723 	return 0;
724  out_free:
725 	spin_lock_bh(&txdata->lock);
726 	txdata->dot1x_open = false;
727 	txdata->enabled = 0;
728 	spin_unlock_bh(&txdata->lock);
729 	wil_ring_free_edma(wil, ring);
730 	wil->ring2cid_tid[ring_id][0] = max_assoc_sta;
731 	wil->ring2cid_tid[ring_id][1] = 0;
732 
733  out:
734 	return rc;
735 }
736 
737 static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id,
738 				   int cid, int tid)
739 {
740 	struct wil6210_priv *wil = vif_to_wil(vif);
741 
742 	wil_err(wil, "ring modify is not supported for EDMA\n");
743 
744 	return -EOPNOTSUPP;
745 }
746 
747 /* This function is used only for RX SW reorder */
748 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid,
749 			 struct sk_buff *skb, struct wil_net_stats *stats)
750 {
751 	u8 ftype;
752 	u8 fc1;
753 	int mid;
754 	int tid;
755 	u16 seq;
756 	struct wil6210_vif *vif;
757 
758 	ftype = wil_rx_status_get_frame_type(wil, msg);
759 	if (ftype == IEEE80211_FTYPE_DATA)
760 		return 0;
761 
762 	fc1 = wil_rx_status_get_fc1(wil, msg);
763 	mid = wil_rx_status_get_mid(msg);
764 	tid = wil_rx_status_get_tid(msg);
765 	seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg));
766 	vif = wil->vifs[mid];
767 
768 	if (unlikely(!vif)) {
769 		wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid);
770 		return -EAGAIN;
771 	}
772 
773 	wil_dbg_txrx(wil,
774 		     "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
775 		     fc1, mid, cid, tid, seq);
776 	if (stats)
777 		stats->rx_non_data_frame++;
778 	if (wil_is_back_req(fc1)) {
779 		wil_dbg_txrx(wil,
780 			     "BAR: MID %d CID %d TID %d Seq 0x%03x\n",
781 			     mid, cid, tid, seq);
782 		wil_rx_bar(wil, vif, cid, tid, seq);
783 	} else {
784 		u32 sz = wil->use_compressed_rx_status ?
785 			sizeof(struct wil_rx_status_compressed) :
786 			sizeof(struct wil_rx_status_extended);
787 
788 		/* print again all info. One can enable only this
789 		 * without overhead for printing every Rx frame
790 		 */
791 		wil_dbg_txrx(wil,
792 			     "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
793 			     fc1, mid, cid, tid, seq);
794 		wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
795 				  (const void *)msg, sz, false);
796 		wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
797 				  skb->data, skb_headlen(skb), false);
798 	}
799 
800 	return -EAGAIN;
801 }
802 
803 static int wil_rx_error_check_edma(struct wil6210_priv *wil,
804 				   struct sk_buff *skb,
805 				   struct wil_net_stats *stats)
806 {
807 	int error;
808 	int l2_rx_status;
809 	int l3_rx_status;
810 	int l4_rx_status;
811 	void *msg = wil_skb_rxstatus(skb);
812 
813 	error = wil_rx_status_get_error(msg);
814 	if (!error) {
815 		skb->ip_summed = CHECKSUM_UNNECESSARY;
816 		return 0;
817 	}
818 
819 	l2_rx_status = wil_rx_status_get_l2_rx_status(msg);
820 	if (l2_rx_status != 0) {
821 		wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n",
822 			     l2_rx_status);
823 		/* Due to HW issue, KEY error will trigger a MIC error */
824 		if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) {
825 			wil_err_ratelimited(wil,
826 					    "L2 MIC/KEY error, dropping packet\n");
827 			stats->rx_mic_error++;
828 		}
829 		if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) {
830 			wil_err_ratelimited(wil,
831 					    "L2 KEY error, dropping packet\n");
832 			stats->rx_key_error++;
833 		}
834 		if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) {
835 			wil_err_ratelimited(wil,
836 					    "L2 REPLAY error, dropping packet\n");
837 			stats->rx_replay++;
838 		}
839 		if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) {
840 			wil_err_ratelimited(wil,
841 					    "L2 AMSDU error, dropping packet\n");
842 			stats->rx_amsdu_error++;
843 		}
844 		return -EFAULT;
845 	}
846 
847 	l3_rx_status = wil_rx_status_get_l3_rx_status(msg);
848 	l4_rx_status = wil_rx_status_get_l4_rx_status(msg);
849 	if (!l3_rx_status && !l4_rx_status)
850 		skb->ip_summed = CHECKSUM_UNNECESSARY;
851 	/* If HW reports bad checksum, let IP stack re-check it
852 	 * For example, HW don't understand Microsoft IP stack that
853 	 * mis-calculates TCP checksum - if it should be 0x0,
854 	 * it writes 0xffff in violation of RFC 1624
855 	 */
856 	else
857 		stats->rx_csum_err++;
858 
859 	return 0;
860 }
861 
862 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
863 					      struct wil_status_ring *sring)
864 {
865 	struct device *dev = wil_to_dev(wil);
866 	struct wil_rx_status_extended msg1;
867 	void *msg = &msg1;
868 	u16 buff_id;
869 	struct sk_buff *skb;
870 	dma_addr_t pa;
871 	struct wil_ring_rx_data *rxdata = &sring->rx_data;
872 	unsigned int sz = wil->rx_buf_len;
873 	struct wil_net_stats *stats = NULL;
874 	u16 dmalen;
875 	int cid;
876 	bool eop, headstolen;
877 	int delta;
878 	u8 dr_bit;
879 	u8 data_offset;
880 	struct wil_rx_status_extended *s;
881 	u16 sring_idx = sring - wil->srings;
882 
883 	BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb));
884 
885 again:
886 	wil_get_next_rx_status_msg(sring, msg);
887 	dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
888 
889 	/* Completed handling all the ready status messages */
890 	if (dr_bit != sring->desc_rdy_pol)
891 		return NULL;
892 
893 	/* Extract the buffer ID from the status message */
894 	buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg));
895 	if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) {
896 		wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n",
897 			buff_id, sring->swhead);
898 		wil_sring_advance_swhead(sring);
899 		goto again;
900 	}
901 
902 	wil_sring_advance_swhead(sring);
903 
904 	/* Extract the SKB from the rx_buff management array */
905 	skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb;
906 	wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL;
907 	if (!skb) {
908 		wil_err(wil, "No Rx skb at buff_id %d\n", buff_id);
909 		/* Move the buffer from the active list to the free list */
910 		list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
911 			  &wil->rx_buff_mgmt.free);
912 		goto again;
913 	}
914 
915 	memcpy(&pa, skb->cb, sizeof(pa));
916 	dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
917 	dmalen = le16_to_cpu(wil_rx_status_get_length(msg));
918 
919 	trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id,
920 				msg);
921 	wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n",
922 		     buff_id, sring_idx, dmalen);
923 	wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
924 			  (const void *)msg, wil->use_compressed_rx_status ?
925 			  sizeof(struct wil_rx_status_compressed) :
926 			  sizeof(struct wil_rx_status_extended), false);
927 
928 	/* Move the buffer from the active list to the free list */
929 	list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
930 		  &wil->rx_buff_mgmt.free);
931 
932 	eop = wil_rx_status_get_eop(msg);
933 
934 	cid = wil_rx_status_get_cid(msg);
935 	if (unlikely(!wil_val_in_range(cid, 0, max_assoc_sta))) {
936 		wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n",
937 			cid, sring->swhead);
938 		rxdata->skipping = true;
939 		goto skipping;
940 	}
941 	stats = &wil->sta[cid].stats;
942 
943 	if (unlikely(skb->len < ETH_HLEN)) {
944 		wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len);
945 		stats->rx_short_frame++;
946 		rxdata->skipping = true;
947 		goto skipping;
948 	}
949 
950 	if (unlikely(dmalen > sz)) {
951 		wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
952 		stats->rx_large_frame++;
953 		rxdata->skipping = true;
954 	}
955 
956 skipping:
957 	/* skipping indicates if a certain SKB should be dropped.
958 	 * It is set in case there is an error on the current SKB or in case
959 	 * of RX chaining: as long as we manage to merge the SKBs it will
960 	 * be false. once we have a bad SKB or we don't manage to merge SKBs
961 	 * it will be set to the !EOP value of the current SKB.
962 	 * This guarantees that all the following SKBs until EOP will also
963 	 * get dropped.
964 	 */
965 	if (unlikely(rxdata->skipping)) {
966 		kfree_skb(skb);
967 		if (rxdata->skb) {
968 			kfree_skb(rxdata->skb);
969 			rxdata->skb = NULL;
970 		}
971 		rxdata->skipping = !eop;
972 		goto again;
973 	}
974 
975 	skb_trim(skb, dmalen);
976 
977 	prefetch(skb->data);
978 
979 	if (!rxdata->skb) {
980 		rxdata->skb = skb;
981 	} else {
982 		if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen,
983 					    &delta))) {
984 			kfree_skb_partial(skb, headstolen);
985 		} else {
986 			wil_err(wil, "failed to merge skbs!\n");
987 			kfree_skb(skb);
988 			kfree_skb(rxdata->skb);
989 			rxdata->skb = NULL;
990 			rxdata->skipping = !eop;
991 			goto again;
992 		}
993 	}
994 
995 	if (!eop)
996 		goto again;
997 
998 	/* reaching here rxdata->skb always contains a full packet */
999 	skb = rxdata->skb;
1000 	rxdata->skb = NULL;
1001 	rxdata->skipping = false;
1002 
1003 	if (stats) {
1004 		stats->last_mcs_rx = wil_rx_status_get_mcs(msg);
1005 		if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs))
1006 			stats->rx_per_mcs[stats->last_mcs_rx]++;
1007 	}
1008 
1009 	if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status &&
1010 	    wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) {
1011 		kfree_skb(skb);
1012 		goto again;
1013 	}
1014 
1015 	/* Compensate for the HW data alignment according to the status
1016 	 * message
1017 	 */
1018 	data_offset = wil_rx_status_get_data_offset(msg);
1019 	if (data_offset == 0xFF ||
1020 	    data_offset > WIL_EDMA_MAX_DATA_OFFSET) {
1021 		wil_err(wil, "Unexpected data offset %d\n", data_offset);
1022 		kfree_skb(skb);
1023 		goto again;
1024 	}
1025 
1026 	skb_pull(skb, data_offset);
1027 
1028 	wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
1029 			  skb->data, skb_headlen(skb), false);
1030 
1031 	/* Has to be done after dma_unmap_single as skb->cb is also
1032 	 * used for holding the pa
1033 	 */
1034 	s = wil_skb_rxstatus(skb);
1035 	memcpy(s, msg, sring->elem_size);
1036 
1037 	return skb;
1038 }
1039 
1040 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota)
1041 {
1042 	struct net_device *ndev;
1043 	struct wil_ring *ring = &wil->ring_rx;
1044 	struct wil_status_ring *sring;
1045 	struct sk_buff *skb;
1046 	int i;
1047 
1048 	if (unlikely(!ring->va)) {
1049 		wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
1050 		return;
1051 	}
1052 	wil_dbg_txrx(wil, "rx_handle\n");
1053 
1054 	for (i = 0; i < wil->num_rx_status_rings; i++) {
1055 		sring = &wil->srings[i];
1056 		if (unlikely(!sring->va)) {
1057 			wil_err(wil,
1058 				"Rx IRQ while Rx status ring %d not yet initialized\n",
1059 				i);
1060 			continue;
1061 		}
1062 
1063 		while ((*quota > 0) &&
1064 		       (NULL != (skb =
1065 			wil_sring_reap_rx_edma(wil, sring)))) {
1066 			(*quota)--;
1067 			if (wil->use_rx_hw_reordering) {
1068 				void *msg = wil_skb_rxstatus(skb);
1069 				int mid = wil_rx_status_get_mid(msg);
1070 				struct wil6210_vif *vif = wil->vifs[mid];
1071 
1072 				if (unlikely(!vif)) {
1073 					wil_dbg_txrx(wil,
1074 						     "RX desc invalid mid %d",
1075 						     mid);
1076 					kfree_skb(skb);
1077 					continue;
1078 				}
1079 				ndev = vif_to_ndev(vif);
1080 				wil_netif_rx_any(skb, ndev);
1081 			} else {
1082 				wil_rx_reorder(wil, skb);
1083 			}
1084 		}
1085 
1086 		wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1087 	}
1088 
1089 	wil_rx_refill_edma(wil);
1090 }
1091 
1092 static int wil_tx_desc_map_edma(union wil_tx_desc *desc,
1093 				dma_addr_t pa,
1094 				u32 len,
1095 				int ring_index)
1096 {
1097 	struct wil_tx_enhanced_desc *d =
1098 		(struct wil_tx_enhanced_desc *)&desc->enhanced;
1099 
1100 	memset(d, 0, sizeof(struct wil_tx_enhanced_desc));
1101 
1102 	wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
1103 
1104 	/* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
1105 	d->dma.length = cpu_to_le16((u16)len);
1106 	d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS);
1107 	/* translation type:  0 - bypass; 1 - 802.3; 2 - native wifi;
1108 	 * 3 - eth mode
1109 	 */
1110 	d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
1111 		      (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
1112 
1113 	return 0;
1114 }
1115 
1116 static inline void
1117 wil_get_next_tx_status_msg(struct wil_status_ring *sring,
1118 			   struct wil_ring_tx_status *msg)
1119 {
1120 	struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *)
1121 		(sring->va + (sring->elem_size * sring->swhead));
1122 
1123 	*msg = *_msg;
1124 }
1125 
1126 /**
1127  * Clean up transmitted skb's from the Tx descriptor RING.
1128  * Return number of descriptors cleared.
1129  */
1130 int wil_tx_sring_handler(struct wil6210_priv *wil,
1131 			 struct wil_status_ring *sring)
1132 {
1133 	struct net_device *ndev;
1134 	struct device *dev = wil_to_dev(wil);
1135 	struct wil_ring *ring = NULL;
1136 	struct wil_ring_tx_data *txdata;
1137 	/* Total number of completed descriptors in all descriptor rings */
1138 	int desc_cnt = 0;
1139 	int cid;
1140 	struct wil_net_stats *stats;
1141 	struct wil_tx_enhanced_desc *_d;
1142 	unsigned int ring_id;
1143 	unsigned int num_descs;
1144 	int i;
1145 	u8 dr_bit; /* Descriptor Ready bit */
1146 	struct wil_ring_tx_status msg;
1147 	struct wil6210_vif *vif;
1148 	int used_before_complete;
1149 	int used_new;
1150 
1151 	wil_get_next_tx_status_msg(sring, &msg);
1152 	dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1153 
1154 	/* Process completion messages while DR bit has the expected polarity */
1155 	while (dr_bit == sring->desc_rdy_pol) {
1156 		num_descs = msg.num_descriptors;
1157 		if (!num_descs) {
1158 			wil_err(wil, "invalid num_descs 0\n");
1159 			goto again;
1160 		}
1161 
1162 		/* Find the corresponding descriptor ring */
1163 		ring_id = msg.ring_id;
1164 
1165 		if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) {
1166 			wil_err(wil, "invalid ring id %d\n", ring_id);
1167 			goto again;
1168 		}
1169 		ring = &wil->ring_tx[ring_id];
1170 		if (unlikely(!ring->va)) {
1171 			wil_err(wil, "Tx irq[%d]: ring not initialized\n",
1172 				ring_id);
1173 			goto again;
1174 		}
1175 		txdata = &wil->ring_tx_data[ring_id];
1176 		if (unlikely(!txdata->enabled)) {
1177 			wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id);
1178 			goto again;
1179 		}
1180 		vif = wil->vifs[txdata->mid];
1181 		if (unlikely(!vif)) {
1182 			wil_dbg_txrx(wil, "invalid MID %d for ring %d\n",
1183 				     txdata->mid, ring_id);
1184 			goto again;
1185 		}
1186 
1187 		ndev = vif_to_ndev(vif);
1188 
1189 		cid = wil->ring2cid_tid[ring_id][0];
1190 		stats = (cid < max_assoc_sta ? &wil->sta[cid].stats : NULL);
1191 
1192 		wil_dbg_txrx(wil,
1193 			     "tx_status: completed desc_ring (%d), num_descs (%d)\n",
1194 			     ring_id, num_descs);
1195 
1196 		used_before_complete = wil_ring_used_tx(ring);
1197 
1198 		for (i = 0 ; i < num_descs; ++i) {
1199 			struct wil_ctx *ctx = &ring->ctx[ring->swtail];
1200 			struct wil_tx_enhanced_desc dd, *d = &dd;
1201 			u16 dmalen;
1202 			struct sk_buff *skb = ctx->skb;
1203 
1204 			_d = (struct wil_tx_enhanced_desc *)
1205 				&ring->va[ring->swtail].tx.enhanced;
1206 			*d = *_d;
1207 
1208 			dmalen = le16_to_cpu(d->dma.length);
1209 			trace_wil6210_tx_status(&msg, ring->swtail, dmalen);
1210 			wil_dbg_txrx(wil,
1211 				     "TxC[%2d][%3d] : %d bytes, status 0x%02x\n",
1212 				     ring_id, ring->swtail, dmalen,
1213 				     msg.status);
1214 			wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4,
1215 					  (const void *)&msg, sizeof(msg),
1216 					  false);
1217 
1218 			wil_tx_desc_unmap_edma(dev,
1219 					       (union wil_tx_desc *)d,
1220 					       ctx);
1221 
1222 			if (skb) {
1223 				if (likely(msg.status == 0)) {
1224 					ndev->stats.tx_packets++;
1225 					ndev->stats.tx_bytes += skb->len;
1226 					if (stats) {
1227 						stats->tx_packets++;
1228 						stats->tx_bytes += skb->len;
1229 
1230 						wil_tx_latency_calc(wil, skb,
1231 							&wil->sta[cid]);
1232 					}
1233 				} else {
1234 					ndev->stats.tx_errors++;
1235 					if (stats)
1236 						stats->tx_errors++;
1237 				}
1238 				wil_consume_skb(skb, msg.status == 0);
1239 			}
1240 			memset(ctx, 0, sizeof(*ctx));
1241 			/* Make sure the ctx is zeroed before updating the tail
1242 			 * to prevent a case where wil_tx_ring will see
1243 			 * this descriptor as used and handle it before ctx zero
1244 			 * is completed.
1245 			 */
1246 			wmb();
1247 
1248 			ring->swtail = wil_ring_next_tail(ring);
1249 
1250 			desc_cnt++;
1251 		}
1252 
1253 		/* performance monitoring */
1254 		used_new = wil_ring_used_tx(ring);
1255 		if (wil_val_in_range(wil->ring_idle_trsh,
1256 				     used_new, used_before_complete)) {
1257 			wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n",
1258 				     ring_id, used_before_complete, used_new);
1259 			txdata->last_idle = get_cycles();
1260 		}
1261 
1262 again:
1263 		wil_sring_advance_swhead(sring);
1264 
1265 		wil_get_next_tx_status_msg(sring, &msg);
1266 		dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1267 	}
1268 
1269 	/* shall we wake net queues? */
1270 	if (desc_cnt)
1271 		wil_update_net_queues(wil, vif, NULL, false);
1272 
1273 	/* Update the HW tail ptr (RD ptr) */
1274 	wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1275 
1276 	return desc_cnt;
1277 }
1278 
1279 /**
1280  * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding
1281  * @skb is used to obtain the protocol and headers length.
1282  * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data,
1283  * 2 - middle, 3 - last descriptor.
1284  */
1285 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d,
1286 					       int tso_desc_type, bool is_ipv4,
1287 					       int tcp_hdr_len,
1288 					       int skb_net_hdr_len,
1289 					       int mss)
1290 {
1291 	/* Number of descriptors */
1292 	d->mac.d[2] |= 1;
1293 	/* Maximum Segment Size */
1294 	d->mac.tso_mss |= cpu_to_le16(mss >> 2);
1295 	/* L4 header len: TCP header length */
1296 	d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK;
1297 	/* EOP, TSO desc type, Segmentation enable,
1298 	 * Insert IPv4 and TCP / UDP Checksum
1299 	 */
1300 	d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) |
1301 		      tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS |
1302 		      BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) |
1303 		      BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) |
1304 		      BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS);
1305 	/* Calculate pseudo-header */
1306 	d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) |
1307 		     BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS);
1308 	/* IP Header Length */
1309 	d->dma.ip_length |= skb_net_hdr_len;
1310 	/* MAC header length and IP address family*/
1311 	d->dma.b11 |= ETH_HLEN |
1312 		      is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS;
1313 }
1314 
1315 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr,
1316 			       int len, uint i, int tso_desc_type,
1317 			       skb_frag_t *frag, struct wil_ring *ring,
1318 			       struct sk_buff *skb, bool is_ipv4,
1319 			       int tcp_hdr_len, int skb_net_hdr_len,
1320 			       int mss, int *descs_used)
1321 {
1322 	struct device *dev = wil_to_dev(wil);
1323 	struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *)
1324 		&ring->va[i].tx.enhanced;
1325 	struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem;
1326 	int ring_index = ring - wil->ring_tx;
1327 	dma_addr_t pa;
1328 
1329 	if (len == 0)
1330 		return 0;
1331 
1332 	if (!frag) {
1333 		pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE);
1334 		ring->ctx[i].mapped_as = wil_mapped_as_single;
1335 	} else {
1336 		pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE);
1337 		ring->ctx[i].mapped_as = wil_mapped_as_page;
1338 	}
1339 	if (unlikely(dma_mapping_error(dev, pa))) {
1340 		wil_err(wil, "TSO: Skb DMA map error\n");
1341 		return -EINVAL;
1342 	}
1343 
1344 	wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa,
1345 				   len, ring_index);
1346 	wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4,
1347 					   tcp_hdr_len,
1348 					   skb_net_hdr_len, mss);
1349 
1350 	/* hold reference to skb
1351 	 * to prevent skb release before accounting
1352 	 * in case of immediate "tx done"
1353 	 */
1354 	if (tso_desc_type == wil_tso_type_lst)
1355 		ring->ctx[i].skb = skb_get(skb);
1356 
1357 	wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1358 			  (const void *)d, sizeof(*d), false);
1359 
1360 	*_desc = *d;
1361 	(*descs_used)++;
1362 
1363 	return 0;
1364 }
1365 
1366 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil,
1367 				  struct wil6210_vif *vif,
1368 				  struct wil_ring *ring,
1369 				  struct sk_buff *skb)
1370 {
1371 	int ring_index = ring - wil->ring_tx;
1372 	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1373 	int nr_frags = skb_shinfo(skb)->nr_frags;
1374 	int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */
1375 	int used, avail = wil_ring_avail_tx(ring);
1376 	int f, hdrlen, headlen;
1377 	int gso_type;
1378 	bool is_ipv4;
1379 	u32 swhead = ring->swhead;
1380 	int descs_used = 0; /* total number of used descriptors */
1381 	int rc = -EINVAL;
1382 	int tcp_hdr_len;
1383 	int skb_net_hdr_len;
1384 	int mss = skb_shinfo(skb)->gso_size;
1385 
1386 	wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len,
1387 		     ring_index);
1388 
1389 	if (unlikely(!txdata->enabled))
1390 		return -EINVAL;
1391 
1392 	if (unlikely(avail < min_desc_required)) {
1393 		wil_err_ratelimited(wil,
1394 				    "TSO: Tx ring[%2d] full. No space for %d fragments\n",
1395 				    ring_index, min_desc_required);
1396 		return -ENOMEM;
1397 	}
1398 
1399 	gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4);
1400 	switch (gso_type) {
1401 	case SKB_GSO_TCPV4:
1402 		is_ipv4 = true;
1403 		break;
1404 	case SKB_GSO_TCPV6:
1405 		is_ipv4 = false;
1406 		break;
1407 	default:
1408 		return -EINVAL;
1409 	}
1410 
1411 	if (skb->ip_summed != CHECKSUM_PARTIAL)
1412 		return -EINVAL;
1413 
1414 	/* tcp header length and skb network header length are fixed for all
1415 	 * packet's descriptors - read them once here
1416 	 */
1417 	tcp_hdr_len = tcp_hdrlen(skb);
1418 	skb_net_hdr_len = skb_network_header_len(skb);
1419 
1420 	/* First descriptor must contain the header only
1421 	 * Header Length = MAC header len + IP header len + TCP header len
1422 	 */
1423 	hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len;
1424 	wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n",
1425 		     hdrlen);
1426 	rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead,
1427 				 wil_tso_type_hdr, NULL, ring, skb,
1428 				 is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1429 				 mss, &descs_used);
1430 	if (rc)
1431 		return -EINVAL;
1432 
1433 	/* Second descriptor contains the head */
1434 	headlen = skb_headlen(skb) - hdrlen;
1435 	wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen);
1436 	rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen,
1437 				 (swhead + descs_used) % ring->size,
1438 				 (nr_frags != 0) ? wil_tso_type_first :
1439 				 wil_tso_type_lst, NULL, ring, skb,
1440 				 is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1441 				 mss, &descs_used);
1442 	if (rc)
1443 		goto mem_error;
1444 
1445 	/* Rest of the descriptors are from the SKB fragments */
1446 	for (f = 0; f < nr_frags; f++) {
1447 		skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1448 		int len = frag->size;
1449 
1450 		wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f,
1451 			     len, descs_used);
1452 
1453 		rc = wil_tx_tso_gen_desc(wil, NULL, len,
1454 					 (swhead + descs_used) % ring->size,
1455 					 (f != nr_frags - 1) ?
1456 					 wil_tso_type_mid : wil_tso_type_lst,
1457 					 frag, ring, skb, is_ipv4,
1458 					 tcp_hdr_len, skb_net_hdr_len,
1459 					 mss, &descs_used);
1460 		if (rc)
1461 			goto mem_error;
1462 	}
1463 
1464 	/* performance monitoring */
1465 	used = wil_ring_used_tx(ring);
1466 	if (wil_val_in_range(wil->ring_idle_trsh,
1467 			     used, used + descs_used)) {
1468 		txdata->idle += get_cycles() - txdata->last_idle;
1469 		wil_dbg_txrx(wil,  "Ring[%2d] not idle %d -> %d\n",
1470 			     ring_index, used, used + descs_used);
1471 	}
1472 
1473 	/* advance swhead */
1474 	wil_ring_advance_head(ring, descs_used);
1475 	wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead);
1476 
1477 	/* make sure all writes to descriptors (shared memory) are done before
1478 	 * committing them to HW
1479 	 */
1480 	wmb();
1481 
1482 	if (wil->tx_latency)
1483 		*(ktime_t *)&skb->cb = ktime_get();
1484 	else
1485 		memset(skb->cb, 0, sizeof(ktime_t));
1486 
1487 	wil_w(wil, ring->hwtail, ring->swhead);
1488 
1489 	return 0;
1490 
1491 mem_error:
1492 	while (descs_used > 0) {
1493 		struct device *dev = wil_to_dev(wil);
1494 		struct wil_ctx *ctx;
1495 		int i = (swhead + descs_used - 1) % ring->size;
1496 		struct wil_tx_enhanced_desc dd, *d = &dd;
1497 		struct wil_tx_enhanced_desc *_desc =
1498 			(struct wil_tx_enhanced_desc *)
1499 			&ring->va[i].tx.enhanced;
1500 
1501 		*d = *_desc;
1502 		ctx = &ring->ctx[i];
1503 		wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
1504 		memset(ctx, 0, sizeof(*ctx));
1505 		descs_used--;
1506 	}
1507 	return rc;
1508 }
1509 
1510 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id,
1511 				    int size)
1512 {
1513 	struct wil6210_priv *wil = vif_to_wil(vif);
1514 	struct wil_ring *ring = &wil->ring_tx[ring_id];
1515 	int rc;
1516 	struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
1517 
1518 	wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n",
1519 		     ring_id, wil->tx_sring_idx);
1520 
1521 	lockdep_assert_held(&wil->mutex);
1522 
1523 	wil_tx_data_init(txdata);
1524 	ring->size = size;
1525 	ring->is_rx = false;
1526 	rc = wil_ring_alloc_desc_ring(wil, ring);
1527 	if (rc)
1528 		goto out;
1529 
1530 	wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */
1531 	wil->ring2cid_tid[ring_id][1] = 0; /* TID */
1532 	if (!vif->privacy)
1533 		txdata->dot1x_open = true;
1534 
1535 	rc = wil_wmi_bcast_desc_ring_add(vif, ring_id);
1536 	if (rc)
1537 		goto out_free;
1538 
1539 	return 0;
1540 
1541  out_free:
1542 	spin_lock_bh(&txdata->lock);
1543 	txdata->enabled = 0;
1544 	txdata->dot1x_open = false;
1545 	spin_unlock_bh(&txdata->lock);
1546 	wil_ring_free_edma(wil, ring);
1547 
1548 out:
1549 	return rc;
1550 }
1551 
1552 static void wil_tx_fini_edma(struct wil6210_priv *wil)
1553 {
1554 	struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx];
1555 
1556 	wil_dbg_misc(wil, "free TX sring\n");
1557 
1558 	wil_sring_free(wil, sring);
1559 }
1560 
1561 static void wil_rx_data_free(struct wil_status_ring *sring)
1562 {
1563 	if (!sring)
1564 		return;
1565 
1566 	kfree_skb(sring->rx_data.skb);
1567 	sring->rx_data.skb = NULL;
1568 }
1569 
1570 static void wil_rx_fini_edma(struct wil6210_priv *wil)
1571 {
1572 	struct wil_ring *ring = &wil->ring_rx;
1573 	int i;
1574 
1575 	wil_dbg_misc(wil, "rx_fini_edma\n");
1576 
1577 	wil_ring_free_edma(wil, ring);
1578 
1579 	for (i = 0; i < wil->num_rx_status_rings; i++) {
1580 		wil_rx_data_free(&wil->srings[i]);
1581 		wil_sring_free(wil, &wil->srings[i]);
1582 	}
1583 
1584 	wil_free_rx_buff_arr(wil);
1585 }
1586 
1587 void wil_init_txrx_ops_edma(struct wil6210_priv *wil)
1588 {
1589 	wil->txrx_ops.configure_interrupt_moderation =
1590 		wil_configure_interrupt_moderation_edma;
1591 	/* TX ops */
1592 	wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma;
1593 	wil->txrx_ops.ring_fini_tx = wil_ring_free_edma;
1594 	wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma;
1595 	wil->txrx_ops.tx_init = wil_tx_init_edma;
1596 	wil->txrx_ops.tx_fini = wil_tx_fini_edma;
1597 	wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma;
1598 	wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma;
1599 	wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma;
1600 	wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma;
1601 	/* RX ops */
1602 	wil->txrx_ops.rx_init = wil_rx_init_edma;
1603 	wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma;
1604 	wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma;
1605 	wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma;
1606 	wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma;
1607 	wil->txrx_ops.rx_error_check = wil_rx_error_check_edma;
1608 	wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma;
1609 	wil->txrx_ops.rx_fini = wil_rx_fini_edma;
1610 }
1611 
1612