1 /* 2 * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/etherdevice.h> 18 #include <linux/moduleparam.h> 19 #include <linux/prefetch.h> 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include "wil6210.h" 25 #include "txrx_edma.h" 26 #include "txrx.h" 27 #include "trace.h" 28 29 #define WIL_EDMA_MAX_DATA_OFFSET (2) 30 /* RX buffer size must be aligned to 4 bytes */ 31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 32 33 static void wil_tx_desc_unmap_edma(struct device *dev, 34 union wil_tx_desc *desc, 35 struct wil_ctx *ctx) 36 { 37 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 38 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 39 u16 dmalen = le16_to_cpu(d->dma.length); 40 41 switch (ctx->mapped_as) { 42 case wil_mapped_as_single: 43 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 44 break; 45 case wil_mapped_as_page: 46 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 47 break; 48 default: 49 break; 50 } 51 } 52 53 static int wil_find_free_sring(struct wil6210_priv *wil) 54 { 55 int i; 56 57 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 58 if (!wil->srings[i].va) 59 return i; 60 } 61 62 return -EINVAL; 63 } 64 65 static void wil_sring_free(struct wil6210_priv *wil, 66 struct wil_status_ring *sring) 67 { 68 struct device *dev = wil_to_dev(wil); 69 size_t sz; 70 71 if (!sring || !sring->va) 72 return; 73 74 sz = sring->elem_size * sring->size; 75 76 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 77 sz, sring->va, &sring->pa); 78 79 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 80 sring->pa = 0; 81 sring->va = NULL; 82 } 83 84 static int wil_sring_alloc(struct wil6210_priv *wil, 85 struct wil_status_ring *sring) 86 { 87 struct device *dev = wil_to_dev(wil); 88 size_t sz = sring->elem_size * sring->size; 89 90 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 91 92 if (sz == 0) { 93 wil_err(wil, "Cannot allocate a zero size status ring\n"); 94 return -EINVAL; 95 } 96 97 sring->swhead = 0; 98 99 /* Status messages are allocated and initialized to 0. This is necessary 100 * since DR bit should be initialized to 0. 101 */ 102 sring->va = dma_zalloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 103 if (!sring->va) 104 return -ENOMEM; 105 106 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 107 &sring->pa); 108 109 return 0; 110 } 111 112 static int wil_tx_init_edma(struct wil6210_priv *wil) 113 { 114 int ring_id = wil_find_free_sring(wil); 115 struct wil_status_ring *sring; 116 int rc; 117 u16 status_ring_size; 118 119 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 120 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 121 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 122 123 status_ring_size = 1 << wil->tx_status_ring_order; 124 125 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 126 status_ring_size, ring_id); 127 128 if (ring_id < 0) 129 return ring_id; 130 131 /* Allocate Tx status ring. Tx descriptor rings will be 132 * allocated on WMI connect event 133 */ 134 sring = &wil->srings[ring_id]; 135 136 sring->is_rx = false; 137 sring->size = status_ring_size; 138 sring->elem_size = sizeof(struct wil_ring_tx_status); 139 rc = wil_sring_alloc(wil, sring); 140 if (rc) 141 return rc; 142 143 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 144 if (rc) 145 goto out_free; 146 147 sring->desc_rdy_pol = 1; 148 wil->tx_sring_idx = ring_id; 149 150 return 0; 151 out_free: 152 wil_sring_free(wil, sring); 153 return rc; 154 } 155 156 /** 157 * Allocate one skb for Rx descriptor RING 158 */ 159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 160 struct wil_ring *ring, u32 i) 161 { 162 struct device *dev = wil_to_dev(wil); 163 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 164 dma_addr_t pa; 165 u16 buff_id; 166 struct list_head *active = &wil->rx_buff_mgmt.active; 167 struct list_head *free = &wil->rx_buff_mgmt.free; 168 struct wil_rx_buff *rx_buff; 169 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 170 struct sk_buff *skb; 171 struct wil_rx_enhanced_desc dd, *d = ⅆ 172 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 173 &ring->va[i].rx.enhanced; 174 175 if (unlikely(list_empty(free))) { 176 wil->rx_buff_mgmt.free_list_empty_cnt++; 177 return -EAGAIN; 178 } 179 180 skb = dev_alloc_skb(sz); 181 if (unlikely(!skb)) 182 return -ENOMEM; 183 184 skb_put(skb, sz); 185 186 /** 187 * Make sure that the network stack calculates checksum for packets 188 * which failed the HW checksum calculation 189 */ 190 skb->ip_summed = CHECKSUM_NONE; 191 192 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 193 if (unlikely(dma_mapping_error(dev, pa))) { 194 kfree_skb(skb); 195 return -ENOMEM; 196 } 197 198 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 199 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 200 buff_id = rx_buff->id; 201 202 /* Move a buffer from the free list to the active list */ 203 list_move(&rx_buff->list, active); 204 205 buff_arr[buff_id].skb = skb; 206 207 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 208 d->dma.length = cpu_to_le16(sz); 209 d->mac.buff_id = cpu_to_le16(buff_id); 210 *_d = *d; 211 212 /* Save the physical address in skb->cb for later use in dma_unmap */ 213 memcpy(skb->cb, &pa, sizeof(pa)); 214 215 return 0; 216 } 217 218 static inline 219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg) 220 { 221 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)), 222 sring->elem_size); 223 } 224 225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 226 { 227 sring->swhead = (sring->swhead + 1) % sring->size; 228 if (sring->swhead == 0) 229 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 230 } 231 232 static int wil_rx_refill_edma(struct wil6210_priv *wil) 233 { 234 struct wil_ring *ring = &wil->ring_rx; 235 u32 next_head; 236 int rc = 0; 237 u32 swtail = *ring->edma_rx_swtail.va; 238 239 for (; next_head = wil_ring_next_head(ring), (next_head != swtail); 240 ring->swhead = next_head) { 241 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 242 if (unlikely(rc)) { 243 if (rc == -EAGAIN) 244 wil_dbg_txrx(wil, "No free buffer ID found\n"); 245 else 246 wil_err_ratelimited(wil, 247 "Error %d in refill desc[%d]\n", 248 rc, ring->swhead); 249 break; 250 } 251 } 252 253 /* make sure all writes to descriptors (shared memory) are done before 254 * committing them to HW 255 */ 256 wmb(); 257 258 wil_w(wil, ring->hwtail, ring->swhead); 259 260 return rc; 261 } 262 263 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 264 struct wil_ring *ring) 265 { 266 struct device *dev = wil_to_dev(wil); 267 u32 next_tail; 268 u32 swhead = (ring->swhead + 1) % ring->size; 269 dma_addr_t pa; 270 u16 dmalen; 271 272 for (; next_tail = wil_ring_next_tail(ring), (next_tail != swhead); 273 ring->swtail = next_tail) { 274 struct wil_rx_enhanced_desc dd, *d = ⅆ 275 struct wil_rx_enhanced_desc *_d = 276 (struct wil_rx_enhanced_desc *) 277 &ring->va[ring->swtail].rx.enhanced; 278 struct sk_buff *skb; 279 u16 buff_id; 280 281 *d = *_d; 282 283 /* Extract the SKB from the rx_buff management array */ 284 buff_id = __le16_to_cpu(d->mac.buff_id); 285 if (buff_id >= wil->rx_buff_mgmt.size) { 286 wil_err(wil, "invalid buff_id %d\n", buff_id); 287 continue; 288 } 289 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 290 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 291 if (unlikely(!skb)) { 292 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 293 } else { 294 pa = wil_rx_desc_get_addr_edma(&d->dma); 295 dmalen = le16_to_cpu(d->dma.length); 296 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE); 297 298 kfree_skb(skb); 299 } 300 301 /* Move the buffer from the active to the free list */ 302 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 303 &wil->rx_buff_mgmt.free); 304 } 305 } 306 307 static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 308 { 309 struct wil_ring *ring = &wil->ring_rx; 310 311 if (!wil->rx_buff_mgmt.buff_arr) 312 return; 313 314 /* Move all the buffers to the free list in case active list is 315 * not empty in order to release all SKBs before deleting the array 316 */ 317 wil_move_all_rx_buff_to_free_list(wil, ring); 318 319 kfree(wil->rx_buff_mgmt.buff_arr); 320 wil->rx_buff_mgmt.buff_arr = NULL; 321 } 322 323 static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 324 size_t size) 325 { 326 struct wil_rx_buff *buff_arr; 327 struct list_head *active = &wil->rx_buff_mgmt.active; 328 struct list_head *free = &wil->rx_buff_mgmt.free; 329 int i; 330 331 wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff), 332 GFP_KERNEL); 333 if (!wil->rx_buff_mgmt.buff_arr) 334 return -ENOMEM; 335 336 /* Set list heads */ 337 INIT_LIST_HEAD(active); 338 INIT_LIST_HEAD(free); 339 340 /* Linkify the list */ 341 buff_arr = wil->rx_buff_mgmt.buff_arr; 342 for (i = 0; i < size; i++) { 343 list_add(&buff_arr[i].list, free); 344 buff_arr[i].id = i; 345 } 346 347 wil->rx_buff_mgmt.size = size; 348 349 return 0; 350 } 351 352 static int wil_init_rx_sring(struct wil6210_priv *wil, 353 u16 status_ring_size, 354 size_t elem_size, 355 u16 ring_id) 356 { 357 struct wil_status_ring *sring = &wil->srings[ring_id]; 358 int rc; 359 360 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", sring->size, 361 ring_id); 362 363 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 364 365 sring->is_rx = true; 366 sring->size = status_ring_size; 367 sring->elem_size = elem_size; 368 rc = wil_sring_alloc(wil, sring); 369 if (rc) 370 return rc; 371 372 rc = wil_wmi_rx_sring_add(wil, ring_id); 373 if (rc) 374 goto out_free; 375 376 sring->desc_rdy_pol = 1; 377 378 return 0; 379 out_free: 380 wil_sring_free(wil, sring); 381 return rc; 382 } 383 384 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 385 struct wil_ring *ring) 386 { 387 struct device *dev = wil_to_dev(wil); 388 size_t sz = ring->size * sizeof(ring->va[0]); 389 390 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 391 392 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 393 394 ring->swhead = 0; 395 ring->swtail = 0; 396 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 397 if (!ring->ctx) 398 goto err; 399 400 ring->va = dma_zalloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 401 if (!ring->va) 402 goto err_free_ctx; 403 404 if (ring->is_rx) { 405 sz = sizeof(*ring->edma_rx_swtail.va); 406 ring->edma_rx_swtail.va = 407 dma_zalloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 408 GFP_KERNEL); 409 if (!ring->edma_rx_swtail.va) 410 goto err_free_va; 411 } 412 413 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 414 ring->is_rx ? "RX" : "TX", 415 ring->size, ring->va, &ring->pa, ring->ctx); 416 417 return 0; 418 err_free_va: 419 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 420 (void *)ring->va, ring->pa); 421 ring->va = NULL; 422 err_free_ctx: 423 kfree(ring->ctx); 424 ring->ctx = NULL; 425 err: 426 return -ENOMEM; 427 } 428 429 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 430 { 431 struct device *dev = wil_to_dev(wil); 432 size_t sz; 433 int ring_index = 0; 434 435 if (!ring->va) 436 return; 437 438 sz = ring->size * sizeof(ring->va[0]); 439 440 lockdep_assert_held(&wil->mutex); 441 if (ring->is_rx) { 442 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 443 ring->size, ring->va, 444 &ring->pa, ring->ctx); 445 446 wil_move_all_rx_buff_to_free_list(wil, ring); 447 goto out; 448 } 449 450 /* TX ring */ 451 ring_index = ring - wil->ring_tx; 452 453 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 454 ring_index, ring->size, ring->va, 455 &ring->pa, ring->ctx); 456 457 while (!wil_ring_is_empty(ring)) { 458 struct wil_ctx *ctx; 459 460 struct wil_tx_enhanced_desc dd, *d = ⅆ 461 struct wil_tx_enhanced_desc *_d = 462 (struct wil_tx_enhanced_desc *) 463 &ring->va[ring->swtail].tx.enhanced; 464 465 ctx = &ring->ctx[ring->swtail]; 466 if (!ctx) { 467 wil_dbg_txrx(wil, 468 "ctx(%d) was already completed\n", 469 ring->swtail); 470 ring->swtail = wil_ring_next_tail(ring); 471 continue; 472 } 473 *d = *_d; 474 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 475 if (ctx->skb) 476 dev_kfree_skb_any(ctx->skb); 477 ring->swtail = wil_ring_next_tail(ring); 478 } 479 480 out: 481 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 482 kfree(ring->ctx); 483 ring->pa = 0; 484 ring->va = NULL; 485 ring->ctx = NULL; 486 } 487 488 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 489 int status_ring_id) 490 { 491 struct wil_ring *ring = &wil->ring_rx; 492 int rc; 493 494 wil_dbg_misc(wil, "init RX desc ring\n"); 495 496 ring->size = desc_ring_size; 497 ring->is_rx = true; 498 rc = wil_ring_alloc_desc_ring(wil, ring); 499 if (rc) 500 return rc; 501 502 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 503 if (rc) 504 goto out_free; 505 506 return 0; 507 out_free: 508 wil_ring_free_edma(wil, ring); 509 return rc; 510 } 511 512 static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 513 struct sk_buff *skb, int *tid, 514 int *cid, int *mid, u16 *seq, 515 int *mcast, int *retry) 516 { 517 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 518 519 *tid = wil_rx_status_get_tid(s); 520 *cid = wil_rx_status_get_cid(s); 521 *mid = wil_rx_status_get_mid(s); 522 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 523 *mcast = wil_rx_status_get_mcast(s); 524 *retry = wil_rx_status_get_retry(s); 525 } 526 527 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 528 int *security) 529 { 530 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 531 532 *cid = wil_rx_status_get_cid(s); 533 *security = wil_rx_status_get_security(s); 534 } 535 536 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 537 struct sk_buff *skb) 538 { 539 struct wil_rx_status_extended *st; 540 int cid, tid, key_id, mc; 541 struct wil_sta_info *s; 542 struct wil_tid_crypto_rx *c; 543 struct wil_tid_crypto_rx_single *cc; 544 const u8 *pn; 545 546 /* In HW reorder, HW is responsible for crypto check */ 547 if (wil->use_rx_hw_reordering) 548 return 0; 549 550 st = wil_skb_rxstatus(skb); 551 552 cid = wil_rx_status_get_cid(st); 553 tid = wil_rx_status_get_tid(st); 554 key_id = wil_rx_status_get_key_id(st); 555 mc = wil_rx_status_get_mcast(st); 556 s = &wil->sta[cid]; 557 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 558 cc = &c->key_id[key_id]; 559 pn = (u8 *)&st->ext.pn_15_0; 560 561 if (!cc->key_set) { 562 wil_err_ratelimited(wil, 563 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 564 cid, tid, mc, key_id); 565 return -EINVAL; 566 } 567 568 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 569 wil_err_ratelimited(wil, 570 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 571 cid, tid, mc, key_id, pn, cc->pn); 572 return -EINVAL; 573 } 574 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 575 576 return 0; 577 } 578 579 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 580 { 581 struct wil_status_ring *sring; 582 struct wil_rx_status_extended msg1; 583 void *msg = &msg1; 584 u8 dr_bit; 585 int i; 586 587 for (i = 0; i < wil->num_rx_status_rings; i++) { 588 sring = &wil->srings[i]; 589 if (!sring->va) 590 continue; 591 592 wil_get_next_rx_status_msg(sring, msg); 593 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 594 595 /* Check if there are unhandled RX status messages */ 596 if (dr_bit == sring->desc_rdy_pol) 597 return false; 598 } 599 600 return true; 601 } 602 603 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 604 { 605 wil->rx_buf_len = rx_large_buf ? 606 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 607 } 608 609 static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size) 610 { 611 u16 status_ring_size; 612 struct wil_ring *ring = &wil->ring_rx; 613 int rc; 614 size_t elem_size = wil->use_compressed_rx_status ? 615 sizeof(struct wil_rx_status_compressed) : 616 sizeof(struct wil_rx_status_extended); 617 int i; 618 u16 max_rx_pl_per_desc; 619 620 /* In SW reorder one must use extended status messages */ 621 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 622 wil_err(wil, 623 "compressed RX status cannot be used with SW reorder\n"); 624 return -EINVAL; 625 } 626 627 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 628 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 629 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 630 631 status_ring_size = 1 << wil->rx_status_ring_order; 632 633 wil_dbg_misc(wil, 634 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 635 desc_ring_size, status_ring_size, elem_size); 636 637 wil_rx_buf_len_init_edma(wil); 638 639 max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4); 640 641 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 642 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 643 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 644 645 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 646 wil->num_rx_status_rings); 647 648 rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc); 649 if (rc) 650 return rc; 651 652 /* Allocate status ring */ 653 for (i = 0; i < wil->num_rx_status_rings; i++) { 654 int sring_id = wil_find_free_sring(wil); 655 656 if (sring_id < 0) { 657 rc = -EFAULT; 658 goto err_free_status; 659 } 660 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 661 sring_id); 662 if (rc) 663 goto err_free_status; 664 } 665 666 /* Allocate descriptor ring */ 667 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 668 WIL_DEFAULT_RX_STATUS_RING_ID); 669 if (rc) 670 goto err_free_status; 671 672 if (wil->rx_buff_id_count >= status_ring_size) { 673 wil_info(wil, 674 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 675 wil->rx_buff_id_count, status_ring_size, 676 status_ring_size - 1); 677 wil->rx_buff_id_count = status_ring_size - 1; 678 } 679 680 /* Allocate Rx buffer array */ 681 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 682 if (rc) 683 goto err_free_desc; 684 685 /* Fill descriptor ring with credits */ 686 rc = wil_rx_refill_edma(wil); 687 if (rc) 688 goto err_free_rx_buff_arr; 689 690 return 0; 691 err_free_rx_buff_arr: 692 wil_free_rx_buff_arr(wil); 693 err_free_desc: 694 wil_ring_free_edma(wil, ring); 695 err_free_status: 696 for (i = 0; i < wil->num_rx_status_rings; i++) 697 wil_sring_free(wil, &wil->srings[i]); 698 699 return rc; 700 } 701 702 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 703 int size, int cid, int tid) 704 { 705 struct wil6210_priv *wil = vif_to_wil(vif); 706 int rc; 707 struct wil_ring *ring = &wil->ring_tx[ring_id]; 708 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 709 710 lockdep_assert_held(&wil->mutex); 711 712 wil_dbg_misc(wil, 713 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 714 ring_id, cid, tid, wil->tx_sring_idx); 715 716 wil_tx_data_init(txdata); 717 ring->size = size; 718 rc = wil_ring_alloc_desc_ring(wil, ring); 719 if (rc) 720 goto out; 721 722 wil->ring2cid_tid[ring_id][0] = cid; 723 wil->ring2cid_tid[ring_id][1] = tid; 724 if (!vif->privacy) 725 txdata->dot1x_open = true; 726 727 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 728 if (rc) { 729 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 730 goto out_free; 731 } 732 733 if (txdata->dot1x_open && agg_wsize >= 0) 734 wil_addba_tx_request(wil, ring_id, agg_wsize); 735 736 return 0; 737 out_free: 738 spin_lock_bh(&txdata->lock); 739 txdata->dot1x_open = false; 740 txdata->enabled = 0; 741 spin_unlock_bh(&txdata->lock); 742 wil_ring_free_edma(wil, ring); 743 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; 744 wil->ring2cid_tid[ring_id][1] = 0; 745 746 out: 747 return rc; 748 } 749 750 static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, 751 int cid, int tid) 752 { 753 struct wil6210_priv *wil = vif_to_wil(vif); 754 755 wil_err(wil, "ring modify is not supported for EDMA\n"); 756 757 return -EOPNOTSUPP; 758 } 759 760 /* This function is used only for RX SW reorder */ 761 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 762 struct sk_buff *skb, struct wil_net_stats *stats) 763 { 764 u8 ftype; 765 u8 fc1; 766 int mid; 767 int tid; 768 u16 seq; 769 struct wil6210_vif *vif; 770 771 ftype = wil_rx_status_get_frame_type(wil, msg); 772 if (ftype == IEEE80211_FTYPE_DATA) 773 return 0; 774 775 fc1 = wil_rx_status_get_fc1(wil, msg); 776 mid = wil_rx_status_get_mid(msg); 777 tid = wil_rx_status_get_tid(msg); 778 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 779 vif = wil->vifs[mid]; 780 781 if (unlikely(!vif)) { 782 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 783 return -EAGAIN; 784 } 785 786 wil_dbg_txrx(wil, 787 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 788 fc1, mid, cid, tid, seq); 789 if (stats) 790 stats->rx_non_data_frame++; 791 if (wil_is_back_req(fc1)) { 792 wil_dbg_txrx(wil, 793 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 794 mid, cid, tid, seq); 795 wil_rx_bar(wil, vif, cid, tid, seq); 796 } else { 797 u32 sz = wil->use_compressed_rx_status ? 798 sizeof(struct wil_rx_status_compressed) : 799 sizeof(struct wil_rx_status_extended); 800 801 /* print again all info. One can enable only this 802 * without overhead for printing every Rx frame 803 */ 804 wil_dbg_txrx(wil, 805 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 806 fc1, mid, cid, tid, seq); 807 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 808 (const void *)msg, sz, false); 809 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 810 skb->data, skb_headlen(skb), false); 811 } 812 813 return -EAGAIN; 814 } 815 816 static int wil_rx_error_check_edma(struct wil6210_priv *wil, 817 struct sk_buff *skb, 818 struct wil_net_stats *stats) 819 { 820 int error; 821 int l2_rx_status; 822 int l3_rx_status; 823 int l4_rx_status; 824 void *msg = wil_skb_rxstatus(skb); 825 826 error = wil_rx_status_get_error(msg); 827 if (!error) { 828 skb->ip_summed = CHECKSUM_UNNECESSARY; 829 return 0; 830 } 831 832 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 833 if (l2_rx_status != 0) { 834 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 835 l2_rx_status); 836 /* Due to HW issue, KEY error will trigger a MIC error */ 837 if (l2_rx_status & WIL_RX_EDMA_ERROR_MIC) { 838 wil_dbg_txrx(wil, 839 "L2 MIC/KEY error, dropping packet\n"); 840 stats->rx_mic_error++; 841 } 842 if (l2_rx_status & WIL_RX_EDMA_ERROR_KEY) { 843 wil_dbg_txrx(wil, "L2 KEY error, dropping packet\n"); 844 stats->rx_key_error++; 845 } 846 if (l2_rx_status & WIL_RX_EDMA_ERROR_REPLAY) { 847 wil_dbg_txrx(wil, 848 "L2 REPLAY error, dropping packet\n"); 849 stats->rx_replay++; 850 } 851 if (l2_rx_status & WIL_RX_EDMA_ERROR_AMSDU) { 852 wil_dbg_txrx(wil, 853 "L2 AMSDU error, dropping packet\n"); 854 stats->rx_amsdu_error++; 855 } 856 return -EFAULT; 857 } 858 859 l3_rx_status = wil_rx_status_get_l3_rx_status(msg); 860 l4_rx_status = wil_rx_status_get_l4_rx_status(msg); 861 if (!l3_rx_status && !l4_rx_status) 862 skb->ip_summed = CHECKSUM_UNNECESSARY; 863 /* If HW reports bad checksum, let IP stack re-check it 864 * For example, HW don't understand Microsoft IP stack that 865 * mis-calculates TCP checksum - if it should be 0x0, 866 * it writes 0xffff in violation of RFC 1624 867 */ 868 else 869 stats->rx_csum_err++; 870 871 return 0; 872 } 873 874 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 875 struct wil_status_ring *sring) 876 { 877 struct device *dev = wil_to_dev(wil); 878 struct wil_rx_status_extended msg1; 879 void *msg = &msg1; 880 u16 buff_id; 881 struct sk_buff *skb; 882 dma_addr_t pa; 883 struct wil_ring_rx_data *rxdata = &sring->rx_data; 884 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 885 struct wil_net_stats *stats = NULL; 886 u16 dmalen; 887 int cid; 888 bool eop, headstolen; 889 int delta; 890 u8 dr_bit; 891 u8 data_offset; 892 struct wil_rx_status_extended *s; 893 u16 sring_idx = sring - wil->srings; 894 895 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 896 897 again: 898 wil_get_next_rx_status_msg(sring, msg); 899 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 900 901 /* Completed handling all the ready status messages */ 902 if (dr_bit != sring->desc_rdy_pol) 903 return NULL; 904 905 /* Extract the buffer ID from the status message */ 906 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 907 if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) { 908 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 909 buff_id, sring->swhead); 910 wil_sring_advance_swhead(sring); 911 goto again; 912 } 913 914 wil_sring_advance_swhead(sring); 915 916 /* Extract the SKB from the rx_buff management array */ 917 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 918 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 919 if (!skb) { 920 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 921 /* Move the buffer from the active list to the free list */ 922 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 923 &wil->rx_buff_mgmt.free); 924 goto again; 925 } 926 927 memcpy(&pa, skb->cb, sizeof(pa)); 928 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 929 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 930 931 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 932 msg); 933 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 934 buff_id, sring_idx, dmalen); 935 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 936 (const void *)msg, wil->use_compressed_rx_status ? 937 sizeof(struct wil_rx_status_compressed) : 938 sizeof(struct wil_rx_status_extended), false); 939 940 /* Move the buffer from the active list to the free list */ 941 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 942 &wil->rx_buff_mgmt.free); 943 944 eop = wil_rx_status_get_eop(msg); 945 946 cid = wil_rx_status_get_cid(msg); 947 if (unlikely(!wil_val_in_range(cid, 0, WIL6210_MAX_CID))) { 948 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 949 cid, sring->swhead); 950 rxdata->skipping = true; 951 goto skipping; 952 } 953 stats = &wil->sta[cid].stats; 954 955 if (unlikely(skb->len < ETH_HLEN)) { 956 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len); 957 stats->rx_short_frame++; 958 rxdata->skipping = true; 959 goto skipping; 960 } 961 962 if (unlikely(dmalen > sz)) { 963 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 964 stats->rx_large_frame++; 965 rxdata->skipping = true; 966 } 967 968 skipping: 969 /* skipping indicates if a certain SKB should be dropped. 970 * It is set in case there is an error on the current SKB or in case 971 * of RX chaining: as long as we manage to merge the SKBs it will 972 * be false. once we have a bad SKB or we don't manage to merge SKBs 973 * it will be set to the !EOP value of the current SKB. 974 * This guarantees that all the following SKBs until EOP will also 975 * get dropped. 976 */ 977 if (unlikely(rxdata->skipping)) { 978 kfree_skb(skb); 979 if (rxdata->skb) { 980 kfree_skb(rxdata->skb); 981 rxdata->skb = NULL; 982 } 983 rxdata->skipping = !eop; 984 goto again; 985 } 986 987 skb_trim(skb, dmalen); 988 989 prefetch(skb->data); 990 991 if (!rxdata->skb) { 992 rxdata->skb = skb; 993 } else { 994 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 995 &delta))) { 996 kfree_skb_partial(skb, headstolen); 997 } else { 998 wil_err(wil, "failed to merge skbs!\n"); 999 kfree_skb(skb); 1000 kfree_skb(rxdata->skb); 1001 rxdata->skb = NULL; 1002 rxdata->skipping = !eop; 1003 goto again; 1004 } 1005 } 1006 1007 if (!eop) 1008 goto again; 1009 1010 /* reaching here rxdata->skb always contains a full packet */ 1011 skb = rxdata->skb; 1012 rxdata->skb = NULL; 1013 rxdata->skipping = false; 1014 1015 if (stats) { 1016 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1017 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1018 stats->rx_per_mcs[stats->last_mcs_rx]++; 1019 } 1020 1021 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1022 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1023 kfree_skb(skb); 1024 goto again; 1025 } 1026 1027 /* Compensate for the HW data alignment according to the status 1028 * message 1029 */ 1030 data_offset = wil_rx_status_get_data_offset(msg); 1031 if (data_offset == 0xFF || 1032 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1033 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1034 kfree_skb(skb); 1035 goto again; 1036 } 1037 1038 skb_pull(skb, data_offset); 1039 1040 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1041 skb->data, skb_headlen(skb), false); 1042 1043 /* Has to be done after dma_unmap_single as skb->cb is also 1044 * used for holding the pa 1045 */ 1046 s = wil_skb_rxstatus(skb); 1047 memcpy(s, msg, sring->elem_size); 1048 1049 return skb; 1050 } 1051 1052 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1053 { 1054 struct net_device *ndev; 1055 struct wil_ring *ring = &wil->ring_rx; 1056 struct wil_status_ring *sring; 1057 struct sk_buff *skb; 1058 int i; 1059 1060 if (unlikely(!ring->va)) { 1061 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1062 return; 1063 } 1064 wil_dbg_txrx(wil, "rx_handle\n"); 1065 1066 for (i = 0; i < wil->num_rx_status_rings; i++) { 1067 sring = &wil->srings[i]; 1068 if (unlikely(!sring->va)) { 1069 wil_err(wil, 1070 "Rx IRQ while Rx status ring %d not yet initialized\n", 1071 i); 1072 continue; 1073 } 1074 1075 while ((*quota > 0) && 1076 (NULL != (skb = 1077 wil_sring_reap_rx_edma(wil, sring)))) { 1078 (*quota)--; 1079 if (wil->use_rx_hw_reordering) { 1080 void *msg = wil_skb_rxstatus(skb); 1081 int mid = wil_rx_status_get_mid(msg); 1082 struct wil6210_vif *vif = wil->vifs[mid]; 1083 1084 if (unlikely(!vif)) { 1085 wil_dbg_txrx(wil, 1086 "RX desc invalid mid %d", 1087 mid); 1088 kfree_skb(skb); 1089 continue; 1090 } 1091 ndev = vif_to_ndev(vif); 1092 wil_netif_rx_any(skb, ndev); 1093 } else { 1094 wil_rx_reorder(wil, skb); 1095 } 1096 } 1097 1098 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1099 } 1100 1101 wil_rx_refill_edma(wil); 1102 } 1103 1104 static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1105 dma_addr_t pa, 1106 u32 len, 1107 int ring_index) 1108 { 1109 struct wil_tx_enhanced_desc *d = 1110 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1111 1112 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1113 1114 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1115 1116 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1117 d->dma.length = cpu_to_le16((u16)len); 1118 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1119 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1120 * 3 - eth mode 1121 */ 1122 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1123 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1124 1125 return 0; 1126 } 1127 1128 static inline void 1129 wil_get_next_tx_status_msg(struct wil_status_ring *sring, 1130 struct wil_ring_tx_status *msg) 1131 { 1132 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1133 (sring->va + (sring->elem_size * sring->swhead)); 1134 1135 *msg = *_msg; 1136 } 1137 1138 /** 1139 * Clean up transmitted skb's from the Tx descriptor RING. 1140 * Return number of descriptors cleared. 1141 */ 1142 int wil_tx_sring_handler(struct wil6210_priv *wil, 1143 struct wil_status_ring *sring) 1144 { 1145 struct net_device *ndev; 1146 struct device *dev = wil_to_dev(wil); 1147 struct wil_ring *ring = NULL; 1148 struct wil_ring_tx_data *txdata; 1149 /* Total number of completed descriptors in all descriptor rings */ 1150 int desc_cnt = 0; 1151 int cid; 1152 struct wil_net_stats *stats = NULL; 1153 struct wil_tx_enhanced_desc *_d; 1154 unsigned int ring_id; 1155 unsigned int num_descs; 1156 int i; 1157 u8 dr_bit; /* Descriptor Ready bit */ 1158 struct wil_ring_tx_status msg; 1159 struct wil6210_vif *vif; 1160 int used_before_complete; 1161 int used_new; 1162 1163 wil_get_next_tx_status_msg(sring, &msg); 1164 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1165 1166 /* Process completion messages while DR bit has the expected polarity */ 1167 while (dr_bit == sring->desc_rdy_pol) { 1168 num_descs = msg.num_descriptors; 1169 if (!num_descs) { 1170 wil_err(wil, "invalid num_descs 0\n"); 1171 goto again; 1172 } 1173 1174 /* Find the corresponding descriptor ring */ 1175 ring_id = msg.ring_id; 1176 1177 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1178 wil_err(wil, "invalid ring id %d\n", ring_id); 1179 goto again; 1180 } 1181 ring = &wil->ring_tx[ring_id]; 1182 if (unlikely(!ring->va)) { 1183 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1184 ring_id); 1185 goto again; 1186 } 1187 txdata = &wil->ring_tx_data[ring_id]; 1188 if (unlikely(!txdata->enabled)) { 1189 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1190 goto again; 1191 } 1192 vif = wil->vifs[txdata->mid]; 1193 if (unlikely(!vif)) { 1194 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1195 txdata->mid, ring_id); 1196 goto again; 1197 } 1198 1199 ndev = vif_to_ndev(vif); 1200 1201 cid = wil->ring2cid_tid[ring_id][0]; 1202 if (cid < WIL6210_MAX_CID) 1203 stats = &wil->sta[cid].stats; 1204 1205 wil_dbg_txrx(wil, 1206 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1207 ring_id, num_descs); 1208 1209 used_before_complete = wil_ring_used_tx(ring); 1210 1211 for (i = 0 ; i < num_descs; ++i) { 1212 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1213 struct wil_tx_enhanced_desc dd, *d = ⅆ 1214 u16 dmalen; 1215 struct sk_buff *skb = ctx->skb; 1216 1217 _d = (struct wil_tx_enhanced_desc *) 1218 &ring->va[ring->swtail].tx.enhanced; 1219 *d = *_d; 1220 1221 dmalen = le16_to_cpu(d->dma.length); 1222 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1223 wil_dbg_txrx(wil, 1224 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1225 ring_id, ring->swtail, dmalen, 1226 msg.status); 1227 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1228 (const void *)&msg, sizeof(msg), 1229 false); 1230 1231 wil_tx_desc_unmap_edma(dev, 1232 (union wil_tx_desc *)d, 1233 ctx); 1234 1235 if (skb) { 1236 if (likely(msg.status == 0)) { 1237 ndev->stats.tx_packets++; 1238 ndev->stats.tx_bytes += skb->len; 1239 if (stats) { 1240 stats->tx_packets++; 1241 stats->tx_bytes += skb->len; 1242 1243 wil_tx_latency_calc(wil, skb, 1244 &wil->sta[cid]); 1245 } 1246 } else { 1247 ndev->stats.tx_errors++; 1248 if (stats) 1249 stats->tx_errors++; 1250 } 1251 wil_consume_skb(skb, msg.status == 0); 1252 } 1253 memset(ctx, 0, sizeof(*ctx)); 1254 /* Make sure the ctx is zeroed before updating the tail 1255 * to prevent a case where wil_tx_ring will see 1256 * this descriptor as used and handle it before ctx zero 1257 * is completed. 1258 */ 1259 wmb(); 1260 1261 ring->swtail = wil_ring_next_tail(ring); 1262 1263 desc_cnt++; 1264 } 1265 1266 /* performance monitoring */ 1267 used_new = wil_ring_used_tx(ring); 1268 if (wil_val_in_range(wil->ring_idle_trsh, 1269 used_new, used_before_complete)) { 1270 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1271 ring_id, used_before_complete, used_new); 1272 txdata->last_idle = get_cycles(); 1273 } 1274 1275 again: 1276 wil_sring_advance_swhead(sring); 1277 1278 wil_get_next_tx_status_msg(sring, &msg); 1279 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1280 } 1281 1282 /* shall we wake net queues? */ 1283 if (desc_cnt) 1284 wil_update_net_queues(wil, vif, NULL, false); 1285 1286 /* Update the HW tail ptr (RD ptr) */ 1287 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1288 1289 return desc_cnt; 1290 } 1291 1292 /** 1293 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1294 * @skb is used to obtain the protocol and headers length. 1295 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1296 * 2 - middle, 3 - last descriptor. 1297 */ 1298 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1299 int tso_desc_type, bool is_ipv4, 1300 int tcp_hdr_len, 1301 int skb_net_hdr_len, 1302 int mss) 1303 { 1304 /* Number of descriptors */ 1305 d->mac.d[2] |= 1; 1306 /* Maximum Segment Size */ 1307 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1308 /* L4 header len: TCP header length */ 1309 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1310 /* EOP, TSO desc type, Segmentation enable, 1311 * Insert IPv4 and TCP / UDP Checksum 1312 */ 1313 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1314 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1315 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1316 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1317 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1318 /* Calculate pseudo-header */ 1319 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1320 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1321 /* IP Header Length */ 1322 d->dma.ip_length |= skb_net_hdr_len; 1323 /* MAC header length and IP address family*/ 1324 d->dma.b11 |= ETH_HLEN | 1325 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1326 } 1327 1328 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1329 int len, uint i, int tso_desc_type, 1330 skb_frag_t *frag, struct wil_ring *ring, 1331 struct sk_buff *skb, bool is_ipv4, 1332 int tcp_hdr_len, int skb_net_hdr_len, 1333 int mss, int *descs_used) 1334 { 1335 struct device *dev = wil_to_dev(wil); 1336 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1337 &ring->va[i].tx.enhanced; 1338 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1339 int ring_index = ring - wil->ring_tx; 1340 dma_addr_t pa; 1341 1342 if (len == 0) 1343 return 0; 1344 1345 if (!frag) { 1346 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1347 ring->ctx[i].mapped_as = wil_mapped_as_single; 1348 } else { 1349 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1350 ring->ctx[i].mapped_as = wil_mapped_as_page; 1351 } 1352 if (unlikely(dma_mapping_error(dev, pa))) { 1353 wil_err(wil, "TSO: Skb DMA map error\n"); 1354 return -EINVAL; 1355 } 1356 1357 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1358 len, ring_index); 1359 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1360 tcp_hdr_len, 1361 skb_net_hdr_len, mss); 1362 1363 /* hold reference to skb 1364 * to prevent skb release before accounting 1365 * in case of immediate "tx done" 1366 */ 1367 if (tso_desc_type == wil_tso_type_lst) 1368 ring->ctx[i].skb = skb_get(skb); 1369 1370 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1371 (const void *)d, sizeof(*d), false); 1372 1373 *_desc = *d; 1374 (*descs_used)++; 1375 1376 return 0; 1377 } 1378 1379 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1380 struct wil6210_vif *vif, 1381 struct wil_ring *ring, 1382 struct sk_buff *skb) 1383 { 1384 int ring_index = ring - wil->ring_tx; 1385 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1386 int nr_frags = skb_shinfo(skb)->nr_frags; 1387 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1388 int used, avail = wil_ring_avail_tx(ring); 1389 int f, hdrlen, headlen; 1390 int gso_type; 1391 bool is_ipv4; 1392 u32 swhead = ring->swhead; 1393 int descs_used = 0; /* total number of used descriptors */ 1394 int rc = -EINVAL; 1395 int tcp_hdr_len; 1396 int skb_net_hdr_len; 1397 int mss = skb_shinfo(skb)->gso_size; 1398 1399 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1400 ring_index); 1401 1402 if (unlikely(!txdata->enabled)) 1403 return -EINVAL; 1404 1405 if (unlikely(avail < min_desc_required)) { 1406 wil_err_ratelimited(wil, 1407 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1408 ring_index, min_desc_required); 1409 return -ENOMEM; 1410 } 1411 1412 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1413 switch (gso_type) { 1414 case SKB_GSO_TCPV4: 1415 is_ipv4 = true; 1416 break; 1417 case SKB_GSO_TCPV6: 1418 is_ipv4 = false; 1419 break; 1420 default: 1421 return -EINVAL; 1422 } 1423 1424 if (skb->ip_summed != CHECKSUM_PARTIAL) 1425 return -EINVAL; 1426 1427 /* tcp header length and skb network header length are fixed for all 1428 * packet's descriptors - read them once here 1429 */ 1430 tcp_hdr_len = tcp_hdrlen(skb); 1431 skb_net_hdr_len = skb_network_header_len(skb); 1432 1433 /* First descriptor must contain the header only 1434 * Header Length = MAC header len + IP header len + TCP header len 1435 */ 1436 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1437 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1438 hdrlen); 1439 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1440 wil_tso_type_hdr, NULL, ring, skb, 1441 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1442 mss, &descs_used); 1443 if (rc) 1444 return -EINVAL; 1445 1446 /* Second descriptor contains the head */ 1447 headlen = skb_headlen(skb) - hdrlen; 1448 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1449 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1450 (swhead + descs_used) % ring->size, 1451 (nr_frags != 0) ? wil_tso_type_first : 1452 wil_tso_type_lst, NULL, ring, skb, 1453 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1454 mss, &descs_used); 1455 if (rc) 1456 goto mem_error; 1457 1458 /* Rest of the descriptors are from the SKB fragments */ 1459 for (f = 0; f < nr_frags; f++) { 1460 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1461 int len = frag->size; 1462 1463 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1464 len, descs_used); 1465 1466 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1467 (swhead + descs_used) % ring->size, 1468 (f != nr_frags - 1) ? 1469 wil_tso_type_mid : wil_tso_type_lst, 1470 frag, ring, skb, is_ipv4, 1471 tcp_hdr_len, skb_net_hdr_len, 1472 mss, &descs_used); 1473 if (rc) 1474 goto mem_error; 1475 } 1476 1477 /* performance monitoring */ 1478 used = wil_ring_used_tx(ring); 1479 if (wil_val_in_range(wil->ring_idle_trsh, 1480 used, used + descs_used)) { 1481 txdata->idle += get_cycles() - txdata->last_idle; 1482 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1483 ring_index, used, used + descs_used); 1484 } 1485 1486 /* advance swhead */ 1487 wil_ring_advance_head(ring, descs_used); 1488 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1489 1490 /* make sure all writes to descriptors (shared memory) are done before 1491 * committing them to HW 1492 */ 1493 wmb(); 1494 1495 if (wil->tx_latency) 1496 *(ktime_t *)&skb->cb = ktime_get(); 1497 else 1498 memset(skb->cb, 0, sizeof(ktime_t)); 1499 1500 wil_w(wil, ring->hwtail, ring->swhead); 1501 1502 return 0; 1503 1504 mem_error: 1505 while (descs_used > 0) { 1506 struct device *dev = wil_to_dev(wil); 1507 struct wil_ctx *ctx; 1508 int i = (swhead + descs_used - 1) % ring->size; 1509 struct wil_tx_enhanced_desc dd, *d = ⅆ 1510 struct wil_tx_enhanced_desc *_desc = 1511 (struct wil_tx_enhanced_desc *) 1512 &ring->va[i].tx.enhanced; 1513 1514 *d = *_desc; 1515 ctx = &ring->ctx[i]; 1516 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1517 memset(ctx, 0, sizeof(*ctx)); 1518 descs_used--; 1519 } 1520 return rc; 1521 } 1522 1523 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1524 int size) 1525 { 1526 struct wil6210_priv *wil = vif_to_wil(vif); 1527 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1528 int rc; 1529 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1530 1531 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1532 ring_id, wil->tx_sring_idx); 1533 1534 lockdep_assert_held(&wil->mutex); 1535 1536 wil_tx_data_init(txdata); 1537 ring->size = size; 1538 ring->is_rx = false; 1539 rc = wil_ring_alloc_desc_ring(wil, ring); 1540 if (rc) 1541 goto out; 1542 1543 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1544 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1545 if (!vif->privacy) 1546 txdata->dot1x_open = true; 1547 1548 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1549 if (rc) 1550 goto out_free; 1551 1552 return 0; 1553 1554 out_free: 1555 spin_lock_bh(&txdata->lock); 1556 txdata->enabled = 0; 1557 txdata->dot1x_open = false; 1558 spin_unlock_bh(&txdata->lock); 1559 wil_ring_free_edma(wil, ring); 1560 1561 out: 1562 return rc; 1563 } 1564 1565 static void wil_tx_fini_edma(struct wil6210_priv *wil) 1566 { 1567 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1568 1569 wil_dbg_misc(wil, "free TX sring\n"); 1570 1571 wil_sring_free(wil, sring); 1572 } 1573 1574 static void wil_rx_data_free(struct wil_status_ring *sring) 1575 { 1576 if (!sring) 1577 return; 1578 1579 kfree_skb(sring->rx_data.skb); 1580 sring->rx_data.skb = NULL; 1581 } 1582 1583 static void wil_rx_fini_edma(struct wil6210_priv *wil) 1584 { 1585 struct wil_ring *ring = &wil->ring_rx; 1586 int i; 1587 1588 wil_dbg_misc(wil, "rx_fini_edma\n"); 1589 1590 wil_ring_free_edma(wil, ring); 1591 1592 for (i = 0; i < wil->num_rx_status_rings; i++) { 1593 wil_rx_data_free(&wil->srings[i]); 1594 wil_sring_free(wil, &wil->srings[i]); 1595 } 1596 1597 wil_free_rx_buff_arr(wil); 1598 } 1599 1600 void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1601 { 1602 wil->txrx_ops.configure_interrupt_moderation = 1603 wil_configure_interrupt_moderation_edma; 1604 /* TX ops */ 1605 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1606 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1607 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1608 wil->txrx_ops.tx_init = wil_tx_init_edma; 1609 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1610 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1611 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1612 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1613 wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma; 1614 /* RX ops */ 1615 wil->txrx_ops.rx_init = wil_rx_init_edma; 1616 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1617 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1618 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1619 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1620 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1621 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1622 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1623 } 1624 1625