1 /* 2 * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/etherdevice.h> 18 #include <linux/moduleparam.h> 19 #include <linux/prefetch.h> 20 #include <linux/types.h> 21 #include <linux/list.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include "wil6210.h" 25 #include "txrx_edma.h" 26 #include "txrx.h" 27 #include "trace.h" 28 29 #define WIL_EDMA_MAX_DATA_OFFSET (2) 30 /* RX buffer size must be aligned to 4 bytes */ 31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048) 32 33 static void wil_tx_desc_unmap_edma(struct device *dev, 34 union wil_tx_desc *desc, 35 struct wil_ctx *ctx) 36 { 37 struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc; 38 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); 39 u16 dmalen = le16_to_cpu(d->dma.length); 40 41 switch (ctx->mapped_as) { 42 case wil_mapped_as_single: 43 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 44 break; 45 case wil_mapped_as_page: 46 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 47 break; 48 default: 49 break; 50 } 51 } 52 53 static int wil_find_free_sring(struct wil6210_priv *wil) 54 { 55 int i; 56 57 for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) { 58 if (!wil->srings[i].va) 59 return i; 60 } 61 62 return -EINVAL; 63 } 64 65 static void wil_sring_free(struct wil6210_priv *wil, 66 struct wil_status_ring *sring) 67 { 68 struct device *dev = wil_to_dev(wil); 69 size_t sz; 70 71 if (!sring || !sring->va) 72 return; 73 74 sz = sring->elem_size * sring->size; 75 76 wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n", 77 sz, sring->va, &sring->pa); 78 79 dma_free_coherent(dev, sz, (void *)sring->va, sring->pa); 80 sring->pa = 0; 81 sring->va = NULL; 82 } 83 84 static int wil_sring_alloc(struct wil6210_priv *wil, 85 struct wil_status_ring *sring) 86 { 87 struct device *dev = wil_to_dev(wil); 88 size_t sz = sring->elem_size * sring->size; 89 90 wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz); 91 92 if (sz == 0) { 93 wil_err(wil, "Cannot allocate a zero size status ring\n"); 94 return -EINVAL; 95 } 96 97 sring->swhead = 0; 98 99 /* Status messages are allocated and initialized to 0. This is necessary 100 * since DR bit should be initialized to 0. 101 */ 102 sring->va = dma_zalloc_coherent(dev, sz, &sring->pa, GFP_KERNEL); 103 if (!sring->va) 104 return -ENOMEM; 105 106 wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va, 107 &sring->pa); 108 109 return 0; 110 } 111 112 static int wil_tx_init_edma(struct wil6210_priv *wil) 113 { 114 int ring_id = wil_find_free_sring(wil); 115 struct wil_status_ring *sring; 116 int rc; 117 u16 status_ring_size; 118 119 if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 120 wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 121 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 122 123 status_ring_size = 1 << wil->tx_status_ring_order; 124 125 wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n", 126 status_ring_size, ring_id); 127 128 if (ring_id < 0) 129 return ring_id; 130 131 /* Allocate Tx status ring. Tx descriptor rings will be 132 * allocated on WMI connect event 133 */ 134 sring = &wil->srings[ring_id]; 135 136 sring->is_rx = false; 137 sring->size = status_ring_size; 138 sring->elem_size = sizeof(struct wil_ring_tx_status); 139 rc = wil_sring_alloc(wil, sring); 140 if (rc) 141 return rc; 142 143 rc = wil_wmi_tx_sring_cfg(wil, ring_id); 144 if (rc) 145 goto out_free; 146 147 sring->desc_rdy_pol = 1; 148 wil->tx_sring_idx = ring_id; 149 150 return 0; 151 out_free: 152 wil_sring_free(wil, sring); 153 return rc; 154 } 155 156 /** 157 * Allocate one skb for Rx descriptor RING 158 */ 159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil, 160 struct wil_ring *ring, u32 i) 161 { 162 struct device *dev = wil_to_dev(wil); 163 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 164 dma_addr_t pa; 165 u16 buff_id; 166 struct list_head *active = &wil->rx_buff_mgmt.active; 167 struct list_head *free = &wil->rx_buff_mgmt.free; 168 struct wil_rx_buff *rx_buff; 169 struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr; 170 struct sk_buff *skb; 171 struct wil_rx_enhanced_desc dd, *d = ⅆ 172 struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *) 173 &ring->va[i].rx.enhanced; 174 175 if (unlikely(list_empty(free))) { 176 wil->rx_buff_mgmt.free_list_empty_cnt++; 177 return -EAGAIN; 178 } 179 180 skb = dev_alloc_skb(sz); 181 if (unlikely(!skb)) 182 return -ENOMEM; 183 184 skb_put(skb, sz); 185 186 /** 187 * Make sure that the network stack calculates checksum for packets 188 * which failed the HW checksum calculation 189 */ 190 skb->ip_summed = CHECKSUM_NONE; 191 192 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 193 if (unlikely(dma_mapping_error(dev, pa))) { 194 kfree_skb(skb); 195 return -ENOMEM; 196 } 197 198 /* Get the buffer ID - the index of the rx buffer in the buff_arr */ 199 rx_buff = list_first_entry(free, struct wil_rx_buff, list); 200 buff_id = rx_buff->id; 201 202 /* Move a buffer from the free list to the active list */ 203 list_move(&rx_buff->list, active); 204 205 buff_arr[buff_id].skb = skb; 206 207 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 208 d->dma.length = cpu_to_le16(sz); 209 d->mac.buff_id = cpu_to_le16(buff_id); 210 *_d = *d; 211 212 /* Save the physical address in skb->cb for later use in dma_unmap */ 213 memcpy(skb->cb, &pa, sizeof(pa)); 214 215 return 0; 216 } 217 218 static inline 219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg) 220 { 221 memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)), 222 sring->elem_size); 223 } 224 225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring) 226 { 227 sring->swhead = (sring->swhead + 1) % sring->size; 228 if (sring->swhead == 0) 229 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol; 230 } 231 232 static int wil_rx_refill_edma(struct wil6210_priv *wil) 233 { 234 struct wil_ring *ring = &wil->ring_rx; 235 u32 next_head; 236 int rc = 0; 237 u32 swtail = *ring->edma_rx_swtail.va; 238 239 for (; next_head = wil_ring_next_head(ring), (next_head != swtail); 240 ring->swhead = next_head) { 241 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead); 242 if (unlikely(rc)) { 243 if (rc == -EAGAIN) 244 wil_dbg_txrx(wil, "No free buffer ID found\n"); 245 else 246 wil_err_ratelimited(wil, 247 "Error %d in refill desc[%d]\n", 248 rc, ring->swhead); 249 break; 250 } 251 } 252 253 /* make sure all writes to descriptors (shared memory) are done before 254 * committing them to HW 255 */ 256 wmb(); 257 258 wil_w(wil, ring->hwtail, ring->swhead); 259 260 return rc; 261 } 262 263 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil, 264 struct wil_ring *ring) 265 { 266 struct device *dev = wil_to_dev(wil); 267 u32 next_tail; 268 u32 swhead = (ring->swhead + 1) % ring->size; 269 dma_addr_t pa; 270 u16 dmalen; 271 272 for (; next_tail = wil_ring_next_tail(ring), (next_tail != swhead); 273 ring->swtail = next_tail) { 274 struct wil_rx_enhanced_desc dd, *d = ⅆ 275 struct wil_rx_enhanced_desc *_d = 276 (struct wil_rx_enhanced_desc *) 277 &ring->va[ring->swtail].rx.enhanced; 278 struct sk_buff *skb; 279 u16 buff_id; 280 281 *d = *_d; 282 283 /* Extract the SKB from the rx_buff management array */ 284 buff_id = __le16_to_cpu(d->mac.buff_id); 285 if (buff_id >= wil->rx_buff_mgmt.size) { 286 wil_err(wil, "invalid buff_id %d\n", buff_id); 287 continue; 288 } 289 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 290 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 291 if (unlikely(!skb)) { 292 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 293 } else { 294 pa = wil_rx_desc_get_addr_edma(&d->dma); 295 dmalen = le16_to_cpu(d->dma.length); 296 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE); 297 298 kfree_skb(skb); 299 } 300 301 /* Move the buffer from the active to the free list */ 302 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 303 &wil->rx_buff_mgmt.free); 304 } 305 } 306 307 static void wil_free_rx_buff_arr(struct wil6210_priv *wil) 308 { 309 struct wil_ring *ring = &wil->ring_rx; 310 311 if (!wil->rx_buff_mgmt.buff_arr) 312 return; 313 314 /* Move all the buffers to the free list in case active list is 315 * not empty in order to release all SKBs before deleting the array 316 */ 317 wil_move_all_rx_buff_to_free_list(wil, ring); 318 319 kfree(wil->rx_buff_mgmt.buff_arr); 320 wil->rx_buff_mgmt.buff_arr = NULL; 321 } 322 323 static int wil_init_rx_buff_arr(struct wil6210_priv *wil, 324 size_t size) 325 { 326 struct wil_rx_buff *buff_arr; 327 struct list_head *active = &wil->rx_buff_mgmt.active; 328 struct list_head *free = &wil->rx_buff_mgmt.free; 329 int i; 330 331 wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff), 332 GFP_KERNEL); 333 if (!wil->rx_buff_mgmt.buff_arr) 334 return -ENOMEM; 335 336 /* Set list heads */ 337 INIT_LIST_HEAD(active); 338 INIT_LIST_HEAD(free); 339 340 /* Linkify the list */ 341 buff_arr = wil->rx_buff_mgmt.buff_arr; 342 for (i = 0; i < size; i++) { 343 list_add(&buff_arr[i].list, free); 344 buff_arr[i].id = i; 345 } 346 347 wil->rx_buff_mgmt.size = size; 348 349 return 0; 350 } 351 352 static int wil_init_rx_sring(struct wil6210_priv *wil, 353 u16 status_ring_size, 354 size_t elem_size, 355 u16 ring_id) 356 { 357 struct wil_status_ring *sring = &wil->srings[ring_id]; 358 int rc; 359 360 wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", 361 status_ring_size, ring_id); 362 363 memset(&sring->rx_data, 0, sizeof(sring->rx_data)); 364 365 sring->is_rx = true; 366 sring->size = status_ring_size; 367 sring->elem_size = elem_size; 368 rc = wil_sring_alloc(wil, sring); 369 if (rc) 370 return rc; 371 372 rc = wil_wmi_rx_sring_add(wil, ring_id); 373 if (rc) 374 goto out_free; 375 376 sring->desc_rdy_pol = 1; 377 378 return 0; 379 out_free: 380 wil_sring_free(wil, sring); 381 return rc; 382 } 383 384 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil, 385 struct wil_ring *ring) 386 { 387 struct device *dev = wil_to_dev(wil); 388 size_t sz = ring->size * sizeof(ring->va[0]); 389 390 wil_dbg_misc(wil, "alloc_desc_ring:\n"); 391 392 BUILD_BUG_ON(sizeof(ring->va[0]) != 32); 393 394 ring->swhead = 0; 395 ring->swtail = 0; 396 ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL); 397 if (!ring->ctx) 398 goto err; 399 400 ring->va = dma_zalloc_coherent(dev, sz, &ring->pa, GFP_KERNEL); 401 if (!ring->va) 402 goto err_free_ctx; 403 404 if (ring->is_rx) { 405 sz = sizeof(*ring->edma_rx_swtail.va); 406 ring->edma_rx_swtail.va = 407 dma_zalloc_coherent(dev, sz, &ring->edma_rx_swtail.pa, 408 GFP_KERNEL); 409 if (!ring->edma_rx_swtail.va) 410 goto err_free_va; 411 } 412 413 wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n", 414 ring->is_rx ? "RX" : "TX", 415 ring->size, ring->va, &ring->pa, ring->ctx); 416 417 return 0; 418 err_free_va: 419 dma_free_coherent(dev, ring->size * sizeof(ring->va[0]), 420 (void *)ring->va, ring->pa); 421 ring->va = NULL; 422 err_free_ctx: 423 kfree(ring->ctx); 424 ring->ctx = NULL; 425 err: 426 return -ENOMEM; 427 } 428 429 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring) 430 { 431 struct device *dev = wil_to_dev(wil); 432 size_t sz; 433 int ring_index = 0; 434 435 if (!ring->va) 436 return; 437 438 sz = ring->size * sizeof(ring->va[0]); 439 440 lockdep_assert_held(&wil->mutex); 441 if (ring->is_rx) { 442 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n", 443 ring->size, ring->va, 444 &ring->pa, ring->ctx); 445 446 wil_move_all_rx_buff_to_free_list(wil, ring); 447 goto out; 448 } 449 450 /* TX ring */ 451 ring_index = ring - wil->ring_tx; 452 453 wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n", 454 ring_index, ring->size, ring->va, 455 &ring->pa, ring->ctx); 456 457 while (!wil_ring_is_empty(ring)) { 458 struct wil_ctx *ctx; 459 460 struct wil_tx_enhanced_desc dd, *d = ⅆ 461 struct wil_tx_enhanced_desc *_d = 462 (struct wil_tx_enhanced_desc *) 463 &ring->va[ring->swtail].tx.enhanced; 464 465 ctx = &ring->ctx[ring->swtail]; 466 if (!ctx) { 467 wil_dbg_txrx(wil, 468 "ctx(%d) was already completed\n", 469 ring->swtail); 470 ring->swtail = wil_ring_next_tail(ring); 471 continue; 472 } 473 *d = *_d; 474 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 475 if (ctx->skb) 476 dev_kfree_skb_any(ctx->skb); 477 ring->swtail = wil_ring_next_tail(ring); 478 } 479 480 out: 481 dma_free_coherent(dev, sz, (void *)ring->va, ring->pa); 482 kfree(ring->ctx); 483 ring->pa = 0; 484 ring->va = NULL; 485 ring->ctx = NULL; 486 } 487 488 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size, 489 int status_ring_id) 490 { 491 struct wil_ring *ring = &wil->ring_rx; 492 int rc; 493 494 wil_dbg_misc(wil, "init RX desc ring\n"); 495 496 ring->size = desc_ring_size; 497 ring->is_rx = true; 498 rc = wil_ring_alloc_desc_ring(wil, ring); 499 if (rc) 500 return rc; 501 502 rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id); 503 if (rc) 504 goto out_free; 505 506 return 0; 507 out_free: 508 wil_ring_free_edma(wil, ring); 509 return rc; 510 } 511 512 static void wil_get_reorder_params_edma(struct wil6210_priv *wil, 513 struct sk_buff *skb, int *tid, 514 int *cid, int *mid, u16 *seq, 515 int *mcast, int *retry) 516 { 517 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 518 519 *tid = wil_rx_status_get_tid(s); 520 *cid = wil_rx_status_get_cid(s); 521 *mid = wil_rx_status_get_mid(s); 522 *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s)); 523 *mcast = wil_rx_status_get_mcast(s); 524 *retry = wil_rx_status_get_retry(s); 525 } 526 527 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid, 528 int *security) 529 { 530 struct wil_rx_status_extended *s = wil_skb_rxstatus(skb); 531 532 *cid = wil_rx_status_get_cid(s); 533 *security = wil_rx_status_get_security(s); 534 } 535 536 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil, 537 struct sk_buff *skb) 538 { 539 struct wil_rx_status_extended *st; 540 int cid, tid, key_id, mc; 541 struct wil_sta_info *s; 542 struct wil_tid_crypto_rx *c; 543 struct wil_tid_crypto_rx_single *cc; 544 const u8 *pn; 545 546 /* In HW reorder, HW is responsible for crypto check */ 547 if (wil->use_rx_hw_reordering) 548 return 0; 549 550 st = wil_skb_rxstatus(skb); 551 552 cid = wil_rx_status_get_cid(st); 553 tid = wil_rx_status_get_tid(st); 554 key_id = wil_rx_status_get_key_id(st); 555 mc = wil_rx_status_get_mcast(st); 556 s = &wil->sta[cid]; 557 c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid]; 558 cc = &c->key_id[key_id]; 559 pn = (u8 *)&st->ext.pn_15_0; 560 561 if (!cc->key_set) { 562 wil_err_ratelimited(wil, 563 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 564 cid, tid, mc, key_id); 565 return -EINVAL; 566 } 567 568 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 569 wil_err_ratelimited(wil, 570 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 571 cid, tid, mc, key_id, pn, cc->pn); 572 return -EINVAL; 573 } 574 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 575 576 return 0; 577 } 578 579 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil) 580 { 581 struct wil_status_ring *sring; 582 struct wil_rx_status_extended msg1; 583 void *msg = &msg1; 584 u8 dr_bit; 585 int i; 586 587 for (i = 0; i < wil->num_rx_status_rings; i++) { 588 sring = &wil->srings[i]; 589 if (!sring->va) 590 continue; 591 592 wil_get_next_rx_status_msg(sring, msg); 593 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 594 595 /* Check if there are unhandled RX status messages */ 596 if (dr_bit == sring->desc_rdy_pol) 597 return false; 598 } 599 600 return true; 601 } 602 603 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil) 604 { 605 wil->rx_buf_len = rx_large_buf ? 606 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT; 607 } 608 609 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order) 610 { 611 u16 status_ring_size, desc_ring_size = 1 << desc_ring_order; 612 struct wil_ring *ring = &wil->ring_rx; 613 int rc; 614 size_t elem_size = wil->use_compressed_rx_status ? 615 sizeof(struct wil_rx_status_compressed) : 616 sizeof(struct wil_rx_status_extended); 617 int i; 618 u16 max_rx_pl_per_desc; 619 620 /* In SW reorder one must use extended status messages */ 621 if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) { 622 wil_err(wil, 623 "compressed RX status cannot be used with SW reorder\n"); 624 return -EINVAL; 625 } 626 if (wil->rx_status_ring_order <= desc_ring_order) 627 /* make sure sring is larger than desc ring */ 628 wil->rx_status_ring_order = desc_ring_order + 1; 629 if (wil->rx_buff_id_count <= desc_ring_size) 630 /* make sure we will not run out of buff_ids */ 631 wil->rx_buff_id_count = desc_ring_size + 512; 632 if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN || 633 wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX) 634 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 635 636 status_ring_size = 1 << wil->rx_status_ring_order; 637 638 wil_dbg_misc(wil, 639 "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n", 640 desc_ring_size, status_ring_size, elem_size); 641 642 wil_rx_buf_len_init_edma(wil); 643 644 max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4); 645 646 /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */ 647 if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1) 648 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1; 649 650 wil_dbg_misc(wil, "rx_init: allocate %d status rings\n", 651 wil->num_rx_status_rings); 652 653 rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc); 654 if (rc) 655 return rc; 656 657 /* Allocate status ring */ 658 for (i = 0; i < wil->num_rx_status_rings; i++) { 659 int sring_id = wil_find_free_sring(wil); 660 661 if (sring_id < 0) { 662 rc = -EFAULT; 663 goto err_free_status; 664 } 665 rc = wil_init_rx_sring(wil, status_ring_size, elem_size, 666 sring_id); 667 if (rc) 668 goto err_free_status; 669 } 670 671 /* Allocate descriptor ring */ 672 rc = wil_init_rx_desc_ring(wil, desc_ring_size, 673 WIL_DEFAULT_RX_STATUS_RING_ID); 674 if (rc) 675 goto err_free_status; 676 677 if (wil->rx_buff_id_count >= status_ring_size) { 678 wil_info(wil, 679 "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n", 680 wil->rx_buff_id_count, status_ring_size, 681 status_ring_size - 1); 682 wil->rx_buff_id_count = status_ring_size - 1; 683 } 684 685 /* Allocate Rx buffer array */ 686 rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count); 687 if (rc) 688 goto err_free_desc; 689 690 /* Fill descriptor ring with credits */ 691 rc = wil_rx_refill_edma(wil); 692 if (rc) 693 goto err_free_rx_buff_arr; 694 695 return 0; 696 err_free_rx_buff_arr: 697 wil_free_rx_buff_arr(wil); 698 err_free_desc: 699 wil_ring_free_edma(wil, ring); 700 err_free_status: 701 for (i = 0; i < wil->num_rx_status_rings; i++) 702 wil_sring_free(wil, &wil->srings[i]); 703 704 return rc; 705 } 706 707 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id, 708 int size, int cid, int tid) 709 { 710 struct wil6210_priv *wil = vif_to_wil(vif); 711 int rc; 712 struct wil_ring *ring = &wil->ring_tx[ring_id]; 713 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 714 715 lockdep_assert_held(&wil->mutex); 716 717 wil_dbg_misc(wil, 718 "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n", 719 ring_id, cid, tid, wil->tx_sring_idx); 720 721 wil_tx_data_init(txdata); 722 ring->size = size; 723 rc = wil_ring_alloc_desc_ring(wil, ring); 724 if (rc) 725 goto out; 726 727 wil->ring2cid_tid[ring_id][0] = cid; 728 wil->ring2cid_tid[ring_id][1] = tid; 729 if (!vif->privacy) 730 txdata->dot1x_open = true; 731 732 rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid); 733 if (rc) { 734 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n"); 735 goto out_free; 736 } 737 738 if (txdata->dot1x_open && agg_wsize >= 0) 739 wil_addba_tx_request(wil, ring_id, agg_wsize); 740 741 return 0; 742 out_free: 743 spin_lock_bh(&txdata->lock); 744 txdata->dot1x_open = false; 745 txdata->enabled = 0; 746 spin_unlock_bh(&txdata->lock); 747 wil_ring_free_edma(wil, ring); 748 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; 749 wil->ring2cid_tid[ring_id][1] = 0; 750 751 out: 752 return rc; 753 } 754 755 static int wil_tx_ring_modify_edma(struct wil6210_vif *vif, int ring_id, 756 int cid, int tid) 757 { 758 struct wil6210_priv *wil = vif_to_wil(vif); 759 760 wil_err(wil, "ring modify is not supported for EDMA\n"); 761 762 return -EOPNOTSUPP; 763 } 764 765 /* This function is used only for RX SW reorder */ 766 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid, 767 struct sk_buff *skb, struct wil_net_stats *stats) 768 { 769 u8 ftype; 770 u8 fc1; 771 int mid; 772 int tid; 773 u16 seq; 774 struct wil6210_vif *vif; 775 776 ftype = wil_rx_status_get_frame_type(wil, msg); 777 if (ftype == IEEE80211_FTYPE_DATA) 778 return 0; 779 780 fc1 = wil_rx_status_get_fc1(wil, msg); 781 mid = wil_rx_status_get_mid(msg); 782 tid = wil_rx_status_get_tid(msg); 783 seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg)); 784 vif = wil->vifs[mid]; 785 786 if (unlikely(!vif)) { 787 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid); 788 return -EAGAIN; 789 } 790 791 wil_dbg_txrx(wil, 792 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 793 fc1, mid, cid, tid, seq); 794 if (stats) 795 stats->rx_non_data_frame++; 796 if (wil_is_back_req(fc1)) { 797 wil_dbg_txrx(wil, 798 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 799 mid, cid, tid, seq); 800 wil_rx_bar(wil, vif, cid, tid, seq); 801 } else { 802 u32 sz = wil->use_compressed_rx_status ? 803 sizeof(struct wil_rx_status_compressed) : 804 sizeof(struct wil_rx_status_extended); 805 806 /* print again all info. One can enable only this 807 * without overhead for printing every Rx frame 808 */ 809 wil_dbg_txrx(wil, 810 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 811 fc1, mid, cid, tid, seq); 812 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 813 (const void *)msg, sz, false); 814 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 815 skb->data, skb_headlen(skb), false); 816 } 817 818 return -EAGAIN; 819 } 820 821 static int wil_rx_error_check_edma(struct wil6210_priv *wil, 822 struct sk_buff *skb, 823 struct wil_net_stats *stats) 824 { 825 int error; 826 int l2_rx_status; 827 int l3_rx_status; 828 int l4_rx_status; 829 void *msg = wil_skb_rxstatus(skb); 830 831 error = wil_rx_status_get_error(msg); 832 if (!error) { 833 skb->ip_summed = CHECKSUM_UNNECESSARY; 834 return 0; 835 } 836 837 l2_rx_status = wil_rx_status_get_l2_rx_status(msg); 838 if (l2_rx_status != 0) { 839 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n", 840 l2_rx_status); 841 /* Due to HW issue, KEY error will trigger a MIC error */ 842 if (l2_rx_status & WIL_RX_EDMA_ERROR_MIC) { 843 wil_dbg_txrx(wil, 844 "L2 MIC/KEY error, dropping packet\n"); 845 stats->rx_mic_error++; 846 } 847 if (l2_rx_status & WIL_RX_EDMA_ERROR_KEY) { 848 wil_dbg_txrx(wil, "L2 KEY error, dropping packet\n"); 849 stats->rx_key_error++; 850 } 851 if (l2_rx_status & WIL_RX_EDMA_ERROR_REPLAY) { 852 wil_dbg_txrx(wil, 853 "L2 REPLAY error, dropping packet\n"); 854 stats->rx_replay++; 855 } 856 if (l2_rx_status & WIL_RX_EDMA_ERROR_AMSDU) { 857 wil_dbg_txrx(wil, 858 "L2 AMSDU error, dropping packet\n"); 859 stats->rx_amsdu_error++; 860 } 861 return -EFAULT; 862 } 863 864 l3_rx_status = wil_rx_status_get_l3_rx_status(msg); 865 l4_rx_status = wil_rx_status_get_l4_rx_status(msg); 866 if (!l3_rx_status && !l4_rx_status) 867 skb->ip_summed = CHECKSUM_UNNECESSARY; 868 /* If HW reports bad checksum, let IP stack re-check it 869 * For example, HW don't understand Microsoft IP stack that 870 * mis-calculates TCP checksum - if it should be 0x0, 871 * it writes 0xffff in violation of RFC 1624 872 */ 873 else 874 stats->rx_csum_err++; 875 876 return 0; 877 } 878 879 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil, 880 struct wil_status_ring *sring) 881 { 882 struct device *dev = wil_to_dev(wil); 883 struct wil_rx_status_extended msg1; 884 void *msg = &msg1; 885 u16 buff_id; 886 struct sk_buff *skb; 887 dma_addr_t pa; 888 struct wil_ring_rx_data *rxdata = &sring->rx_data; 889 unsigned int sz = ALIGN(wil->rx_buf_len, 4); 890 struct wil_net_stats *stats = NULL; 891 u16 dmalen; 892 int cid; 893 bool eop, headstolen; 894 int delta; 895 u8 dr_bit; 896 u8 data_offset; 897 struct wil_rx_status_extended *s; 898 u16 sring_idx = sring - wil->srings; 899 900 BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb)); 901 902 again: 903 wil_get_next_rx_status_msg(sring, msg); 904 dr_bit = wil_rx_status_get_desc_rdy_bit(msg); 905 906 /* Completed handling all the ready status messages */ 907 if (dr_bit != sring->desc_rdy_pol) 908 return NULL; 909 910 /* Extract the buffer ID from the status message */ 911 buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg)); 912 if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) { 913 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n", 914 buff_id, sring->swhead); 915 wil_sring_advance_swhead(sring); 916 goto again; 917 } 918 919 wil_sring_advance_swhead(sring); 920 921 /* Extract the SKB from the rx_buff management array */ 922 skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb; 923 wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL; 924 if (!skb) { 925 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id); 926 /* Move the buffer from the active list to the free list */ 927 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 928 &wil->rx_buff_mgmt.free); 929 goto again; 930 } 931 932 memcpy(&pa, skb->cb, sizeof(pa)); 933 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 934 dmalen = le16_to_cpu(wil_rx_status_get_length(msg)); 935 936 trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id, 937 msg); 938 wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n", 939 buff_id, sring_idx, dmalen); 940 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4, 941 (const void *)msg, wil->use_compressed_rx_status ? 942 sizeof(struct wil_rx_status_compressed) : 943 sizeof(struct wil_rx_status_extended), false); 944 945 /* Move the buffer from the active list to the free list */ 946 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list, 947 &wil->rx_buff_mgmt.free); 948 949 eop = wil_rx_status_get_eop(msg); 950 951 cid = wil_rx_status_get_cid(msg); 952 if (unlikely(!wil_val_in_range(cid, 0, WIL6210_MAX_CID))) { 953 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n", 954 cid, sring->swhead); 955 rxdata->skipping = true; 956 goto skipping; 957 } 958 stats = &wil->sta[cid].stats; 959 960 if (unlikely(skb->len < ETH_HLEN)) { 961 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len); 962 stats->rx_short_frame++; 963 rxdata->skipping = true; 964 goto skipping; 965 } 966 967 if (unlikely(dmalen > sz)) { 968 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 969 stats->rx_large_frame++; 970 rxdata->skipping = true; 971 } 972 973 skipping: 974 /* skipping indicates if a certain SKB should be dropped. 975 * It is set in case there is an error on the current SKB or in case 976 * of RX chaining: as long as we manage to merge the SKBs it will 977 * be false. once we have a bad SKB or we don't manage to merge SKBs 978 * it will be set to the !EOP value of the current SKB. 979 * This guarantees that all the following SKBs until EOP will also 980 * get dropped. 981 */ 982 if (unlikely(rxdata->skipping)) { 983 kfree_skb(skb); 984 if (rxdata->skb) { 985 kfree_skb(rxdata->skb); 986 rxdata->skb = NULL; 987 } 988 rxdata->skipping = !eop; 989 goto again; 990 } 991 992 skb_trim(skb, dmalen); 993 994 prefetch(skb->data); 995 996 if (!rxdata->skb) { 997 rxdata->skb = skb; 998 } else { 999 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen, 1000 &delta))) { 1001 kfree_skb_partial(skb, headstolen); 1002 } else { 1003 wil_err(wil, "failed to merge skbs!\n"); 1004 kfree_skb(skb); 1005 kfree_skb(rxdata->skb); 1006 rxdata->skb = NULL; 1007 rxdata->skipping = !eop; 1008 goto again; 1009 } 1010 } 1011 1012 if (!eop) 1013 goto again; 1014 1015 /* reaching here rxdata->skb always contains a full packet */ 1016 skb = rxdata->skb; 1017 rxdata->skb = NULL; 1018 rxdata->skipping = false; 1019 1020 if (stats) { 1021 stats->last_mcs_rx = wil_rx_status_get_mcs(msg); 1022 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 1023 stats->rx_per_mcs[stats->last_mcs_rx]++; 1024 } 1025 1026 if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status && 1027 wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) { 1028 kfree_skb(skb); 1029 goto again; 1030 } 1031 1032 /* Compensate for the HW data alignment according to the status 1033 * message 1034 */ 1035 data_offset = wil_rx_status_get_data_offset(msg); 1036 if (data_offset == 0xFF || 1037 data_offset > WIL_EDMA_MAX_DATA_OFFSET) { 1038 wil_err(wil, "Unexpected data offset %d\n", data_offset); 1039 kfree_skb(skb); 1040 goto again; 1041 } 1042 1043 skb_pull(skb, data_offset); 1044 1045 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 1046 skb->data, skb_headlen(skb), false); 1047 1048 /* Has to be done after dma_unmap_single as skb->cb is also 1049 * used for holding the pa 1050 */ 1051 s = wil_skb_rxstatus(skb); 1052 memcpy(s, msg, sring->elem_size); 1053 1054 return skb; 1055 } 1056 1057 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota) 1058 { 1059 struct net_device *ndev; 1060 struct wil_ring *ring = &wil->ring_rx; 1061 struct wil_status_ring *sring; 1062 struct sk_buff *skb; 1063 int i; 1064 1065 if (unlikely(!ring->va)) { 1066 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 1067 return; 1068 } 1069 wil_dbg_txrx(wil, "rx_handle\n"); 1070 1071 for (i = 0; i < wil->num_rx_status_rings; i++) { 1072 sring = &wil->srings[i]; 1073 if (unlikely(!sring->va)) { 1074 wil_err(wil, 1075 "Rx IRQ while Rx status ring %d not yet initialized\n", 1076 i); 1077 continue; 1078 } 1079 1080 while ((*quota > 0) && 1081 (NULL != (skb = 1082 wil_sring_reap_rx_edma(wil, sring)))) { 1083 (*quota)--; 1084 if (wil->use_rx_hw_reordering) { 1085 void *msg = wil_skb_rxstatus(skb); 1086 int mid = wil_rx_status_get_mid(msg); 1087 struct wil6210_vif *vif = wil->vifs[mid]; 1088 1089 if (unlikely(!vif)) { 1090 wil_dbg_txrx(wil, 1091 "RX desc invalid mid %d", 1092 mid); 1093 kfree_skb(skb); 1094 continue; 1095 } 1096 ndev = vif_to_ndev(vif); 1097 wil_netif_rx_any(skb, ndev); 1098 } else { 1099 wil_rx_reorder(wil, skb); 1100 } 1101 } 1102 1103 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1104 } 1105 1106 wil_rx_refill_edma(wil); 1107 } 1108 1109 static int wil_tx_desc_map_edma(union wil_tx_desc *desc, 1110 dma_addr_t pa, 1111 u32 len, 1112 int ring_index) 1113 { 1114 struct wil_tx_enhanced_desc *d = 1115 (struct wil_tx_enhanced_desc *)&desc->enhanced; 1116 1117 memset(d, 0, sizeof(struct wil_tx_enhanced_desc)); 1118 1119 wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa); 1120 1121 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 1122 d->dma.length = cpu_to_le16((u16)len); 1123 d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS); 1124 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi; 1125 * 3 - eth mode 1126 */ 1127 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 1128 (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 1129 1130 return 0; 1131 } 1132 1133 static inline void 1134 wil_get_next_tx_status_msg(struct wil_status_ring *sring, 1135 struct wil_ring_tx_status *msg) 1136 { 1137 struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *) 1138 (sring->va + (sring->elem_size * sring->swhead)); 1139 1140 *msg = *_msg; 1141 } 1142 1143 /** 1144 * Clean up transmitted skb's from the Tx descriptor RING. 1145 * Return number of descriptors cleared. 1146 */ 1147 int wil_tx_sring_handler(struct wil6210_priv *wil, 1148 struct wil_status_ring *sring) 1149 { 1150 struct net_device *ndev; 1151 struct device *dev = wil_to_dev(wil); 1152 struct wil_ring *ring = NULL; 1153 struct wil_ring_tx_data *txdata; 1154 /* Total number of completed descriptors in all descriptor rings */ 1155 int desc_cnt = 0; 1156 int cid; 1157 struct wil_net_stats *stats = NULL; 1158 struct wil_tx_enhanced_desc *_d; 1159 unsigned int ring_id; 1160 unsigned int num_descs; 1161 int i; 1162 u8 dr_bit; /* Descriptor Ready bit */ 1163 struct wil_ring_tx_status msg; 1164 struct wil6210_vif *vif; 1165 int used_before_complete; 1166 int used_new; 1167 1168 wil_get_next_tx_status_msg(sring, &msg); 1169 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1170 1171 /* Process completion messages while DR bit has the expected polarity */ 1172 while (dr_bit == sring->desc_rdy_pol) { 1173 num_descs = msg.num_descriptors; 1174 if (!num_descs) { 1175 wil_err(wil, "invalid num_descs 0\n"); 1176 goto again; 1177 } 1178 1179 /* Find the corresponding descriptor ring */ 1180 ring_id = msg.ring_id; 1181 1182 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) { 1183 wil_err(wil, "invalid ring id %d\n", ring_id); 1184 goto again; 1185 } 1186 ring = &wil->ring_tx[ring_id]; 1187 if (unlikely(!ring->va)) { 1188 wil_err(wil, "Tx irq[%d]: ring not initialized\n", 1189 ring_id); 1190 goto again; 1191 } 1192 txdata = &wil->ring_tx_data[ring_id]; 1193 if (unlikely(!txdata->enabled)) { 1194 wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id); 1195 goto again; 1196 } 1197 vif = wil->vifs[txdata->mid]; 1198 if (unlikely(!vif)) { 1199 wil_dbg_txrx(wil, "invalid MID %d for ring %d\n", 1200 txdata->mid, ring_id); 1201 goto again; 1202 } 1203 1204 ndev = vif_to_ndev(vif); 1205 1206 cid = wil->ring2cid_tid[ring_id][0]; 1207 if (cid < WIL6210_MAX_CID) 1208 stats = &wil->sta[cid].stats; 1209 1210 wil_dbg_txrx(wil, 1211 "tx_status: completed desc_ring (%d), num_descs (%d)\n", 1212 ring_id, num_descs); 1213 1214 used_before_complete = wil_ring_used_tx(ring); 1215 1216 for (i = 0 ; i < num_descs; ++i) { 1217 struct wil_ctx *ctx = &ring->ctx[ring->swtail]; 1218 struct wil_tx_enhanced_desc dd, *d = ⅆ 1219 u16 dmalen; 1220 struct sk_buff *skb = ctx->skb; 1221 1222 _d = (struct wil_tx_enhanced_desc *) 1223 &ring->va[ring->swtail].tx.enhanced; 1224 *d = *_d; 1225 1226 dmalen = le16_to_cpu(d->dma.length); 1227 trace_wil6210_tx_status(&msg, ring->swtail, dmalen); 1228 wil_dbg_txrx(wil, 1229 "TxC[%2d][%3d] : %d bytes, status 0x%02x\n", 1230 ring_id, ring->swtail, dmalen, 1231 msg.status); 1232 wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4, 1233 (const void *)&msg, sizeof(msg), 1234 false); 1235 1236 wil_tx_desc_unmap_edma(dev, 1237 (union wil_tx_desc *)d, 1238 ctx); 1239 1240 if (skb) { 1241 if (likely(msg.status == 0)) { 1242 ndev->stats.tx_packets++; 1243 ndev->stats.tx_bytes += skb->len; 1244 if (stats) { 1245 stats->tx_packets++; 1246 stats->tx_bytes += skb->len; 1247 1248 wil_tx_latency_calc(wil, skb, 1249 &wil->sta[cid]); 1250 } 1251 } else { 1252 ndev->stats.tx_errors++; 1253 if (stats) 1254 stats->tx_errors++; 1255 } 1256 wil_consume_skb(skb, msg.status == 0); 1257 } 1258 memset(ctx, 0, sizeof(*ctx)); 1259 /* Make sure the ctx is zeroed before updating the tail 1260 * to prevent a case where wil_tx_ring will see 1261 * this descriptor as used and handle it before ctx zero 1262 * is completed. 1263 */ 1264 wmb(); 1265 1266 ring->swtail = wil_ring_next_tail(ring); 1267 1268 desc_cnt++; 1269 } 1270 1271 /* performance monitoring */ 1272 used_new = wil_ring_used_tx(ring); 1273 if (wil_val_in_range(wil->ring_idle_trsh, 1274 used_new, used_before_complete)) { 1275 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 1276 ring_id, used_before_complete, used_new); 1277 txdata->last_idle = get_cycles(); 1278 } 1279 1280 again: 1281 wil_sring_advance_swhead(sring); 1282 1283 wil_get_next_tx_status_msg(sring, &msg); 1284 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS; 1285 } 1286 1287 /* shall we wake net queues? */ 1288 if (desc_cnt) 1289 wil_update_net_queues(wil, vif, NULL, false); 1290 1291 /* Update the HW tail ptr (RD ptr) */ 1292 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size); 1293 1294 return desc_cnt; 1295 } 1296 1297 /** 1298 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1299 * @skb is used to obtain the protocol and headers length. 1300 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1301 * 2 - middle, 3 - last descriptor. 1302 */ 1303 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d, 1304 int tso_desc_type, bool is_ipv4, 1305 int tcp_hdr_len, 1306 int skb_net_hdr_len, 1307 int mss) 1308 { 1309 /* Number of descriptors */ 1310 d->mac.d[2] |= 1; 1311 /* Maximum Segment Size */ 1312 d->mac.tso_mss |= cpu_to_le16(mss >> 2); 1313 /* L4 header len: TCP header length */ 1314 d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK; 1315 /* EOP, TSO desc type, Segmentation enable, 1316 * Insert IPv4 and TCP / UDP Checksum 1317 */ 1318 d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) | 1319 tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS | 1320 BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) | 1321 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) | 1322 BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS); 1323 /* Calculate pseudo-header */ 1324 d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) | 1325 BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS); 1326 /* IP Header Length */ 1327 d->dma.ip_length |= skb_net_hdr_len; 1328 /* MAC header length and IP address family*/ 1329 d->dma.b11 |= ETH_HLEN | 1330 is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1331 } 1332 1333 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr, 1334 int len, uint i, int tso_desc_type, 1335 skb_frag_t *frag, struct wil_ring *ring, 1336 struct sk_buff *skb, bool is_ipv4, 1337 int tcp_hdr_len, int skb_net_hdr_len, 1338 int mss, int *descs_used) 1339 { 1340 struct device *dev = wil_to_dev(wil); 1341 struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *) 1342 &ring->va[i].tx.enhanced; 1343 struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem; 1344 int ring_index = ring - wil->ring_tx; 1345 dma_addr_t pa; 1346 1347 if (len == 0) 1348 return 0; 1349 1350 if (!frag) { 1351 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE); 1352 ring->ctx[i].mapped_as = wil_mapped_as_single; 1353 } else { 1354 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE); 1355 ring->ctx[i].mapped_as = wil_mapped_as_page; 1356 } 1357 if (unlikely(dma_mapping_error(dev, pa))) { 1358 wil_err(wil, "TSO: Skb DMA map error\n"); 1359 return -EINVAL; 1360 } 1361 1362 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, 1363 len, ring_index); 1364 wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4, 1365 tcp_hdr_len, 1366 skb_net_hdr_len, mss); 1367 1368 /* hold reference to skb 1369 * to prevent skb release before accounting 1370 * in case of immediate "tx done" 1371 */ 1372 if (tso_desc_type == wil_tso_type_lst) 1373 ring->ctx[i].skb = skb_get(skb); 1374 1375 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1376 (const void *)d, sizeof(*d), false); 1377 1378 *_desc = *d; 1379 (*descs_used)++; 1380 1381 return 0; 1382 } 1383 1384 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil, 1385 struct wil6210_vif *vif, 1386 struct wil_ring *ring, 1387 struct sk_buff *skb) 1388 { 1389 int ring_index = ring - wil->ring_tx; 1390 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1391 int nr_frags = skb_shinfo(skb)->nr_frags; 1392 int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */ 1393 int used, avail = wil_ring_avail_tx(ring); 1394 int f, hdrlen, headlen; 1395 int gso_type; 1396 bool is_ipv4; 1397 u32 swhead = ring->swhead; 1398 int descs_used = 0; /* total number of used descriptors */ 1399 int rc = -EINVAL; 1400 int tcp_hdr_len; 1401 int skb_net_hdr_len; 1402 int mss = skb_shinfo(skb)->gso_size; 1403 1404 wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len, 1405 ring_index); 1406 1407 if (unlikely(!txdata->enabled)) 1408 return -EINVAL; 1409 1410 if (unlikely(avail < min_desc_required)) { 1411 wil_err_ratelimited(wil, 1412 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1413 ring_index, min_desc_required); 1414 return -ENOMEM; 1415 } 1416 1417 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1418 switch (gso_type) { 1419 case SKB_GSO_TCPV4: 1420 is_ipv4 = true; 1421 break; 1422 case SKB_GSO_TCPV6: 1423 is_ipv4 = false; 1424 break; 1425 default: 1426 return -EINVAL; 1427 } 1428 1429 if (skb->ip_summed != CHECKSUM_PARTIAL) 1430 return -EINVAL; 1431 1432 /* tcp header length and skb network header length are fixed for all 1433 * packet's descriptors - read them once here 1434 */ 1435 tcp_hdr_len = tcp_hdrlen(skb); 1436 skb_net_hdr_len = skb_network_header_len(skb); 1437 1438 /* First descriptor must contain the header only 1439 * Header Length = MAC header len + IP header len + TCP header len 1440 */ 1441 hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len; 1442 wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n", 1443 hdrlen); 1444 rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead, 1445 wil_tso_type_hdr, NULL, ring, skb, 1446 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1447 mss, &descs_used); 1448 if (rc) 1449 return -EINVAL; 1450 1451 /* Second descriptor contains the head */ 1452 headlen = skb_headlen(skb) - hdrlen; 1453 wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen); 1454 rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen, 1455 (swhead + descs_used) % ring->size, 1456 (nr_frags != 0) ? wil_tso_type_first : 1457 wil_tso_type_lst, NULL, ring, skb, 1458 is_ipv4, tcp_hdr_len, skb_net_hdr_len, 1459 mss, &descs_used); 1460 if (rc) 1461 goto mem_error; 1462 1463 /* Rest of the descriptors are from the SKB fragments */ 1464 for (f = 0; f < nr_frags; f++) { 1465 skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; 1466 int len = frag->size; 1467 1468 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f, 1469 len, descs_used); 1470 1471 rc = wil_tx_tso_gen_desc(wil, NULL, len, 1472 (swhead + descs_used) % ring->size, 1473 (f != nr_frags - 1) ? 1474 wil_tso_type_mid : wil_tso_type_lst, 1475 frag, ring, skb, is_ipv4, 1476 tcp_hdr_len, skb_net_hdr_len, 1477 mss, &descs_used); 1478 if (rc) 1479 goto mem_error; 1480 } 1481 1482 /* performance monitoring */ 1483 used = wil_ring_used_tx(ring); 1484 if (wil_val_in_range(wil->ring_idle_trsh, 1485 used, used + descs_used)) { 1486 txdata->idle += get_cycles() - txdata->last_idle; 1487 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1488 ring_index, used, used + descs_used); 1489 } 1490 1491 /* advance swhead */ 1492 wil_ring_advance_head(ring, descs_used); 1493 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead); 1494 1495 /* make sure all writes to descriptors (shared memory) are done before 1496 * committing them to HW 1497 */ 1498 wmb(); 1499 1500 if (wil->tx_latency) 1501 *(ktime_t *)&skb->cb = ktime_get(); 1502 else 1503 memset(skb->cb, 0, sizeof(ktime_t)); 1504 1505 wil_w(wil, ring->hwtail, ring->swhead); 1506 1507 return 0; 1508 1509 mem_error: 1510 while (descs_used > 0) { 1511 struct device *dev = wil_to_dev(wil); 1512 struct wil_ctx *ctx; 1513 int i = (swhead + descs_used - 1) % ring->size; 1514 struct wil_tx_enhanced_desc dd, *d = ⅆ 1515 struct wil_tx_enhanced_desc *_desc = 1516 (struct wil_tx_enhanced_desc *) 1517 &ring->va[i].tx.enhanced; 1518 1519 *d = *_desc; 1520 ctx = &ring->ctx[i]; 1521 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx); 1522 memset(ctx, 0, sizeof(*ctx)); 1523 descs_used--; 1524 } 1525 return rc; 1526 } 1527 1528 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id, 1529 int size) 1530 { 1531 struct wil6210_priv *wil = vif_to_wil(vif); 1532 struct wil_ring *ring = &wil->ring_tx[ring_id]; 1533 int rc; 1534 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1535 1536 wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n", 1537 ring_id, wil->tx_sring_idx); 1538 1539 lockdep_assert_held(&wil->mutex); 1540 1541 wil_tx_data_init(txdata); 1542 ring->size = size; 1543 ring->is_rx = false; 1544 rc = wil_ring_alloc_desc_ring(wil, ring); 1545 if (rc) 1546 goto out; 1547 1548 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */ 1549 wil->ring2cid_tid[ring_id][1] = 0; /* TID */ 1550 if (!vif->privacy) 1551 txdata->dot1x_open = true; 1552 1553 rc = wil_wmi_bcast_desc_ring_add(vif, ring_id); 1554 if (rc) 1555 goto out_free; 1556 1557 return 0; 1558 1559 out_free: 1560 spin_lock_bh(&txdata->lock); 1561 txdata->enabled = 0; 1562 txdata->dot1x_open = false; 1563 spin_unlock_bh(&txdata->lock); 1564 wil_ring_free_edma(wil, ring); 1565 1566 out: 1567 return rc; 1568 } 1569 1570 static void wil_tx_fini_edma(struct wil6210_priv *wil) 1571 { 1572 struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx]; 1573 1574 wil_dbg_misc(wil, "free TX sring\n"); 1575 1576 wil_sring_free(wil, sring); 1577 } 1578 1579 static void wil_rx_data_free(struct wil_status_ring *sring) 1580 { 1581 if (!sring) 1582 return; 1583 1584 kfree_skb(sring->rx_data.skb); 1585 sring->rx_data.skb = NULL; 1586 } 1587 1588 static void wil_rx_fini_edma(struct wil6210_priv *wil) 1589 { 1590 struct wil_ring *ring = &wil->ring_rx; 1591 int i; 1592 1593 wil_dbg_misc(wil, "rx_fini_edma\n"); 1594 1595 wil_ring_free_edma(wil, ring); 1596 1597 for (i = 0; i < wil->num_rx_status_rings; i++) { 1598 wil_rx_data_free(&wil->srings[i]); 1599 wil_sring_free(wil, &wil->srings[i]); 1600 } 1601 1602 wil_free_rx_buff_arr(wil); 1603 } 1604 1605 void wil_init_txrx_ops_edma(struct wil6210_priv *wil) 1606 { 1607 wil->txrx_ops.configure_interrupt_moderation = 1608 wil_configure_interrupt_moderation_edma; 1609 /* TX ops */ 1610 wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma; 1611 wil->txrx_ops.ring_fini_tx = wil_ring_free_edma; 1612 wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma; 1613 wil->txrx_ops.tx_init = wil_tx_init_edma; 1614 wil->txrx_ops.tx_fini = wil_tx_fini_edma; 1615 wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma; 1616 wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma; 1617 wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma; 1618 wil->txrx_ops.tx_ring_modify = wil_tx_ring_modify_edma; 1619 /* RX ops */ 1620 wil->txrx_ops.rx_init = wil_rx_init_edma; 1621 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma; 1622 wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma; 1623 wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma; 1624 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma; 1625 wil->txrx_ops.rx_error_check = wil_rx_error_check_edma; 1626 wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma; 1627 wil->txrx_ops.rx_fini = wil_rx_fini_edma; 1628 } 1629 1630