1 /*
2  * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 
18 #ifndef WIL6210_TXRX_H
19 #define WIL6210_TXRX_H
20 
21 #include "wil6210.h"
22 #include "txrx_edma.h"
23 
24 #define BUF_SW_OWNED    (1)
25 #define BUF_HW_OWNED    (0)
26 
27 /* default size of MAC Tx/Rx buffers */
28 #define TXRX_BUF_LEN_DEFAULT (2048)
29 
30 /* how many bytes to reserve for rtap header? */
31 #define WIL6210_RTAP_SIZE (128)
32 
33 /* Tx/Rx path */
34 
35 static inline dma_addr_t wil_desc_addr(struct wil_ring_dma_addr *addr)
36 {
37 	return le32_to_cpu(addr->addr_low) |
38 			   ((u64)le16_to_cpu(addr->addr_high) << 32);
39 }
40 
41 static inline void wil_desc_addr_set(struct wil_ring_dma_addr *addr,
42 				     dma_addr_t pa)
43 {
44 	addr->addr_low = cpu_to_le32(lower_32_bits(pa));
45 	addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
46 }
47 
48 /* Tx descriptor - MAC part
49  * [dword 0]
50  * bit  0.. 9 : lifetime_expiry_value:10
51  * bit     10 : interrupt_en:1
52  * bit     11 : status_en:1
53  * bit 12..13 : txss_override:2
54  * bit     14 : timestamp_insertion:1
55  * bit     15 : duration_preserve:1
56  * bit 16..21 : reserved0:6
57  * bit 22..26 : mcs_index:5
58  * bit     27 : mcs_en:1
59  * bit 28..30 : reserved1:3
60  * bit     31 : sn_preserved:1
61  * [dword 1]
62  * bit  0.. 3 : pkt_mode:4
63  * bit      4 : pkt_mode_en:1
64  * bit      5 : mac_id_en:1
65  * bit   6..7 : mac_id:2
66  * bit  8..14 : reserved0:7
67  * bit     15 : ack_policy_en:1
68  * bit 16..19 : dst_index:4
69  * bit     20 : dst_index_en:1
70  * bit 21..22 : ack_policy:2
71  * bit     23 : lifetime_en:1
72  * bit 24..30 : max_retry:7
73  * bit     31 : max_retry_en:1
74  * [dword 2]
75  * bit  0.. 7 : num_of_descriptors:8
76  * bit  8..17 : reserved:10
77  * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
78  * bit     20 : snap_hdr_insertion_en:1
79  * bit     21 : vlan_removal_en:1
80  * bit 22..31 : reserved0:10
81  * [dword 3]
82  * bit  0.. 31: ucode_cmd:32
83  */
84 struct vring_tx_mac {
85 	u32 d[3];
86 	u32 ucode_cmd;
87 } __packed;
88 
89 /* TX MAC Dword 0 */
90 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
91 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
92 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
93 
94 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
95 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
96 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
97 
98 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
99 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
100 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
101 
102 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
103 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
104 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
105 
106 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
107 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
108 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
109 
110 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
111 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
112 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
113 
114 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
115 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
116 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
117 
118 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
119 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
120 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
121 
122 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
123 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
124 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
125 
126 /* TX MAC Dword 1 */
127 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
128 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
129 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
130 
131 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
132 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
133 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
134 
135 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_POS 5
136 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_LEN 1
137 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_MSK 0x20
138 
139 #define MAC_CFG_DESC_TX_1_MAC_ID_POS 6
140 #define MAC_CFG_DESC_TX_1_MAC_ID_LEN 2
141 #define MAC_CFG_DESC_TX_1_MAC_ID_MSK 0xc0
142 
143 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
144 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
145 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
146 
147 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
148 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
149 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
150 
151 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
152 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
153 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
154 
155 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
156 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
157 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
158 
159 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
160 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
161 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
162 
163 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
164 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
165 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
166 
167 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
168 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
169 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
170 
171 /* TX MAC Dword 2 */
172 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
173 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
174 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
175 
176 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8
177 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
178 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
179 
180 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
181 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
182 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
183 
184 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
185 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
186 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
187 
188 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
189 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
190 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
191 
192 /* TX MAC Dword 3 */
193 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
194 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
195 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
196 
197 /* TX DMA Dword 0 */
198 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
199 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
200 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
201 
202 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
203 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
204 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
205 
206 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9
207 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
208 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200
209 
210 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
211 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
212 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
213 
214 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
215 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
216 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
217 
218 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
219 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
220 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
221 
222 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
223 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
224 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
225 
226 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
227 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
228 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
229 
230 #define DMA_CFG_DESC_TX_0_QID_POS 16
231 #define DMA_CFG_DESC_TX_0_QID_LEN 5
232 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
233 
234 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
235 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
236 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
237 
238 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
239 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
240 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */
241 
242 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0
243 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7
244 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */
245 
246 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7
247 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
248 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */
249 
250 #define TX_DMA_STATUS_DU         BIT(0)
251 
252 /* Tx descriptor - DMA part
253  * [dword 0]
254  * bit  0.. 7 : l4_length:8 layer 4 length
255  * bit      8 : cmd_eop:1 This descriptor is the last one in the packet
256  * bit      9 : reserved
257  * bit     10 : cmd_dma_it:1 immediate interrupt
258  * bit 11..12 : SBD - Segment Buffer Details
259  *		00 - Header Segment
260  *		01 - First Data Segment
261  *		10 - Medium Data Segment
262  *		11 - Last Data Segment
263  * bit     13 : TSE - TCP Segmentation Enable
264  * bit     14 : IIC - Directs the HW to Insert IPv4 Checksum
265  * bit     15 : ITC - Directs the HW to Insert TCP/UDP Checksum
266  * bit 16..20 : QID - The target QID that the packet should be stored
267  *		in the MAC.
268  * bit     21 : PO - Pseudo header Offload:
269  *		0 - Use the pseudo header value from the TCP checksum field
270  *		1- Calculate Pseudo header Checksum
271  * bit     22 : NC - No UDP Checksum
272  * bit 23..29 : reserved
273  * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved
274  *		If L4Len equal 0, no L4 at all
275  * [dword 1]
276  * bit  0..31 : addr_low:32 The payload buffer low address
277  * [dword 2]
278  * bit  0..15 : addr_high:16 The payload buffer high address
279  * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
280  *		offload feature
281  * bit 24..30 : mac_length:7
282  * bit     31 : ip_version:1 1 - IPv4, 0 - IPv6
283  * [dword 3]
284  *  [byte 12] error
285  * bit  0   2 : mac_status:3
286  * bit  3   7 : reserved:5
287  *  [byte 13] status
288  * bit      0 : DU:1 Descriptor Used
289  * bit  1   7 : reserved:7
290  *  [word 7] length
291  */
292 struct vring_tx_dma {
293 	u32 d0;
294 	struct wil_ring_dma_addr addr;
295 	u8  ip_length;
296 	u8  b11;       /* 0..6: mac_length; 7:ip_version */
297 	u8  error;     /* 0..2: err; 3..7: reserved; */
298 	u8  status;    /* 0: used; 1..7; reserved */
299 	__le16 length;
300 } __packed;
301 
302 /* TSO type used in dma descriptor d0 bits 11-12 */
303 enum {
304 	wil_tso_type_hdr = 0,
305 	wil_tso_type_first = 1,
306 	wil_tso_type_mid  = 2,
307 	wil_tso_type_lst  = 3,
308 };
309 
310 /* Rx descriptor - MAC part
311  * [dword 0]
312  * bit  0.. 3 : tid:4 The QoS (b3-0) TID Field
313  * bit  4.. 6 : cid:3 The Source index that  was found during parsing the TA.
314  *		This field is used to define the source of the packet
315  * bit      7 : MAC_id_valid:1, 1 if MAC virtual number is valid.
316  * bit  8.. 9 : mid:2 The MAC virtual number
317  * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type
318  *		(management, data, control and extension)
319  * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype
320  * bit 16..27 : seq_number:12 The received Sequence number field
321  * bit 28..31 : extended:4 extended subtype
322  * [dword 1]
323  * bit  0.. 3 : reserved
324  * bit  4.. 5 : key_id:2
325  * bit      6 : decrypt_bypass:1
326  * bit      7 : security:1 FC (b14)
327  * bit  8.. 9 : ds_bits:2 FC (b9-8)
328  * bit     10 : a_msdu_present:1  QoS (b7)
329  * bit     11 : a_msdu_type:1  QoS (b8)
330  * bit     12 : a_mpdu:1  part of AMPDU aggregation
331  * bit     13 : broadcast:1
332  * bit     14 : mutlicast:1
333  * bit     15 : reserved:1
334  * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
335  *		is received from
336  * bit 21..24 : mcs:4
337  * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt
338  *		after it writes the packet
339  * bit 29..31 : reserved:3
340  * [dword 2]
341  * bit  0.. 2 : time_slot:3 The timeslot that the MPDU is received
342  * bit  3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version
343  * bit      5 : fc_order:1 The FC Control (b15) -Order
344  * bit  6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field
345  * bit      8 : esop:1 The QoS (b4) ESOP field
346  * bit      9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
347  * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
348  * bit     15 : qos_ac_constraint:1 QoS (b15)
349  * bit 16..31 : pn_15_0:16 low 2 bytes of PN
350  * [dword 3]
351  * bit  0..31 : pn_47_16:32 high 4 bytes of PN
352  */
353 struct vring_rx_mac {
354 	u32 d0;
355 	u32 d1;
356 	u16 w4;
357 	u16 pn_15_0;
358 	u32 pn_47_16;
359 } __packed;
360 
361 /* Rx descriptor - DMA part
362  * [dword 0]
363  * bit  0.. 7 : l4_length:8 layer 4 length. The field is only valid if
364  *		L4I bit is set
365  * bit      8 : cmd_eop:1 set to 1
366  * bit      9 : cmd_rt:1 set to 1
367  * bit     10 : cmd_dma_it:1 immediate interrupt
368  * bit 11..15 : reserved:5
369  * bit 16..29 : phy_info_length:14 It is valid when the PII is set.
370  *		When the FFM bit is set bits 29-27 are used for for
371  *		Flex Filter Match. Matching Index to one of the L2
372  *		EtherType Flex Filter
373  * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
374  *		00 - UDP, 01 - TCP, 10, 11 - reserved
375  * [dword 1]
376  * bit  0..31 : addr_low:32 The payload buffer low address
377  * [dword 2]
378  * bit  0..15 : addr_high:16 The payload buffer high address
379  * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set
380  * bit 24..30 : mac_length:7
381  * bit     31 : ip_version:1 1 - IPv4, 0 - IPv6
382  * [dword 3]
383  *  [byte 12] error
384  * bit      0 : FCS:1
385  * bit      1 : MIC:1
386  * bit      2 : Key miss:1
387  * bit      3 : Replay:1
388  * bit      4 : L3:1 IPv4 checksum
389  * bit      5 : L4:1 TCP/UDP checksum
390  * bit  6   7 : reserved:2
391  *  [byte 13] status
392  * bit      0 : DU:1 Descriptor Used
393  * bit      1 : EOP:1 The descriptor indicates the End of Packet
394  * bit      2 : error:1
395  * bit      3 : MI:1 MAC Interrupt is asserted (according to parser decision)
396  * bit      4 : L3I:1 L3 identified and checksum calculated
397  * bit      5 : L4I:1 L4 identified and checksum calculated
398  * bit      6 : PII:1 PHY Info Included in the packet
399  * bit      7 : FFM:1 EtherType Flex Filter Match
400  *  [word 7] length
401  */
402 
403 #define RX_DMA_D0_CMD_DMA_EOP	BIT(8)
404 #define RX_DMA_D0_CMD_DMA_RT	BIT(9)  /* always 1 */
405 #define RX_DMA_D0_CMD_DMA_IT	BIT(10) /* interrupt */
406 #define RX_MAC_D0_MAC_ID_VALID	BIT(7)
407 
408 /* Error field */
409 #define RX_DMA_ERROR_FCS	BIT(0)
410 #define RX_DMA_ERROR_MIC	BIT(1)
411 #define RX_DMA_ERROR_KEY	BIT(2) /* Key missing */
412 #define RX_DMA_ERROR_REPLAY	BIT(3)
413 #define RX_DMA_ERROR_L3_ERR	BIT(4)
414 #define RX_DMA_ERROR_L4_ERR	BIT(5)
415 
416 /* Status field */
417 #define RX_DMA_STATUS_DU	BIT(0)
418 #define RX_DMA_STATUS_EOP	BIT(1)
419 #define RX_DMA_STATUS_ERROR	BIT(2)
420 #define RX_DMA_STATUS_MI	BIT(3) /* MAC Interrupt is asserted */
421 #define RX_DMA_STATUS_L3I	BIT(4)
422 #define RX_DMA_STATUS_L4I	BIT(5)
423 #define RX_DMA_STATUS_PHY_INFO	BIT(6)
424 #define RX_DMA_STATUS_FFM	BIT(7) /* EtherType Flex Filter Match */
425 
426 struct vring_rx_dma {
427 	u32 d0;
428 	struct wil_ring_dma_addr addr;
429 	u8  ip_length;
430 	u8  b11;
431 	u8  error;
432 	u8  status;
433 	__le16 length;
434 } __packed;
435 
436 struct vring_tx_desc {
437 	struct vring_tx_mac mac;
438 	struct vring_tx_dma dma;
439 } __packed;
440 
441 union wil_tx_desc {
442 	struct vring_tx_desc legacy;
443 	struct wil_tx_enhanced_desc enhanced;
444 } __packed;
445 
446 struct vring_rx_desc {
447 	struct vring_rx_mac mac;
448 	struct vring_rx_dma dma;
449 } __packed;
450 
451 union wil_rx_desc {
452 	struct vring_rx_desc legacy;
453 	struct wil_rx_enhanced_desc enhanced;
454 } __packed;
455 
456 union wil_ring_desc {
457 	union wil_tx_desc tx;
458 	union wil_rx_desc rx;
459 } __packed;
460 
461 static inline int wil_rxdesc_tid(struct vring_rx_desc *d)
462 {
463 	return WIL_GET_BITS(d->mac.d0, 0, 3);
464 }
465 
466 static inline int wil_rxdesc_cid(struct vring_rx_desc *d)
467 {
468 	return WIL_GET_BITS(d->mac.d0, 4, 6);
469 }
470 
471 static inline int wil_rxdesc_mid(struct vring_rx_desc *d)
472 {
473 	return (d->mac.d0 & RX_MAC_D0_MAC_ID_VALID) ?
474 		WIL_GET_BITS(d->mac.d0, 8, 9) : 0;
475 }
476 
477 static inline int wil_rxdesc_ftype(struct vring_rx_desc *d)
478 {
479 	return WIL_GET_BITS(d->mac.d0, 10, 11);
480 }
481 
482 static inline int wil_rxdesc_subtype(struct vring_rx_desc *d)
483 {
484 	return WIL_GET_BITS(d->mac.d0, 12, 15);
485 }
486 
487 /* 1-st byte (with frame type/subtype) of FC field */
488 static inline u8 wil_rxdesc_fc1(struct vring_rx_desc *d)
489 {
490 	return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2);
491 }
492 
493 static inline int wil_rxdesc_seq(struct vring_rx_desc *d)
494 {
495 	return WIL_GET_BITS(d->mac.d0, 16, 27);
496 }
497 
498 static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d)
499 {
500 	return WIL_GET_BITS(d->mac.d0, 28, 31);
501 }
502 
503 static inline int wil_rxdesc_retry(struct vring_rx_desc *d)
504 {
505 	return WIL_GET_BITS(d->mac.d0, 31, 31);
506 }
507 
508 static inline int wil_rxdesc_key_id(struct vring_rx_desc *d)
509 {
510 	return WIL_GET_BITS(d->mac.d1, 4, 5);
511 }
512 
513 static inline int wil_rxdesc_security(struct vring_rx_desc *d)
514 {
515 	return WIL_GET_BITS(d->mac.d1, 7, 7);
516 }
517 
518 static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d)
519 {
520 	return WIL_GET_BITS(d->mac.d1, 8, 9);
521 }
522 
523 static inline int wil_rxdesc_mcs(struct vring_rx_desc *d)
524 {
525 	return WIL_GET_BITS(d->mac.d1, 21, 24);
526 }
527 
528 static inline int wil_rxdesc_mcast(struct vring_rx_desc *d)
529 {
530 	return WIL_GET_BITS(d->mac.d1, 13, 14);
531 }
532 
533 static inline int wil_rxdesc_phy_length(struct vring_rx_desc *d)
534 {
535 	return WIL_GET_BITS(d->dma.d0, 16, 29);
536 }
537 
538 static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb)
539 {
540 	return (void *)skb->cb;
541 }
542 
543 static inline int wil_ring_is_empty(struct wil_ring *ring)
544 {
545 	return ring->swhead == ring->swtail;
546 }
547 
548 static inline u32 wil_ring_next_tail(struct wil_ring *ring)
549 {
550 	return (ring->swtail + 1) % ring->size;
551 }
552 
553 static inline void wil_ring_advance_head(struct wil_ring *ring, int n)
554 {
555 	ring->swhead = (ring->swhead + n) % ring->size;
556 }
557 
558 static inline int wil_ring_is_full(struct wil_ring *ring)
559 {
560 	return wil_ring_next_tail(ring) == ring->swhead;
561 }
562 
563 static inline bool wil_need_txstat(struct sk_buff *skb)
564 {
565 	struct ethhdr *eth = (void *)skb->data;
566 
567 	return is_unicast_ether_addr(eth->h_dest) && skb->sk &&
568 	       (skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS);
569 }
570 
571 static inline void wil_consume_skb(struct sk_buff *skb, bool acked)
572 {
573 	if (unlikely(wil_need_txstat(skb)))
574 		skb_complete_wifi_ack(skb, acked);
575 	else
576 		acked ? dev_consume_skb_any(skb) : dev_kfree_skb_any(skb);
577 }
578 
579 /* Used space in Tx ring */
580 static inline int wil_ring_used_tx(struct wil_ring *ring)
581 {
582 	u32 swhead = ring->swhead;
583 	u32 swtail = ring->swtail;
584 
585 	return (ring->size + swhead - swtail) % ring->size;
586 }
587 
588 /* Available space in Tx ring */
589 static inline int wil_ring_avail_tx(struct wil_ring *ring)
590 {
591 	return ring->size - wil_ring_used_tx(ring) - 1;
592 }
593 
594 static inline int wil_get_min_tx_ring_id(struct wil6210_priv *wil)
595 {
596 	/* In Enhanced DMA ring 0 is reserved for RX */
597 	return wil->use_enhanced_dma_hw ? 1 : 0;
598 }
599 
600 /* similar to ieee80211_ version, but FC contain only 1-st byte */
601 static inline int wil_is_back_req(u8 fc)
602 {
603 	return (fc & (IEEE80211_FCTL_FTYPE | IEEE80211_FCTL_STYPE)) ==
604 	       (IEEE80211_FTYPE_CTL | IEEE80211_STYPE_BACK_REQ);
605 }
606 
607 /* wil_val_in_range - check if value in [min,max) */
608 static inline bool wil_val_in_range(int val, int min, int max)
609 {
610 	return val >= min && val < max;
611 }
612 
613 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev);
614 void wil_rx_reorder(struct wil6210_priv *wil, struct sk_buff *skb);
615 void wil_rx_bar(struct wil6210_priv *wil, struct wil6210_vif *vif,
616 		u8 cid, u8 tid, u16 seq);
617 struct wil_tid_ampdu_rx *wil_tid_ampdu_rx_alloc(struct wil6210_priv *wil,
618 						int size, u16 ssn);
619 void wil_tid_ampdu_rx_free(struct wil6210_priv *wil,
620 			   struct wil_tid_ampdu_rx *r);
621 void wil_tx_data_init(struct wil_ring_tx_data *txdata);
622 void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil);
623 void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb,
624 			 struct wil_sta_info *sta);
625 
626 #endif /* WIL6210_TXRX_H */
627