1 /*
2  * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef WIL6210_TXRX_H
18 #define WIL6210_TXRX_H
19 
20 #define BUF_SW_OWNED    (1)
21 #define BUF_HW_OWNED    (0)
22 
23 /* default size of MAC Tx/Rx buffers */
24 #define TXRX_BUF_LEN_DEFAULT (2048)
25 
26 /* how many bytes to reserve for rtap header? */
27 #define WIL6210_RTAP_SIZE (128)
28 
29 /* Tx/Rx path */
30 
31 /* Common representation of physical address in Vring */
32 struct vring_dma_addr {
33 	__le32 addr_low;
34 	__le16 addr_high;
35 } __packed;
36 
37 static inline dma_addr_t wil_desc_addr(struct vring_dma_addr *addr)
38 {
39 	return le32_to_cpu(addr->addr_low) |
40 			   ((u64)le16_to_cpu(addr->addr_high) << 32);
41 }
42 
43 static inline void wil_desc_addr_set(struct vring_dma_addr *addr,
44 				     dma_addr_t pa)
45 {
46 	addr->addr_low = cpu_to_le32(lower_32_bits(pa));
47 	addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
48 }
49 
50 /* Tx descriptor - MAC part
51  * [dword 0]
52  * bit  0.. 9 : lifetime_expiry_value:10
53  * bit     10 : interrupt_en:1
54  * bit     11 : status_en:1
55  * bit 12..13 : txss_override:2
56  * bit     14 : timestamp_insertion:1
57  * bit     15 : duration_preserve:1
58  * bit 16..21 : reserved0:6
59  * bit 22..26 : mcs_index:5
60  * bit     27 : mcs_en:1
61  * bit 28..30 : reserved1:3
62  * bit     31 : sn_preserved:1
63  * [dword 1]
64  * bit  0.. 3 : pkt_mode:4
65  * bit      4 : pkt_mode_en:1
66  * bit  5..14 : reserved0:10
67  * bit     15 : ack_policy_en:1
68  * bit 16..19 : dst_index:4
69  * bit     20 : dst_index_en:1
70  * bit 21..22 : ack_policy:2
71  * bit     23 : lifetime_en:1
72  * bit 24..30 : max_retry:7
73  * bit     31 : max_retry_en:1
74  * [dword 2]
75  * bit  0.. 7 : num_of_descriptors:8
76  * bit  8..17 : reserved:10
77  * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
78  * bit     20 : snap_hdr_insertion_en:1
79  * bit     21 : vlan_removal_en:1
80  * bit 22..31 : reserved0:10
81  * [dword 3]
82  * bit  0.. 31: ucode_cmd:32
83  */
84 struct vring_tx_mac {
85 	u32 d[3];
86 	u32 ucode_cmd;
87 } __packed;
88 
89 /* TX MAC Dword 0 */
90 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
91 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
92 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
93 
94 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
95 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
96 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
97 
98 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
99 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
100 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
101 
102 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
103 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
104 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
105 
106 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
107 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
108 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
109 
110 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
111 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
112 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
113 
114 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
115 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
116 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
117 
118 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
119 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
120 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
121 
122 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
123 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
124 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
125 
126 /* TX MAC Dword 1 */
127 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
128 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
129 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
130 
131 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
132 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
133 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
134 
135 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
136 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
137 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
138 
139 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
140 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
141 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
142 
143 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
144 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
145 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
146 
147 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
148 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
149 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
150 
151 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
152 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
153 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
154 
155 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
156 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
157 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
158 
159 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
160 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
161 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
162 
163 /* TX MAC Dword 2 */
164 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
165 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
166 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
167 
168 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8
169 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
170 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
171 
172 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
173 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
174 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
175 
176 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
177 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
178 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
179 
180 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
181 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
182 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
183 
184 /* TX MAC Dword 3 */
185 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
186 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
187 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
188 
189 /* TX DMA Dword 0 */
190 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
191 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
192 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
193 
194 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
195 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
196 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
197 
198 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9
199 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
200 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200
201 
202 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
203 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
204 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
205 
206 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
207 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
208 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
209 
210 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
211 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
212 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
213 
214 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
215 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
216 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
217 
218 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
219 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
220 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
221 
222 #define DMA_CFG_DESC_TX_0_QID_POS 16
223 #define DMA_CFG_DESC_TX_0_QID_LEN 5
224 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
225 
226 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
227 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
228 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
229 
230 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
231 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
232 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */
233 
234 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0
235 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7
236 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */
237 
238 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7
239 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
240 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */
241 
242 #define TX_DMA_STATUS_DU         BIT(0)
243 
244 /* Tx descriptor - DMA part
245  * [dword 0]
246  * bit  0.. 7 : l4_length:8 layer 4 length
247  * bit      8 : cmd_eop:1 This descriptor is the last one in the packet
248  * bit      9 : reserved
249  * bit     10 : cmd_dma_it:1 immediate interrupt
250  * bit 11..12 : SBD - Segment Buffer Details
251  *		00 - Header Segment
252  *		01 - First Data Segment
253  *		10 - Medium Data Segment
254  *		11 - Last Data Segment
255  * bit     13 : TSE - TCP Segmentation Enable
256  * bit     14 : IIC - Directs the HW to Insert IPv4 Checksum
257  * bit     15 : ITC - Directs the HW to Insert TCP/UDP Checksum
258  * bit 16..20 : QID - The target QID that the packet should be stored
259  *		in the MAC.
260  * bit     21 : PO - Pseudo header Offload:
261  *		0 - Use the pseudo header value from the TCP checksum field
262  *		1- Calculate Pseudo header Checksum
263  * bit     22 : NC - No UDP Checksum
264  * bit 23..29 : reserved
265  * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved
266  *		If L4Len equal 0, no L4 at all
267  * [dword 1]
268  * bit  0..31 : addr_low:32 The payload buffer low address
269  * [dword 2]
270  * bit  0..15 : addr_high:16 The payload buffer high address
271  * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
272  *		offload feature
273  * bit 24..30 : mac_length:7
274  * bit     31 : ip_version:1 1 - IPv4, 0 - IPv6
275  * [dword 3]
276  *  [byte 12] error
277  * bit  0   2 : mac_status:3
278  * bit  3   7 : reserved:5
279  *  [byte 13] status
280  * bit      0 : DU:1 Descriptor Used
281  * bit  1   7 : reserved:7
282  *  [word 7] length
283  */
284 struct vring_tx_dma {
285 	u32 d0;
286 	struct vring_dma_addr addr;
287 	u8  ip_length;
288 	u8  b11;       /* 0..6: mac_length; 7:ip_version */
289 	u8  error;     /* 0..2: err; 3..7: reserved; */
290 	u8  status;    /* 0: used; 1..7; reserved */
291 	__le16 length;
292 } __packed;
293 
294 /* TSO type used in dma descriptor d0 bits 11-12 */
295 enum {
296 	wil_tso_type_hdr = 0,
297 	wil_tso_type_first = 1,
298 	wil_tso_type_mid  = 2,
299 	wil_tso_type_lst  = 3,
300 };
301 
302 /* Rx descriptor - MAC part
303  * [dword 0]
304  * bit  0.. 3 : tid:4 The QoS (b3-0) TID Field
305  * bit  4.. 6 : cid:3 The Source index that  was found during parsing the TA.
306  *		This field is used to define the source of the packet
307  * bit      7 : reserved:1
308  * bit  8.. 9 : mid:2 The MAC virtual number
309  * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type
310  *		(management, data, control and extension)
311  * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype
312  * bit 16..27 : seq_number:12 The received Sequence number field
313  * bit 28..31 : extended:4 extended subtype
314  * [dword 1]
315  * bit  0.. 3 : reserved
316  * bit  4.. 5 : key_id:2
317  * bit      6 : decrypt_bypass:1
318  * bit      7 : security:1 FC (b14)
319  * bit  8.. 9 : ds_bits:2 FC (b9-8)
320  * bit     10 : a_msdu_present:1  QoS (b7)
321  * bit     11 : a_msdu_type:1  QoS (b8)
322  * bit     12 : a_mpdu:1  part of AMPDU aggregation
323  * bit     13 : broadcast:1
324  * bit     14 : mutlicast:1
325  * bit     15 : reserved:1
326  * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
327  *		is received from
328  * bit 21..24 : mcs:4
329  * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt
330  *		after it writes the packet
331  * bit 29..31 : reserved:3
332  * [dword 2]
333  * bit  0.. 2 : time_slot:3 The timeslot that the MPDU is received
334  * bit  3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version
335  * bit      5 : fc_order:1 The FC Control (b15) -Order
336  * bit  6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field
337  * bit      8 : esop:1 The QoS (b4) ESOP field
338  * bit      9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
339  * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
340  * bit     15 : qos_ac_constraint:1 QoS (b15)
341  * bit 16..31 : pn_15_0:16 low 2 bytes of PN
342  * [dword 3]
343  * bit  0..31 : pn_47_16:32 high 4 bytes of PN
344  */
345 struct vring_rx_mac {
346 	u32 d0;
347 	u32 d1;
348 	u16 w4;
349 	u16 pn_15_0;
350 	u32 pn_47_16;
351 } __packed;
352 
353 /* Rx descriptor - DMA part
354  * [dword 0]
355  * bit  0.. 7 : l4_length:8 layer 4 length. The field is only valid if
356  *		L4I bit is set
357  * bit      8 : cmd_eop:1 set to 1
358  * bit      9 : cmd_rt:1 set to 1
359  * bit     10 : cmd_dma_it:1 immediate interrupt
360  * bit 11..15 : reserved:5
361  * bit 16..29 : phy_info_length:14 It is valid when the PII is set.
362  *		When the FFM bit is set bits 29-27 are used for for
363  *		Flex Filter Match. Matching Index to one of the L2
364  *		EtherType Flex Filter
365  * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
366  *		00 - UDP, 01 - TCP, 10, 11 - reserved
367  * [dword 1]
368  * bit  0..31 : addr_low:32 The payload buffer low address
369  * [dword 2]
370  * bit  0..15 : addr_high:16 The payload buffer high address
371  * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set
372  * bit 24..30 : mac_length:7
373  * bit     31 : ip_version:1 1 - IPv4, 0 - IPv6
374  * [dword 3]
375  *  [byte 12] error
376  * bit      0 : FCS:1
377  * bit      1 : MIC:1
378  * bit      2 : Key miss:1
379  * bit      3 : Replay:1
380  * bit      4 : L3:1 IPv4 checksum
381  * bit      5 : L4:1 TCP/UDP checksum
382  * bit  6   7 : reserved:2
383  *  [byte 13] status
384  * bit      0 : DU:1 Descriptor Used
385  * bit      1 : EOP:1 The descriptor indicates the End of Packet
386  * bit      2 : error:1
387  * bit      3 : MI:1 MAC Interrupt is asserted (according to parser decision)
388  * bit      4 : L3I:1 L3 identified and checksum calculated
389  * bit      5 : L4I:1 L4 identified and checksum calculated
390  * bit      6 : PII:1 PHY Info Included in the packet
391  * bit      7 : FFM:1 EtherType Flex Filter Match
392  *  [word 7] length
393  */
394 
395 #define RX_DMA_D0_CMD_DMA_EOP	BIT(8)
396 #define RX_DMA_D0_CMD_DMA_RT	BIT(9)  /* always 1 */
397 #define RX_DMA_D0_CMD_DMA_IT	BIT(10) /* interrupt */
398 
399 /* Error field */
400 #define RX_DMA_ERROR_FCS	BIT(0)
401 #define RX_DMA_ERROR_MIC	BIT(1)
402 #define RX_DMA_ERROR_KEY	BIT(2) /* Key missing */
403 #define RX_DMA_ERROR_REPLAY	BIT(3)
404 #define RX_DMA_ERROR_L3_ERR	BIT(4)
405 #define RX_DMA_ERROR_L4_ERR	BIT(5)
406 
407 /* Status field */
408 #define RX_DMA_STATUS_DU	BIT(0)
409 #define RX_DMA_STATUS_EOP	BIT(1)
410 #define RX_DMA_STATUS_ERROR	BIT(2)
411 #define RX_DMA_STATUS_MI	BIT(3) /* MAC Interrupt is asserted */
412 #define RX_DMA_STATUS_L3I	BIT(4)
413 #define RX_DMA_STATUS_L4I	BIT(5)
414 #define RX_DMA_STATUS_PHY_INFO	BIT(6)
415 #define RX_DMA_STATUS_FFM	BIT(7) /* EtherType Flex Filter Match */
416 
417 struct vring_rx_dma {
418 	u32 d0;
419 	struct vring_dma_addr addr;
420 	u8  ip_length;
421 	u8  b11;
422 	u8  error;
423 	u8  status;
424 	__le16 length;
425 } __packed;
426 
427 struct vring_tx_desc {
428 	struct vring_tx_mac mac;
429 	struct vring_tx_dma dma;
430 } __packed;
431 
432 struct vring_rx_desc {
433 	struct vring_rx_mac mac;
434 	struct vring_rx_dma dma;
435 } __packed;
436 
437 union vring_desc {
438 	struct vring_tx_desc tx;
439 	struct vring_rx_desc rx;
440 } __packed;
441 
442 static inline int wil_rxdesc_tid(struct vring_rx_desc *d)
443 {
444 	return WIL_GET_BITS(d->mac.d0, 0, 3);
445 }
446 
447 static inline int wil_rxdesc_cid(struct vring_rx_desc *d)
448 {
449 	return WIL_GET_BITS(d->mac.d0, 4, 6);
450 }
451 
452 static inline int wil_rxdesc_mid(struct vring_rx_desc *d)
453 {
454 	return WIL_GET_BITS(d->mac.d0, 8, 9);
455 }
456 
457 static inline int wil_rxdesc_ftype(struct vring_rx_desc *d)
458 {
459 	return WIL_GET_BITS(d->mac.d0, 10, 11);
460 }
461 
462 static inline int wil_rxdesc_subtype(struct vring_rx_desc *d)
463 {
464 	return WIL_GET_BITS(d->mac.d0, 12, 15);
465 }
466 
467 /* 1-st byte (with frame type/subtype) of FC field */
468 static inline u8 wil_rxdesc_fc1(struct vring_rx_desc *d)
469 {
470 	return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2);
471 }
472 
473 static inline int wil_rxdesc_seq(struct vring_rx_desc *d)
474 {
475 	return WIL_GET_BITS(d->mac.d0, 16, 27);
476 }
477 
478 static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d)
479 {
480 	return WIL_GET_BITS(d->mac.d0, 28, 31);
481 }
482 
483 static inline int wil_rxdesc_key_id(struct vring_rx_desc *d)
484 {
485 	return WIL_GET_BITS(d->mac.d1, 4, 5);
486 }
487 
488 static inline int wil_rxdesc_security(struct vring_rx_desc *d)
489 {
490 	return WIL_GET_BITS(d->mac.d1, 7, 7);
491 }
492 
493 static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d)
494 {
495 	return WIL_GET_BITS(d->mac.d1, 8, 9);
496 }
497 
498 static inline int wil_rxdesc_mcs(struct vring_rx_desc *d)
499 {
500 	return WIL_GET_BITS(d->mac.d1, 21, 24);
501 }
502 
503 static inline int wil_rxdesc_mcast(struct vring_rx_desc *d)
504 {
505 	return WIL_GET_BITS(d->mac.d1, 13, 14);
506 }
507 
508 static inline int wil_rxdesc_phy_length(struct vring_rx_desc *d)
509 {
510 	return WIL_GET_BITS(d->dma.d0, 16, 29);
511 }
512 
513 static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb)
514 {
515 	return (void *)skb->cb;
516 }
517 
518 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev);
519 void wil_rx_reorder(struct wil6210_priv *wil, struct sk_buff *skb);
520 void wil_rx_bar(struct wil6210_priv *wil, u8 cid, u8 tid, u16 seq);
521 struct wil_tid_ampdu_rx *wil_tid_ampdu_rx_alloc(struct wil6210_priv *wil,
522 						int size, u16 ssn);
523 void wil_tid_ampdu_rx_free(struct wil6210_priv *wil,
524 			   struct wil_tid_ampdu_rx *r);
525 
526 #endif /* WIL6210_TXRX_H */
527