1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/etherdevice.h> 19 #include <net/ieee80211_radiotap.h> 20 #include <linux/if_arp.h> 21 #include <linux/moduleparam.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ipv6.h> 25 #include <linux/prefetch.h> 26 27 #include "wil6210.h" 28 #include "wmi.h" 29 #include "txrx.h" 30 #include "trace.h" 31 #include "txrx_edma.h" 32 33 static bool rtap_include_phy_info; 34 module_param(rtap_include_phy_info, bool, 0444); 35 MODULE_PARM_DESC(rtap_include_phy_info, 36 " Include PHY info in the radiotap header, default - no"); 37 38 bool rx_align_2; 39 module_param(rx_align_2, bool, 0444); 40 MODULE_PARM_DESC(rx_align_2, " align Rx buffers on 4*n+2, default - no"); 41 42 bool rx_large_buf; 43 module_param(rx_large_buf, bool, 0444); 44 MODULE_PARM_DESC(rx_large_buf, " allocate 8KB RX buffers, default - no"); 45 46 static inline uint wil_rx_snaplen(void) 47 { 48 return rx_align_2 ? 6 : 0; 49 } 50 51 /* wil_ring_wmark_low - low watermark for available descriptor space */ 52 static inline int wil_ring_wmark_low(struct wil_ring *ring) 53 { 54 return ring->size / 8; 55 } 56 57 /* wil_ring_wmark_high - high watermark for available descriptor space */ 58 static inline int wil_ring_wmark_high(struct wil_ring *ring) 59 { 60 return ring->size / 4; 61 } 62 63 /* returns true if num avail descriptors is lower than wmark_low */ 64 static inline int wil_ring_avail_low(struct wil_ring *ring) 65 { 66 return wil_ring_avail_tx(ring) < wil_ring_wmark_low(ring); 67 } 68 69 /* returns true if num avail descriptors is higher than wmark_high */ 70 static inline int wil_ring_avail_high(struct wil_ring *ring) 71 { 72 return wil_ring_avail_tx(ring) > wil_ring_wmark_high(ring); 73 } 74 75 /* returns true when all tx vrings are empty */ 76 bool wil_is_tx_idle(struct wil6210_priv *wil) 77 { 78 int i; 79 unsigned long data_comp_to; 80 int min_ring_id = wil_get_min_tx_ring_id(wil); 81 82 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 83 struct wil_ring *vring = &wil->ring_tx[i]; 84 int vring_index = vring - wil->ring_tx; 85 struct wil_ring_tx_data *txdata = 86 &wil->ring_tx_data[vring_index]; 87 88 spin_lock(&txdata->lock); 89 90 if (!vring->va || !txdata->enabled) { 91 spin_unlock(&txdata->lock); 92 continue; 93 } 94 95 data_comp_to = jiffies + msecs_to_jiffies( 96 WIL_DATA_COMPLETION_TO_MS); 97 if (test_bit(wil_status_napi_en, wil->status)) { 98 while (!wil_ring_is_empty(vring)) { 99 if (time_after(jiffies, data_comp_to)) { 100 wil_dbg_pm(wil, 101 "TO waiting for idle tx\n"); 102 spin_unlock(&txdata->lock); 103 return false; 104 } 105 wil_dbg_ratelimited(wil, 106 "tx vring is not empty -> NAPI\n"); 107 spin_unlock(&txdata->lock); 108 napi_synchronize(&wil->napi_tx); 109 msleep(20); 110 spin_lock(&txdata->lock); 111 if (!vring->va || !txdata->enabled) 112 break; 113 } 114 } 115 116 spin_unlock(&txdata->lock); 117 } 118 119 return true; 120 } 121 122 static int wil_vring_alloc(struct wil6210_priv *wil, struct wil_ring *vring) 123 { 124 struct device *dev = wil_to_dev(wil); 125 size_t sz = vring->size * sizeof(vring->va[0]); 126 uint i; 127 128 wil_dbg_misc(wil, "vring_alloc:\n"); 129 130 BUILD_BUG_ON(sizeof(vring->va[0]) != 32); 131 132 vring->swhead = 0; 133 vring->swtail = 0; 134 vring->ctx = kcalloc(vring->size, sizeof(vring->ctx[0]), GFP_KERNEL); 135 if (!vring->ctx) { 136 vring->va = NULL; 137 return -ENOMEM; 138 } 139 140 /* vring->va should be aligned on its size rounded up to power of 2 141 * This is granted by the dma_alloc_coherent. 142 * 143 * HW has limitation that all vrings addresses must share the same 144 * upper 16 msb bits part of 48 bits address. To workaround that, 145 * if we are using more than 32 bit addresses switch to 32 bit 146 * allocation before allocating vring memory. 147 * 148 * There's no check for the return value of dma_set_mask_and_coherent, 149 * since we assume if we were able to set the mask during 150 * initialization in this system it will not fail if we set it again 151 */ 152 if (wil->dma_addr_size > 32) 153 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 154 155 vring->va = dma_alloc_coherent(dev, sz, &vring->pa, GFP_KERNEL); 156 if (!vring->va) { 157 kfree(vring->ctx); 158 vring->ctx = NULL; 159 return -ENOMEM; 160 } 161 162 if (wil->dma_addr_size > 32) 163 dma_set_mask_and_coherent(dev, 164 DMA_BIT_MASK(wil->dma_addr_size)); 165 166 /* initially, all descriptors are SW owned 167 * For Tx and Rx, ownership bit is at the same location, thus 168 * we can use any 169 */ 170 for (i = 0; i < vring->size; i++) { 171 volatile struct vring_tx_desc *_d = 172 &vring->va[i].tx.legacy; 173 174 _d->dma.status = TX_DMA_STATUS_DU; 175 } 176 177 wil_dbg_misc(wil, "vring[%d] 0x%p:%pad 0x%p\n", vring->size, 178 vring->va, &vring->pa, vring->ctx); 179 180 return 0; 181 } 182 183 static void wil_txdesc_unmap(struct device *dev, union wil_tx_desc *desc, 184 struct wil_ctx *ctx) 185 { 186 struct vring_tx_desc *d = &desc->legacy; 187 dma_addr_t pa = wil_desc_addr(&d->dma.addr); 188 u16 dmalen = le16_to_cpu(d->dma.length); 189 190 switch (ctx->mapped_as) { 191 case wil_mapped_as_single: 192 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 193 break; 194 case wil_mapped_as_page: 195 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 196 break; 197 default: 198 break; 199 } 200 } 201 202 static void wil_vring_free(struct wil6210_priv *wil, struct wil_ring *vring) 203 { 204 struct device *dev = wil_to_dev(wil); 205 size_t sz = vring->size * sizeof(vring->va[0]); 206 207 lockdep_assert_held(&wil->mutex); 208 if (!vring->is_rx) { 209 int vring_index = vring - wil->ring_tx; 210 211 wil_dbg_misc(wil, "free Tx vring %d [%d] 0x%p:%pad 0x%p\n", 212 vring_index, vring->size, vring->va, 213 &vring->pa, vring->ctx); 214 } else { 215 wil_dbg_misc(wil, "free Rx vring [%d] 0x%p:%pad 0x%p\n", 216 vring->size, vring->va, 217 &vring->pa, vring->ctx); 218 } 219 220 while (!wil_ring_is_empty(vring)) { 221 dma_addr_t pa; 222 u16 dmalen; 223 struct wil_ctx *ctx; 224 225 if (!vring->is_rx) { 226 struct vring_tx_desc dd, *d = ⅆ 227 volatile struct vring_tx_desc *_d = 228 &vring->va[vring->swtail].tx.legacy; 229 230 ctx = &vring->ctx[vring->swtail]; 231 if (!ctx) { 232 wil_dbg_txrx(wil, 233 "ctx(%d) was already completed\n", 234 vring->swtail); 235 vring->swtail = wil_ring_next_tail(vring); 236 continue; 237 } 238 *d = *_d; 239 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx); 240 if (ctx->skb) 241 dev_kfree_skb_any(ctx->skb); 242 vring->swtail = wil_ring_next_tail(vring); 243 } else { /* rx */ 244 struct vring_rx_desc dd, *d = ⅆ 245 volatile struct vring_rx_desc *_d = 246 &vring->va[vring->swhead].rx.legacy; 247 248 ctx = &vring->ctx[vring->swhead]; 249 *d = *_d; 250 pa = wil_desc_addr(&d->dma.addr); 251 dmalen = le16_to_cpu(d->dma.length); 252 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE); 253 kfree_skb(ctx->skb); 254 wil_ring_advance_head(vring, 1); 255 } 256 } 257 dma_free_coherent(dev, sz, (void *)vring->va, vring->pa); 258 kfree(vring->ctx); 259 vring->pa = 0; 260 vring->va = NULL; 261 vring->ctx = NULL; 262 } 263 264 /** 265 * Allocate one skb for Rx VRING 266 * 267 * Safe to call from IRQ 268 */ 269 static int wil_vring_alloc_skb(struct wil6210_priv *wil, struct wil_ring *vring, 270 u32 i, int headroom) 271 { 272 struct device *dev = wil_to_dev(wil); 273 unsigned int sz = wil->rx_buf_len + ETH_HLEN + wil_rx_snaplen(); 274 struct vring_rx_desc dd, *d = ⅆ 275 volatile struct vring_rx_desc *_d = &vring->va[i].rx.legacy; 276 dma_addr_t pa; 277 struct sk_buff *skb = dev_alloc_skb(sz + headroom); 278 279 if (unlikely(!skb)) 280 return -ENOMEM; 281 282 skb_reserve(skb, headroom); 283 skb_put(skb, sz); 284 285 /** 286 * Make sure that the network stack calculates checksum for packets 287 * which failed the HW checksum calculation 288 */ 289 skb->ip_summed = CHECKSUM_NONE; 290 291 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 292 if (unlikely(dma_mapping_error(dev, pa))) { 293 kfree_skb(skb); 294 return -ENOMEM; 295 } 296 297 d->dma.d0 = RX_DMA_D0_CMD_DMA_RT | RX_DMA_D0_CMD_DMA_IT; 298 wil_desc_addr_set(&d->dma.addr, pa); 299 /* ip_length don't care */ 300 /* b11 don't care */ 301 /* error don't care */ 302 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ 303 d->dma.length = cpu_to_le16(sz); 304 *_d = *d; 305 vring->ctx[i].skb = skb; 306 307 return 0; 308 } 309 310 /** 311 * Adds radiotap header 312 * 313 * Any error indicated as "Bad FCS" 314 * 315 * Vendor data for 04:ce:14-1 (Wilocity-1) consists of: 316 * - Rx descriptor: 32 bytes 317 * - Phy info 318 */ 319 static void wil_rx_add_radiotap_header(struct wil6210_priv *wil, 320 struct sk_buff *skb) 321 { 322 struct wil6210_rtap { 323 struct ieee80211_radiotap_header rthdr; 324 /* fields should be in the order of bits in rthdr.it_present */ 325 /* flags */ 326 u8 flags; 327 /* channel */ 328 __le16 chnl_freq __aligned(2); 329 __le16 chnl_flags; 330 /* MCS */ 331 u8 mcs_present; 332 u8 mcs_flags; 333 u8 mcs_index; 334 } __packed; 335 struct wil6210_rtap_vendor { 336 struct wil6210_rtap rtap; 337 /* vendor */ 338 u8 vendor_oui[3] __aligned(2); 339 u8 vendor_ns; 340 __le16 vendor_skip; 341 u8 vendor_data[0]; 342 } __packed; 343 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 344 struct wil6210_rtap_vendor *rtap_vendor; 345 int rtap_len = sizeof(struct wil6210_rtap); 346 int phy_length = 0; /* phy info header size, bytes */ 347 static char phy_data[128]; 348 struct ieee80211_channel *ch = wil->monitor_chandef.chan; 349 350 if (rtap_include_phy_info) { 351 rtap_len = sizeof(*rtap_vendor) + sizeof(*d); 352 /* calculate additional length */ 353 if (d->dma.status & RX_DMA_STATUS_PHY_INFO) { 354 /** 355 * PHY info starts from 8-byte boundary 356 * there are 8-byte lines, last line may be partially 357 * written (HW bug), thus FW configures for last line 358 * to be excessive. Driver skips this last line. 359 */ 360 int len = min_t(int, 8 + sizeof(phy_data), 361 wil_rxdesc_phy_length(d)); 362 363 if (len > 8) { 364 void *p = skb_tail_pointer(skb); 365 void *pa = PTR_ALIGN(p, 8); 366 367 if (skb_tailroom(skb) >= len + (pa - p)) { 368 phy_length = len - 8; 369 memcpy(phy_data, pa, phy_length); 370 } 371 } 372 } 373 rtap_len += phy_length; 374 } 375 376 if (skb_headroom(skb) < rtap_len && 377 pskb_expand_head(skb, rtap_len, 0, GFP_ATOMIC)) { 378 wil_err(wil, "Unable to expand headroom to %d\n", rtap_len); 379 return; 380 } 381 382 rtap_vendor = skb_push(skb, rtap_len); 383 memset(rtap_vendor, 0, rtap_len); 384 385 rtap_vendor->rtap.rthdr.it_version = PKTHDR_RADIOTAP_VERSION; 386 rtap_vendor->rtap.rthdr.it_len = cpu_to_le16(rtap_len); 387 rtap_vendor->rtap.rthdr.it_present = cpu_to_le32( 388 (1 << IEEE80211_RADIOTAP_FLAGS) | 389 (1 << IEEE80211_RADIOTAP_CHANNEL) | 390 (1 << IEEE80211_RADIOTAP_MCS)); 391 if (d->dma.status & RX_DMA_STATUS_ERROR) 392 rtap_vendor->rtap.flags |= IEEE80211_RADIOTAP_F_BADFCS; 393 394 rtap_vendor->rtap.chnl_freq = cpu_to_le16(ch ? ch->center_freq : 58320); 395 rtap_vendor->rtap.chnl_flags = cpu_to_le16(0); 396 397 rtap_vendor->rtap.mcs_present = IEEE80211_RADIOTAP_MCS_HAVE_MCS; 398 rtap_vendor->rtap.mcs_flags = 0; 399 rtap_vendor->rtap.mcs_index = wil_rxdesc_mcs(d); 400 401 if (rtap_include_phy_info) { 402 rtap_vendor->rtap.rthdr.it_present |= cpu_to_le32(1 << 403 IEEE80211_RADIOTAP_VENDOR_NAMESPACE); 404 /* OUI for Wilocity 04:ce:14 */ 405 rtap_vendor->vendor_oui[0] = 0x04; 406 rtap_vendor->vendor_oui[1] = 0xce; 407 rtap_vendor->vendor_oui[2] = 0x14; 408 rtap_vendor->vendor_ns = 1; 409 /* Rx descriptor + PHY data */ 410 rtap_vendor->vendor_skip = cpu_to_le16(sizeof(*d) + 411 phy_length); 412 memcpy(rtap_vendor->vendor_data, (void *)d, sizeof(*d)); 413 memcpy(rtap_vendor->vendor_data + sizeof(*d), phy_data, 414 phy_length); 415 } 416 } 417 418 static bool wil_is_rx_idle(struct wil6210_priv *wil) 419 { 420 struct vring_rx_desc *_d; 421 struct wil_ring *ring = &wil->ring_rx; 422 423 _d = (struct vring_rx_desc *)&ring->va[ring->swhead].rx.legacy; 424 if (_d->dma.status & RX_DMA_STATUS_DU) 425 return false; 426 427 return true; 428 } 429 430 /** 431 * reap 1 frame from @swhead 432 * 433 * Rx descriptor copied to skb->cb 434 * 435 * Safe to call from IRQ 436 */ 437 static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil, 438 struct wil_ring *vring) 439 { 440 struct device *dev = wil_to_dev(wil); 441 struct wil6210_vif *vif; 442 struct net_device *ndev; 443 volatile struct vring_rx_desc *_d; 444 struct vring_rx_desc *d; 445 struct sk_buff *skb; 446 dma_addr_t pa; 447 unsigned int snaplen = wil_rx_snaplen(); 448 unsigned int sz = wil->rx_buf_len + ETH_HLEN + snaplen; 449 u16 dmalen; 450 u8 ftype; 451 int cid, mid; 452 int i; 453 struct wil_net_stats *stats; 454 455 BUILD_BUG_ON(sizeof(struct vring_rx_desc) > sizeof(skb->cb)); 456 457 again: 458 if (unlikely(wil_ring_is_empty(vring))) 459 return NULL; 460 461 i = (int)vring->swhead; 462 _d = &vring->va[i].rx.legacy; 463 if (unlikely(!(_d->dma.status & RX_DMA_STATUS_DU))) { 464 /* it is not error, we just reached end of Rx done area */ 465 return NULL; 466 } 467 468 skb = vring->ctx[i].skb; 469 vring->ctx[i].skb = NULL; 470 wil_ring_advance_head(vring, 1); 471 if (!skb) { 472 wil_err(wil, "No Rx skb at [%d]\n", i); 473 goto again; 474 } 475 d = wil_skb_rxdesc(skb); 476 *d = *_d; 477 pa = wil_desc_addr(&d->dma.addr); 478 479 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 480 dmalen = le16_to_cpu(d->dma.length); 481 482 trace_wil6210_rx(i, d); 483 wil_dbg_txrx(wil, "Rx[%3d] : %d bytes\n", i, dmalen); 484 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4, 485 (const void *)d, sizeof(*d), false); 486 487 cid = wil_rxdesc_cid(d); 488 mid = wil_rxdesc_mid(d); 489 vif = wil->vifs[mid]; 490 491 if (unlikely(!vif)) { 492 wil_dbg_txrx(wil, "skipped RX descriptor with invalid mid %d", 493 mid); 494 kfree_skb(skb); 495 goto again; 496 } 497 ndev = vif_to_ndev(vif); 498 stats = &wil->sta[cid].stats; 499 500 if (unlikely(dmalen > sz)) { 501 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 502 stats->rx_large_frame++; 503 kfree_skb(skb); 504 goto again; 505 } 506 skb_trim(skb, dmalen); 507 508 prefetch(skb->data); 509 510 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 511 skb->data, skb_headlen(skb), false); 512 513 stats->last_mcs_rx = wil_rxdesc_mcs(d); 514 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 515 stats->rx_per_mcs[stats->last_mcs_rx]++; 516 517 /* use radiotap header only if required */ 518 if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) 519 wil_rx_add_radiotap_header(wil, skb); 520 521 /* no extra checks if in sniffer mode */ 522 if (ndev->type != ARPHRD_ETHER) 523 return skb; 524 /* Non-data frames may be delivered through Rx DMA channel (ex: BAR) 525 * Driver should recognize it by frame type, that is found 526 * in Rx descriptor. If type is not data, it is 802.11 frame as is 527 */ 528 ftype = wil_rxdesc_ftype(d) << 2; 529 if (unlikely(ftype != IEEE80211_FTYPE_DATA)) { 530 u8 fc1 = wil_rxdesc_fc1(d); 531 int tid = wil_rxdesc_tid(d); 532 u16 seq = wil_rxdesc_seq(d); 533 534 wil_dbg_txrx(wil, 535 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 536 fc1, mid, cid, tid, seq); 537 stats->rx_non_data_frame++; 538 if (wil_is_back_req(fc1)) { 539 wil_dbg_txrx(wil, 540 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 541 mid, cid, tid, seq); 542 wil_rx_bar(wil, vif, cid, tid, seq); 543 } else { 544 /* print again all info. One can enable only this 545 * without overhead for printing every Rx frame 546 */ 547 wil_dbg_txrx(wil, 548 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 549 fc1, mid, cid, tid, seq); 550 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4, 551 (const void *)d, sizeof(*d), false); 552 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 553 skb->data, skb_headlen(skb), false); 554 } 555 kfree_skb(skb); 556 goto again; 557 } 558 559 if (unlikely(skb->len < ETH_HLEN + snaplen)) { 560 wil_err(wil, "Short frame, len = %d\n", skb->len); 561 stats->rx_short_frame++; 562 kfree_skb(skb); 563 goto again; 564 } 565 566 /* L4 IDENT is on when HW calculated checksum, check status 567 * and in case of error drop the packet 568 * higher stack layers will handle retransmission (if required) 569 */ 570 if (likely(d->dma.status & RX_DMA_STATUS_L4I)) { 571 /* L4 protocol identified, csum calculated */ 572 if (likely((d->dma.error & RX_DMA_ERROR_L4_ERR) == 0)) 573 skb->ip_summed = CHECKSUM_UNNECESSARY; 574 /* If HW reports bad checksum, let IP stack re-check it 575 * For example, HW don't understand Microsoft IP stack that 576 * mis-calculates TCP checksum - if it should be 0x0, 577 * it writes 0xffff in violation of RFC 1624 578 */ 579 else 580 stats->rx_csum_err++; 581 } 582 583 if (snaplen) { 584 /* Packet layout 585 * +-------+-------+---------+------------+------+ 586 * | SA(6) | DA(6) | SNAP(6) | ETHTYPE(2) | DATA | 587 * +-------+-------+---------+------------+------+ 588 * Need to remove SNAP, shifting SA and DA forward 589 */ 590 memmove(skb->data + snaplen, skb->data, 2 * ETH_ALEN); 591 skb_pull(skb, snaplen); 592 } 593 594 return skb; 595 } 596 597 /** 598 * allocate and fill up to @count buffers in rx ring 599 * buffers posted at @swtail 600 * Note: we have a single RX queue for servicing all VIFs, but we 601 * allocate skbs with headroom according to main interface only. This 602 * means it will not work with monitor interface together with other VIFs. 603 * Currently we only support monitor interface on its own without other VIFs, 604 * and we will need to fix this code once we add support. 605 */ 606 static int wil_rx_refill(struct wil6210_priv *wil, int count) 607 { 608 struct net_device *ndev = wil->main_ndev; 609 struct wil_ring *v = &wil->ring_rx; 610 u32 next_tail; 611 int rc = 0; 612 int headroom = ndev->type == ARPHRD_IEEE80211_RADIOTAP ? 613 WIL6210_RTAP_SIZE : 0; 614 615 for (; next_tail = wil_ring_next_tail(v), 616 (next_tail != v->swhead) && (count-- > 0); 617 v->swtail = next_tail) { 618 rc = wil_vring_alloc_skb(wil, v, v->swtail, headroom); 619 if (unlikely(rc)) { 620 wil_err_ratelimited(wil, "Error %d in rx refill[%d]\n", 621 rc, v->swtail); 622 break; 623 } 624 } 625 626 /* make sure all writes to descriptors (shared memory) are done before 627 * committing them to HW 628 */ 629 wmb(); 630 631 wil_w(wil, v->hwtail, v->swtail); 632 633 return rc; 634 } 635 636 /** 637 * reverse_memcmp - Compare two areas of memory, in reverse order 638 * @cs: One area of memory 639 * @ct: Another area of memory 640 * @count: The size of the area. 641 * 642 * Cut'n'paste from original memcmp (see lib/string.c) 643 * with minimal modifications 644 */ 645 int reverse_memcmp(const void *cs, const void *ct, size_t count) 646 { 647 const unsigned char *su1, *su2; 648 int res = 0; 649 650 for (su1 = cs + count - 1, su2 = ct + count - 1; count > 0; 651 --su1, --su2, count--) { 652 res = *su1 - *su2; 653 if (res) 654 break; 655 } 656 return res; 657 } 658 659 static int wil_rx_crypto_check(struct wil6210_priv *wil, struct sk_buff *skb) 660 { 661 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 662 int cid = wil_rxdesc_cid(d); 663 int tid = wil_rxdesc_tid(d); 664 int key_id = wil_rxdesc_key_id(d); 665 int mc = wil_rxdesc_mcast(d); 666 struct wil_sta_info *s = &wil->sta[cid]; 667 struct wil_tid_crypto_rx *c = mc ? &s->group_crypto_rx : 668 &s->tid_crypto_rx[tid]; 669 struct wil_tid_crypto_rx_single *cc = &c->key_id[key_id]; 670 const u8 *pn = (u8 *)&d->mac.pn_15_0; 671 672 if (!cc->key_set) { 673 wil_err_ratelimited(wil, 674 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 675 cid, tid, mc, key_id); 676 return -EINVAL; 677 } 678 679 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 680 wil_err_ratelimited(wil, 681 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 682 cid, tid, mc, key_id, pn, cc->pn); 683 return -EINVAL; 684 } 685 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 686 687 return 0; 688 } 689 690 static int wil_rx_error_check(struct wil6210_priv *wil, struct sk_buff *skb, 691 struct wil_net_stats *stats) 692 { 693 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 694 695 if ((d->dma.status & RX_DMA_STATUS_ERROR) && 696 (d->dma.error & RX_DMA_ERROR_MIC)) { 697 stats->rx_mic_error++; 698 wil_dbg_txrx(wil, "MIC error, dropping packet\n"); 699 return -EFAULT; 700 } 701 702 return 0; 703 } 704 705 static void wil_get_netif_rx_params(struct sk_buff *skb, int *cid, 706 int *security) 707 { 708 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 709 710 *cid = wil_rxdesc_cid(d); /* always 0..7, no need to check */ 711 *security = wil_rxdesc_security(d); 712 } 713 714 /* 715 * Pass Rx packet to the netif. Update statistics. 716 * Called in softirq context (NAPI poll). 717 */ 718 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev) 719 { 720 gro_result_t rc = GRO_NORMAL; 721 struct wil6210_vif *vif = ndev_to_vif(ndev); 722 struct wil6210_priv *wil = ndev_to_wil(ndev); 723 struct wireless_dev *wdev = vif_to_wdev(vif); 724 unsigned int len = skb->len; 725 int cid; 726 int security; 727 struct ethhdr *eth = (void *)skb->data; 728 /* here looking for DA, not A1, thus Rxdesc's 'mcast' indication 729 * is not suitable, need to look at data 730 */ 731 int mcast = is_multicast_ether_addr(eth->h_dest); 732 struct wil_net_stats *stats; 733 struct sk_buff *xmit_skb = NULL; 734 static const char * const gro_res_str[] = { 735 [GRO_MERGED] = "GRO_MERGED", 736 [GRO_MERGED_FREE] = "GRO_MERGED_FREE", 737 [GRO_HELD] = "GRO_HELD", 738 [GRO_NORMAL] = "GRO_NORMAL", 739 [GRO_DROP] = "GRO_DROP", 740 }; 741 742 wil->txrx_ops.get_netif_rx_params(skb, &cid, &security); 743 744 stats = &wil->sta[cid].stats; 745 746 skb_orphan(skb); 747 748 if (security && (wil->txrx_ops.rx_crypto_check(wil, skb) != 0)) { 749 rc = GRO_DROP; 750 dev_kfree_skb(skb); 751 stats->rx_replay++; 752 goto stats; 753 } 754 755 /* check errors reported by HW and update statistics */ 756 if (unlikely(wil->txrx_ops.rx_error_check(wil, skb, stats))) { 757 dev_kfree_skb(skb); 758 return; 759 } 760 761 if (wdev->iftype == NL80211_IFTYPE_STATION) { 762 if (mcast && ether_addr_equal(eth->h_source, ndev->dev_addr)) { 763 /* mcast packet looped back to us */ 764 rc = GRO_DROP; 765 dev_kfree_skb(skb); 766 goto stats; 767 } 768 } else if (wdev->iftype == NL80211_IFTYPE_AP && !vif->ap_isolate) { 769 if (mcast) { 770 /* send multicast frames both to higher layers in 771 * local net stack and back to the wireless medium 772 */ 773 xmit_skb = skb_copy(skb, GFP_ATOMIC); 774 } else { 775 int xmit_cid = wil_find_cid(wil, vif->mid, 776 eth->h_dest); 777 778 if (xmit_cid >= 0) { 779 /* The destination station is associated to 780 * this AP (in this VLAN), so send the frame 781 * directly to it and do not pass it to local 782 * net stack. 783 */ 784 xmit_skb = skb; 785 skb = NULL; 786 } 787 } 788 } 789 if (xmit_skb) { 790 /* Send to wireless media and increase priority by 256 to 791 * keep the received priority instead of reclassifying 792 * the frame (see cfg80211_classify8021d). 793 */ 794 xmit_skb->dev = ndev; 795 xmit_skb->priority += 256; 796 xmit_skb->protocol = htons(ETH_P_802_3); 797 skb_reset_network_header(xmit_skb); 798 skb_reset_mac_header(xmit_skb); 799 wil_dbg_txrx(wil, "Rx -> Tx %d bytes\n", len); 800 dev_queue_xmit(xmit_skb); 801 } 802 803 if (skb) { /* deliver to local stack */ 804 skb->protocol = eth_type_trans(skb, ndev); 805 skb->dev = ndev; 806 rc = napi_gro_receive(&wil->napi_rx, skb); 807 wil_dbg_txrx(wil, "Rx complete %d bytes => %s\n", 808 len, gro_res_str[rc]); 809 } 810 stats: 811 /* statistics. rc set to GRO_NORMAL for AP bridging */ 812 if (unlikely(rc == GRO_DROP)) { 813 ndev->stats.rx_dropped++; 814 stats->rx_dropped++; 815 wil_dbg_txrx(wil, "Rx drop %d bytes\n", len); 816 } else { 817 ndev->stats.rx_packets++; 818 stats->rx_packets++; 819 ndev->stats.rx_bytes += len; 820 stats->rx_bytes += len; 821 if (mcast) 822 ndev->stats.multicast++; 823 } 824 } 825 826 /** 827 * Proceed all completed skb's from Rx VRING 828 * 829 * Safe to call from NAPI poll, i.e. softirq with interrupts enabled 830 */ 831 void wil_rx_handle(struct wil6210_priv *wil, int *quota) 832 { 833 struct net_device *ndev = wil->main_ndev; 834 struct wireless_dev *wdev = ndev->ieee80211_ptr; 835 struct wil_ring *v = &wil->ring_rx; 836 struct sk_buff *skb; 837 838 if (unlikely(!v->va)) { 839 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 840 return; 841 } 842 wil_dbg_txrx(wil, "rx_handle\n"); 843 while ((*quota > 0) && (NULL != (skb = wil_vring_reap_rx(wil, v)))) { 844 (*quota)--; 845 846 /* monitor is currently supported on main interface only */ 847 if (wdev->iftype == NL80211_IFTYPE_MONITOR) { 848 skb->dev = ndev; 849 skb_reset_mac_header(skb); 850 skb->ip_summed = CHECKSUM_UNNECESSARY; 851 skb->pkt_type = PACKET_OTHERHOST; 852 skb->protocol = htons(ETH_P_802_2); 853 wil_netif_rx_any(skb, ndev); 854 } else { 855 wil_rx_reorder(wil, skb); 856 } 857 } 858 wil_rx_refill(wil, v->size); 859 } 860 861 static void wil_rx_buf_len_init(struct wil6210_priv *wil) 862 { 863 wil->rx_buf_len = rx_large_buf ? 864 WIL_MAX_ETH_MTU : TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD; 865 if (mtu_max > wil->rx_buf_len) { 866 /* do not allow RX buffers to be smaller than mtu_max, for 867 * backward compatibility (mtu_max parameter was also used 868 * to support receiving large packets) 869 */ 870 wil_info(wil, "Override RX buffer to mtu_max(%d)\n", mtu_max); 871 wil->rx_buf_len = mtu_max; 872 } 873 } 874 875 static int wil_rx_init(struct wil6210_priv *wil, uint order) 876 { 877 struct wil_ring *vring = &wil->ring_rx; 878 int rc; 879 880 wil_dbg_misc(wil, "rx_init\n"); 881 882 if (vring->va) { 883 wil_err(wil, "Rx ring already allocated\n"); 884 return -EINVAL; 885 } 886 887 wil_rx_buf_len_init(wil); 888 889 vring->size = 1 << order; 890 vring->is_rx = true; 891 rc = wil_vring_alloc(wil, vring); 892 if (rc) 893 return rc; 894 895 rc = wmi_rx_chain_add(wil, vring); 896 if (rc) 897 goto err_free; 898 899 rc = wil_rx_refill(wil, vring->size); 900 if (rc) 901 goto err_free; 902 903 return 0; 904 err_free: 905 wil_vring_free(wil, vring); 906 907 return rc; 908 } 909 910 static void wil_rx_fini(struct wil6210_priv *wil) 911 { 912 struct wil_ring *vring = &wil->ring_rx; 913 914 wil_dbg_misc(wil, "rx_fini\n"); 915 916 if (vring->va) 917 wil_vring_free(wil, vring); 918 } 919 920 static int wil_tx_desc_map(union wil_tx_desc *desc, dma_addr_t pa, 921 u32 len, int vring_index) 922 { 923 struct vring_tx_desc *d = &desc->legacy; 924 925 wil_desc_addr_set(&d->dma.addr, pa); 926 d->dma.ip_length = 0; 927 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 928 d->dma.b11 = 0/*14 | BIT(7)*/; 929 d->dma.error = 0; 930 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ 931 d->dma.length = cpu_to_le16((u16)len); 932 d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS); 933 d->mac.d[0] = 0; 934 d->mac.d[1] = 0; 935 d->mac.d[2] = 0; 936 d->mac.ucode_cmd = 0; 937 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi */ 938 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 939 (1 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 940 941 return 0; 942 } 943 944 void wil_tx_data_init(struct wil_ring_tx_data *txdata) 945 { 946 spin_lock_bh(&txdata->lock); 947 txdata->dot1x_open = 0; 948 txdata->enabled = 0; 949 txdata->idle = 0; 950 txdata->last_idle = 0; 951 txdata->begin = 0; 952 txdata->agg_wsize = 0; 953 txdata->agg_timeout = 0; 954 txdata->agg_amsdu = 0; 955 txdata->addba_in_progress = false; 956 txdata->mid = U8_MAX; 957 spin_unlock_bh(&txdata->lock); 958 } 959 960 static int wil_vring_init_tx(struct wil6210_vif *vif, int id, int size, 961 int cid, int tid) 962 { 963 struct wil6210_priv *wil = vif_to_wil(vif); 964 int rc; 965 struct wmi_vring_cfg_cmd cmd = { 966 .action = cpu_to_le32(WMI_VRING_CMD_ADD), 967 .vring_cfg = { 968 .tx_sw_ring = { 969 .max_mpdu_size = 970 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 971 .ring_size = cpu_to_le16(size), 972 }, 973 .ringid = id, 974 .cidxtid = mk_cidxtid(cid, tid), 975 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 976 .mac_ctrl = 0, 977 .to_resolution = 0, 978 .agg_max_wsize = 0, 979 .schd_params = { 980 .priority = cpu_to_le16(0), 981 .timeslot_us = cpu_to_le16(0xfff), 982 }, 983 }, 984 }; 985 struct { 986 struct wmi_cmd_hdr wmi; 987 struct wmi_vring_cfg_done_event cmd; 988 } __packed reply = { 989 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 990 }; 991 struct wil_ring *vring = &wil->ring_tx[id]; 992 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id]; 993 994 wil_dbg_misc(wil, "vring_init_tx: max_mpdu_size %d\n", 995 cmd.vring_cfg.tx_sw_ring.max_mpdu_size); 996 lockdep_assert_held(&wil->mutex); 997 998 if (vring->va) { 999 wil_err(wil, "Tx ring [%d] already allocated\n", id); 1000 rc = -EINVAL; 1001 goto out; 1002 } 1003 1004 wil_tx_data_init(txdata); 1005 vring->is_rx = false; 1006 vring->size = size; 1007 rc = wil_vring_alloc(wil, vring); 1008 if (rc) 1009 goto out; 1010 1011 wil->ring2cid_tid[id][0] = cid; 1012 wil->ring2cid_tid[id][1] = tid; 1013 1014 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1015 1016 if (!vif->privacy) 1017 txdata->dot1x_open = true; 1018 rc = wmi_call(wil, WMI_VRING_CFG_CMDID, vif->mid, &cmd, sizeof(cmd), 1019 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1020 if (rc) 1021 goto out_free; 1022 1023 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1024 wil_err(wil, "Tx config failed, status 0x%02x\n", 1025 reply.cmd.status); 1026 rc = -EINVAL; 1027 goto out_free; 1028 } 1029 1030 spin_lock_bh(&txdata->lock); 1031 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr); 1032 txdata->mid = vif->mid; 1033 txdata->enabled = 1; 1034 spin_unlock_bh(&txdata->lock); 1035 1036 if (txdata->dot1x_open && (agg_wsize >= 0)) 1037 wil_addba_tx_request(wil, id, agg_wsize); 1038 1039 return 0; 1040 out_free: 1041 spin_lock_bh(&txdata->lock); 1042 txdata->dot1x_open = false; 1043 txdata->enabled = 0; 1044 spin_unlock_bh(&txdata->lock); 1045 wil_vring_free(wil, vring); 1046 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID; 1047 wil->ring2cid_tid[id][1] = 0; 1048 1049 out: 1050 1051 return rc; 1052 } 1053 1054 static int wil_tx_vring_modify(struct wil6210_vif *vif, int ring_id, int cid, 1055 int tid) 1056 { 1057 struct wil6210_priv *wil = vif_to_wil(vif); 1058 int rc; 1059 struct wmi_vring_cfg_cmd cmd = { 1060 .action = cpu_to_le32(WMI_VRING_CMD_MODIFY), 1061 .vring_cfg = { 1062 .tx_sw_ring = { 1063 .max_mpdu_size = 1064 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 1065 .ring_size = 0, 1066 }, 1067 .ringid = ring_id, 1068 .cidxtid = mk_cidxtid(cid, tid), 1069 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 1070 .mac_ctrl = 0, 1071 .to_resolution = 0, 1072 .agg_max_wsize = 0, 1073 .schd_params = { 1074 .priority = cpu_to_le16(0), 1075 .timeslot_us = cpu_to_le16(0xfff), 1076 }, 1077 }, 1078 }; 1079 struct { 1080 struct wmi_cmd_hdr wmi; 1081 struct wmi_vring_cfg_done_event cmd; 1082 } __packed reply = { 1083 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 1084 }; 1085 struct wil_ring *vring = &wil->ring_tx[ring_id]; 1086 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1087 1088 wil_dbg_misc(wil, "vring_modify: ring %d cid %d tid %d\n", ring_id, 1089 cid, tid); 1090 lockdep_assert_held(&wil->mutex); 1091 1092 if (!vring->va) { 1093 wil_err(wil, "Tx ring [%d] not allocated\n", ring_id); 1094 return -EINVAL; 1095 } 1096 1097 if (wil->ring2cid_tid[ring_id][0] != cid || 1098 wil->ring2cid_tid[ring_id][1] != tid) { 1099 wil_err(wil, "ring info does not match cid=%u tid=%u\n", 1100 wil->ring2cid_tid[ring_id][0], 1101 wil->ring2cid_tid[ring_id][1]); 1102 } 1103 1104 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1105 1106 rc = wmi_call(wil, WMI_VRING_CFG_CMDID, vif->mid, &cmd, sizeof(cmd), 1107 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1108 if (rc) 1109 goto fail; 1110 1111 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1112 wil_err(wil, "Tx modify failed, status 0x%02x\n", 1113 reply.cmd.status); 1114 rc = -EINVAL; 1115 goto fail; 1116 } 1117 1118 /* set BA aggregation window size to 0 to force a new BA with the 1119 * new AP 1120 */ 1121 txdata->agg_wsize = 0; 1122 if (txdata->dot1x_open && agg_wsize >= 0) 1123 wil_addba_tx_request(wil, ring_id, agg_wsize); 1124 1125 return 0; 1126 fail: 1127 spin_lock_bh(&txdata->lock); 1128 txdata->dot1x_open = false; 1129 txdata->enabled = 0; 1130 spin_unlock_bh(&txdata->lock); 1131 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; 1132 wil->ring2cid_tid[ring_id][1] = 0; 1133 return rc; 1134 } 1135 1136 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size) 1137 { 1138 struct wil6210_priv *wil = vif_to_wil(vif); 1139 int rc; 1140 struct wmi_bcast_vring_cfg_cmd cmd = { 1141 .action = cpu_to_le32(WMI_VRING_CMD_ADD), 1142 .vring_cfg = { 1143 .tx_sw_ring = { 1144 .max_mpdu_size = 1145 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 1146 .ring_size = cpu_to_le16(size), 1147 }, 1148 .ringid = id, 1149 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 1150 }, 1151 }; 1152 struct { 1153 struct wmi_cmd_hdr wmi; 1154 struct wmi_vring_cfg_done_event cmd; 1155 } __packed reply = { 1156 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 1157 }; 1158 struct wil_ring *vring = &wil->ring_tx[id]; 1159 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id]; 1160 1161 wil_dbg_misc(wil, "vring_init_bcast: max_mpdu_size %d\n", 1162 cmd.vring_cfg.tx_sw_ring.max_mpdu_size); 1163 lockdep_assert_held(&wil->mutex); 1164 1165 if (vring->va) { 1166 wil_err(wil, "Tx ring [%d] already allocated\n", id); 1167 rc = -EINVAL; 1168 goto out; 1169 } 1170 1171 wil_tx_data_init(txdata); 1172 vring->is_rx = false; 1173 vring->size = size; 1174 rc = wil_vring_alloc(wil, vring); 1175 if (rc) 1176 goto out; 1177 1178 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID; /* CID */ 1179 wil->ring2cid_tid[id][1] = 0; /* TID */ 1180 1181 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1182 1183 if (!vif->privacy) 1184 txdata->dot1x_open = true; 1185 rc = wmi_call(wil, WMI_BCAST_VRING_CFG_CMDID, vif->mid, 1186 &cmd, sizeof(cmd), 1187 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1188 if (rc) 1189 goto out_free; 1190 1191 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1192 wil_err(wil, "Tx config failed, status 0x%02x\n", 1193 reply.cmd.status); 1194 rc = -EINVAL; 1195 goto out_free; 1196 } 1197 1198 spin_lock_bh(&txdata->lock); 1199 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr); 1200 txdata->mid = vif->mid; 1201 txdata->enabled = 1; 1202 spin_unlock_bh(&txdata->lock); 1203 1204 return 0; 1205 out_free: 1206 spin_lock_bh(&txdata->lock); 1207 txdata->enabled = 0; 1208 txdata->dot1x_open = false; 1209 spin_unlock_bh(&txdata->lock); 1210 wil_vring_free(wil, vring); 1211 out: 1212 1213 return rc; 1214 } 1215 1216 static struct wil_ring *wil_find_tx_ucast(struct wil6210_priv *wil, 1217 struct wil6210_vif *vif, 1218 struct sk_buff *skb) 1219 { 1220 int i; 1221 struct ethhdr *eth = (void *)skb->data; 1222 int cid = wil_find_cid(wil, vif->mid, eth->h_dest); 1223 int min_ring_id = wil_get_min_tx_ring_id(wil); 1224 1225 if (cid < 0) 1226 return NULL; 1227 1228 /* TODO: fix for multiple TID */ 1229 for (i = min_ring_id; i < ARRAY_SIZE(wil->ring2cid_tid); i++) { 1230 if (!wil->ring_tx_data[i].dot1x_open && 1231 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1232 continue; 1233 if (wil->ring2cid_tid[i][0] == cid) { 1234 struct wil_ring *v = &wil->ring_tx[i]; 1235 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i]; 1236 1237 wil_dbg_txrx(wil, "find_tx_ucast: (%pM) -> [%d]\n", 1238 eth->h_dest, i); 1239 if (v->va && txdata->enabled) { 1240 return v; 1241 } else { 1242 wil_dbg_txrx(wil, 1243 "find_tx_ucast: vring[%d] not valid\n", 1244 i); 1245 return NULL; 1246 } 1247 } 1248 } 1249 1250 return NULL; 1251 } 1252 1253 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1254 struct wil_ring *ring, struct sk_buff *skb); 1255 1256 static struct wil_ring *wil_find_tx_ring_sta(struct wil6210_priv *wil, 1257 struct wil6210_vif *vif, 1258 struct sk_buff *skb) 1259 { 1260 struct wil_ring *ring; 1261 int i; 1262 u8 cid; 1263 struct wil_ring_tx_data *txdata; 1264 int min_ring_id = wil_get_min_tx_ring_id(wil); 1265 1266 /* In the STA mode, it is expected to have only 1 VRING 1267 * for the AP we connected to. 1268 * find 1-st vring eligible for this skb and use it. 1269 */ 1270 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 1271 ring = &wil->ring_tx[i]; 1272 txdata = &wil->ring_tx_data[i]; 1273 if (!ring->va || !txdata->enabled || txdata->mid != vif->mid) 1274 continue; 1275 1276 cid = wil->ring2cid_tid[i][0]; 1277 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1278 continue; 1279 1280 if (!wil->ring_tx_data[i].dot1x_open && 1281 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1282 continue; 1283 1284 wil_dbg_txrx(wil, "Tx -> ring %d\n", i); 1285 1286 return ring; 1287 } 1288 1289 wil_dbg_txrx(wil, "Tx while no rings active?\n"); 1290 1291 return NULL; 1292 } 1293 1294 /* Use one of 2 strategies: 1295 * 1296 * 1. New (real broadcast): 1297 * use dedicated broadcast vring 1298 * 2. Old (pseudo-DMS): 1299 * Find 1-st vring and return it; 1300 * duplicate skb and send it to other active vrings; 1301 * in all cases override dest address to unicast peer's address 1302 * Use old strategy when new is not supported yet: 1303 * - for PBSS 1304 */ 1305 static struct wil_ring *wil_find_tx_bcast_1(struct wil6210_priv *wil, 1306 struct wil6210_vif *vif, 1307 struct sk_buff *skb) 1308 { 1309 struct wil_ring *v; 1310 struct wil_ring_tx_data *txdata; 1311 int i = vif->bcast_ring; 1312 1313 if (i < 0) 1314 return NULL; 1315 v = &wil->ring_tx[i]; 1316 txdata = &wil->ring_tx_data[i]; 1317 if (!v->va || !txdata->enabled) 1318 return NULL; 1319 if (!wil->ring_tx_data[i].dot1x_open && 1320 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1321 return NULL; 1322 1323 return v; 1324 } 1325 1326 static void wil_set_da_for_vring(struct wil6210_priv *wil, 1327 struct sk_buff *skb, int vring_index) 1328 { 1329 struct ethhdr *eth = (void *)skb->data; 1330 int cid = wil->ring2cid_tid[vring_index][0]; 1331 1332 ether_addr_copy(eth->h_dest, wil->sta[cid].addr); 1333 } 1334 1335 static struct wil_ring *wil_find_tx_bcast_2(struct wil6210_priv *wil, 1336 struct wil6210_vif *vif, 1337 struct sk_buff *skb) 1338 { 1339 struct wil_ring *v, *v2; 1340 struct sk_buff *skb2; 1341 int i; 1342 u8 cid; 1343 struct ethhdr *eth = (void *)skb->data; 1344 char *src = eth->h_source; 1345 struct wil_ring_tx_data *txdata, *txdata2; 1346 int min_ring_id = wil_get_min_tx_ring_id(wil); 1347 1348 /* find 1-st vring eligible for data */ 1349 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 1350 v = &wil->ring_tx[i]; 1351 txdata = &wil->ring_tx_data[i]; 1352 if (!v->va || !txdata->enabled || txdata->mid != vif->mid) 1353 continue; 1354 1355 cid = wil->ring2cid_tid[i][0]; 1356 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1357 continue; 1358 if (!wil->ring_tx_data[i].dot1x_open && 1359 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1360 continue; 1361 1362 /* don't Tx back to source when re-routing Rx->Tx at the AP */ 1363 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN)) 1364 continue; 1365 1366 goto found; 1367 } 1368 1369 wil_dbg_txrx(wil, "Tx while no vrings active?\n"); 1370 1371 return NULL; 1372 1373 found: 1374 wil_dbg_txrx(wil, "BCAST -> ring %d\n", i); 1375 wil_set_da_for_vring(wil, skb, i); 1376 1377 /* find other active vrings and duplicate skb for each */ 1378 for (i++; i < WIL6210_MAX_TX_RINGS; i++) { 1379 v2 = &wil->ring_tx[i]; 1380 txdata2 = &wil->ring_tx_data[i]; 1381 if (!v2->va || txdata2->mid != vif->mid) 1382 continue; 1383 cid = wil->ring2cid_tid[i][0]; 1384 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1385 continue; 1386 if (!wil->ring_tx_data[i].dot1x_open && 1387 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1388 continue; 1389 1390 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN)) 1391 continue; 1392 1393 skb2 = skb_copy(skb, GFP_ATOMIC); 1394 if (skb2) { 1395 wil_dbg_txrx(wil, "BCAST DUP -> ring %d\n", i); 1396 wil_set_da_for_vring(wil, skb2, i); 1397 wil_tx_ring(wil, vif, v2, skb2); 1398 /* successful call to wil_tx_ring takes skb2 ref */ 1399 dev_kfree_skb_any(skb2); 1400 } else { 1401 wil_err(wil, "skb_copy failed\n"); 1402 } 1403 } 1404 1405 return v; 1406 } 1407 1408 static inline 1409 void wil_tx_desc_set_nr_frags(struct vring_tx_desc *d, int nr_frags) 1410 { 1411 d->mac.d[2] |= (nr_frags << MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS); 1412 } 1413 1414 /** 1415 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1416 * @skb is used to obtain the protocol and headers length. 1417 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1418 * 2 - middle, 3 - last descriptor. 1419 */ 1420 1421 static void wil_tx_desc_offload_setup_tso(struct vring_tx_desc *d, 1422 struct sk_buff *skb, 1423 int tso_desc_type, bool is_ipv4, 1424 int tcp_hdr_len, int skb_net_hdr_len) 1425 { 1426 d->dma.b11 = ETH_HLEN; /* MAC header length */ 1427 d->dma.b11 |= is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1428 1429 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); 1430 /* L4 header len: TCP header length */ 1431 d->dma.d0 |= (tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1432 1433 /* Setup TSO: bit and desc type */ 1434 d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) | 1435 (tso_desc_type << DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS); 1436 d->dma.d0 |= (is_ipv4 << DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS); 1437 1438 d->dma.ip_length = skb_net_hdr_len; 1439 /* Enable TCP/UDP checksum */ 1440 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); 1441 /* Calculate pseudo-header */ 1442 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); 1443 } 1444 1445 /** 1446 * Sets the descriptor @d up for csum. The corresponding 1447 * @skb is used to obtain the protocol and headers length. 1448 * Returns the protocol: 0 - not TCP, 1 - TCPv4, 2 - TCPv6. 1449 * Note, if d==NULL, the function only returns the protocol result. 1450 * 1451 * It is very similar to previous wil_tx_desc_offload_setup_tso. This 1452 * is "if unrolling" to optimize the critical path. 1453 */ 1454 1455 static int wil_tx_desc_offload_setup(struct vring_tx_desc *d, 1456 struct sk_buff *skb){ 1457 int protocol; 1458 1459 if (skb->ip_summed != CHECKSUM_PARTIAL) 1460 return 0; 1461 1462 d->dma.b11 = ETH_HLEN; /* MAC header length */ 1463 1464 switch (skb->protocol) { 1465 case cpu_to_be16(ETH_P_IP): 1466 protocol = ip_hdr(skb)->protocol; 1467 d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS); 1468 break; 1469 case cpu_to_be16(ETH_P_IPV6): 1470 protocol = ipv6_hdr(skb)->nexthdr; 1471 break; 1472 default: 1473 return -EINVAL; 1474 } 1475 1476 switch (protocol) { 1477 case IPPROTO_TCP: 1478 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); 1479 /* L4 header len: TCP header length */ 1480 d->dma.d0 |= 1481 (tcp_hdrlen(skb) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1482 break; 1483 case IPPROTO_UDP: 1484 /* L4 header len: UDP header length */ 1485 d->dma.d0 |= 1486 (sizeof(struct udphdr) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1487 break; 1488 default: 1489 return -EINVAL; 1490 } 1491 1492 d->dma.ip_length = skb_network_header_len(skb); 1493 /* Enable TCP/UDP checksum */ 1494 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); 1495 /* Calculate pseudo-header */ 1496 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); 1497 1498 return 0; 1499 } 1500 1501 static inline void wil_tx_last_desc(struct vring_tx_desc *d) 1502 { 1503 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) | 1504 BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS) | 1505 BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); 1506 } 1507 1508 static inline void wil_set_tx_desc_last_tso(volatile struct vring_tx_desc *d) 1509 { 1510 d->dma.d0 |= wil_tso_type_lst << 1511 DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS; 1512 } 1513 1514 static int __wil_tx_vring_tso(struct wil6210_priv *wil, struct wil6210_vif *vif, 1515 struct wil_ring *vring, struct sk_buff *skb) 1516 { 1517 struct device *dev = wil_to_dev(wil); 1518 1519 /* point to descriptors in shared memory */ 1520 volatile struct vring_tx_desc *_desc = NULL, *_hdr_desc, 1521 *_first_desc = NULL; 1522 1523 /* pointers to shadow descriptors */ 1524 struct vring_tx_desc desc_mem, hdr_desc_mem, first_desc_mem, 1525 *d = &hdr_desc_mem, *hdr_desc = &hdr_desc_mem, 1526 *first_desc = &first_desc_mem; 1527 1528 /* pointer to shadow descriptors' context */ 1529 struct wil_ctx *hdr_ctx, *first_ctx = NULL; 1530 1531 int descs_used = 0; /* total number of used descriptors */ 1532 int sg_desc_cnt = 0; /* number of descriptors for current mss*/ 1533 1534 u32 swhead = vring->swhead; 1535 int used, avail = wil_ring_avail_tx(vring); 1536 int nr_frags = skb_shinfo(skb)->nr_frags; 1537 int min_desc_required = nr_frags + 1; 1538 int mss = skb_shinfo(skb)->gso_size; /* payload size w/o headers */ 1539 int f, len, hdrlen, headlen; 1540 int vring_index = vring - wil->ring_tx; 1541 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[vring_index]; 1542 uint i = swhead; 1543 dma_addr_t pa; 1544 const skb_frag_t *frag = NULL; 1545 int rem_data = mss; 1546 int lenmss; 1547 int hdr_compensation_need = true; 1548 int desc_tso_type = wil_tso_type_first; 1549 bool is_ipv4; 1550 int tcp_hdr_len; 1551 int skb_net_hdr_len; 1552 int gso_type; 1553 int rc = -EINVAL; 1554 1555 wil_dbg_txrx(wil, "tx_vring_tso: %d bytes to vring %d\n", skb->len, 1556 vring_index); 1557 1558 if (unlikely(!txdata->enabled)) 1559 return -EINVAL; 1560 1561 /* A typical page 4K is 3-4 payloads, we assume each fragment 1562 * is a full payload, that's how min_desc_required has been 1563 * calculated. In real we might need more or less descriptors, 1564 * this is the initial check only. 1565 */ 1566 if (unlikely(avail < min_desc_required)) { 1567 wil_err_ratelimited(wil, 1568 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1569 vring_index, min_desc_required); 1570 return -ENOMEM; 1571 } 1572 1573 /* Header Length = MAC header len + IP header len + TCP header len*/ 1574 hdrlen = ETH_HLEN + 1575 (int)skb_network_header_len(skb) + 1576 tcp_hdrlen(skb); 1577 1578 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1579 switch (gso_type) { 1580 case SKB_GSO_TCPV4: 1581 /* TCP v4, zero out the IP length and IPv4 checksum fields 1582 * as required by the offloading doc 1583 */ 1584 ip_hdr(skb)->tot_len = 0; 1585 ip_hdr(skb)->check = 0; 1586 is_ipv4 = true; 1587 break; 1588 case SKB_GSO_TCPV6: 1589 /* TCP v6, zero out the payload length */ 1590 ipv6_hdr(skb)->payload_len = 0; 1591 is_ipv4 = false; 1592 break; 1593 default: 1594 /* other than TCPv4 or TCPv6 types are not supported for TSO. 1595 * It is also illegal for both to be set simultaneously 1596 */ 1597 return -EINVAL; 1598 } 1599 1600 if (skb->ip_summed != CHECKSUM_PARTIAL) 1601 return -EINVAL; 1602 1603 /* tcp header length and skb network header length are fixed for all 1604 * packet's descriptors - read then once here 1605 */ 1606 tcp_hdr_len = tcp_hdrlen(skb); 1607 skb_net_hdr_len = skb_network_header_len(skb); 1608 1609 _hdr_desc = &vring->va[i].tx.legacy; 1610 1611 pa = dma_map_single(dev, skb->data, hdrlen, DMA_TO_DEVICE); 1612 if (unlikely(dma_mapping_error(dev, pa))) { 1613 wil_err(wil, "TSO: Skb head DMA map error\n"); 1614 goto err_exit; 1615 } 1616 1617 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)hdr_desc, pa, 1618 hdrlen, vring_index); 1619 wil_tx_desc_offload_setup_tso(hdr_desc, skb, wil_tso_type_hdr, is_ipv4, 1620 tcp_hdr_len, skb_net_hdr_len); 1621 wil_tx_last_desc(hdr_desc); 1622 1623 vring->ctx[i].mapped_as = wil_mapped_as_single; 1624 hdr_ctx = &vring->ctx[i]; 1625 1626 descs_used++; 1627 headlen = skb_headlen(skb) - hdrlen; 1628 1629 for (f = headlen ? -1 : 0; f < nr_frags; f++) { 1630 if (headlen) { 1631 len = headlen; 1632 wil_dbg_txrx(wil, "TSO: process skb head, len %u\n", 1633 len); 1634 } else { 1635 frag = &skb_shinfo(skb)->frags[f]; 1636 len = frag->size; 1637 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u\n", f, len); 1638 } 1639 1640 while (len) { 1641 wil_dbg_txrx(wil, 1642 "TSO: len %d, rem_data %d, descs_used %d\n", 1643 len, rem_data, descs_used); 1644 1645 if (descs_used == avail) { 1646 wil_err_ratelimited(wil, "TSO: ring overflow\n"); 1647 rc = -ENOMEM; 1648 goto mem_error; 1649 } 1650 1651 lenmss = min_t(int, rem_data, len); 1652 i = (swhead + descs_used) % vring->size; 1653 wil_dbg_txrx(wil, "TSO: lenmss %d, i %d\n", lenmss, i); 1654 1655 if (!headlen) { 1656 pa = skb_frag_dma_map(dev, frag, 1657 frag->size - len, lenmss, 1658 DMA_TO_DEVICE); 1659 vring->ctx[i].mapped_as = wil_mapped_as_page; 1660 } else { 1661 pa = dma_map_single(dev, 1662 skb->data + 1663 skb_headlen(skb) - headlen, 1664 lenmss, 1665 DMA_TO_DEVICE); 1666 vring->ctx[i].mapped_as = wil_mapped_as_single; 1667 headlen -= lenmss; 1668 } 1669 1670 if (unlikely(dma_mapping_error(dev, pa))) { 1671 wil_err(wil, "TSO: DMA map page error\n"); 1672 goto mem_error; 1673 } 1674 1675 _desc = &vring->va[i].tx.legacy; 1676 1677 if (!_first_desc) { 1678 _first_desc = _desc; 1679 first_ctx = &vring->ctx[i]; 1680 d = first_desc; 1681 } else { 1682 d = &desc_mem; 1683 } 1684 1685 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, 1686 pa, lenmss, vring_index); 1687 wil_tx_desc_offload_setup_tso(d, skb, desc_tso_type, 1688 is_ipv4, tcp_hdr_len, 1689 skb_net_hdr_len); 1690 1691 /* use tso_type_first only once */ 1692 desc_tso_type = wil_tso_type_mid; 1693 1694 descs_used++; /* desc used so far */ 1695 sg_desc_cnt++; /* desc used for this segment */ 1696 len -= lenmss; 1697 rem_data -= lenmss; 1698 1699 wil_dbg_txrx(wil, 1700 "TSO: len %d, rem_data %d, descs_used %d, sg_desc_cnt %d,\n", 1701 len, rem_data, descs_used, sg_desc_cnt); 1702 1703 /* Close the segment if reached mss size or last frag*/ 1704 if (rem_data == 0 || (f == nr_frags - 1 && len == 0)) { 1705 if (hdr_compensation_need) { 1706 /* first segment include hdr desc for 1707 * release 1708 */ 1709 hdr_ctx->nr_frags = sg_desc_cnt; 1710 wil_tx_desc_set_nr_frags(first_desc, 1711 sg_desc_cnt + 1712 1); 1713 hdr_compensation_need = false; 1714 } else { 1715 wil_tx_desc_set_nr_frags(first_desc, 1716 sg_desc_cnt); 1717 } 1718 first_ctx->nr_frags = sg_desc_cnt - 1; 1719 1720 wil_tx_last_desc(d); 1721 1722 /* first descriptor may also be the last 1723 * for this mss - make sure not to copy 1724 * it twice 1725 */ 1726 if (first_desc != d) 1727 *_first_desc = *first_desc; 1728 1729 /*last descriptor will be copied at the end 1730 * of this TS processing 1731 */ 1732 if (f < nr_frags - 1 || len > 0) 1733 *_desc = *d; 1734 1735 rem_data = mss; 1736 _first_desc = NULL; 1737 sg_desc_cnt = 0; 1738 } else if (first_desc != d) /* update mid descriptor */ 1739 *_desc = *d; 1740 } 1741 } 1742 1743 /* first descriptor may also be the last. 1744 * in this case d pointer is invalid 1745 */ 1746 if (_first_desc == _desc) 1747 d = first_desc; 1748 1749 /* Last data descriptor */ 1750 wil_set_tx_desc_last_tso(d); 1751 *_desc = *d; 1752 1753 /* Fill the total number of descriptors in first desc (hdr)*/ 1754 wil_tx_desc_set_nr_frags(hdr_desc, descs_used); 1755 *_hdr_desc = *hdr_desc; 1756 1757 /* hold reference to skb 1758 * to prevent skb release before accounting 1759 * in case of immediate "tx done" 1760 */ 1761 vring->ctx[i].skb = skb_get(skb); 1762 1763 /* performance monitoring */ 1764 used = wil_ring_used_tx(vring); 1765 if (wil_val_in_range(wil->ring_idle_trsh, 1766 used, used + descs_used)) { 1767 txdata->idle += get_cycles() - txdata->last_idle; 1768 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1769 vring_index, used, used + descs_used); 1770 } 1771 1772 /* Make sure to advance the head only after descriptor update is done. 1773 * This will prevent a race condition where the completion thread 1774 * will see the DU bit set from previous run and will handle the 1775 * skb before it was completed. 1776 */ 1777 wmb(); 1778 1779 /* advance swhead */ 1780 wil_ring_advance_head(vring, descs_used); 1781 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, vring->swhead); 1782 1783 /* make sure all writes to descriptors (shared memory) are done before 1784 * committing them to HW 1785 */ 1786 wmb(); 1787 1788 if (wil->tx_latency) 1789 *(ktime_t *)&skb->cb = ktime_get(); 1790 else 1791 memset(skb->cb, 0, sizeof(ktime_t)); 1792 1793 wil_w(wil, vring->hwtail, vring->swhead); 1794 return 0; 1795 1796 mem_error: 1797 while (descs_used > 0) { 1798 struct wil_ctx *ctx; 1799 1800 i = (swhead + descs_used - 1) % vring->size; 1801 d = (struct vring_tx_desc *)&vring->va[i].tx.legacy; 1802 _desc = &vring->va[i].tx.legacy; 1803 *d = *_desc; 1804 _desc->dma.status = TX_DMA_STATUS_DU; 1805 ctx = &vring->ctx[i]; 1806 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx); 1807 memset(ctx, 0, sizeof(*ctx)); 1808 descs_used--; 1809 } 1810 err_exit: 1811 return rc; 1812 } 1813 1814 static int __wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1815 struct wil_ring *ring, struct sk_buff *skb) 1816 { 1817 struct device *dev = wil_to_dev(wil); 1818 struct vring_tx_desc dd, *d = ⅆ 1819 volatile struct vring_tx_desc *_d; 1820 u32 swhead = ring->swhead; 1821 int avail = wil_ring_avail_tx(ring); 1822 int nr_frags = skb_shinfo(skb)->nr_frags; 1823 uint f = 0; 1824 int ring_index = ring - wil->ring_tx; 1825 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1826 uint i = swhead; 1827 dma_addr_t pa; 1828 int used; 1829 bool mcast = (ring_index == vif->bcast_ring); 1830 uint len = skb_headlen(skb); 1831 1832 wil_dbg_txrx(wil, "tx_ring: %d bytes to ring %d, nr_frags %d\n", 1833 skb->len, ring_index, nr_frags); 1834 1835 if (unlikely(!txdata->enabled)) 1836 return -EINVAL; 1837 1838 if (unlikely(avail < 1 + nr_frags)) { 1839 wil_err_ratelimited(wil, 1840 "Tx ring[%2d] full. No space for %d fragments\n", 1841 ring_index, 1 + nr_frags); 1842 return -ENOMEM; 1843 } 1844 _d = &ring->va[i].tx.legacy; 1845 1846 pa = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1847 1848 wil_dbg_txrx(wil, "Tx[%2d] skb %d bytes 0x%p -> %pad\n", ring_index, 1849 skb_headlen(skb), skb->data, &pa); 1850 wil_hex_dump_txrx("Tx ", DUMP_PREFIX_OFFSET, 16, 1, 1851 skb->data, skb_headlen(skb), false); 1852 1853 if (unlikely(dma_mapping_error(dev, pa))) 1854 return -EINVAL; 1855 ring->ctx[i].mapped_as = wil_mapped_as_single; 1856 /* 1-st segment */ 1857 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, len, 1858 ring_index); 1859 if (unlikely(mcast)) { 1860 d->mac.d[0] |= BIT(MAC_CFG_DESC_TX_0_MCS_EN_POS); /* MCS 0 */ 1861 if (unlikely(len > WIL_BCAST_MCS0_LIMIT)) /* set MCS 1 */ 1862 d->mac.d[0] |= (1 << MAC_CFG_DESC_TX_0_MCS_INDEX_POS); 1863 } 1864 /* Process TCP/UDP checksum offloading */ 1865 if (unlikely(wil_tx_desc_offload_setup(d, skb))) { 1866 wil_err(wil, "Tx[%2d] Failed to set cksum, drop packet\n", 1867 ring_index); 1868 goto dma_error; 1869 } 1870 1871 ring->ctx[i].nr_frags = nr_frags; 1872 wil_tx_desc_set_nr_frags(d, nr_frags + 1); 1873 1874 /* middle segments */ 1875 for (; f < nr_frags; f++) { 1876 const struct skb_frag_struct *frag = 1877 &skb_shinfo(skb)->frags[f]; 1878 int len = skb_frag_size(frag); 1879 1880 *_d = *d; 1881 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i); 1882 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1883 (const void *)d, sizeof(*d), false); 1884 i = (swhead + f + 1) % ring->size; 1885 _d = &ring->va[i].tx.legacy; 1886 pa = skb_frag_dma_map(dev, frag, 0, skb_frag_size(frag), 1887 DMA_TO_DEVICE); 1888 if (unlikely(dma_mapping_error(dev, pa))) { 1889 wil_err(wil, "Tx[%2d] failed to map fragment\n", 1890 ring_index); 1891 goto dma_error; 1892 } 1893 ring->ctx[i].mapped_as = wil_mapped_as_page; 1894 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, 1895 pa, len, ring_index); 1896 /* no need to check return code - 1897 * if it succeeded for 1-st descriptor, 1898 * it will succeed here too 1899 */ 1900 wil_tx_desc_offload_setup(d, skb); 1901 } 1902 /* for the last seg only */ 1903 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS); 1904 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS); 1905 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); 1906 *_d = *d; 1907 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i); 1908 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1909 (const void *)d, sizeof(*d), false); 1910 1911 /* hold reference to skb 1912 * to prevent skb release before accounting 1913 * in case of immediate "tx done" 1914 */ 1915 ring->ctx[i].skb = skb_get(skb); 1916 1917 /* performance monitoring */ 1918 used = wil_ring_used_tx(ring); 1919 if (wil_val_in_range(wil->ring_idle_trsh, 1920 used, used + nr_frags + 1)) { 1921 txdata->idle += get_cycles() - txdata->last_idle; 1922 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1923 ring_index, used, used + nr_frags + 1); 1924 } 1925 1926 /* Make sure to advance the head only after descriptor update is done. 1927 * This will prevent a race condition where the completion thread 1928 * will see the DU bit set from previous run and will handle the 1929 * skb before it was completed. 1930 */ 1931 wmb(); 1932 1933 /* advance swhead */ 1934 wil_ring_advance_head(ring, nr_frags + 1); 1935 wil_dbg_txrx(wil, "Tx[%2d] swhead %d -> %d\n", ring_index, swhead, 1936 ring->swhead); 1937 trace_wil6210_tx(ring_index, swhead, skb->len, nr_frags); 1938 1939 /* make sure all writes to descriptors (shared memory) are done before 1940 * committing them to HW 1941 */ 1942 wmb(); 1943 1944 if (wil->tx_latency) 1945 *(ktime_t *)&skb->cb = ktime_get(); 1946 else 1947 memset(skb->cb, 0, sizeof(ktime_t)); 1948 1949 wil_w(wil, ring->hwtail, ring->swhead); 1950 1951 return 0; 1952 dma_error: 1953 /* unmap what we have mapped */ 1954 nr_frags = f + 1; /* frags mapped + one for skb head */ 1955 for (f = 0; f < nr_frags; f++) { 1956 struct wil_ctx *ctx; 1957 1958 i = (swhead + f) % ring->size; 1959 ctx = &ring->ctx[i]; 1960 _d = &ring->va[i].tx.legacy; 1961 *d = *_d; 1962 _d->dma.status = TX_DMA_STATUS_DU; 1963 wil->txrx_ops.tx_desc_unmap(dev, 1964 (union wil_tx_desc *)d, 1965 ctx); 1966 1967 memset(ctx, 0, sizeof(*ctx)); 1968 } 1969 1970 return -EINVAL; 1971 } 1972 1973 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1974 struct wil_ring *ring, struct sk_buff *skb) 1975 { 1976 int ring_index = ring - wil->ring_tx; 1977 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1978 int rc; 1979 1980 spin_lock(&txdata->lock); 1981 1982 if (test_bit(wil_status_suspending, wil->status) || 1983 test_bit(wil_status_suspended, wil->status) || 1984 test_bit(wil_status_resuming, wil->status)) { 1985 wil_dbg_txrx(wil, 1986 "suspend/resume in progress. drop packet\n"); 1987 spin_unlock(&txdata->lock); 1988 return -EINVAL; 1989 } 1990 1991 rc = (skb_is_gso(skb) ? wil->txrx_ops.tx_ring_tso : __wil_tx_ring) 1992 (wil, vif, ring, skb); 1993 1994 spin_unlock(&txdata->lock); 1995 1996 return rc; 1997 } 1998 1999 /** 2000 * Check status of tx vrings and stop/wake net queues if needed 2001 * It will start/stop net queues of a specific VIF net_device. 2002 * 2003 * This function does one of two checks: 2004 * In case check_stop is true, will check if net queues need to be stopped. If 2005 * the conditions for stopping are met, netif_tx_stop_all_queues() is called. 2006 * In case check_stop is false, will check if net queues need to be waked. If 2007 * the conditions for waking are met, netif_tx_wake_all_queues() is called. 2008 * vring is the vring which is currently being modified by either adding 2009 * descriptors (tx) into it or removing descriptors (tx complete) from it. Can 2010 * be null when irrelevant (e.g. connect/disconnect events). 2011 * 2012 * The implementation is to stop net queues if modified vring has low 2013 * descriptor availability. Wake if all vrings are not in low descriptor 2014 * availability and modified vring has high descriptor availability. 2015 */ 2016 static inline void __wil_update_net_queues(struct wil6210_priv *wil, 2017 struct wil6210_vif *vif, 2018 struct wil_ring *ring, 2019 bool check_stop) 2020 { 2021 int i; 2022 int min_ring_id = wil_get_min_tx_ring_id(wil); 2023 2024 if (unlikely(!vif)) 2025 return; 2026 2027 if (ring) 2028 wil_dbg_txrx(wil, "vring %d, mid %d, check_stop=%d, stopped=%d", 2029 (int)(ring - wil->ring_tx), vif->mid, check_stop, 2030 vif->net_queue_stopped); 2031 else 2032 wil_dbg_txrx(wil, "check_stop=%d, mid=%d, stopped=%d", 2033 check_stop, vif->mid, vif->net_queue_stopped); 2034 2035 if (check_stop == vif->net_queue_stopped) 2036 /* net queues already in desired state */ 2037 return; 2038 2039 if (check_stop) { 2040 if (!ring || unlikely(wil_ring_avail_low(ring))) { 2041 /* not enough room in the vring */ 2042 netif_tx_stop_all_queues(vif_to_ndev(vif)); 2043 vif->net_queue_stopped = true; 2044 wil_dbg_txrx(wil, "netif_tx_stop called\n"); 2045 } 2046 return; 2047 } 2048 2049 /* Do not wake the queues in suspend flow */ 2050 if (test_bit(wil_status_suspending, wil->status) || 2051 test_bit(wil_status_suspended, wil->status)) 2052 return; 2053 2054 /* check wake */ 2055 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 2056 struct wil_ring *cur_ring = &wil->ring_tx[i]; 2057 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i]; 2058 2059 if (txdata->mid != vif->mid || !cur_ring->va || 2060 !txdata->enabled || cur_ring == ring) 2061 continue; 2062 2063 if (wil_ring_avail_low(cur_ring)) { 2064 wil_dbg_txrx(wil, "ring %d full, can't wake\n", 2065 (int)(cur_ring - wil->ring_tx)); 2066 return; 2067 } 2068 } 2069 2070 if (!ring || wil_ring_avail_high(ring)) { 2071 /* enough room in the ring */ 2072 wil_dbg_txrx(wil, "calling netif_tx_wake\n"); 2073 netif_tx_wake_all_queues(vif_to_ndev(vif)); 2074 vif->net_queue_stopped = false; 2075 } 2076 } 2077 2078 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 2079 struct wil_ring *ring, bool check_stop) 2080 { 2081 spin_lock(&wil->net_queue_lock); 2082 __wil_update_net_queues(wil, vif, ring, check_stop); 2083 spin_unlock(&wil->net_queue_lock); 2084 } 2085 2086 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 2087 struct wil_ring *ring, bool check_stop) 2088 { 2089 spin_lock_bh(&wil->net_queue_lock); 2090 __wil_update_net_queues(wil, vif, ring, check_stop); 2091 spin_unlock_bh(&wil->net_queue_lock); 2092 } 2093 2094 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2095 { 2096 struct wil6210_vif *vif = ndev_to_vif(ndev); 2097 struct wil6210_priv *wil = vif_to_wil(vif); 2098 struct ethhdr *eth = (void *)skb->data; 2099 bool bcast = is_multicast_ether_addr(eth->h_dest); 2100 struct wil_ring *ring; 2101 static bool pr_once_fw; 2102 int rc; 2103 2104 wil_dbg_txrx(wil, "start_xmit\n"); 2105 if (unlikely(!test_bit(wil_status_fwready, wil->status))) { 2106 if (!pr_once_fw) { 2107 wil_err(wil, "FW not ready\n"); 2108 pr_once_fw = true; 2109 } 2110 goto drop; 2111 } 2112 if (unlikely(!test_bit(wil_vif_fwconnected, vif->status))) { 2113 wil_dbg_ratelimited(wil, 2114 "VIF not connected, packet dropped\n"); 2115 goto drop; 2116 } 2117 if (unlikely(vif->wdev.iftype == NL80211_IFTYPE_MONITOR)) { 2118 wil_err(wil, "Xmit in monitor mode not supported\n"); 2119 goto drop; 2120 } 2121 pr_once_fw = false; 2122 2123 /* find vring */ 2124 if (vif->wdev.iftype == NL80211_IFTYPE_STATION && !vif->pbss) { 2125 /* in STA mode (ESS), all to same VRING (to AP) */ 2126 ring = wil_find_tx_ring_sta(wil, vif, skb); 2127 } else if (bcast) { 2128 if (vif->pbss) 2129 /* in pbss, no bcast VRING - duplicate skb in 2130 * all stations VRINGs 2131 */ 2132 ring = wil_find_tx_bcast_2(wil, vif, skb); 2133 else if (vif->wdev.iftype == NL80211_IFTYPE_AP) 2134 /* AP has a dedicated bcast VRING */ 2135 ring = wil_find_tx_bcast_1(wil, vif, skb); 2136 else 2137 /* unexpected combination, fallback to duplicating 2138 * the skb in all stations VRINGs 2139 */ 2140 ring = wil_find_tx_bcast_2(wil, vif, skb); 2141 } else { 2142 /* unicast, find specific VRING by dest. address */ 2143 ring = wil_find_tx_ucast(wil, vif, skb); 2144 } 2145 if (unlikely(!ring)) { 2146 wil_dbg_txrx(wil, "No Tx RING found for %pM\n", eth->h_dest); 2147 goto drop; 2148 } 2149 /* set up vring entry */ 2150 rc = wil_tx_ring(wil, vif, ring, skb); 2151 2152 switch (rc) { 2153 case 0: 2154 /* shall we stop net queues? */ 2155 wil_update_net_queues_bh(wil, vif, ring, true); 2156 /* statistics will be updated on the tx_complete */ 2157 dev_kfree_skb_any(skb); 2158 return NETDEV_TX_OK; 2159 case -ENOMEM: 2160 return NETDEV_TX_BUSY; 2161 default: 2162 break; /* goto drop; */ 2163 } 2164 drop: 2165 ndev->stats.tx_dropped++; 2166 dev_kfree_skb_any(skb); 2167 2168 return NET_XMIT_DROP; 2169 } 2170 2171 void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb, 2172 struct wil_sta_info *sta) 2173 { 2174 int skb_time_us; 2175 int bin; 2176 2177 if (!wil->tx_latency) 2178 return; 2179 2180 if (ktime_to_ms(*(ktime_t *)&skb->cb) == 0) 2181 return; 2182 2183 skb_time_us = ktime_us_delta(ktime_get(), *(ktime_t *)&skb->cb); 2184 bin = skb_time_us / wil->tx_latency_res; 2185 bin = min_t(int, bin, WIL_NUM_LATENCY_BINS - 1); 2186 2187 wil_dbg_txrx(wil, "skb time %dus => bin %d\n", skb_time_us, bin); 2188 sta->tx_latency_bins[bin]++; 2189 sta->stats.tx_latency_total_us += skb_time_us; 2190 if (skb_time_us < sta->stats.tx_latency_min_us) 2191 sta->stats.tx_latency_min_us = skb_time_us; 2192 if (skb_time_us > sta->stats.tx_latency_max_us) 2193 sta->stats.tx_latency_max_us = skb_time_us; 2194 } 2195 2196 /** 2197 * Clean up transmitted skb's from the Tx VRING 2198 * 2199 * Return number of descriptors cleared 2200 * 2201 * Safe to call from IRQ 2202 */ 2203 int wil_tx_complete(struct wil6210_vif *vif, int ringid) 2204 { 2205 struct wil6210_priv *wil = vif_to_wil(vif); 2206 struct net_device *ndev = vif_to_ndev(vif); 2207 struct device *dev = wil_to_dev(wil); 2208 struct wil_ring *vring = &wil->ring_tx[ringid]; 2209 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ringid]; 2210 int done = 0; 2211 int cid = wil->ring2cid_tid[ringid][0]; 2212 struct wil_net_stats *stats = NULL; 2213 volatile struct vring_tx_desc *_d; 2214 int used_before_complete; 2215 int used_new; 2216 2217 if (unlikely(!vring->va)) { 2218 wil_err(wil, "Tx irq[%d]: vring not initialized\n", ringid); 2219 return 0; 2220 } 2221 2222 if (unlikely(!txdata->enabled)) { 2223 wil_info(wil, "Tx irq[%d]: vring disabled\n", ringid); 2224 return 0; 2225 } 2226 2227 wil_dbg_txrx(wil, "tx_complete: (%d)\n", ringid); 2228 2229 used_before_complete = wil_ring_used_tx(vring); 2230 2231 if (cid < WIL6210_MAX_CID) 2232 stats = &wil->sta[cid].stats; 2233 2234 while (!wil_ring_is_empty(vring)) { 2235 int new_swtail; 2236 struct wil_ctx *ctx = &vring->ctx[vring->swtail]; 2237 /** 2238 * For the fragmented skb, HW will set DU bit only for the 2239 * last fragment. look for it. 2240 * In TSO the first DU will include hdr desc 2241 */ 2242 int lf = (vring->swtail + ctx->nr_frags) % vring->size; 2243 /* TODO: check we are not past head */ 2244 2245 _d = &vring->va[lf].tx.legacy; 2246 if (unlikely(!(_d->dma.status & TX_DMA_STATUS_DU))) 2247 break; 2248 2249 new_swtail = (lf + 1) % vring->size; 2250 while (vring->swtail != new_swtail) { 2251 struct vring_tx_desc dd, *d = ⅆ 2252 u16 dmalen; 2253 struct sk_buff *skb; 2254 2255 ctx = &vring->ctx[vring->swtail]; 2256 skb = ctx->skb; 2257 _d = &vring->va[vring->swtail].tx.legacy; 2258 2259 *d = *_d; 2260 2261 dmalen = le16_to_cpu(d->dma.length); 2262 trace_wil6210_tx_done(ringid, vring->swtail, dmalen, 2263 d->dma.error); 2264 wil_dbg_txrx(wil, 2265 "TxC[%2d][%3d] : %d bytes, status 0x%02x err 0x%02x\n", 2266 ringid, vring->swtail, dmalen, 2267 d->dma.status, d->dma.error); 2268 wil_hex_dump_txrx("TxCD ", DUMP_PREFIX_NONE, 32, 4, 2269 (const void *)d, sizeof(*d), false); 2270 2271 wil->txrx_ops.tx_desc_unmap(dev, 2272 (union wil_tx_desc *)d, 2273 ctx); 2274 2275 if (skb) { 2276 if (likely(d->dma.error == 0)) { 2277 ndev->stats.tx_packets++; 2278 ndev->stats.tx_bytes += skb->len; 2279 if (stats) { 2280 stats->tx_packets++; 2281 stats->tx_bytes += skb->len; 2282 2283 wil_tx_latency_calc(wil, skb, 2284 &wil->sta[cid]); 2285 } 2286 } else { 2287 ndev->stats.tx_errors++; 2288 if (stats) 2289 stats->tx_errors++; 2290 } 2291 wil_consume_skb(skb, d->dma.error == 0); 2292 } 2293 memset(ctx, 0, sizeof(*ctx)); 2294 /* Make sure the ctx is zeroed before updating the tail 2295 * to prevent a case where wil_tx_ring will see 2296 * this descriptor as used and handle it before ctx zero 2297 * is completed. 2298 */ 2299 wmb(); 2300 /* There is no need to touch HW descriptor: 2301 * - ststus bit TX_DMA_STATUS_DU is set by design, 2302 * so hardware will not try to process this desc., 2303 * - rest of descriptor will be initialized on Tx. 2304 */ 2305 vring->swtail = wil_ring_next_tail(vring); 2306 done++; 2307 } 2308 } 2309 2310 /* performance monitoring */ 2311 used_new = wil_ring_used_tx(vring); 2312 if (wil_val_in_range(wil->ring_idle_trsh, 2313 used_new, used_before_complete)) { 2314 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 2315 ringid, used_before_complete, used_new); 2316 txdata->last_idle = get_cycles(); 2317 } 2318 2319 /* shall we wake net queues? */ 2320 if (done) 2321 wil_update_net_queues(wil, vif, vring, false); 2322 2323 return done; 2324 } 2325 2326 static inline int wil_tx_init(struct wil6210_priv *wil) 2327 { 2328 return 0; 2329 } 2330 2331 static inline void wil_tx_fini(struct wil6210_priv *wil) {} 2332 2333 static void wil_get_reorder_params(struct wil6210_priv *wil, 2334 struct sk_buff *skb, int *tid, int *cid, 2335 int *mid, u16 *seq, int *mcast, int *retry) 2336 { 2337 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 2338 2339 *tid = wil_rxdesc_tid(d); 2340 *cid = wil_rxdesc_cid(d); 2341 *mid = wil_rxdesc_mid(d); 2342 *seq = wil_rxdesc_seq(d); 2343 *mcast = wil_rxdesc_mcast(d); 2344 *retry = wil_rxdesc_retry(d); 2345 } 2346 2347 void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil) 2348 { 2349 wil->txrx_ops.configure_interrupt_moderation = 2350 wil_configure_interrupt_moderation; 2351 /* TX ops */ 2352 wil->txrx_ops.tx_desc_map = wil_tx_desc_map; 2353 wil->txrx_ops.tx_desc_unmap = wil_txdesc_unmap; 2354 wil->txrx_ops.tx_ring_tso = __wil_tx_vring_tso; 2355 wil->txrx_ops.ring_init_tx = wil_vring_init_tx; 2356 wil->txrx_ops.ring_fini_tx = wil_vring_free; 2357 wil->txrx_ops.ring_init_bcast = wil_vring_init_bcast; 2358 wil->txrx_ops.tx_init = wil_tx_init; 2359 wil->txrx_ops.tx_fini = wil_tx_fini; 2360 wil->txrx_ops.tx_ring_modify = wil_tx_vring_modify; 2361 /* RX ops */ 2362 wil->txrx_ops.rx_init = wil_rx_init; 2363 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp; 2364 wil->txrx_ops.get_reorder_params = wil_get_reorder_params; 2365 wil->txrx_ops.get_netif_rx_params = 2366 wil_get_netif_rx_params; 2367 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check; 2368 wil->txrx_ops.rx_error_check = wil_rx_error_check; 2369 wil->txrx_ops.is_rx_idle = wil_is_rx_idle; 2370 wil->txrx_ops.rx_fini = wil_rx_fini; 2371 } 2372