1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/etherdevice.h> 19 #include <net/ieee80211_radiotap.h> 20 #include <linux/if_arp.h> 21 #include <linux/moduleparam.h> 22 #include <linux/ip.h> 23 #include <linux/ipv6.h> 24 #include <net/ipv6.h> 25 #include <linux/prefetch.h> 26 27 #include "wil6210.h" 28 #include "wmi.h" 29 #include "txrx.h" 30 #include "trace.h" 31 #include "txrx_edma.h" 32 33 static bool rtap_include_phy_info; 34 module_param(rtap_include_phy_info, bool, 0444); 35 MODULE_PARM_DESC(rtap_include_phy_info, 36 " Include PHY info in the radiotap header, default - no"); 37 38 bool rx_align_2; 39 module_param(rx_align_2, bool, 0444); 40 MODULE_PARM_DESC(rx_align_2, " align Rx buffers on 4*n+2, default - no"); 41 42 bool rx_large_buf; 43 module_param(rx_large_buf, bool, 0444); 44 MODULE_PARM_DESC(rx_large_buf, " allocate 8KB RX buffers, default - no"); 45 46 static inline uint wil_rx_snaplen(void) 47 { 48 return rx_align_2 ? 6 : 0; 49 } 50 51 /* wil_ring_wmark_low - low watermark for available descriptor space */ 52 static inline int wil_ring_wmark_low(struct wil_ring *ring) 53 { 54 return ring->size / 8; 55 } 56 57 /* wil_ring_wmark_high - high watermark for available descriptor space */ 58 static inline int wil_ring_wmark_high(struct wil_ring *ring) 59 { 60 return ring->size / 4; 61 } 62 63 /* returns true if num avail descriptors is lower than wmark_low */ 64 static inline int wil_ring_avail_low(struct wil_ring *ring) 65 { 66 return wil_ring_avail_tx(ring) < wil_ring_wmark_low(ring); 67 } 68 69 /* returns true if num avail descriptors is higher than wmark_high */ 70 static inline int wil_ring_avail_high(struct wil_ring *ring) 71 { 72 return wil_ring_avail_tx(ring) > wil_ring_wmark_high(ring); 73 } 74 75 /* returns true when all tx vrings are empty */ 76 bool wil_is_tx_idle(struct wil6210_priv *wil) 77 { 78 int i; 79 unsigned long data_comp_to; 80 int min_ring_id = wil_get_min_tx_ring_id(wil); 81 82 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 83 struct wil_ring *vring = &wil->ring_tx[i]; 84 int vring_index = vring - wil->ring_tx; 85 struct wil_ring_tx_data *txdata = 86 &wil->ring_tx_data[vring_index]; 87 88 spin_lock(&txdata->lock); 89 90 if (!vring->va || !txdata->enabled) { 91 spin_unlock(&txdata->lock); 92 continue; 93 } 94 95 data_comp_to = jiffies + msecs_to_jiffies( 96 WIL_DATA_COMPLETION_TO_MS); 97 if (test_bit(wil_status_napi_en, wil->status)) { 98 while (!wil_ring_is_empty(vring)) { 99 if (time_after(jiffies, data_comp_to)) { 100 wil_dbg_pm(wil, 101 "TO waiting for idle tx\n"); 102 spin_unlock(&txdata->lock); 103 return false; 104 } 105 wil_dbg_ratelimited(wil, 106 "tx vring is not empty -> NAPI\n"); 107 spin_unlock(&txdata->lock); 108 napi_synchronize(&wil->napi_tx); 109 msleep(20); 110 spin_lock(&txdata->lock); 111 if (!vring->va || !txdata->enabled) 112 break; 113 } 114 } 115 116 spin_unlock(&txdata->lock); 117 } 118 119 return true; 120 } 121 122 static int wil_vring_alloc(struct wil6210_priv *wil, struct wil_ring *vring) 123 { 124 struct device *dev = wil_to_dev(wil); 125 size_t sz = vring->size * sizeof(vring->va[0]); 126 uint i; 127 128 wil_dbg_misc(wil, "vring_alloc:\n"); 129 130 BUILD_BUG_ON(sizeof(vring->va[0]) != 32); 131 132 vring->swhead = 0; 133 vring->swtail = 0; 134 vring->ctx = kcalloc(vring->size, sizeof(vring->ctx[0]), GFP_KERNEL); 135 if (!vring->ctx) { 136 vring->va = NULL; 137 return -ENOMEM; 138 } 139 140 /* vring->va should be aligned on its size rounded up to power of 2 141 * This is granted by the dma_alloc_coherent. 142 * 143 * HW has limitation that all vrings addresses must share the same 144 * upper 16 msb bits part of 48 bits address. To workaround that, 145 * if we are using more than 32 bit addresses switch to 32 bit 146 * allocation before allocating vring memory. 147 * 148 * There's no check for the return value of dma_set_mask_and_coherent, 149 * since we assume if we were able to set the mask during 150 * initialization in this system it will not fail if we set it again 151 */ 152 if (wil->dma_addr_size > 32) 153 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); 154 155 vring->va = dma_alloc_coherent(dev, sz, &vring->pa, GFP_KERNEL); 156 if (!vring->va) { 157 kfree(vring->ctx); 158 vring->ctx = NULL; 159 return -ENOMEM; 160 } 161 162 if (wil->dma_addr_size > 32) 163 dma_set_mask_and_coherent(dev, 164 DMA_BIT_MASK(wil->dma_addr_size)); 165 166 /* initially, all descriptors are SW owned 167 * For Tx and Rx, ownership bit is at the same location, thus 168 * we can use any 169 */ 170 for (i = 0; i < vring->size; i++) { 171 volatile struct vring_tx_desc *_d = 172 &vring->va[i].tx.legacy; 173 174 _d->dma.status = TX_DMA_STATUS_DU; 175 } 176 177 wil_dbg_misc(wil, "vring[%d] 0x%p:%pad 0x%p\n", vring->size, 178 vring->va, &vring->pa, vring->ctx); 179 180 return 0; 181 } 182 183 static void wil_txdesc_unmap(struct device *dev, union wil_tx_desc *desc, 184 struct wil_ctx *ctx) 185 { 186 struct vring_tx_desc *d = &desc->legacy; 187 dma_addr_t pa = wil_desc_addr(&d->dma.addr); 188 u16 dmalen = le16_to_cpu(d->dma.length); 189 190 switch (ctx->mapped_as) { 191 case wil_mapped_as_single: 192 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE); 193 break; 194 case wil_mapped_as_page: 195 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE); 196 break; 197 default: 198 break; 199 } 200 } 201 202 static void wil_vring_free(struct wil6210_priv *wil, struct wil_ring *vring) 203 { 204 struct device *dev = wil_to_dev(wil); 205 size_t sz = vring->size * sizeof(vring->va[0]); 206 207 lockdep_assert_held(&wil->mutex); 208 if (!vring->is_rx) { 209 int vring_index = vring - wil->ring_tx; 210 211 wil_dbg_misc(wil, "free Tx vring %d [%d] 0x%p:%pad 0x%p\n", 212 vring_index, vring->size, vring->va, 213 &vring->pa, vring->ctx); 214 } else { 215 wil_dbg_misc(wil, "free Rx vring [%d] 0x%p:%pad 0x%p\n", 216 vring->size, vring->va, 217 &vring->pa, vring->ctx); 218 } 219 220 while (!wil_ring_is_empty(vring)) { 221 dma_addr_t pa; 222 u16 dmalen; 223 struct wil_ctx *ctx; 224 225 if (!vring->is_rx) { 226 struct vring_tx_desc dd, *d = ⅆ 227 volatile struct vring_tx_desc *_d = 228 &vring->va[vring->swtail].tx.legacy; 229 230 ctx = &vring->ctx[vring->swtail]; 231 if (!ctx) { 232 wil_dbg_txrx(wil, 233 "ctx(%d) was already completed\n", 234 vring->swtail); 235 vring->swtail = wil_ring_next_tail(vring); 236 continue; 237 } 238 *d = *_d; 239 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx); 240 if (ctx->skb) 241 dev_kfree_skb_any(ctx->skb); 242 vring->swtail = wil_ring_next_tail(vring); 243 } else { /* rx */ 244 struct vring_rx_desc dd, *d = ⅆ 245 volatile struct vring_rx_desc *_d = 246 &vring->va[vring->swhead].rx.legacy; 247 248 ctx = &vring->ctx[vring->swhead]; 249 *d = *_d; 250 pa = wil_desc_addr(&d->dma.addr); 251 dmalen = le16_to_cpu(d->dma.length); 252 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE); 253 kfree_skb(ctx->skb); 254 wil_ring_advance_head(vring, 1); 255 } 256 } 257 dma_free_coherent(dev, sz, (void *)vring->va, vring->pa); 258 kfree(vring->ctx); 259 vring->pa = 0; 260 vring->va = NULL; 261 vring->ctx = NULL; 262 } 263 264 /** 265 * Allocate one skb for Rx VRING 266 * 267 * Safe to call from IRQ 268 */ 269 static int wil_vring_alloc_skb(struct wil6210_priv *wil, struct wil_ring *vring, 270 u32 i, int headroom) 271 { 272 struct device *dev = wil_to_dev(wil); 273 unsigned int sz = wil->rx_buf_len + ETH_HLEN + wil_rx_snaplen(); 274 struct vring_rx_desc dd, *d = ⅆ 275 volatile struct vring_rx_desc *_d = &vring->va[i].rx.legacy; 276 dma_addr_t pa; 277 struct sk_buff *skb = dev_alloc_skb(sz + headroom); 278 279 if (unlikely(!skb)) 280 return -ENOMEM; 281 282 skb_reserve(skb, headroom); 283 skb_put(skb, sz); 284 285 /** 286 * Make sure that the network stack calculates checksum for packets 287 * which failed the HW checksum calculation 288 */ 289 skb->ip_summed = CHECKSUM_NONE; 290 291 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE); 292 if (unlikely(dma_mapping_error(dev, pa))) { 293 kfree_skb(skb); 294 return -ENOMEM; 295 } 296 297 d->dma.d0 = RX_DMA_D0_CMD_DMA_RT | RX_DMA_D0_CMD_DMA_IT; 298 wil_desc_addr_set(&d->dma.addr, pa); 299 /* ip_length don't care */ 300 /* b11 don't care */ 301 /* error don't care */ 302 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ 303 d->dma.length = cpu_to_le16(sz); 304 *_d = *d; 305 vring->ctx[i].skb = skb; 306 307 return 0; 308 } 309 310 /** 311 * Adds radiotap header 312 * 313 * Any error indicated as "Bad FCS" 314 * 315 * Vendor data for 04:ce:14-1 (Wilocity-1) consists of: 316 * - Rx descriptor: 32 bytes 317 * - Phy info 318 */ 319 static void wil_rx_add_radiotap_header(struct wil6210_priv *wil, 320 struct sk_buff *skb) 321 { 322 struct wil6210_rtap { 323 struct ieee80211_radiotap_header rthdr; 324 /* fields should be in the order of bits in rthdr.it_present */ 325 /* flags */ 326 u8 flags; 327 /* channel */ 328 __le16 chnl_freq __aligned(2); 329 __le16 chnl_flags; 330 /* MCS */ 331 u8 mcs_present; 332 u8 mcs_flags; 333 u8 mcs_index; 334 } __packed; 335 struct wil6210_rtap_vendor { 336 struct wil6210_rtap rtap; 337 /* vendor */ 338 u8 vendor_oui[3] __aligned(2); 339 u8 vendor_ns; 340 __le16 vendor_skip; 341 u8 vendor_data[0]; 342 } __packed; 343 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 344 struct wil6210_rtap_vendor *rtap_vendor; 345 int rtap_len = sizeof(struct wil6210_rtap); 346 int phy_length = 0; /* phy info header size, bytes */ 347 static char phy_data[128]; 348 struct ieee80211_channel *ch = wil->monitor_chandef.chan; 349 350 if (rtap_include_phy_info) { 351 rtap_len = sizeof(*rtap_vendor) + sizeof(*d); 352 /* calculate additional length */ 353 if (d->dma.status & RX_DMA_STATUS_PHY_INFO) { 354 /** 355 * PHY info starts from 8-byte boundary 356 * there are 8-byte lines, last line may be partially 357 * written (HW bug), thus FW configures for last line 358 * to be excessive. Driver skips this last line. 359 */ 360 int len = min_t(int, 8 + sizeof(phy_data), 361 wil_rxdesc_phy_length(d)); 362 363 if (len > 8) { 364 void *p = skb_tail_pointer(skb); 365 void *pa = PTR_ALIGN(p, 8); 366 367 if (skb_tailroom(skb) >= len + (pa - p)) { 368 phy_length = len - 8; 369 memcpy(phy_data, pa, phy_length); 370 } 371 } 372 } 373 rtap_len += phy_length; 374 } 375 376 if (skb_headroom(skb) < rtap_len && 377 pskb_expand_head(skb, rtap_len, 0, GFP_ATOMIC)) { 378 wil_err(wil, "Unable to expand headroom to %d\n", rtap_len); 379 return; 380 } 381 382 rtap_vendor = skb_push(skb, rtap_len); 383 memset(rtap_vendor, 0, rtap_len); 384 385 rtap_vendor->rtap.rthdr.it_version = PKTHDR_RADIOTAP_VERSION; 386 rtap_vendor->rtap.rthdr.it_len = cpu_to_le16(rtap_len); 387 rtap_vendor->rtap.rthdr.it_present = cpu_to_le32( 388 (1 << IEEE80211_RADIOTAP_FLAGS) | 389 (1 << IEEE80211_RADIOTAP_CHANNEL) | 390 (1 << IEEE80211_RADIOTAP_MCS)); 391 if (d->dma.status & RX_DMA_STATUS_ERROR) 392 rtap_vendor->rtap.flags |= IEEE80211_RADIOTAP_F_BADFCS; 393 394 rtap_vendor->rtap.chnl_freq = cpu_to_le16(ch ? ch->center_freq : 58320); 395 rtap_vendor->rtap.chnl_flags = cpu_to_le16(0); 396 397 rtap_vendor->rtap.mcs_present = IEEE80211_RADIOTAP_MCS_HAVE_MCS; 398 rtap_vendor->rtap.mcs_flags = 0; 399 rtap_vendor->rtap.mcs_index = wil_rxdesc_mcs(d); 400 401 if (rtap_include_phy_info) { 402 rtap_vendor->rtap.rthdr.it_present |= cpu_to_le32(1 << 403 IEEE80211_RADIOTAP_VENDOR_NAMESPACE); 404 /* OUI for Wilocity 04:ce:14 */ 405 rtap_vendor->vendor_oui[0] = 0x04; 406 rtap_vendor->vendor_oui[1] = 0xce; 407 rtap_vendor->vendor_oui[2] = 0x14; 408 rtap_vendor->vendor_ns = 1; 409 /* Rx descriptor + PHY data */ 410 rtap_vendor->vendor_skip = cpu_to_le16(sizeof(*d) + 411 phy_length); 412 memcpy(rtap_vendor->vendor_data, (void *)d, sizeof(*d)); 413 memcpy(rtap_vendor->vendor_data + sizeof(*d), phy_data, 414 phy_length); 415 } 416 } 417 418 static bool wil_is_rx_idle(struct wil6210_priv *wil) 419 { 420 struct vring_rx_desc *_d; 421 struct wil_ring *ring = &wil->ring_rx; 422 423 _d = (struct vring_rx_desc *)&ring->va[ring->swhead].rx.legacy; 424 if (_d->dma.status & RX_DMA_STATUS_DU) 425 return false; 426 427 return true; 428 } 429 430 /** 431 * reap 1 frame from @swhead 432 * 433 * Rx descriptor copied to skb->cb 434 * 435 * Safe to call from IRQ 436 */ 437 static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil, 438 struct wil_ring *vring) 439 { 440 struct device *dev = wil_to_dev(wil); 441 struct wil6210_vif *vif; 442 struct net_device *ndev; 443 volatile struct vring_rx_desc *_d; 444 struct vring_rx_desc *d; 445 struct sk_buff *skb; 446 dma_addr_t pa; 447 unsigned int snaplen = wil_rx_snaplen(); 448 unsigned int sz = wil->rx_buf_len + ETH_HLEN + snaplen; 449 u16 dmalen; 450 u8 ftype; 451 int cid, mid; 452 int i; 453 struct wil_net_stats *stats; 454 455 BUILD_BUG_ON(sizeof(struct vring_rx_desc) > sizeof(skb->cb)); 456 457 again: 458 if (unlikely(wil_ring_is_empty(vring))) 459 return NULL; 460 461 i = (int)vring->swhead; 462 _d = &vring->va[i].rx.legacy; 463 if (unlikely(!(_d->dma.status & RX_DMA_STATUS_DU))) { 464 /* it is not error, we just reached end of Rx done area */ 465 return NULL; 466 } 467 468 skb = vring->ctx[i].skb; 469 vring->ctx[i].skb = NULL; 470 wil_ring_advance_head(vring, 1); 471 if (!skb) { 472 wil_err(wil, "No Rx skb at [%d]\n", i); 473 goto again; 474 } 475 d = wil_skb_rxdesc(skb); 476 *d = *_d; 477 pa = wil_desc_addr(&d->dma.addr); 478 479 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE); 480 dmalen = le16_to_cpu(d->dma.length); 481 482 trace_wil6210_rx(i, d); 483 wil_dbg_txrx(wil, "Rx[%3d] : %d bytes\n", i, dmalen); 484 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4, 485 (const void *)d, sizeof(*d), false); 486 487 cid = wil_rxdesc_cid(d); 488 mid = wil_rxdesc_mid(d); 489 vif = wil->vifs[mid]; 490 491 if (unlikely(!vif)) { 492 wil_dbg_txrx(wil, "skipped RX descriptor with invalid mid %d", 493 mid); 494 kfree_skb(skb); 495 goto again; 496 } 497 ndev = vif_to_ndev(vif); 498 stats = &wil->sta[cid].stats; 499 500 if (unlikely(dmalen > sz)) { 501 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen); 502 stats->rx_large_frame++; 503 kfree_skb(skb); 504 goto again; 505 } 506 skb_trim(skb, dmalen); 507 508 prefetch(skb->data); 509 510 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 511 skb->data, skb_headlen(skb), false); 512 513 stats->last_mcs_rx = wil_rxdesc_mcs(d); 514 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs)) 515 stats->rx_per_mcs[stats->last_mcs_rx]++; 516 517 /* use radiotap header only if required */ 518 if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) 519 wil_rx_add_radiotap_header(wil, skb); 520 521 /* no extra checks if in sniffer mode */ 522 if (ndev->type != ARPHRD_ETHER) 523 return skb; 524 /* Non-data frames may be delivered through Rx DMA channel (ex: BAR) 525 * Driver should recognize it by frame type, that is found 526 * in Rx descriptor. If type is not data, it is 802.11 frame as is 527 */ 528 ftype = wil_rxdesc_ftype(d) << 2; 529 if (unlikely(ftype != IEEE80211_FTYPE_DATA)) { 530 u8 fc1 = wil_rxdesc_fc1(d); 531 int tid = wil_rxdesc_tid(d); 532 u16 seq = wil_rxdesc_seq(d); 533 534 wil_dbg_txrx(wil, 535 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 536 fc1, mid, cid, tid, seq); 537 stats->rx_non_data_frame++; 538 if (wil_is_back_req(fc1)) { 539 wil_dbg_txrx(wil, 540 "BAR: MID %d CID %d TID %d Seq 0x%03x\n", 541 mid, cid, tid, seq); 542 wil_rx_bar(wil, vif, cid, tid, seq); 543 } else { 544 /* print again all info. One can enable only this 545 * without overhead for printing every Rx frame 546 */ 547 wil_dbg_txrx(wil, 548 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n", 549 fc1, mid, cid, tid, seq); 550 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4, 551 (const void *)d, sizeof(*d), false); 552 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1, 553 skb->data, skb_headlen(skb), false); 554 } 555 kfree_skb(skb); 556 goto again; 557 } 558 559 if (unlikely(skb->len < ETH_HLEN + snaplen)) { 560 wil_err(wil, "Short frame, len = %d\n", skb->len); 561 stats->rx_short_frame++; 562 kfree_skb(skb); 563 goto again; 564 } 565 566 /* L4 IDENT is on when HW calculated checksum, check status 567 * and in case of error drop the packet 568 * higher stack layers will handle retransmission (if required) 569 */ 570 if (likely(d->dma.status & RX_DMA_STATUS_L4I)) { 571 /* L4 protocol identified, csum calculated */ 572 if (likely((d->dma.error & RX_DMA_ERROR_L4_ERR) == 0)) 573 skb->ip_summed = CHECKSUM_UNNECESSARY; 574 /* If HW reports bad checksum, let IP stack re-check it 575 * For example, HW don't understand Microsoft IP stack that 576 * mis-calculates TCP checksum - if it should be 0x0, 577 * it writes 0xffff in violation of RFC 1624 578 */ 579 else 580 stats->rx_csum_err++; 581 } 582 583 if (snaplen) { 584 /* Packet layout 585 * +-------+-------+---------+------------+------+ 586 * | SA(6) | DA(6) | SNAP(6) | ETHTYPE(2) | DATA | 587 * +-------+-------+---------+------------+------+ 588 * Need to remove SNAP, shifting SA and DA forward 589 */ 590 memmove(skb->data + snaplen, skb->data, 2 * ETH_ALEN); 591 skb_pull(skb, snaplen); 592 } 593 594 return skb; 595 } 596 597 /** 598 * allocate and fill up to @count buffers in rx ring 599 * buffers posted at @swtail 600 * Note: we have a single RX queue for servicing all VIFs, but we 601 * allocate skbs with headroom according to main interface only. This 602 * means it will not work with monitor interface together with other VIFs. 603 * Currently we only support monitor interface on its own without other VIFs, 604 * and we will need to fix this code once we add support. 605 */ 606 static int wil_rx_refill(struct wil6210_priv *wil, int count) 607 { 608 struct net_device *ndev = wil->main_ndev; 609 struct wil_ring *v = &wil->ring_rx; 610 u32 next_tail; 611 int rc = 0; 612 int headroom = ndev->type == ARPHRD_IEEE80211_RADIOTAP ? 613 WIL6210_RTAP_SIZE : 0; 614 615 for (; next_tail = wil_ring_next_tail(v), 616 (next_tail != v->swhead) && (count-- > 0); 617 v->swtail = next_tail) { 618 rc = wil_vring_alloc_skb(wil, v, v->swtail, headroom); 619 if (unlikely(rc)) { 620 wil_err_ratelimited(wil, "Error %d in rx refill[%d]\n", 621 rc, v->swtail); 622 break; 623 } 624 } 625 626 /* make sure all writes to descriptors (shared memory) are done before 627 * committing them to HW 628 */ 629 wmb(); 630 631 wil_w(wil, v->hwtail, v->swtail); 632 633 return rc; 634 } 635 636 /** 637 * reverse_memcmp - Compare two areas of memory, in reverse order 638 * @cs: One area of memory 639 * @ct: Another area of memory 640 * @count: The size of the area. 641 * 642 * Cut'n'paste from original memcmp (see lib/string.c) 643 * with minimal modifications 644 */ 645 int reverse_memcmp(const void *cs, const void *ct, size_t count) 646 { 647 const unsigned char *su1, *su2; 648 int res = 0; 649 650 for (su1 = cs + count - 1, su2 = ct + count - 1; count > 0; 651 --su1, --su2, count--) { 652 res = *su1 - *su2; 653 if (res) 654 break; 655 } 656 return res; 657 } 658 659 static int wil_rx_crypto_check(struct wil6210_priv *wil, struct sk_buff *skb) 660 { 661 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 662 int cid = wil_rxdesc_cid(d); 663 int tid = wil_rxdesc_tid(d); 664 int key_id = wil_rxdesc_key_id(d); 665 int mc = wil_rxdesc_mcast(d); 666 struct wil_sta_info *s = &wil->sta[cid]; 667 struct wil_tid_crypto_rx *c = mc ? &s->group_crypto_rx : 668 &s->tid_crypto_rx[tid]; 669 struct wil_tid_crypto_rx_single *cc = &c->key_id[key_id]; 670 const u8 *pn = (u8 *)&d->mac.pn_15_0; 671 672 if (!cc->key_set) { 673 wil_err_ratelimited(wil, 674 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n", 675 cid, tid, mc, key_id); 676 return -EINVAL; 677 } 678 679 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) { 680 wil_err_ratelimited(wil, 681 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n", 682 cid, tid, mc, key_id, pn, cc->pn); 683 return -EINVAL; 684 } 685 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN); 686 687 return 0; 688 } 689 690 static int wil_rx_error_check(struct wil6210_priv *wil, struct sk_buff *skb, 691 struct wil_net_stats *stats) 692 { 693 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 694 695 if ((d->dma.status & RX_DMA_STATUS_ERROR) && 696 (d->dma.error & RX_DMA_ERROR_MIC)) { 697 stats->rx_mic_error++; 698 wil_dbg_txrx(wil, "MIC error, dropping packet\n"); 699 return -EFAULT; 700 } 701 702 return 0; 703 } 704 705 static void wil_get_netif_rx_params(struct sk_buff *skb, int *cid, 706 int *security) 707 { 708 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 709 710 *cid = wil_rxdesc_cid(d); /* always 0..7, no need to check */ 711 *security = wil_rxdesc_security(d); 712 } 713 714 /* 715 * Pass Rx packet to the netif. Update statistics. 716 * Called in softirq context (NAPI poll). 717 */ 718 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev) 719 { 720 gro_result_t rc = GRO_NORMAL; 721 struct wil6210_vif *vif = ndev_to_vif(ndev); 722 struct wil6210_priv *wil = ndev_to_wil(ndev); 723 struct wireless_dev *wdev = vif_to_wdev(vif); 724 unsigned int len = skb->len; 725 int cid; 726 int security; 727 struct ethhdr *eth = (void *)skb->data; 728 /* here looking for DA, not A1, thus Rxdesc's 'mcast' indication 729 * is not suitable, need to look at data 730 */ 731 int mcast = is_multicast_ether_addr(eth->h_dest); 732 struct wil_net_stats *stats; 733 struct sk_buff *xmit_skb = NULL; 734 static const char * const gro_res_str[] = { 735 [GRO_MERGED] = "GRO_MERGED", 736 [GRO_MERGED_FREE] = "GRO_MERGED_FREE", 737 [GRO_HELD] = "GRO_HELD", 738 [GRO_NORMAL] = "GRO_NORMAL", 739 [GRO_DROP] = "GRO_DROP", 740 }; 741 742 wil->txrx_ops.get_netif_rx_params(skb, &cid, &security); 743 744 stats = &wil->sta[cid].stats; 745 746 if (ndev->features & NETIF_F_RXHASH) 747 /* fake L4 to ensure it won't be re-calculated later 748 * set hash to any non-zero value to activate rps 749 * mechanism, core will be chosen according 750 * to user-level rps configuration. 751 */ 752 skb_set_hash(skb, 1, PKT_HASH_TYPE_L4); 753 754 skb_orphan(skb); 755 756 if (security && (wil->txrx_ops.rx_crypto_check(wil, skb) != 0)) { 757 rc = GRO_DROP; 758 dev_kfree_skb(skb); 759 stats->rx_replay++; 760 goto stats; 761 } 762 763 /* check errors reported by HW and update statistics */ 764 if (unlikely(wil->txrx_ops.rx_error_check(wil, skb, stats))) { 765 dev_kfree_skb(skb); 766 return; 767 } 768 769 if (wdev->iftype == NL80211_IFTYPE_STATION) { 770 if (mcast && ether_addr_equal(eth->h_source, ndev->dev_addr)) { 771 /* mcast packet looped back to us */ 772 rc = GRO_DROP; 773 dev_kfree_skb(skb); 774 goto stats; 775 } 776 } else if (wdev->iftype == NL80211_IFTYPE_AP && !vif->ap_isolate) { 777 if (mcast) { 778 /* send multicast frames both to higher layers in 779 * local net stack and back to the wireless medium 780 */ 781 xmit_skb = skb_copy(skb, GFP_ATOMIC); 782 } else { 783 int xmit_cid = wil_find_cid(wil, vif->mid, 784 eth->h_dest); 785 786 if (xmit_cid >= 0) { 787 /* The destination station is associated to 788 * this AP (in this VLAN), so send the frame 789 * directly to it and do not pass it to local 790 * net stack. 791 */ 792 xmit_skb = skb; 793 skb = NULL; 794 } 795 } 796 } 797 if (xmit_skb) { 798 /* Send to wireless media and increase priority by 256 to 799 * keep the received priority instead of reclassifying 800 * the frame (see cfg80211_classify8021d). 801 */ 802 xmit_skb->dev = ndev; 803 xmit_skb->priority += 256; 804 xmit_skb->protocol = htons(ETH_P_802_3); 805 skb_reset_network_header(xmit_skb); 806 skb_reset_mac_header(xmit_skb); 807 wil_dbg_txrx(wil, "Rx -> Tx %d bytes\n", len); 808 dev_queue_xmit(xmit_skb); 809 } 810 811 if (skb) { /* deliver to local stack */ 812 skb->protocol = eth_type_trans(skb, ndev); 813 skb->dev = ndev; 814 rc = napi_gro_receive(&wil->napi_rx, skb); 815 wil_dbg_txrx(wil, "Rx complete %d bytes => %s\n", 816 len, gro_res_str[rc]); 817 } 818 stats: 819 /* statistics. rc set to GRO_NORMAL for AP bridging */ 820 if (unlikely(rc == GRO_DROP)) { 821 ndev->stats.rx_dropped++; 822 stats->rx_dropped++; 823 wil_dbg_txrx(wil, "Rx drop %d bytes\n", len); 824 } else { 825 ndev->stats.rx_packets++; 826 stats->rx_packets++; 827 ndev->stats.rx_bytes += len; 828 stats->rx_bytes += len; 829 if (mcast) 830 ndev->stats.multicast++; 831 } 832 } 833 834 /** 835 * Proceed all completed skb's from Rx VRING 836 * 837 * Safe to call from NAPI poll, i.e. softirq with interrupts enabled 838 */ 839 void wil_rx_handle(struct wil6210_priv *wil, int *quota) 840 { 841 struct net_device *ndev = wil->main_ndev; 842 struct wireless_dev *wdev = ndev->ieee80211_ptr; 843 struct wil_ring *v = &wil->ring_rx; 844 struct sk_buff *skb; 845 846 if (unlikely(!v->va)) { 847 wil_err(wil, "Rx IRQ while Rx not yet initialized\n"); 848 return; 849 } 850 wil_dbg_txrx(wil, "rx_handle\n"); 851 while ((*quota > 0) && (NULL != (skb = wil_vring_reap_rx(wil, v)))) { 852 (*quota)--; 853 854 /* monitor is currently supported on main interface only */ 855 if (wdev->iftype == NL80211_IFTYPE_MONITOR) { 856 skb->dev = ndev; 857 skb_reset_mac_header(skb); 858 skb->ip_summed = CHECKSUM_UNNECESSARY; 859 skb->pkt_type = PACKET_OTHERHOST; 860 skb->protocol = htons(ETH_P_802_2); 861 wil_netif_rx_any(skb, ndev); 862 } else { 863 wil_rx_reorder(wil, skb); 864 } 865 } 866 wil_rx_refill(wil, v->size); 867 } 868 869 static void wil_rx_buf_len_init(struct wil6210_priv *wil) 870 { 871 wil->rx_buf_len = rx_large_buf ? 872 WIL_MAX_ETH_MTU : TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD; 873 if (mtu_max > wil->rx_buf_len) { 874 /* do not allow RX buffers to be smaller than mtu_max, for 875 * backward compatibility (mtu_max parameter was also used 876 * to support receiving large packets) 877 */ 878 wil_info(wil, "Override RX buffer to mtu_max(%d)\n", mtu_max); 879 wil->rx_buf_len = mtu_max; 880 } 881 } 882 883 static int wil_rx_init(struct wil6210_priv *wil, u16 size) 884 { 885 struct wil_ring *vring = &wil->ring_rx; 886 int rc; 887 888 wil_dbg_misc(wil, "rx_init\n"); 889 890 if (vring->va) { 891 wil_err(wil, "Rx ring already allocated\n"); 892 return -EINVAL; 893 } 894 895 wil_rx_buf_len_init(wil); 896 897 vring->size = size; 898 vring->is_rx = true; 899 rc = wil_vring_alloc(wil, vring); 900 if (rc) 901 return rc; 902 903 rc = wmi_rx_chain_add(wil, vring); 904 if (rc) 905 goto err_free; 906 907 rc = wil_rx_refill(wil, vring->size); 908 if (rc) 909 goto err_free; 910 911 return 0; 912 err_free: 913 wil_vring_free(wil, vring); 914 915 return rc; 916 } 917 918 static void wil_rx_fini(struct wil6210_priv *wil) 919 { 920 struct wil_ring *vring = &wil->ring_rx; 921 922 wil_dbg_misc(wil, "rx_fini\n"); 923 924 if (vring->va) 925 wil_vring_free(wil, vring); 926 } 927 928 static int wil_tx_desc_map(union wil_tx_desc *desc, dma_addr_t pa, 929 u32 len, int vring_index) 930 { 931 struct vring_tx_desc *d = &desc->legacy; 932 933 wil_desc_addr_set(&d->dma.addr, pa); 934 d->dma.ip_length = 0; 935 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/ 936 d->dma.b11 = 0/*14 | BIT(7)*/; 937 d->dma.error = 0; 938 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */ 939 d->dma.length = cpu_to_le16((u16)len); 940 d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS); 941 d->mac.d[0] = 0; 942 d->mac.d[1] = 0; 943 d->mac.d[2] = 0; 944 d->mac.ucode_cmd = 0; 945 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi */ 946 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) | 947 (1 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS); 948 949 return 0; 950 } 951 952 void wil_tx_data_init(struct wil_ring_tx_data *txdata) 953 { 954 spin_lock_bh(&txdata->lock); 955 txdata->dot1x_open = 0; 956 txdata->enabled = 0; 957 txdata->idle = 0; 958 txdata->last_idle = 0; 959 txdata->begin = 0; 960 txdata->agg_wsize = 0; 961 txdata->agg_timeout = 0; 962 txdata->agg_amsdu = 0; 963 txdata->addba_in_progress = false; 964 txdata->mid = U8_MAX; 965 spin_unlock_bh(&txdata->lock); 966 } 967 968 static int wil_vring_init_tx(struct wil6210_vif *vif, int id, int size, 969 int cid, int tid) 970 { 971 struct wil6210_priv *wil = vif_to_wil(vif); 972 int rc; 973 struct wmi_vring_cfg_cmd cmd = { 974 .action = cpu_to_le32(WMI_VRING_CMD_ADD), 975 .vring_cfg = { 976 .tx_sw_ring = { 977 .max_mpdu_size = 978 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 979 .ring_size = cpu_to_le16(size), 980 }, 981 .ringid = id, 982 .cidxtid = mk_cidxtid(cid, tid), 983 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 984 .mac_ctrl = 0, 985 .to_resolution = 0, 986 .agg_max_wsize = 0, 987 .schd_params = { 988 .priority = cpu_to_le16(0), 989 .timeslot_us = cpu_to_le16(0xfff), 990 }, 991 }, 992 }; 993 struct { 994 struct wmi_cmd_hdr wmi; 995 struct wmi_vring_cfg_done_event cmd; 996 } __packed reply = { 997 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 998 }; 999 struct wil_ring *vring = &wil->ring_tx[id]; 1000 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id]; 1001 1002 wil_dbg_misc(wil, "vring_init_tx: max_mpdu_size %d\n", 1003 cmd.vring_cfg.tx_sw_ring.max_mpdu_size); 1004 lockdep_assert_held(&wil->mutex); 1005 1006 if (vring->va) { 1007 wil_err(wil, "Tx ring [%d] already allocated\n", id); 1008 rc = -EINVAL; 1009 goto out; 1010 } 1011 1012 wil_tx_data_init(txdata); 1013 vring->is_rx = false; 1014 vring->size = size; 1015 rc = wil_vring_alloc(wil, vring); 1016 if (rc) 1017 goto out; 1018 1019 wil->ring2cid_tid[id][0] = cid; 1020 wil->ring2cid_tid[id][1] = tid; 1021 1022 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1023 1024 if (!vif->privacy) 1025 txdata->dot1x_open = true; 1026 rc = wmi_call(wil, WMI_VRING_CFG_CMDID, vif->mid, &cmd, sizeof(cmd), 1027 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1028 if (rc) 1029 goto out_free; 1030 1031 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1032 wil_err(wil, "Tx config failed, status 0x%02x\n", 1033 reply.cmd.status); 1034 rc = -EINVAL; 1035 goto out_free; 1036 } 1037 1038 spin_lock_bh(&txdata->lock); 1039 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr); 1040 txdata->mid = vif->mid; 1041 txdata->enabled = 1; 1042 spin_unlock_bh(&txdata->lock); 1043 1044 if (txdata->dot1x_open && (agg_wsize >= 0)) 1045 wil_addba_tx_request(wil, id, agg_wsize); 1046 1047 return 0; 1048 out_free: 1049 spin_lock_bh(&txdata->lock); 1050 txdata->dot1x_open = false; 1051 txdata->enabled = 0; 1052 spin_unlock_bh(&txdata->lock); 1053 wil_vring_free(wil, vring); 1054 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID; 1055 wil->ring2cid_tid[id][1] = 0; 1056 1057 out: 1058 1059 return rc; 1060 } 1061 1062 static int wil_tx_vring_modify(struct wil6210_vif *vif, int ring_id, int cid, 1063 int tid) 1064 { 1065 struct wil6210_priv *wil = vif_to_wil(vif); 1066 int rc; 1067 struct wmi_vring_cfg_cmd cmd = { 1068 .action = cpu_to_le32(WMI_VRING_CMD_MODIFY), 1069 .vring_cfg = { 1070 .tx_sw_ring = { 1071 .max_mpdu_size = 1072 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 1073 .ring_size = 0, 1074 }, 1075 .ringid = ring_id, 1076 .cidxtid = mk_cidxtid(cid, tid), 1077 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 1078 .mac_ctrl = 0, 1079 .to_resolution = 0, 1080 .agg_max_wsize = 0, 1081 .schd_params = { 1082 .priority = cpu_to_le16(0), 1083 .timeslot_us = cpu_to_le16(0xfff), 1084 }, 1085 }, 1086 }; 1087 struct { 1088 struct wmi_cmd_hdr wmi; 1089 struct wmi_vring_cfg_done_event cmd; 1090 } __packed reply = { 1091 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 1092 }; 1093 struct wil_ring *vring = &wil->ring_tx[ring_id]; 1094 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id]; 1095 1096 wil_dbg_misc(wil, "vring_modify: ring %d cid %d tid %d\n", ring_id, 1097 cid, tid); 1098 lockdep_assert_held(&wil->mutex); 1099 1100 if (!vring->va) { 1101 wil_err(wil, "Tx ring [%d] not allocated\n", ring_id); 1102 return -EINVAL; 1103 } 1104 1105 if (wil->ring2cid_tid[ring_id][0] != cid || 1106 wil->ring2cid_tid[ring_id][1] != tid) { 1107 wil_err(wil, "ring info does not match cid=%u tid=%u\n", 1108 wil->ring2cid_tid[ring_id][0], 1109 wil->ring2cid_tid[ring_id][1]); 1110 } 1111 1112 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1113 1114 rc = wmi_call(wil, WMI_VRING_CFG_CMDID, vif->mid, &cmd, sizeof(cmd), 1115 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1116 if (rc) 1117 goto fail; 1118 1119 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1120 wil_err(wil, "Tx modify failed, status 0x%02x\n", 1121 reply.cmd.status); 1122 rc = -EINVAL; 1123 goto fail; 1124 } 1125 1126 /* set BA aggregation window size to 0 to force a new BA with the 1127 * new AP 1128 */ 1129 txdata->agg_wsize = 0; 1130 if (txdata->dot1x_open && agg_wsize >= 0) 1131 wil_addba_tx_request(wil, ring_id, agg_wsize); 1132 1133 return 0; 1134 fail: 1135 spin_lock_bh(&txdata->lock); 1136 txdata->dot1x_open = false; 1137 txdata->enabled = 0; 1138 spin_unlock_bh(&txdata->lock); 1139 wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; 1140 wil->ring2cid_tid[ring_id][1] = 0; 1141 return rc; 1142 } 1143 1144 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size) 1145 { 1146 struct wil6210_priv *wil = vif_to_wil(vif); 1147 int rc; 1148 struct wmi_bcast_vring_cfg_cmd cmd = { 1149 .action = cpu_to_le32(WMI_VRING_CMD_ADD), 1150 .vring_cfg = { 1151 .tx_sw_ring = { 1152 .max_mpdu_size = 1153 cpu_to_le16(wil_mtu2macbuf(mtu_max)), 1154 .ring_size = cpu_to_le16(size), 1155 }, 1156 .ringid = id, 1157 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3, 1158 }, 1159 }; 1160 struct { 1161 struct wmi_cmd_hdr wmi; 1162 struct wmi_vring_cfg_done_event cmd; 1163 } __packed reply = { 1164 .cmd = {.status = WMI_FW_STATUS_FAILURE}, 1165 }; 1166 struct wil_ring *vring = &wil->ring_tx[id]; 1167 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id]; 1168 1169 wil_dbg_misc(wil, "vring_init_bcast: max_mpdu_size %d\n", 1170 cmd.vring_cfg.tx_sw_ring.max_mpdu_size); 1171 lockdep_assert_held(&wil->mutex); 1172 1173 if (vring->va) { 1174 wil_err(wil, "Tx ring [%d] already allocated\n", id); 1175 rc = -EINVAL; 1176 goto out; 1177 } 1178 1179 wil_tx_data_init(txdata); 1180 vring->is_rx = false; 1181 vring->size = size; 1182 rc = wil_vring_alloc(wil, vring); 1183 if (rc) 1184 goto out; 1185 1186 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID; /* CID */ 1187 wil->ring2cid_tid[id][1] = 0; /* TID */ 1188 1189 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa); 1190 1191 if (!vif->privacy) 1192 txdata->dot1x_open = true; 1193 rc = wmi_call(wil, WMI_BCAST_VRING_CFG_CMDID, vif->mid, 1194 &cmd, sizeof(cmd), 1195 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100); 1196 if (rc) 1197 goto out_free; 1198 1199 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) { 1200 wil_err(wil, "Tx config failed, status 0x%02x\n", 1201 reply.cmd.status); 1202 rc = -EINVAL; 1203 goto out_free; 1204 } 1205 1206 spin_lock_bh(&txdata->lock); 1207 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr); 1208 txdata->mid = vif->mid; 1209 txdata->enabled = 1; 1210 spin_unlock_bh(&txdata->lock); 1211 1212 return 0; 1213 out_free: 1214 spin_lock_bh(&txdata->lock); 1215 txdata->enabled = 0; 1216 txdata->dot1x_open = false; 1217 spin_unlock_bh(&txdata->lock); 1218 wil_vring_free(wil, vring); 1219 out: 1220 1221 return rc; 1222 } 1223 1224 static struct wil_ring *wil_find_tx_ucast(struct wil6210_priv *wil, 1225 struct wil6210_vif *vif, 1226 struct sk_buff *skb) 1227 { 1228 int i; 1229 struct ethhdr *eth = (void *)skb->data; 1230 int cid = wil_find_cid(wil, vif->mid, eth->h_dest); 1231 int min_ring_id = wil_get_min_tx_ring_id(wil); 1232 1233 if (cid < 0) 1234 return NULL; 1235 1236 /* TODO: fix for multiple TID */ 1237 for (i = min_ring_id; i < ARRAY_SIZE(wil->ring2cid_tid); i++) { 1238 if (!wil->ring_tx_data[i].dot1x_open && 1239 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1240 continue; 1241 if (wil->ring2cid_tid[i][0] == cid) { 1242 struct wil_ring *v = &wil->ring_tx[i]; 1243 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i]; 1244 1245 wil_dbg_txrx(wil, "find_tx_ucast: (%pM) -> [%d]\n", 1246 eth->h_dest, i); 1247 if (v->va && txdata->enabled) { 1248 return v; 1249 } else { 1250 wil_dbg_txrx(wil, 1251 "find_tx_ucast: vring[%d] not valid\n", 1252 i); 1253 return NULL; 1254 } 1255 } 1256 } 1257 1258 return NULL; 1259 } 1260 1261 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1262 struct wil_ring *ring, struct sk_buff *skb); 1263 1264 static struct wil_ring *wil_find_tx_ring_sta(struct wil6210_priv *wil, 1265 struct wil6210_vif *vif, 1266 struct sk_buff *skb) 1267 { 1268 struct wil_ring *ring; 1269 int i; 1270 u8 cid; 1271 struct wil_ring_tx_data *txdata; 1272 int min_ring_id = wil_get_min_tx_ring_id(wil); 1273 1274 /* In the STA mode, it is expected to have only 1 VRING 1275 * for the AP we connected to. 1276 * find 1-st vring eligible for this skb and use it. 1277 */ 1278 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 1279 ring = &wil->ring_tx[i]; 1280 txdata = &wil->ring_tx_data[i]; 1281 if (!ring->va || !txdata->enabled || txdata->mid != vif->mid) 1282 continue; 1283 1284 cid = wil->ring2cid_tid[i][0]; 1285 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1286 continue; 1287 1288 if (!wil->ring_tx_data[i].dot1x_open && 1289 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1290 continue; 1291 1292 wil_dbg_txrx(wil, "Tx -> ring %d\n", i); 1293 1294 return ring; 1295 } 1296 1297 wil_dbg_txrx(wil, "Tx while no rings active?\n"); 1298 1299 return NULL; 1300 } 1301 1302 /* Use one of 2 strategies: 1303 * 1304 * 1. New (real broadcast): 1305 * use dedicated broadcast vring 1306 * 2. Old (pseudo-DMS): 1307 * Find 1-st vring and return it; 1308 * duplicate skb and send it to other active vrings; 1309 * in all cases override dest address to unicast peer's address 1310 * Use old strategy when new is not supported yet: 1311 * - for PBSS 1312 */ 1313 static struct wil_ring *wil_find_tx_bcast_1(struct wil6210_priv *wil, 1314 struct wil6210_vif *vif, 1315 struct sk_buff *skb) 1316 { 1317 struct wil_ring *v; 1318 struct wil_ring_tx_data *txdata; 1319 int i = vif->bcast_ring; 1320 1321 if (i < 0) 1322 return NULL; 1323 v = &wil->ring_tx[i]; 1324 txdata = &wil->ring_tx_data[i]; 1325 if (!v->va || !txdata->enabled) 1326 return NULL; 1327 if (!wil->ring_tx_data[i].dot1x_open && 1328 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1329 return NULL; 1330 1331 return v; 1332 } 1333 1334 static void wil_set_da_for_vring(struct wil6210_priv *wil, 1335 struct sk_buff *skb, int vring_index) 1336 { 1337 struct ethhdr *eth = (void *)skb->data; 1338 int cid = wil->ring2cid_tid[vring_index][0]; 1339 1340 ether_addr_copy(eth->h_dest, wil->sta[cid].addr); 1341 } 1342 1343 static struct wil_ring *wil_find_tx_bcast_2(struct wil6210_priv *wil, 1344 struct wil6210_vif *vif, 1345 struct sk_buff *skb) 1346 { 1347 struct wil_ring *v, *v2; 1348 struct sk_buff *skb2; 1349 int i; 1350 u8 cid; 1351 struct ethhdr *eth = (void *)skb->data; 1352 char *src = eth->h_source; 1353 struct wil_ring_tx_data *txdata, *txdata2; 1354 int min_ring_id = wil_get_min_tx_ring_id(wil); 1355 1356 /* find 1-st vring eligible for data */ 1357 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 1358 v = &wil->ring_tx[i]; 1359 txdata = &wil->ring_tx_data[i]; 1360 if (!v->va || !txdata->enabled || txdata->mid != vif->mid) 1361 continue; 1362 1363 cid = wil->ring2cid_tid[i][0]; 1364 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1365 continue; 1366 if (!wil->ring_tx_data[i].dot1x_open && 1367 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1368 continue; 1369 1370 /* don't Tx back to source when re-routing Rx->Tx at the AP */ 1371 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN)) 1372 continue; 1373 1374 goto found; 1375 } 1376 1377 wil_dbg_txrx(wil, "Tx while no vrings active?\n"); 1378 1379 return NULL; 1380 1381 found: 1382 wil_dbg_txrx(wil, "BCAST -> ring %d\n", i); 1383 wil_set_da_for_vring(wil, skb, i); 1384 1385 /* find other active vrings and duplicate skb for each */ 1386 for (i++; i < WIL6210_MAX_TX_RINGS; i++) { 1387 v2 = &wil->ring_tx[i]; 1388 txdata2 = &wil->ring_tx_data[i]; 1389 if (!v2->va || txdata2->mid != vif->mid) 1390 continue; 1391 cid = wil->ring2cid_tid[i][0]; 1392 if (cid >= WIL6210_MAX_CID) /* skip BCAST */ 1393 continue; 1394 if (!wil->ring_tx_data[i].dot1x_open && 1395 skb->protocol != cpu_to_be16(ETH_P_PAE)) 1396 continue; 1397 1398 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN)) 1399 continue; 1400 1401 skb2 = skb_copy(skb, GFP_ATOMIC); 1402 if (skb2) { 1403 wil_dbg_txrx(wil, "BCAST DUP -> ring %d\n", i); 1404 wil_set_da_for_vring(wil, skb2, i); 1405 wil_tx_ring(wil, vif, v2, skb2); 1406 } else { 1407 wil_err(wil, "skb_copy failed\n"); 1408 } 1409 } 1410 1411 return v; 1412 } 1413 1414 static inline 1415 void wil_tx_desc_set_nr_frags(struct vring_tx_desc *d, int nr_frags) 1416 { 1417 d->mac.d[2] |= (nr_frags << MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS); 1418 } 1419 1420 /** 1421 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding 1422 * @skb is used to obtain the protocol and headers length. 1423 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data, 1424 * 2 - middle, 3 - last descriptor. 1425 */ 1426 1427 static void wil_tx_desc_offload_setup_tso(struct vring_tx_desc *d, 1428 struct sk_buff *skb, 1429 int tso_desc_type, bool is_ipv4, 1430 int tcp_hdr_len, int skb_net_hdr_len) 1431 { 1432 d->dma.b11 = ETH_HLEN; /* MAC header length */ 1433 d->dma.b11 |= is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS; 1434 1435 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); 1436 /* L4 header len: TCP header length */ 1437 d->dma.d0 |= (tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1438 1439 /* Setup TSO: bit and desc type */ 1440 d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) | 1441 (tso_desc_type << DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS); 1442 d->dma.d0 |= (is_ipv4 << DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS); 1443 1444 d->dma.ip_length = skb_net_hdr_len; 1445 /* Enable TCP/UDP checksum */ 1446 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); 1447 /* Calculate pseudo-header */ 1448 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); 1449 } 1450 1451 /** 1452 * Sets the descriptor @d up for csum. The corresponding 1453 * @skb is used to obtain the protocol and headers length. 1454 * Returns the protocol: 0 - not TCP, 1 - TCPv4, 2 - TCPv6. 1455 * Note, if d==NULL, the function only returns the protocol result. 1456 * 1457 * It is very similar to previous wil_tx_desc_offload_setup_tso. This 1458 * is "if unrolling" to optimize the critical path. 1459 */ 1460 1461 static int wil_tx_desc_offload_setup(struct vring_tx_desc *d, 1462 struct sk_buff *skb){ 1463 int protocol; 1464 1465 if (skb->ip_summed != CHECKSUM_PARTIAL) 1466 return 0; 1467 1468 d->dma.b11 = ETH_HLEN; /* MAC header length */ 1469 1470 switch (skb->protocol) { 1471 case cpu_to_be16(ETH_P_IP): 1472 protocol = ip_hdr(skb)->protocol; 1473 d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS); 1474 break; 1475 case cpu_to_be16(ETH_P_IPV6): 1476 protocol = ipv6_hdr(skb)->nexthdr; 1477 break; 1478 default: 1479 return -EINVAL; 1480 } 1481 1482 switch (protocol) { 1483 case IPPROTO_TCP: 1484 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); 1485 /* L4 header len: TCP header length */ 1486 d->dma.d0 |= 1487 (tcp_hdrlen(skb) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1488 break; 1489 case IPPROTO_UDP: 1490 /* L4 header len: UDP header length */ 1491 d->dma.d0 |= 1492 (sizeof(struct udphdr) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); 1493 break; 1494 default: 1495 return -EINVAL; 1496 } 1497 1498 d->dma.ip_length = skb_network_header_len(skb); 1499 /* Enable TCP/UDP checksum */ 1500 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); 1501 /* Calculate pseudo-header */ 1502 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); 1503 1504 return 0; 1505 } 1506 1507 static inline void wil_tx_last_desc(struct vring_tx_desc *d) 1508 { 1509 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) | 1510 BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS) | 1511 BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); 1512 } 1513 1514 static inline void wil_set_tx_desc_last_tso(volatile struct vring_tx_desc *d) 1515 { 1516 d->dma.d0 |= wil_tso_type_lst << 1517 DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS; 1518 } 1519 1520 static int __wil_tx_vring_tso(struct wil6210_priv *wil, struct wil6210_vif *vif, 1521 struct wil_ring *vring, struct sk_buff *skb) 1522 { 1523 struct device *dev = wil_to_dev(wil); 1524 1525 /* point to descriptors in shared memory */ 1526 volatile struct vring_tx_desc *_desc = NULL, *_hdr_desc, 1527 *_first_desc = NULL; 1528 1529 /* pointers to shadow descriptors */ 1530 struct vring_tx_desc desc_mem, hdr_desc_mem, first_desc_mem, 1531 *d = &hdr_desc_mem, *hdr_desc = &hdr_desc_mem, 1532 *first_desc = &first_desc_mem; 1533 1534 /* pointer to shadow descriptors' context */ 1535 struct wil_ctx *hdr_ctx, *first_ctx = NULL; 1536 1537 int descs_used = 0; /* total number of used descriptors */ 1538 int sg_desc_cnt = 0; /* number of descriptors for current mss*/ 1539 1540 u32 swhead = vring->swhead; 1541 int used, avail = wil_ring_avail_tx(vring); 1542 int nr_frags = skb_shinfo(skb)->nr_frags; 1543 int min_desc_required = nr_frags + 1; 1544 int mss = skb_shinfo(skb)->gso_size; /* payload size w/o headers */ 1545 int f, len, hdrlen, headlen; 1546 int vring_index = vring - wil->ring_tx; 1547 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[vring_index]; 1548 uint i = swhead; 1549 dma_addr_t pa; 1550 const skb_frag_t *frag = NULL; 1551 int rem_data = mss; 1552 int lenmss; 1553 int hdr_compensation_need = true; 1554 int desc_tso_type = wil_tso_type_first; 1555 bool is_ipv4; 1556 int tcp_hdr_len; 1557 int skb_net_hdr_len; 1558 int gso_type; 1559 int rc = -EINVAL; 1560 1561 wil_dbg_txrx(wil, "tx_vring_tso: %d bytes to vring %d\n", skb->len, 1562 vring_index); 1563 1564 if (unlikely(!txdata->enabled)) 1565 return -EINVAL; 1566 1567 /* A typical page 4K is 3-4 payloads, we assume each fragment 1568 * is a full payload, that's how min_desc_required has been 1569 * calculated. In real we might need more or less descriptors, 1570 * this is the initial check only. 1571 */ 1572 if (unlikely(avail < min_desc_required)) { 1573 wil_err_ratelimited(wil, 1574 "TSO: Tx ring[%2d] full. No space for %d fragments\n", 1575 vring_index, min_desc_required); 1576 return -ENOMEM; 1577 } 1578 1579 /* Header Length = MAC header len + IP header len + TCP header len*/ 1580 hdrlen = ETH_HLEN + 1581 (int)skb_network_header_len(skb) + 1582 tcp_hdrlen(skb); 1583 1584 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4); 1585 switch (gso_type) { 1586 case SKB_GSO_TCPV4: 1587 /* TCP v4, zero out the IP length and IPv4 checksum fields 1588 * as required by the offloading doc 1589 */ 1590 ip_hdr(skb)->tot_len = 0; 1591 ip_hdr(skb)->check = 0; 1592 is_ipv4 = true; 1593 break; 1594 case SKB_GSO_TCPV6: 1595 /* TCP v6, zero out the payload length */ 1596 ipv6_hdr(skb)->payload_len = 0; 1597 is_ipv4 = false; 1598 break; 1599 default: 1600 /* other than TCPv4 or TCPv6 types are not supported for TSO. 1601 * It is also illegal for both to be set simultaneously 1602 */ 1603 return -EINVAL; 1604 } 1605 1606 if (skb->ip_summed != CHECKSUM_PARTIAL) 1607 return -EINVAL; 1608 1609 /* tcp header length and skb network header length are fixed for all 1610 * packet's descriptors - read then once here 1611 */ 1612 tcp_hdr_len = tcp_hdrlen(skb); 1613 skb_net_hdr_len = skb_network_header_len(skb); 1614 1615 _hdr_desc = &vring->va[i].tx.legacy; 1616 1617 pa = dma_map_single(dev, skb->data, hdrlen, DMA_TO_DEVICE); 1618 if (unlikely(dma_mapping_error(dev, pa))) { 1619 wil_err(wil, "TSO: Skb head DMA map error\n"); 1620 goto err_exit; 1621 } 1622 1623 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)hdr_desc, pa, 1624 hdrlen, vring_index); 1625 wil_tx_desc_offload_setup_tso(hdr_desc, skb, wil_tso_type_hdr, is_ipv4, 1626 tcp_hdr_len, skb_net_hdr_len); 1627 wil_tx_last_desc(hdr_desc); 1628 1629 vring->ctx[i].mapped_as = wil_mapped_as_single; 1630 hdr_ctx = &vring->ctx[i]; 1631 1632 descs_used++; 1633 headlen = skb_headlen(skb) - hdrlen; 1634 1635 for (f = headlen ? -1 : 0; f < nr_frags; f++) { 1636 if (headlen) { 1637 len = headlen; 1638 wil_dbg_txrx(wil, "TSO: process skb head, len %u\n", 1639 len); 1640 } else { 1641 frag = &skb_shinfo(skb)->frags[f]; 1642 len = frag->size; 1643 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u\n", f, len); 1644 } 1645 1646 while (len) { 1647 wil_dbg_txrx(wil, 1648 "TSO: len %d, rem_data %d, descs_used %d\n", 1649 len, rem_data, descs_used); 1650 1651 if (descs_used == avail) { 1652 wil_err_ratelimited(wil, "TSO: ring overflow\n"); 1653 rc = -ENOMEM; 1654 goto mem_error; 1655 } 1656 1657 lenmss = min_t(int, rem_data, len); 1658 i = (swhead + descs_used) % vring->size; 1659 wil_dbg_txrx(wil, "TSO: lenmss %d, i %d\n", lenmss, i); 1660 1661 if (!headlen) { 1662 pa = skb_frag_dma_map(dev, frag, 1663 frag->size - len, lenmss, 1664 DMA_TO_DEVICE); 1665 vring->ctx[i].mapped_as = wil_mapped_as_page; 1666 } else { 1667 pa = dma_map_single(dev, 1668 skb->data + 1669 skb_headlen(skb) - headlen, 1670 lenmss, 1671 DMA_TO_DEVICE); 1672 vring->ctx[i].mapped_as = wil_mapped_as_single; 1673 headlen -= lenmss; 1674 } 1675 1676 if (unlikely(dma_mapping_error(dev, pa))) { 1677 wil_err(wil, "TSO: DMA map page error\n"); 1678 goto mem_error; 1679 } 1680 1681 _desc = &vring->va[i].tx.legacy; 1682 1683 if (!_first_desc) { 1684 _first_desc = _desc; 1685 first_ctx = &vring->ctx[i]; 1686 d = first_desc; 1687 } else { 1688 d = &desc_mem; 1689 } 1690 1691 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, 1692 pa, lenmss, vring_index); 1693 wil_tx_desc_offload_setup_tso(d, skb, desc_tso_type, 1694 is_ipv4, tcp_hdr_len, 1695 skb_net_hdr_len); 1696 1697 /* use tso_type_first only once */ 1698 desc_tso_type = wil_tso_type_mid; 1699 1700 descs_used++; /* desc used so far */ 1701 sg_desc_cnt++; /* desc used for this segment */ 1702 len -= lenmss; 1703 rem_data -= lenmss; 1704 1705 wil_dbg_txrx(wil, 1706 "TSO: len %d, rem_data %d, descs_used %d, sg_desc_cnt %d,\n", 1707 len, rem_data, descs_used, sg_desc_cnt); 1708 1709 /* Close the segment if reached mss size or last frag*/ 1710 if (rem_data == 0 || (f == nr_frags - 1 && len == 0)) { 1711 if (hdr_compensation_need) { 1712 /* first segment include hdr desc for 1713 * release 1714 */ 1715 hdr_ctx->nr_frags = sg_desc_cnt; 1716 wil_tx_desc_set_nr_frags(first_desc, 1717 sg_desc_cnt + 1718 1); 1719 hdr_compensation_need = false; 1720 } else { 1721 wil_tx_desc_set_nr_frags(first_desc, 1722 sg_desc_cnt); 1723 } 1724 first_ctx->nr_frags = sg_desc_cnt - 1; 1725 1726 wil_tx_last_desc(d); 1727 1728 /* first descriptor may also be the last 1729 * for this mss - make sure not to copy 1730 * it twice 1731 */ 1732 if (first_desc != d) 1733 *_first_desc = *first_desc; 1734 1735 /*last descriptor will be copied at the end 1736 * of this TS processing 1737 */ 1738 if (f < nr_frags - 1 || len > 0) 1739 *_desc = *d; 1740 1741 rem_data = mss; 1742 _first_desc = NULL; 1743 sg_desc_cnt = 0; 1744 } else if (first_desc != d) /* update mid descriptor */ 1745 *_desc = *d; 1746 } 1747 } 1748 1749 /* first descriptor may also be the last. 1750 * in this case d pointer is invalid 1751 */ 1752 if (_first_desc == _desc) 1753 d = first_desc; 1754 1755 /* Last data descriptor */ 1756 wil_set_tx_desc_last_tso(d); 1757 *_desc = *d; 1758 1759 /* Fill the total number of descriptors in first desc (hdr)*/ 1760 wil_tx_desc_set_nr_frags(hdr_desc, descs_used); 1761 *_hdr_desc = *hdr_desc; 1762 1763 /* hold reference to skb 1764 * to prevent skb release before accounting 1765 * in case of immediate "tx done" 1766 */ 1767 vring->ctx[i].skb = skb_get(skb); 1768 1769 /* performance monitoring */ 1770 used = wil_ring_used_tx(vring); 1771 if (wil_val_in_range(wil->ring_idle_trsh, 1772 used, used + descs_used)) { 1773 txdata->idle += get_cycles() - txdata->last_idle; 1774 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1775 vring_index, used, used + descs_used); 1776 } 1777 1778 /* Make sure to advance the head only after descriptor update is done. 1779 * This will prevent a race condition where the completion thread 1780 * will see the DU bit set from previous run and will handle the 1781 * skb before it was completed. 1782 */ 1783 wmb(); 1784 1785 /* advance swhead */ 1786 wil_ring_advance_head(vring, descs_used); 1787 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, vring->swhead); 1788 1789 /* make sure all writes to descriptors (shared memory) are done before 1790 * committing them to HW 1791 */ 1792 wmb(); 1793 1794 if (wil->tx_latency) 1795 *(ktime_t *)&skb->cb = ktime_get(); 1796 else 1797 memset(skb->cb, 0, sizeof(ktime_t)); 1798 1799 wil_w(wil, vring->hwtail, vring->swhead); 1800 return 0; 1801 1802 mem_error: 1803 while (descs_used > 0) { 1804 struct wil_ctx *ctx; 1805 1806 i = (swhead + descs_used - 1) % vring->size; 1807 d = (struct vring_tx_desc *)&vring->va[i].tx.legacy; 1808 _desc = &vring->va[i].tx.legacy; 1809 *d = *_desc; 1810 _desc->dma.status = TX_DMA_STATUS_DU; 1811 ctx = &vring->ctx[i]; 1812 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx); 1813 memset(ctx, 0, sizeof(*ctx)); 1814 descs_used--; 1815 } 1816 err_exit: 1817 return rc; 1818 } 1819 1820 static int __wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1821 struct wil_ring *ring, struct sk_buff *skb) 1822 { 1823 struct device *dev = wil_to_dev(wil); 1824 struct vring_tx_desc dd, *d = ⅆ 1825 volatile struct vring_tx_desc *_d; 1826 u32 swhead = ring->swhead; 1827 int avail = wil_ring_avail_tx(ring); 1828 int nr_frags = skb_shinfo(skb)->nr_frags; 1829 uint f = 0; 1830 int ring_index = ring - wil->ring_tx; 1831 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1832 uint i = swhead; 1833 dma_addr_t pa; 1834 int used; 1835 bool mcast = (ring_index == vif->bcast_ring); 1836 uint len = skb_headlen(skb); 1837 1838 wil_dbg_txrx(wil, "tx_ring: %d bytes to ring %d, nr_frags %d\n", 1839 skb->len, ring_index, nr_frags); 1840 1841 if (unlikely(!txdata->enabled)) 1842 return -EINVAL; 1843 1844 if (unlikely(avail < 1 + nr_frags)) { 1845 wil_err_ratelimited(wil, 1846 "Tx ring[%2d] full. No space for %d fragments\n", 1847 ring_index, 1 + nr_frags); 1848 return -ENOMEM; 1849 } 1850 _d = &ring->va[i].tx.legacy; 1851 1852 pa = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE); 1853 1854 wil_dbg_txrx(wil, "Tx[%2d] skb %d bytes 0x%p -> %pad\n", ring_index, 1855 skb_headlen(skb), skb->data, &pa); 1856 wil_hex_dump_txrx("Tx ", DUMP_PREFIX_OFFSET, 16, 1, 1857 skb->data, skb_headlen(skb), false); 1858 1859 if (unlikely(dma_mapping_error(dev, pa))) 1860 return -EINVAL; 1861 ring->ctx[i].mapped_as = wil_mapped_as_single; 1862 /* 1-st segment */ 1863 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, len, 1864 ring_index); 1865 if (unlikely(mcast)) { 1866 d->mac.d[0] |= BIT(MAC_CFG_DESC_TX_0_MCS_EN_POS); /* MCS 0 */ 1867 if (unlikely(len > WIL_BCAST_MCS0_LIMIT)) /* set MCS 1 */ 1868 d->mac.d[0] |= (1 << MAC_CFG_DESC_TX_0_MCS_INDEX_POS); 1869 } 1870 /* Process TCP/UDP checksum offloading */ 1871 if (unlikely(wil_tx_desc_offload_setup(d, skb))) { 1872 wil_err(wil, "Tx[%2d] Failed to set cksum, drop packet\n", 1873 ring_index); 1874 goto dma_error; 1875 } 1876 1877 ring->ctx[i].nr_frags = nr_frags; 1878 wil_tx_desc_set_nr_frags(d, nr_frags + 1); 1879 1880 /* middle segments */ 1881 for (; f < nr_frags; f++) { 1882 const struct skb_frag_struct *frag = 1883 &skb_shinfo(skb)->frags[f]; 1884 int len = skb_frag_size(frag); 1885 1886 *_d = *d; 1887 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i); 1888 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1889 (const void *)d, sizeof(*d), false); 1890 i = (swhead + f + 1) % ring->size; 1891 _d = &ring->va[i].tx.legacy; 1892 pa = skb_frag_dma_map(dev, frag, 0, skb_frag_size(frag), 1893 DMA_TO_DEVICE); 1894 if (unlikely(dma_mapping_error(dev, pa))) { 1895 wil_err(wil, "Tx[%2d] failed to map fragment\n", 1896 ring_index); 1897 goto dma_error; 1898 } 1899 ring->ctx[i].mapped_as = wil_mapped_as_page; 1900 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, 1901 pa, len, ring_index); 1902 /* no need to check return code - 1903 * if it succeeded for 1-st descriptor, 1904 * it will succeed here too 1905 */ 1906 wil_tx_desc_offload_setup(d, skb); 1907 } 1908 /* for the last seg only */ 1909 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS); 1910 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS); 1911 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); 1912 *_d = *d; 1913 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i); 1914 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4, 1915 (const void *)d, sizeof(*d), false); 1916 1917 /* hold reference to skb 1918 * to prevent skb release before accounting 1919 * in case of immediate "tx done" 1920 */ 1921 ring->ctx[i].skb = skb_get(skb); 1922 1923 /* performance monitoring */ 1924 used = wil_ring_used_tx(ring); 1925 if (wil_val_in_range(wil->ring_idle_trsh, 1926 used, used + nr_frags + 1)) { 1927 txdata->idle += get_cycles() - txdata->last_idle; 1928 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n", 1929 ring_index, used, used + nr_frags + 1); 1930 } 1931 1932 /* Make sure to advance the head only after descriptor update is done. 1933 * This will prevent a race condition where the completion thread 1934 * will see the DU bit set from previous run and will handle the 1935 * skb before it was completed. 1936 */ 1937 wmb(); 1938 1939 /* advance swhead */ 1940 wil_ring_advance_head(ring, nr_frags + 1); 1941 wil_dbg_txrx(wil, "Tx[%2d] swhead %d -> %d\n", ring_index, swhead, 1942 ring->swhead); 1943 trace_wil6210_tx(ring_index, swhead, skb->len, nr_frags); 1944 1945 /* make sure all writes to descriptors (shared memory) are done before 1946 * committing them to HW 1947 */ 1948 wmb(); 1949 1950 if (wil->tx_latency) 1951 *(ktime_t *)&skb->cb = ktime_get(); 1952 else 1953 memset(skb->cb, 0, sizeof(ktime_t)); 1954 1955 wil_w(wil, ring->hwtail, ring->swhead); 1956 1957 return 0; 1958 dma_error: 1959 /* unmap what we have mapped */ 1960 nr_frags = f + 1; /* frags mapped + one for skb head */ 1961 for (f = 0; f < nr_frags; f++) { 1962 struct wil_ctx *ctx; 1963 1964 i = (swhead + f) % ring->size; 1965 ctx = &ring->ctx[i]; 1966 _d = &ring->va[i].tx.legacy; 1967 *d = *_d; 1968 _d->dma.status = TX_DMA_STATUS_DU; 1969 wil->txrx_ops.tx_desc_unmap(dev, 1970 (union wil_tx_desc *)d, 1971 ctx); 1972 1973 memset(ctx, 0, sizeof(*ctx)); 1974 } 1975 1976 return -EINVAL; 1977 } 1978 1979 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif, 1980 struct wil_ring *ring, struct sk_buff *skb) 1981 { 1982 int ring_index = ring - wil->ring_tx; 1983 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index]; 1984 int rc; 1985 1986 spin_lock(&txdata->lock); 1987 1988 if (test_bit(wil_status_suspending, wil->status) || 1989 test_bit(wil_status_suspended, wil->status) || 1990 test_bit(wil_status_resuming, wil->status)) { 1991 wil_dbg_txrx(wil, 1992 "suspend/resume in progress. drop packet\n"); 1993 spin_unlock(&txdata->lock); 1994 return -EINVAL; 1995 } 1996 1997 rc = (skb_is_gso(skb) ? wil->txrx_ops.tx_ring_tso : __wil_tx_ring) 1998 (wil, vif, ring, skb); 1999 2000 spin_unlock(&txdata->lock); 2001 2002 return rc; 2003 } 2004 2005 /** 2006 * Check status of tx vrings and stop/wake net queues if needed 2007 * It will start/stop net queues of a specific VIF net_device. 2008 * 2009 * This function does one of two checks: 2010 * In case check_stop is true, will check if net queues need to be stopped. If 2011 * the conditions for stopping are met, netif_tx_stop_all_queues() is called. 2012 * In case check_stop is false, will check if net queues need to be waked. If 2013 * the conditions for waking are met, netif_tx_wake_all_queues() is called. 2014 * vring is the vring which is currently being modified by either adding 2015 * descriptors (tx) into it or removing descriptors (tx complete) from it. Can 2016 * be null when irrelevant (e.g. connect/disconnect events). 2017 * 2018 * The implementation is to stop net queues if modified vring has low 2019 * descriptor availability. Wake if all vrings are not in low descriptor 2020 * availability and modified vring has high descriptor availability. 2021 */ 2022 static inline void __wil_update_net_queues(struct wil6210_priv *wil, 2023 struct wil6210_vif *vif, 2024 struct wil_ring *ring, 2025 bool check_stop) 2026 { 2027 int i; 2028 int min_ring_id = wil_get_min_tx_ring_id(wil); 2029 2030 if (unlikely(!vif)) 2031 return; 2032 2033 if (ring) 2034 wil_dbg_txrx(wil, "vring %d, mid %d, check_stop=%d, stopped=%d", 2035 (int)(ring - wil->ring_tx), vif->mid, check_stop, 2036 vif->net_queue_stopped); 2037 else 2038 wil_dbg_txrx(wil, "check_stop=%d, mid=%d, stopped=%d", 2039 check_stop, vif->mid, vif->net_queue_stopped); 2040 2041 if (check_stop == vif->net_queue_stopped) 2042 /* net queues already in desired state */ 2043 return; 2044 2045 if (check_stop) { 2046 if (!ring || unlikely(wil_ring_avail_low(ring))) { 2047 /* not enough room in the vring */ 2048 netif_tx_stop_all_queues(vif_to_ndev(vif)); 2049 vif->net_queue_stopped = true; 2050 wil_dbg_txrx(wil, "netif_tx_stop called\n"); 2051 } 2052 return; 2053 } 2054 2055 /* Do not wake the queues in suspend flow */ 2056 if (test_bit(wil_status_suspending, wil->status) || 2057 test_bit(wil_status_suspended, wil->status)) 2058 return; 2059 2060 /* check wake */ 2061 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 2062 struct wil_ring *cur_ring = &wil->ring_tx[i]; 2063 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i]; 2064 2065 if (txdata->mid != vif->mid || !cur_ring->va || 2066 !txdata->enabled || cur_ring == ring) 2067 continue; 2068 2069 if (wil_ring_avail_low(cur_ring)) { 2070 wil_dbg_txrx(wil, "ring %d full, can't wake\n", 2071 (int)(cur_ring - wil->ring_tx)); 2072 return; 2073 } 2074 } 2075 2076 if (!ring || wil_ring_avail_high(ring)) { 2077 /* enough room in the ring */ 2078 wil_dbg_txrx(wil, "calling netif_tx_wake\n"); 2079 netif_tx_wake_all_queues(vif_to_ndev(vif)); 2080 vif->net_queue_stopped = false; 2081 } 2082 } 2083 2084 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif, 2085 struct wil_ring *ring, bool check_stop) 2086 { 2087 spin_lock(&wil->net_queue_lock); 2088 __wil_update_net_queues(wil, vif, ring, check_stop); 2089 spin_unlock(&wil->net_queue_lock); 2090 } 2091 2092 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif, 2093 struct wil_ring *ring, bool check_stop) 2094 { 2095 spin_lock_bh(&wil->net_queue_lock); 2096 __wil_update_net_queues(wil, vif, ring, check_stop); 2097 spin_unlock_bh(&wil->net_queue_lock); 2098 } 2099 2100 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2101 { 2102 struct wil6210_vif *vif = ndev_to_vif(ndev); 2103 struct wil6210_priv *wil = vif_to_wil(vif); 2104 struct ethhdr *eth = (void *)skb->data; 2105 bool bcast = is_multicast_ether_addr(eth->h_dest); 2106 struct wil_ring *ring; 2107 static bool pr_once_fw; 2108 int rc; 2109 2110 wil_dbg_txrx(wil, "start_xmit\n"); 2111 if (unlikely(!test_bit(wil_status_fwready, wil->status))) { 2112 if (!pr_once_fw) { 2113 wil_err(wil, "FW not ready\n"); 2114 pr_once_fw = true; 2115 } 2116 goto drop; 2117 } 2118 if (unlikely(!test_bit(wil_vif_fwconnected, vif->status))) { 2119 wil_dbg_ratelimited(wil, 2120 "VIF not connected, packet dropped\n"); 2121 goto drop; 2122 } 2123 if (unlikely(vif->wdev.iftype == NL80211_IFTYPE_MONITOR)) { 2124 wil_err(wil, "Xmit in monitor mode not supported\n"); 2125 goto drop; 2126 } 2127 pr_once_fw = false; 2128 2129 /* find vring */ 2130 if (vif->wdev.iftype == NL80211_IFTYPE_STATION && !vif->pbss) { 2131 /* in STA mode (ESS), all to same VRING (to AP) */ 2132 ring = wil_find_tx_ring_sta(wil, vif, skb); 2133 } else if (bcast) { 2134 if (vif->pbss) 2135 /* in pbss, no bcast VRING - duplicate skb in 2136 * all stations VRINGs 2137 */ 2138 ring = wil_find_tx_bcast_2(wil, vif, skb); 2139 else if (vif->wdev.iftype == NL80211_IFTYPE_AP) 2140 /* AP has a dedicated bcast VRING */ 2141 ring = wil_find_tx_bcast_1(wil, vif, skb); 2142 else 2143 /* unexpected combination, fallback to duplicating 2144 * the skb in all stations VRINGs 2145 */ 2146 ring = wil_find_tx_bcast_2(wil, vif, skb); 2147 } else { 2148 /* unicast, find specific VRING by dest. address */ 2149 ring = wil_find_tx_ucast(wil, vif, skb); 2150 } 2151 if (unlikely(!ring)) { 2152 wil_dbg_txrx(wil, "No Tx RING found for %pM\n", eth->h_dest); 2153 goto drop; 2154 } 2155 /* set up vring entry */ 2156 rc = wil_tx_ring(wil, vif, ring, skb); 2157 2158 switch (rc) { 2159 case 0: 2160 /* shall we stop net queues? */ 2161 wil_update_net_queues_bh(wil, vif, ring, true); 2162 /* statistics will be updated on the tx_complete */ 2163 dev_kfree_skb_any(skb); 2164 return NETDEV_TX_OK; 2165 case -ENOMEM: 2166 return NETDEV_TX_BUSY; 2167 default: 2168 break; /* goto drop; */ 2169 } 2170 drop: 2171 ndev->stats.tx_dropped++; 2172 dev_kfree_skb_any(skb); 2173 2174 return NET_XMIT_DROP; 2175 } 2176 2177 void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb, 2178 struct wil_sta_info *sta) 2179 { 2180 int skb_time_us; 2181 int bin; 2182 2183 if (!wil->tx_latency) 2184 return; 2185 2186 if (ktime_to_ms(*(ktime_t *)&skb->cb) == 0) 2187 return; 2188 2189 skb_time_us = ktime_us_delta(ktime_get(), *(ktime_t *)&skb->cb); 2190 bin = skb_time_us / wil->tx_latency_res; 2191 bin = min_t(int, bin, WIL_NUM_LATENCY_BINS - 1); 2192 2193 wil_dbg_txrx(wil, "skb time %dus => bin %d\n", skb_time_us, bin); 2194 sta->tx_latency_bins[bin]++; 2195 sta->stats.tx_latency_total_us += skb_time_us; 2196 if (skb_time_us < sta->stats.tx_latency_min_us) 2197 sta->stats.tx_latency_min_us = skb_time_us; 2198 if (skb_time_us > sta->stats.tx_latency_max_us) 2199 sta->stats.tx_latency_max_us = skb_time_us; 2200 } 2201 2202 /** 2203 * Clean up transmitted skb's from the Tx VRING 2204 * 2205 * Return number of descriptors cleared 2206 * 2207 * Safe to call from IRQ 2208 */ 2209 int wil_tx_complete(struct wil6210_vif *vif, int ringid) 2210 { 2211 struct wil6210_priv *wil = vif_to_wil(vif); 2212 struct net_device *ndev = vif_to_ndev(vif); 2213 struct device *dev = wil_to_dev(wil); 2214 struct wil_ring *vring = &wil->ring_tx[ringid]; 2215 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ringid]; 2216 int done = 0; 2217 int cid = wil->ring2cid_tid[ringid][0]; 2218 struct wil_net_stats *stats = NULL; 2219 volatile struct vring_tx_desc *_d; 2220 int used_before_complete; 2221 int used_new; 2222 2223 if (unlikely(!vring->va)) { 2224 wil_err(wil, "Tx irq[%d]: vring not initialized\n", ringid); 2225 return 0; 2226 } 2227 2228 if (unlikely(!txdata->enabled)) { 2229 wil_info(wil, "Tx irq[%d]: vring disabled\n", ringid); 2230 return 0; 2231 } 2232 2233 wil_dbg_txrx(wil, "tx_complete: (%d)\n", ringid); 2234 2235 used_before_complete = wil_ring_used_tx(vring); 2236 2237 if (cid < WIL6210_MAX_CID) 2238 stats = &wil->sta[cid].stats; 2239 2240 while (!wil_ring_is_empty(vring)) { 2241 int new_swtail; 2242 struct wil_ctx *ctx = &vring->ctx[vring->swtail]; 2243 /** 2244 * For the fragmented skb, HW will set DU bit only for the 2245 * last fragment. look for it. 2246 * In TSO the first DU will include hdr desc 2247 */ 2248 int lf = (vring->swtail + ctx->nr_frags) % vring->size; 2249 /* TODO: check we are not past head */ 2250 2251 _d = &vring->va[lf].tx.legacy; 2252 if (unlikely(!(_d->dma.status & TX_DMA_STATUS_DU))) 2253 break; 2254 2255 new_swtail = (lf + 1) % vring->size; 2256 while (vring->swtail != new_swtail) { 2257 struct vring_tx_desc dd, *d = ⅆ 2258 u16 dmalen; 2259 struct sk_buff *skb; 2260 2261 ctx = &vring->ctx[vring->swtail]; 2262 skb = ctx->skb; 2263 _d = &vring->va[vring->swtail].tx.legacy; 2264 2265 *d = *_d; 2266 2267 dmalen = le16_to_cpu(d->dma.length); 2268 trace_wil6210_tx_done(ringid, vring->swtail, dmalen, 2269 d->dma.error); 2270 wil_dbg_txrx(wil, 2271 "TxC[%2d][%3d] : %d bytes, status 0x%02x err 0x%02x\n", 2272 ringid, vring->swtail, dmalen, 2273 d->dma.status, d->dma.error); 2274 wil_hex_dump_txrx("TxCD ", DUMP_PREFIX_NONE, 32, 4, 2275 (const void *)d, sizeof(*d), false); 2276 2277 wil->txrx_ops.tx_desc_unmap(dev, 2278 (union wil_tx_desc *)d, 2279 ctx); 2280 2281 if (skb) { 2282 if (likely(d->dma.error == 0)) { 2283 ndev->stats.tx_packets++; 2284 ndev->stats.tx_bytes += skb->len; 2285 if (stats) { 2286 stats->tx_packets++; 2287 stats->tx_bytes += skb->len; 2288 2289 wil_tx_latency_calc(wil, skb, 2290 &wil->sta[cid]); 2291 } 2292 } else { 2293 ndev->stats.tx_errors++; 2294 if (stats) 2295 stats->tx_errors++; 2296 } 2297 wil_consume_skb(skb, d->dma.error == 0); 2298 } 2299 memset(ctx, 0, sizeof(*ctx)); 2300 /* Make sure the ctx is zeroed before updating the tail 2301 * to prevent a case where wil_tx_ring will see 2302 * this descriptor as used and handle it before ctx zero 2303 * is completed. 2304 */ 2305 wmb(); 2306 /* There is no need to touch HW descriptor: 2307 * - ststus bit TX_DMA_STATUS_DU is set by design, 2308 * so hardware will not try to process this desc., 2309 * - rest of descriptor will be initialized on Tx. 2310 */ 2311 vring->swtail = wil_ring_next_tail(vring); 2312 done++; 2313 } 2314 } 2315 2316 /* performance monitoring */ 2317 used_new = wil_ring_used_tx(vring); 2318 if (wil_val_in_range(wil->ring_idle_trsh, 2319 used_new, used_before_complete)) { 2320 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n", 2321 ringid, used_before_complete, used_new); 2322 txdata->last_idle = get_cycles(); 2323 } 2324 2325 /* shall we wake net queues? */ 2326 if (done) 2327 wil_update_net_queues(wil, vif, vring, false); 2328 2329 return done; 2330 } 2331 2332 static inline int wil_tx_init(struct wil6210_priv *wil) 2333 { 2334 return 0; 2335 } 2336 2337 static inline void wil_tx_fini(struct wil6210_priv *wil) {} 2338 2339 static void wil_get_reorder_params(struct wil6210_priv *wil, 2340 struct sk_buff *skb, int *tid, int *cid, 2341 int *mid, u16 *seq, int *mcast, int *retry) 2342 { 2343 struct vring_rx_desc *d = wil_skb_rxdesc(skb); 2344 2345 *tid = wil_rxdesc_tid(d); 2346 *cid = wil_rxdesc_cid(d); 2347 *mid = wil_rxdesc_mid(d); 2348 *seq = wil_rxdesc_seq(d); 2349 *mcast = wil_rxdesc_mcast(d); 2350 *retry = wil_rxdesc_retry(d); 2351 } 2352 2353 void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil) 2354 { 2355 wil->txrx_ops.configure_interrupt_moderation = 2356 wil_configure_interrupt_moderation; 2357 /* TX ops */ 2358 wil->txrx_ops.tx_desc_map = wil_tx_desc_map; 2359 wil->txrx_ops.tx_desc_unmap = wil_txdesc_unmap; 2360 wil->txrx_ops.tx_ring_tso = __wil_tx_vring_tso; 2361 wil->txrx_ops.ring_init_tx = wil_vring_init_tx; 2362 wil->txrx_ops.ring_fini_tx = wil_vring_free; 2363 wil->txrx_ops.ring_init_bcast = wil_vring_init_bcast; 2364 wil->txrx_ops.tx_init = wil_tx_init; 2365 wil->txrx_ops.tx_fini = wil_tx_fini; 2366 wil->txrx_ops.tx_ring_modify = wil_tx_vring_modify; 2367 /* RX ops */ 2368 wil->txrx_ops.rx_init = wil_rx_init; 2369 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp; 2370 wil->txrx_ops.get_reorder_params = wil_get_reorder_params; 2371 wil->txrx_ops.get_netif_rx_params = 2372 wil_get_netif_rx_params; 2373 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check; 2374 wil->txrx_ops.rx_error_check = wil_rx_error_check; 2375 wil->txrx_ops.is_rx_idle = wil_is_rx_idle; 2376 wil->txrx_ops.rx_fini = wil_rx_fini; 2377 } 2378