1 /* 2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc. 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <linux/moduleparam.h> 19 #include <linux/if_arp.h> 20 #include <linux/etherdevice.h> 21 22 #include "wil6210.h" 23 #include "txrx.h" 24 #include "txrx_edma.h" 25 #include "wmi.h" 26 #include "boot_loader.h" 27 28 #define WAIT_FOR_HALP_VOTE_MS 100 29 #define WAIT_FOR_SCAN_ABORT_MS 1000 30 #define WIL_DEFAULT_NUM_RX_STATUS_RINGS 1 31 #define WIL_BOARD_FILE_MAX_NAMELEN 128 32 33 bool debug_fw; /* = false; */ 34 module_param(debug_fw, bool, 0444); 35 MODULE_PARM_DESC(debug_fw, " do not perform card reset. For FW debug"); 36 37 static u8 oob_mode; 38 module_param(oob_mode, byte, 0444); 39 MODULE_PARM_DESC(oob_mode, 40 " enable out of the box (OOB) mode in FW, for diagnostics and certification"); 41 42 bool no_fw_recovery; 43 module_param(no_fw_recovery, bool, 0644); 44 MODULE_PARM_DESC(no_fw_recovery, " disable automatic FW error recovery"); 45 46 /* if not set via modparam, will be set to default value of 1/8 of 47 * rx ring size during init flow 48 */ 49 unsigned short rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_INIT; 50 module_param(rx_ring_overflow_thrsh, ushort, 0444); 51 MODULE_PARM_DESC(rx_ring_overflow_thrsh, 52 " RX ring overflow threshold in descriptors."); 53 54 /* We allow allocation of more than 1 page buffers to support large packets. 55 * It is suboptimal behavior performance wise in case MTU above page size. 56 */ 57 unsigned int mtu_max = TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD; 58 static int mtu_max_set(const char *val, const struct kernel_param *kp) 59 { 60 int ret; 61 62 /* sets mtu_max directly. no need to restore it in case of 63 * illegal value since we assume this will fail insmod 64 */ 65 ret = param_set_uint(val, kp); 66 if (ret) 67 return ret; 68 69 if (mtu_max < 68 || mtu_max > WIL_MAX_ETH_MTU) 70 ret = -EINVAL; 71 72 return ret; 73 } 74 75 static const struct kernel_param_ops mtu_max_ops = { 76 .set = mtu_max_set, 77 .get = param_get_uint, 78 }; 79 80 module_param_cb(mtu_max, &mtu_max_ops, &mtu_max, 0444); 81 MODULE_PARM_DESC(mtu_max, " Max MTU value."); 82 83 static uint rx_ring_order = WIL_RX_RING_SIZE_ORDER_DEFAULT; 84 static uint tx_ring_order = WIL_TX_RING_SIZE_ORDER_DEFAULT; 85 static uint bcast_ring_order = WIL_BCAST_RING_SIZE_ORDER_DEFAULT; 86 87 static int ring_order_set(const char *val, const struct kernel_param *kp) 88 { 89 int ret; 90 uint x; 91 92 ret = kstrtouint(val, 0, &x); 93 if (ret) 94 return ret; 95 96 if ((x < WIL_RING_SIZE_ORDER_MIN) || (x > WIL_RING_SIZE_ORDER_MAX)) 97 return -EINVAL; 98 99 *((uint *)kp->arg) = x; 100 101 return 0; 102 } 103 104 static const struct kernel_param_ops ring_order_ops = { 105 .set = ring_order_set, 106 .get = param_get_uint, 107 }; 108 109 module_param_cb(rx_ring_order, &ring_order_ops, &rx_ring_order, 0444); 110 MODULE_PARM_DESC(rx_ring_order, " Rx ring order; size = 1 << order"); 111 module_param_cb(tx_ring_order, &ring_order_ops, &tx_ring_order, 0444); 112 MODULE_PARM_DESC(tx_ring_order, " Tx ring order; size = 1 << order"); 113 module_param_cb(bcast_ring_order, &ring_order_ops, &bcast_ring_order, 0444); 114 MODULE_PARM_DESC(bcast_ring_order, " Bcast ring order; size = 1 << order"); 115 116 enum { 117 WIL_BOOT_ERR, 118 WIL_BOOT_VANILLA, 119 WIL_BOOT_PRODUCTION, 120 WIL_BOOT_DEVELOPMENT, 121 }; 122 123 enum { 124 WIL_SIG_STATUS_VANILLA = 0x0, 125 WIL_SIG_STATUS_DEVELOPMENT = 0x1, 126 WIL_SIG_STATUS_PRODUCTION = 0x2, 127 WIL_SIG_STATUS_CORRUPTED_PRODUCTION = 0x3, 128 }; 129 130 #define RST_DELAY (20) /* msec, for loop in @wil_wait_device_ready */ 131 #define RST_COUNT (1 + 1000/RST_DELAY) /* round up to be above 1 sec total */ 132 133 #define PMU_READY_DELAY_MS (4) /* ms, for sleep in @wil_wait_device_ready */ 134 135 #define OTP_HW_DELAY (200) /* usec, loop in @wil_wait_device_ready_talyn_mb */ 136 /* round up to be above 2 ms total */ 137 #define OTP_HW_COUNT (1 + 2000 / OTP_HW_DELAY) 138 139 /* 140 * Due to a hardware issue, 141 * one has to read/write to/from NIC in 32-bit chunks; 142 * regular memcpy_fromio and siblings will 143 * not work on 64-bit platform - it uses 64-bit transactions 144 * 145 * Force 32-bit transactions to enable NIC on 64-bit platforms 146 * 147 * To avoid byte swap on big endian host, __raw_{read|write}l 148 * should be used - {read|write}l would swap bytes to provide 149 * little endian on PCI value in host endianness. 150 */ 151 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src, 152 size_t count) 153 { 154 u32 *d = dst; 155 const volatile u32 __iomem *s = src; 156 157 for (; count >= 4; count -= 4) 158 *d++ = __raw_readl(s++); 159 160 if (unlikely(count)) { 161 /* count can be 1..3 */ 162 u32 tmp = __raw_readl(s); 163 164 memcpy(d, &tmp, count); 165 } 166 } 167 168 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src, 169 size_t count) 170 { 171 volatile u32 __iomem *d = dst; 172 const u32 *s = src; 173 174 for (; count >= 4; count -= 4) 175 __raw_writel(*s++, d++); 176 177 if (unlikely(count)) { 178 /* count can be 1..3 */ 179 u32 tmp = 0; 180 181 memcpy(&tmp, s, count); 182 __raw_writel(tmp, d); 183 } 184 } 185 186 static void wil_ring_fini_tx(struct wil6210_priv *wil, int id) 187 { 188 struct wil_ring *ring = &wil->ring_tx[id]; 189 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id]; 190 191 lockdep_assert_held(&wil->mutex); 192 193 if (!ring->va) 194 return; 195 196 wil_dbg_misc(wil, "vring_fini_tx: id=%d\n", id); 197 198 spin_lock_bh(&txdata->lock); 199 txdata->dot1x_open = false; 200 txdata->mid = U8_MAX; 201 txdata->enabled = 0; /* no Tx can be in progress or start anew */ 202 spin_unlock_bh(&txdata->lock); 203 /* napi_synchronize waits for completion of the current NAPI but will 204 * not prevent the next NAPI run. 205 * Add a memory barrier to guarantee that txdata->enabled is zeroed 206 * before napi_synchronize so that the next scheduled NAPI will not 207 * handle this vring 208 */ 209 wmb(); 210 /* make sure NAPI won't touch this vring */ 211 if (test_bit(wil_status_napi_en, wil->status)) 212 napi_synchronize(&wil->napi_tx); 213 214 wil->txrx_ops.ring_fini_tx(wil, ring); 215 } 216 217 static void wil_disconnect_cid(struct wil6210_vif *vif, int cid, 218 u16 reason_code, bool from_event) 219 __acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock) 220 { 221 uint i; 222 struct wil6210_priv *wil = vif_to_wil(vif); 223 struct net_device *ndev = vif_to_ndev(vif); 224 struct wireless_dev *wdev = vif_to_wdev(vif); 225 struct wil_sta_info *sta = &wil->sta[cid]; 226 int min_ring_id = wil_get_min_tx_ring_id(wil); 227 228 might_sleep(); 229 wil_dbg_misc(wil, "disconnect_cid: CID %d, MID %d, status %d\n", 230 cid, sta->mid, sta->status); 231 /* inform upper/lower layers */ 232 if (sta->status != wil_sta_unused) { 233 if (vif->mid != sta->mid) { 234 wil_err(wil, "STA MID mismatch with VIF MID(%d)\n", 235 vif->mid); 236 /* let FW override sta->mid but be more strict with 237 * user space requests 238 */ 239 if (!from_event) 240 return; 241 } 242 if (!from_event) { 243 bool del_sta = (wdev->iftype == NL80211_IFTYPE_AP) ? 244 disable_ap_sme : false; 245 wmi_disconnect_sta(vif, sta->addr, reason_code, 246 true, del_sta); 247 } 248 249 switch (wdev->iftype) { 250 case NL80211_IFTYPE_AP: 251 case NL80211_IFTYPE_P2P_GO: 252 /* AP-like interface */ 253 cfg80211_del_sta(ndev, sta->addr, GFP_KERNEL); 254 break; 255 default: 256 break; 257 } 258 sta->status = wil_sta_unused; 259 sta->mid = U8_MAX; 260 } 261 /* reorder buffers */ 262 for (i = 0; i < WIL_STA_TID_NUM; i++) { 263 struct wil_tid_ampdu_rx *r; 264 265 spin_lock_bh(&sta->tid_rx_lock); 266 267 r = sta->tid_rx[i]; 268 sta->tid_rx[i] = NULL; 269 wil_tid_ampdu_rx_free(wil, r); 270 271 spin_unlock_bh(&sta->tid_rx_lock); 272 } 273 /* crypto context */ 274 memset(sta->tid_crypto_rx, 0, sizeof(sta->tid_crypto_rx)); 275 memset(&sta->group_crypto_rx, 0, sizeof(sta->group_crypto_rx)); 276 /* release vrings */ 277 for (i = min_ring_id; i < ARRAY_SIZE(wil->ring_tx); i++) { 278 if (wil->ring2cid_tid[i][0] == cid) 279 wil_ring_fini_tx(wil, i); 280 } 281 /* statistics */ 282 memset(&sta->stats, 0, sizeof(sta->stats)); 283 sta->stats.tx_latency_min_us = U32_MAX; 284 } 285 286 static bool wil_vif_is_connected(struct wil6210_priv *wil, u8 mid) 287 { 288 int i; 289 290 for (i = 0; i < ARRAY_SIZE(wil->sta); i++) { 291 if (wil->sta[i].mid == mid && 292 wil->sta[i].status == wil_sta_connected) 293 return true; 294 } 295 296 return false; 297 } 298 299 static void _wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 300 u16 reason_code, bool from_event) 301 { 302 struct wil6210_priv *wil = vif_to_wil(vif); 303 int cid = -ENOENT; 304 struct net_device *ndev; 305 struct wireless_dev *wdev; 306 307 if (unlikely(!vif)) 308 return; 309 310 ndev = vif_to_ndev(vif); 311 wdev = vif_to_wdev(vif); 312 313 might_sleep(); 314 wil_info(wil, "bssid=%pM, reason=%d, ev%s\n", bssid, 315 reason_code, from_event ? "+" : "-"); 316 317 /* Cases are: 318 * - disconnect single STA, still connected 319 * - disconnect single STA, already disconnected 320 * - disconnect all 321 * 322 * For "disconnect all", there are 3 options: 323 * - bssid == NULL 324 * - bssid is broadcast address (ff:ff:ff:ff:ff:ff) 325 * - bssid is our MAC address 326 */ 327 if (bssid && !is_broadcast_ether_addr(bssid) && 328 !ether_addr_equal_unaligned(ndev->dev_addr, bssid)) { 329 cid = wil_find_cid(wil, vif->mid, bssid); 330 wil_dbg_misc(wil, "Disconnect %pM, CID=%d, reason=%d\n", 331 bssid, cid, reason_code); 332 if (cid >= 0) /* disconnect 1 peer */ 333 wil_disconnect_cid(vif, cid, reason_code, from_event); 334 } else { /* all */ 335 wil_dbg_misc(wil, "Disconnect all\n"); 336 for (cid = 0; cid < WIL6210_MAX_CID; cid++) 337 wil_disconnect_cid(vif, cid, reason_code, from_event); 338 } 339 340 /* link state */ 341 switch (wdev->iftype) { 342 case NL80211_IFTYPE_STATION: 343 case NL80211_IFTYPE_P2P_CLIENT: 344 wil_bcast_fini(vif); 345 wil_update_net_queues_bh(wil, vif, NULL, true); 346 netif_carrier_off(ndev); 347 if (!wil_has_other_active_ifaces(wil, ndev, false, true)) 348 wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS); 349 350 if (test_and_clear_bit(wil_vif_fwconnected, vif->status)) { 351 atomic_dec(&wil->connected_vifs); 352 cfg80211_disconnected(ndev, reason_code, 353 NULL, 0, 354 vif->locally_generated_disc, 355 GFP_KERNEL); 356 vif->locally_generated_disc = false; 357 } else if (test_bit(wil_vif_fwconnecting, vif->status)) { 358 cfg80211_connect_result(ndev, bssid, NULL, 0, NULL, 0, 359 WLAN_STATUS_UNSPECIFIED_FAILURE, 360 GFP_KERNEL); 361 vif->bss = NULL; 362 } 363 clear_bit(wil_vif_fwconnecting, vif->status); 364 clear_bit(wil_vif_ft_roam, vif->status); 365 366 break; 367 case NL80211_IFTYPE_AP: 368 case NL80211_IFTYPE_P2P_GO: 369 if (!wil_vif_is_connected(wil, vif->mid)) { 370 wil_update_net_queues_bh(wil, vif, NULL, true); 371 if (test_and_clear_bit(wil_vif_fwconnected, 372 vif->status)) 373 atomic_dec(&wil->connected_vifs); 374 } else { 375 wil_update_net_queues_bh(wil, vif, NULL, false); 376 } 377 break; 378 default: 379 break; 380 } 381 } 382 383 void wil_disconnect_worker(struct work_struct *work) 384 { 385 struct wil6210_vif *vif = container_of(work, 386 struct wil6210_vif, disconnect_worker); 387 struct wil6210_priv *wil = vif_to_wil(vif); 388 struct net_device *ndev = vif_to_ndev(vif); 389 int rc; 390 struct { 391 struct wmi_cmd_hdr wmi; 392 struct wmi_disconnect_event evt; 393 } __packed reply; 394 395 if (test_bit(wil_vif_fwconnected, vif->status)) 396 /* connect succeeded after all */ 397 return; 398 399 if (!test_bit(wil_vif_fwconnecting, vif->status)) 400 /* already disconnected */ 401 return; 402 403 memset(&reply, 0, sizeof(reply)); 404 405 rc = wmi_call(wil, WMI_DISCONNECT_CMDID, vif->mid, NULL, 0, 406 WMI_DISCONNECT_EVENTID, &reply, sizeof(reply), 407 WIL6210_DISCONNECT_TO_MS); 408 if (rc) { 409 wil_err(wil, "disconnect error %d\n", rc); 410 return; 411 } 412 413 wil_update_net_queues_bh(wil, vif, NULL, true); 414 netif_carrier_off(ndev); 415 cfg80211_connect_result(ndev, NULL, NULL, 0, NULL, 0, 416 WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_KERNEL); 417 clear_bit(wil_vif_fwconnecting, vif->status); 418 } 419 420 static int wil_wait_for_recovery(struct wil6210_priv *wil) 421 { 422 if (wait_event_interruptible(wil->wq, wil->recovery_state != 423 fw_recovery_pending)) { 424 wil_err(wil, "Interrupt, canceling recovery\n"); 425 return -ERESTARTSYS; 426 } 427 if (wil->recovery_state != fw_recovery_running) { 428 wil_info(wil, "Recovery cancelled\n"); 429 return -EINTR; 430 } 431 wil_info(wil, "Proceed with recovery\n"); 432 return 0; 433 } 434 435 void wil_set_recovery_state(struct wil6210_priv *wil, int state) 436 { 437 wil_dbg_misc(wil, "set_recovery_state: %d -> %d\n", 438 wil->recovery_state, state); 439 440 wil->recovery_state = state; 441 wake_up_interruptible(&wil->wq); 442 } 443 444 bool wil_is_recovery_blocked(struct wil6210_priv *wil) 445 { 446 return no_fw_recovery && (wil->recovery_state == fw_recovery_pending); 447 } 448 449 static void wil_fw_error_worker(struct work_struct *work) 450 { 451 struct wil6210_priv *wil = container_of(work, struct wil6210_priv, 452 fw_error_worker); 453 struct net_device *ndev = wil->main_ndev; 454 struct wireless_dev *wdev; 455 456 wil_dbg_misc(wil, "fw error worker\n"); 457 458 if (!ndev || !(ndev->flags & IFF_UP)) { 459 wil_info(wil, "No recovery - interface is down\n"); 460 return; 461 } 462 wdev = ndev->ieee80211_ptr; 463 464 /* increment @recovery_count if less then WIL6210_FW_RECOVERY_TO 465 * passed since last recovery attempt 466 */ 467 if (time_is_after_jiffies(wil->last_fw_recovery + 468 WIL6210_FW_RECOVERY_TO)) 469 wil->recovery_count++; 470 else 471 wil->recovery_count = 1; /* fw was alive for a long time */ 472 473 if (wil->recovery_count > WIL6210_FW_RECOVERY_RETRIES) { 474 wil_err(wil, "too many recovery attempts (%d), giving up\n", 475 wil->recovery_count); 476 return; 477 } 478 479 wil->last_fw_recovery = jiffies; 480 481 wil_info(wil, "fw error recovery requested (try %d)...\n", 482 wil->recovery_count); 483 if (!no_fw_recovery) 484 wil->recovery_state = fw_recovery_running; 485 if (wil_wait_for_recovery(wil) != 0) 486 return; 487 488 mutex_lock(&wil->mutex); 489 /* Needs adaptation for multiple VIFs 490 * need to go over all VIFs and consider the appropriate 491 * recovery. 492 */ 493 switch (wdev->iftype) { 494 case NL80211_IFTYPE_STATION: 495 case NL80211_IFTYPE_P2P_CLIENT: 496 case NL80211_IFTYPE_MONITOR: 497 /* silent recovery, upper layers will see disconnect */ 498 __wil_down(wil); 499 __wil_up(wil); 500 break; 501 case NL80211_IFTYPE_AP: 502 case NL80211_IFTYPE_P2P_GO: 503 wil_info(wil, "No recovery for AP-like interface\n"); 504 /* recovery in these modes is done by upper layers */ 505 break; 506 default: 507 wil_err(wil, "No recovery - unknown interface type %d\n", 508 wdev->iftype); 509 break; 510 } 511 mutex_unlock(&wil->mutex); 512 } 513 514 static int wil_find_free_ring(struct wil6210_priv *wil) 515 { 516 int i; 517 int min_ring_id = wil_get_min_tx_ring_id(wil); 518 519 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) { 520 if (!wil->ring_tx[i].va) 521 return i; 522 } 523 return -EINVAL; 524 } 525 526 int wil_ring_init_tx(struct wil6210_vif *vif, int cid) 527 { 528 struct wil6210_priv *wil = vif_to_wil(vif); 529 int rc = -EINVAL, ringid; 530 531 if (cid < 0) { 532 wil_err(wil, "No connection pending\n"); 533 goto out; 534 } 535 ringid = wil_find_free_ring(wil); 536 if (ringid < 0) { 537 wil_err(wil, "No free vring found\n"); 538 goto out; 539 } 540 541 wil_dbg_wmi(wil, "Configure for connection CID %d MID %d ring %d\n", 542 cid, vif->mid, ringid); 543 544 rc = wil->txrx_ops.ring_init_tx(vif, ringid, 1 << tx_ring_order, 545 cid, 0); 546 if (rc) 547 wil_err(wil, "init TX for CID %d MID %d vring %d failed\n", 548 cid, vif->mid, ringid); 549 550 out: 551 return rc; 552 } 553 554 int wil_bcast_init(struct wil6210_vif *vif) 555 { 556 struct wil6210_priv *wil = vif_to_wil(vif); 557 int ri = vif->bcast_ring, rc; 558 559 if (ri >= 0 && wil->ring_tx[ri].va) 560 return 0; 561 562 ri = wil_find_free_ring(wil); 563 if (ri < 0) 564 return ri; 565 566 vif->bcast_ring = ri; 567 rc = wil->txrx_ops.ring_init_bcast(vif, ri, 1 << bcast_ring_order); 568 if (rc) 569 vif->bcast_ring = -1; 570 571 return rc; 572 } 573 574 void wil_bcast_fini(struct wil6210_vif *vif) 575 { 576 struct wil6210_priv *wil = vif_to_wil(vif); 577 int ri = vif->bcast_ring; 578 579 if (ri < 0) 580 return; 581 582 vif->bcast_ring = -1; 583 wil_ring_fini_tx(wil, ri); 584 } 585 586 void wil_bcast_fini_all(struct wil6210_priv *wil) 587 { 588 int i; 589 struct wil6210_vif *vif; 590 591 for (i = 0; i < wil->max_vifs; i++) { 592 vif = wil->vifs[i]; 593 if (vif) 594 wil_bcast_fini(vif); 595 } 596 } 597 598 int wil_priv_init(struct wil6210_priv *wil) 599 { 600 uint i; 601 602 wil_dbg_misc(wil, "priv_init\n"); 603 604 memset(wil->sta, 0, sizeof(wil->sta)); 605 for (i = 0; i < WIL6210_MAX_CID; i++) { 606 spin_lock_init(&wil->sta[i].tid_rx_lock); 607 wil->sta[i].mid = U8_MAX; 608 } 609 610 for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) { 611 spin_lock_init(&wil->ring_tx_data[i].lock); 612 wil->ring2cid_tid[i][0] = WIL6210_MAX_CID; 613 } 614 615 mutex_init(&wil->mutex); 616 mutex_init(&wil->vif_mutex); 617 mutex_init(&wil->wmi_mutex); 618 mutex_init(&wil->halp.lock); 619 620 init_completion(&wil->wmi_ready); 621 init_completion(&wil->wmi_call); 622 init_completion(&wil->halp.comp); 623 624 INIT_WORK(&wil->wmi_event_worker, wmi_event_worker); 625 INIT_WORK(&wil->fw_error_worker, wil_fw_error_worker); 626 627 INIT_LIST_HEAD(&wil->pending_wmi_ev); 628 spin_lock_init(&wil->wmi_ev_lock); 629 spin_lock_init(&wil->net_queue_lock); 630 init_waitqueue_head(&wil->wq); 631 632 wil->wmi_wq = create_singlethread_workqueue(WIL_NAME "_wmi"); 633 if (!wil->wmi_wq) 634 return -EAGAIN; 635 636 wil->wq_service = create_singlethread_workqueue(WIL_NAME "_service"); 637 if (!wil->wq_service) 638 goto out_wmi_wq; 639 640 wil->last_fw_recovery = jiffies; 641 wil->tx_interframe_timeout = WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT; 642 wil->rx_interframe_timeout = WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT; 643 wil->tx_max_burst_duration = WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT; 644 wil->rx_max_burst_duration = WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT; 645 646 if (rx_ring_overflow_thrsh == WIL6210_RX_HIGH_TRSH_INIT) 647 rx_ring_overflow_thrsh = WIL6210_RX_HIGH_TRSH_DEFAULT; 648 649 wil->ps_profile = WMI_PS_PROFILE_TYPE_DEFAULT; 650 651 wil->wakeup_trigger = WMI_WAKEUP_TRIGGER_UCAST | 652 WMI_WAKEUP_TRIGGER_BCAST; 653 memset(&wil->suspend_stats, 0, sizeof(wil->suspend_stats)); 654 wil->ring_idle_trsh = 16; 655 656 wil->reply_mid = U8_MAX; 657 wil->max_vifs = 1; 658 659 /* edma configuration can be updated via debugfs before allocation */ 660 wil->num_rx_status_rings = WIL_DEFAULT_NUM_RX_STATUS_RINGS; 661 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT; 662 663 /* Rx status ring size should be bigger than the number of RX buffers 664 * in order to prevent backpressure on the status ring, which may 665 * cause HW freeze. 666 */ 667 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT; 668 /* Number of RX buffer IDs should be bigger than the RX descriptor 669 * ring size as in HW reorder flow, the HW can consume additional 670 * buffers before releasing the previous ones. 671 */ 672 wil->rx_buff_id_count = WIL_RX_BUFF_ARR_SIZE_DEFAULT; 673 674 wil->amsdu_en = 1; 675 676 return 0; 677 678 out_wmi_wq: 679 destroy_workqueue(wil->wmi_wq); 680 681 return -EAGAIN; 682 } 683 684 void wil6210_bus_request(struct wil6210_priv *wil, u32 kbps) 685 { 686 if (wil->platform_ops.bus_request) { 687 wil->bus_request_kbps = kbps; 688 wil->platform_ops.bus_request(wil->platform_handle, kbps); 689 } 690 } 691 692 /** 693 * wil6210_disconnect - disconnect one connection 694 * @vif: virtual interface context 695 * @bssid: peer to disconnect, NULL to disconnect all 696 * @reason_code: Reason code for the Disassociation frame 697 * @from_event: whether is invoked from FW event handler 698 * 699 * Disconnect and release associated resources. If invoked not from the 700 * FW event handler, issue WMI command(s) to trigger MAC disconnect. 701 */ 702 void wil6210_disconnect(struct wil6210_vif *vif, const u8 *bssid, 703 u16 reason_code, bool from_event) 704 { 705 struct wil6210_priv *wil = vif_to_wil(vif); 706 707 wil_dbg_misc(wil, "disconnect\n"); 708 709 del_timer_sync(&vif->connect_timer); 710 _wil6210_disconnect(vif, bssid, reason_code, from_event); 711 } 712 713 void wil_priv_deinit(struct wil6210_priv *wil) 714 { 715 wil_dbg_misc(wil, "priv_deinit\n"); 716 717 wil_set_recovery_state(wil, fw_recovery_idle); 718 cancel_work_sync(&wil->fw_error_worker); 719 wmi_event_flush(wil); 720 destroy_workqueue(wil->wq_service); 721 destroy_workqueue(wil->wmi_wq); 722 } 723 724 static void wil_shutdown_bl(struct wil6210_priv *wil) 725 { 726 u32 val; 727 728 wil_s(wil, RGF_USER_BL + 729 offsetof(struct bl_dedicated_registers_v1, 730 bl_shutdown_handshake), BL_SHUTDOWN_HS_GRTD); 731 732 usleep_range(100, 150); 733 734 val = wil_r(wil, RGF_USER_BL + 735 offsetof(struct bl_dedicated_registers_v1, 736 bl_shutdown_handshake)); 737 if (val & BL_SHUTDOWN_HS_RTD) { 738 wil_dbg_misc(wil, "BL is ready for halt\n"); 739 return; 740 } 741 742 wil_err(wil, "BL did not report ready for halt\n"); 743 } 744 745 /* this format is used by ARC embedded CPU for instruction memory */ 746 static inline u32 ARC_me_imm32(u32 d) 747 { 748 return ((d & 0xffff0000) >> 16) | ((d & 0x0000ffff) << 16); 749 } 750 751 /* defines access to interrupt vectors for wil_freeze_bl */ 752 #define ARC_IRQ_VECTOR_OFFSET(N) ((N) * 8) 753 /* ARC long jump instruction */ 754 #define ARC_JAL_INST (0x20200f80) 755 756 static void wil_freeze_bl(struct wil6210_priv *wil) 757 { 758 u32 jal, upc, saved; 759 u32 ivt3 = ARC_IRQ_VECTOR_OFFSET(3); 760 761 jal = wil_r(wil, wil->iccm_base + ivt3); 762 if (jal != ARC_me_imm32(ARC_JAL_INST)) { 763 wil_dbg_misc(wil, "invalid IVT entry found, skipping\n"); 764 return; 765 } 766 767 /* prevent the target from entering deep sleep 768 * and disabling memory access 769 */ 770 saved = wil_r(wil, RGF_USER_USAGE_8); 771 wil_w(wil, RGF_USER_USAGE_8, saved | BIT_USER_PREVENT_DEEP_SLEEP); 772 usleep_range(20, 25); /* let the BL process the bit */ 773 774 /* redirect to endless loop in the INT_L1 context and let it trap */ 775 wil_w(wil, wil->iccm_base + ivt3 + 4, ARC_me_imm32(ivt3)); 776 usleep_range(20, 25); /* let the BL get into the trap */ 777 778 /* verify the BL is frozen */ 779 upc = wil_r(wil, RGF_USER_CPU_PC); 780 if (upc < ivt3 || (upc > (ivt3 + 8))) 781 wil_dbg_misc(wil, "BL freeze failed, PC=0x%08X\n", upc); 782 783 wil_w(wil, RGF_USER_USAGE_8, saved); 784 } 785 786 static void wil_bl_prepare_halt(struct wil6210_priv *wil) 787 { 788 u32 tmp, ver; 789 790 /* before halting device CPU driver must make sure BL is not accessing 791 * host memory. This is done differently depending on BL version: 792 * 1. For very old BL versions the procedure is skipped 793 * (not supported). 794 * 2. For old BL version we use a special trick to freeze the BL 795 * 3. For new BL versions we shutdown the BL using handshake procedure. 796 */ 797 tmp = wil_r(wil, RGF_USER_BL + 798 offsetof(struct bl_dedicated_registers_v0, 799 boot_loader_struct_version)); 800 if (!tmp) { 801 wil_dbg_misc(wil, "old BL, skipping halt preparation\n"); 802 return; 803 } 804 805 tmp = wil_r(wil, RGF_USER_BL + 806 offsetof(struct bl_dedicated_registers_v1, 807 bl_shutdown_handshake)); 808 ver = BL_SHUTDOWN_HS_PROT_VER(tmp); 809 810 if (ver > 0) 811 wil_shutdown_bl(wil); 812 else 813 wil_freeze_bl(wil); 814 } 815 816 static inline void wil_halt_cpu(struct wil6210_priv *wil) 817 { 818 if (wil->hw_version >= HW_VER_TALYN_MB) { 819 wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB, 820 BIT_USER_USER_CPU_MAN_RST); 821 wil_w(wil, RGF_USER_MAC_CPU_0_TALYN_MB, 822 BIT_USER_MAC_CPU_MAN_RST); 823 } else { 824 wil_w(wil, RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST); 825 wil_w(wil, RGF_USER_MAC_CPU_0, BIT_USER_MAC_CPU_MAN_RST); 826 } 827 } 828 829 static inline void wil_release_cpu(struct wil6210_priv *wil) 830 { 831 /* Start CPU */ 832 if (wil->hw_version >= HW_VER_TALYN_MB) 833 wil_w(wil, RGF_USER_USER_CPU_0_TALYN_MB, 1); 834 else 835 wil_w(wil, RGF_USER_USER_CPU_0, 1); 836 } 837 838 static void wil_set_oob_mode(struct wil6210_priv *wil, u8 mode) 839 { 840 wil_info(wil, "oob_mode to %d\n", mode); 841 switch (mode) { 842 case 0: 843 wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE | 844 BIT_USER_OOB_R2_MODE); 845 break; 846 case 1: 847 wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE); 848 wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE); 849 break; 850 case 2: 851 wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE); 852 wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_R2_MODE); 853 break; 854 default: 855 wil_err(wil, "invalid oob_mode: %d\n", mode); 856 } 857 } 858 859 static int wil_wait_device_ready(struct wil6210_priv *wil, int no_flash) 860 { 861 int delay = 0; 862 u32 x, x1 = 0; 863 864 /* wait until device ready. */ 865 if (no_flash) { 866 msleep(PMU_READY_DELAY_MS); 867 868 wil_dbg_misc(wil, "Reset completed\n"); 869 } else { 870 do { 871 msleep(RST_DELAY); 872 x = wil_r(wil, RGF_USER_BL + 873 offsetof(struct bl_dedicated_registers_v0, 874 boot_loader_ready)); 875 if (x1 != x) { 876 wil_dbg_misc(wil, "BL.ready 0x%08x => 0x%08x\n", 877 x1, x); 878 x1 = x; 879 } 880 if (delay++ > RST_COUNT) { 881 wil_err(wil, "Reset not completed, bl.ready 0x%08x\n", 882 x); 883 return -ETIME; 884 } 885 } while (x != BL_READY); 886 887 wil_dbg_misc(wil, "Reset completed in %d ms\n", 888 delay * RST_DELAY); 889 } 890 891 return 0; 892 } 893 894 static int wil_wait_device_ready_talyn_mb(struct wil6210_priv *wil) 895 { 896 u32 otp_hw; 897 u8 signature_status; 898 bool otp_signature_err; 899 bool hw_section_done; 900 u32 otp_qc_secured; 901 int delay = 0; 902 903 /* Wait for OTP signature test to complete */ 904 usleep_range(2000, 2200); 905 906 wil->boot_config = WIL_BOOT_ERR; 907 908 /* Poll until OTP signature status is valid. 909 * In vanilla and development modes, when signature test is complete 910 * HW sets BIT_OTP_SIGNATURE_ERR_TALYN_MB. 911 * In production mode BIT_OTP_SIGNATURE_ERR_TALYN_MB remains 0, poll 912 * for signature status change to 2 or 3. 913 */ 914 do { 915 otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1); 916 signature_status = WIL_GET_BITS(otp_hw, 8, 9); 917 otp_signature_err = otp_hw & BIT_OTP_SIGNATURE_ERR_TALYN_MB; 918 919 if (otp_signature_err && 920 signature_status == WIL_SIG_STATUS_VANILLA) { 921 wil->boot_config = WIL_BOOT_VANILLA; 922 break; 923 } 924 if (otp_signature_err && 925 signature_status == WIL_SIG_STATUS_DEVELOPMENT) { 926 wil->boot_config = WIL_BOOT_DEVELOPMENT; 927 break; 928 } 929 if (!otp_signature_err && 930 signature_status == WIL_SIG_STATUS_PRODUCTION) { 931 wil->boot_config = WIL_BOOT_PRODUCTION; 932 break; 933 } 934 if (!otp_signature_err && 935 signature_status == 936 WIL_SIG_STATUS_CORRUPTED_PRODUCTION) { 937 /* Unrecognized OTP signature found. Possibly a 938 * corrupted production signature, access control 939 * is applied as in production mode, therefore 940 * do not fail 941 */ 942 wil->boot_config = WIL_BOOT_PRODUCTION; 943 break; 944 } 945 if (delay++ > OTP_HW_COUNT) 946 break; 947 948 usleep_range(OTP_HW_DELAY, OTP_HW_DELAY + 10); 949 } while (!otp_signature_err && signature_status == 0); 950 951 if (wil->boot_config == WIL_BOOT_ERR) { 952 wil_err(wil, 953 "invalid boot config, signature_status %d otp_signature_err %d\n", 954 signature_status, otp_signature_err); 955 return -ETIME; 956 } 957 958 wil_dbg_misc(wil, 959 "signature test done in %d usec, otp_hw 0x%x, boot_config %d\n", 960 delay * OTP_HW_DELAY, otp_hw, wil->boot_config); 961 962 if (wil->boot_config == WIL_BOOT_VANILLA) 963 /* Assuming not SPI boot (currently not supported) */ 964 goto out; 965 966 hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB; 967 delay = 0; 968 969 while (!hw_section_done) { 970 msleep(RST_DELAY); 971 972 otp_hw = wil_r(wil, RGF_USER_OTP_HW_RD_MACHINE_1); 973 hw_section_done = otp_hw & BIT_OTP_HW_SECTION_DONE_TALYN_MB; 974 975 if (delay++ > RST_COUNT) { 976 wil_err(wil, "TO waiting for hw_section_done\n"); 977 return -ETIME; 978 } 979 } 980 981 wil_dbg_misc(wil, "HW section done in %d ms\n", delay * RST_DELAY); 982 983 otp_qc_secured = wil_r(wil, RGF_OTP_QC_SECURED); 984 wil->secured_boot = otp_qc_secured & BIT_BOOT_FROM_ROM ? 1 : 0; 985 wil_dbg_misc(wil, "secured boot is %sabled\n", 986 wil->secured_boot ? "en" : "dis"); 987 988 out: 989 wil_dbg_misc(wil, "Reset completed\n"); 990 991 return 0; 992 } 993 994 static int wil_target_reset(struct wil6210_priv *wil, int no_flash) 995 { 996 u32 x; 997 int rc; 998 999 wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name); 1000 1001 /* Clear MAC link up */ 1002 wil_s(wil, RGF_HP_CTRL, BIT(15)); 1003 wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_HPAL_PERST_FROM_PAD); 1004 wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_CAR_PERST_RST); 1005 1006 wil_halt_cpu(wil); 1007 1008 if (!no_flash) { 1009 /* clear all boot loader "ready" bits */ 1010 wil_w(wil, RGF_USER_BL + 1011 offsetof(struct bl_dedicated_registers_v0, 1012 boot_loader_ready), 0); 1013 /* this should be safe to write even with old BLs */ 1014 wil_w(wil, RGF_USER_BL + 1015 offsetof(struct bl_dedicated_registers_v1, 1016 bl_shutdown_handshake), 0); 1017 } 1018 /* Clear Fw Download notification */ 1019 wil_c(wil, RGF_USER_USAGE_6, BIT(0)); 1020 1021 wil_s(wil, RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN); 1022 /* XTAL stabilization should take about 3ms */ 1023 usleep_range(5000, 7000); 1024 x = wil_r(wil, RGF_CAF_PLL_LOCK_STATUS); 1025 if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) { 1026 wil_err(wil, "Xtal stabilization timeout\n" 1027 "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x); 1028 return -ETIME; 1029 } 1030 /* switch 10k to XTAL*/ 1031 wil_c(wil, RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF); 1032 /* 40 MHz */ 1033 wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL); 1034 1035 wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f); 1036 wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf); 1037 1038 if (wil->hw_version >= HW_VER_TALYN_MB) { 1039 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x7e000000); 1040 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f); 1041 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0xc00000f0); 1042 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00); 1043 } else { 1044 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xfe000000); 1045 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003f); 1046 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0); 1047 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xffe7fe00); 1048 } 1049 1050 wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0); 1051 wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0); 1052 1053 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0); 1054 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0); 1055 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0); 1056 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0); 1057 1058 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003); 1059 /* reset A2 PCIE AHB */ 1060 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000); 1061 1062 wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0); 1063 1064 if (wil->hw_version == HW_VER_TALYN_MB) 1065 rc = wil_wait_device_ready_talyn_mb(wil); 1066 else 1067 rc = wil_wait_device_ready(wil, no_flash); 1068 if (rc) 1069 return rc; 1070 1071 wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD); 1072 1073 /* enable fix for HW bug related to the SA/DA swap in AP Rx */ 1074 wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN | 1075 BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC); 1076 1077 if (wil->hw_version < HW_VER_TALYN_MB && no_flash) { 1078 /* Reset OTP HW vectors to fit 40MHz */ 1079 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME1, 0x60001); 1080 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME2, 0x20027); 1081 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME3, 0x1); 1082 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME4, 0x20027); 1083 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME5, 0x30003); 1084 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME6, 0x20002); 1085 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME7, 0x60001); 1086 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME8, 0x60001); 1087 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME9, 0x60001); 1088 wil_w(wil, RGF_USER_XPM_IFC_RD_TIME10, 0x60001); 1089 wil_w(wil, RGF_USER_XPM_RD_DOUT_SAMPLE_TIME, 0x57); 1090 } 1091 1092 return 0; 1093 } 1094 1095 static void wil_collect_fw_info(struct wil6210_priv *wil) 1096 { 1097 struct wiphy *wiphy = wil_to_wiphy(wil); 1098 u8 retry_short; 1099 int rc; 1100 1101 wil_refresh_fw_capabilities(wil); 1102 1103 rc = wmi_get_mgmt_retry(wil, &retry_short); 1104 if (!rc) { 1105 wiphy->retry_short = retry_short; 1106 wil_dbg_misc(wil, "FW retry_short: %d\n", retry_short); 1107 } 1108 } 1109 1110 void wil_refresh_fw_capabilities(struct wil6210_priv *wil) 1111 { 1112 struct wiphy *wiphy = wil_to_wiphy(wil); 1113 int features; 1114 1115 wil->keep_radio_on_during_sleep = 1116 test_bit(WIL_PLATFORM_CAPA_RADIO_ON_IN_SUSPEND, 1117 wil->platform_capa) && 1118 test_bit(WMI_FW_CAPABILITY_D3_SUSPEND, wil->fw_capabilities); 1119 1120 wil_info(wil, "keep_radio_on_during_sleep (%d)\n", 1121 wil->keep_radio_on_during_sleep); 1122 1123 if (test_bit(WMI_FW_CAPABILITY_RSSI_REPORTING, wil->fw_capabilities)) 1124 wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; 1125 else 1126 wiphy->signal_type = CFG80211_SIGNAL_TYPE_UNSPEC; 1127 1128 if (test_bit(WMI_FW_CAPABILITY_PNO, wil->fw_capabilities)) { 1129 wiphy->max_sched_scan_reqs = 1; 1130 wiphy->max_sched_scan_ssids = WMI_MAX_PNO_SSID_NUM; 1131 wiphy->max_match_sets = WMI_MAX_PNO_SSID_NUM; 1132 wiphy->max_sched_scan_ie_len = WMI_MAX_IE_LEN; 1133 wiphy->max_sched_scan_plans = WMI_MAX_PLANS_NUM; 1134 } 1135 1136 if (test_bit(WMI_FW_CAPABILITY_TX_REQ_EXT, wil->fw_capabilities)) 1137 wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX; 1138 1139 if (wil->platform_ops.set_features) { 1140 features = (test_bit(WMI_FW_CAPABILITY_REF_CLOCK_CONTROL, 1141 wil->fw_capabilities) && 1142 test_bit(WIL_PLATFORM_CAPA_EXT_CLK, 1143 wil->platform_capa)) ? 1144 BIT(WIL_PLATFORM_FEATURE_FW_EXT_CLK_CONTROL) : 0; 1145 1146 if (wil->n_msi == 3) 1147 features |= BIT(WIL_PLATFORM_FEATURE_TRIPLE_MSI); 1148 1149 wil->platform_ops.set_features(wil->platform_handle, features); 1150 } 1151 1152 if (test_bit(WMI_FW_CAPABILITY_BACK_WIN_SIZE_64, 1153 wil->fw_capabilities)) { 1154 wil->max_agg_wsize = WIL_MAX_AGG_WSIZE_64; 1155 wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE_128; 1156 } else { 1157 wil->max_agg_wsize = WIL_MAX_AGG_WSIZE; 1158 wil->max_ampdu_size = WIL_MAX_AMPDU_SIZE; 1159 } 1160 1161 update_supported_bands(wil); 1162 } 1163 1164 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r) 1165 { 1166 le32_to_cpus(&r->base); 1167 le16_to_cpus(&r->entry_size); 1168 le16_to_cpus(&r->size); 1169 le32_to_cpus(&r->tail); 1170 le32_to_cpus(&r->head); 1171 } 1172 1173 /* construct actual board file name to use */ 1174 void wil_get_board_file(struct wil6210_priv *wil, char *buf, size_t len) 1175 { 1176 const char *board_file; 1177 const char *wil_talyn_fw_name = ftm_mode ? WIL_FW_NAME_FTM_TALYN : 1178 WIL_FW_NAME_TALYN; 1179 1180 if (wil->board_file) { 1181 board_file = wil->board_file; 1182 } else { 1183 /* If specific FW file is used for Talyn, 1184 * use specific board file 1185 */ 1186 if (strcmp(wil->wil_fw_name, wil_talyn_fw_name) == 0) 1187 board_file = WIL_BRD_NAME_TALYN; 1188 else 1189 board_file = WIL_BOARD_FILE_NAME; 1190 } 1191 1192 strlcpy(buf, board_file, len); 1193 } 1194 1195 static int wil_get_bl_info(struct wil6210_priv *wil) 1196 { 1197 struct net_device *ndev = wil->main_ndev; 1198 struct wiphy *wiphy = wil_to_wiphy(wil); 1199 union { 1200 struct bl_dedicated_registers_v0 bl0; 1201 struct bl_dedicated_registers_v1 bl1; 1202 } bl; 1203 u32 bl_ver; 1204 u8 *mac; 1205 u16 rf_status; 1206 1207 wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL), 1208 sizeof(bl)); 1209 bl_ver = le32_to_cpu(bl.bl0.boot_loader_struct_version); 1210 mac = bl.bl0.mac_address; 1211 1212 if (bl_ver == 0) { 1213 le32_to_cpus(&bl.bl0.rf_type); 1214 le32_to_cpus(&bl.bl0.baseband_type); 1215 rf_status = 0; /* actually, unknown */ 1216 wil_info(wil, 1217 "Boot Loader struct v%d: MAC = %pM RF = 0x%08x bband = 0x%08x\n", 1218 bl_ver, mac, 1219 bl.bl0.rf_type, bl.bl0.baseband_type); 1220 wil_info(wil, "Boot Loader build unknown for struct v0\n"); 1221 } else { 1222 le16_to_cpus(&bl.bl1.rf_type); 1223 rf_status = le16_to_cpu(bl.bl1.rf_status); 1224 le32_to_cpus(&bl.bl1.baseband_type); 1225 le16_to_cpus(&bl.bl1.bl_version_subminor); 1226 le16_to_cpus(&bl.bl1.bl_version_build); 1227 wil_info(wil, 1228 "Boot Loader struct v%d: MAC = %pM RF = 0x%04x (status 0x%04x) bband = 0x%08x\n", 1229 bl_ver, mac, 1230 bl.bl1.rf_type, rf_status, 1231 bl.bl1.baseband_type); 1232 wil_info(wil, "Boot Loader build %d.%d.%d.%d\n", 1233 bl.bl1.bl_version_major, bl.bl1.bl_version_minor, 1234 bl.bl1.bl_version_subminor, bl.bl1.bl_version_build); 1235 } 1236 1237 if (!is_valid_ether_addr(mac)) { 1238 wil_err(wil, "BL: Invalid MAC %pM\n", mac); 1239 return -EINVAL; 1240 } 1241 1242 ether_addr_copy(ndev->perm_addr, mac); 1243 ether_addr_copy(wiphy->perm_addr, mac); 1244 if (!is_valid_ether_addr(ndev->dev_addr)) 1245 ether_addr_copy(ndev->dev_addr, mac); 1246 1247 if (rf_status) {/* bad RF cable? */ 1248 wil_err(wil, "RF communication error 0x%04x", 1249 rf_status); 1250 return -EAGAIN; 1251 } 1252 1253 return 0; 1254 } 1255 1256 static void wil_bl_crash_info(struct wil6210_priv *wil, bool is_err) 1257 { 1258 u32 bl_assert_code, bl_assert_blink, bl_magic_number; 1259 u32 bl_ver = wil_r(wil, RGF_USER_BL + 1260 offsetof(struct bl_dedicated_registers_v0, 1261 boot_loader_struct_version)); 1262 1263 if (bl_ver < 2) 1264 return; 1265 1266 bl_assert_code = wil_r(wil, RGF_USER_BL + 1267 offsetof(struct bl_dedicated_registers_v1, 1268 bl_assert_code)); 1269 bl_assert_blink = wil_r(wil, RGF_USER_BL + 1270 offsetof(struct bl_dedicated_registers_v1, 1271 bl_assert_blink)); 1272 bl_magic_number = wil_r(wil, RGF_USER_BL + 1273 offsetof(struct bl_dedicated_registers_v1, 1274 bl_magic_number)); 1275 1276 if (is_err) { 1277 wil_err(wil, 1278 "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n", 1279 bl_assert_code, bl_assert_blink, bl_magic_number); 1280 } else { 1281 wil_dbg_misc(wil, 1282 "BL assert code 0x%08x blink 0x%08x magic 0x%08x\n", 1283 bl_assert_code, bl_assert_blink, bl_magic_number); 1284 } 1285 } 1286 1287 static int wil_get_otp_info(struct wil6210_priv *wil) 1288 { 1289 struct net_device *ndev = wil->main_ndev; 1290 struct wiphy *wiphy = wil_to_wiphy(wil); 1291 u8 mac[8]; 1292 int mac_addr; 1293 1294 if (wil->hw_version >= HW_VER_TALYN_MB) 1295 mac_addr = RGF_OTP_MAC_TALYN_MB; 1296 else 1297 mac_addr = RGF_OTP_MAC; 1298 1299 wil_memcpy_fromio_32(mac, wil->csr + HOSTADDR(mac_addr), 1300 sizeof(mac)); 1301 if (!is_valid_ether_addr(mac)) { 1302 wil_err(wil, "Invalid MAC %pM\n", mac); 1303 return -EINVAL; 1304 } 1305 1306 ether_addr_copy(ndev->perm_addr, mac); 1307 ether_addr_copy(wiphy->perm_addr, mac); 1308 if (!is_valid_ether_addr(ndev->dev_addr)) 1309 ether_addr_copy(ndev->dev_addr, mac); 1310 1311 return 0; 1312 } 1313 1314 static int wil_wait_for_fw_ready(struct wil6210_priv *wil) 1315 { 1316 ulong to = msecs_to_jiffies(2000); 1317 ulong left = wait_for_completion_timeout(&wil->wmi_ready, to); 1318 1319 if (0 == left) { 1320 wil_err(wil, "Firmware not ready\n"); 1321 return -ETIME; 1322 } else { 1323 wil_info(wil, "FW ready after %d ms. HW version 0x%08x\n", 1324 jiffies_to_msecs(to-left), wil->hw_version); 1325 } 1326 return 0; 1327 } 1328 1329 void wil_abort_scan(struct wil6210_vif *vif, bool sync) 1330 { 1331 struct wil6210_priv *wil = vif_to_wil(vif); 1332 int rc; 1333 struct cfg80211_scan_info info = { 1334 .aborted = true, 1335 }; 1336 1337 lockdep_assert_held(&wil->vif_mutex); 1338 1339 if (!vif->scan_request) 1340 return; 1341 1342 wil_dbg_misc(wil, "Abort scan_request 0x%p\n", vif->scan_request); 1343 del_timer_sync(&vif->scan_timer); 1344 mutex_unlock(&wil->vif_mutex); 1345 rc = wmi_abort_scan(vif); 1346 if (!rc && sync) 1347 wait_event_interruptible_timeout(wil->wq, !vif->scan_request, 1348 msecs_to_jiffies( 1349 WAIT_FOR_SCAN_ABORT_MS)); 1350 1351 mutex_lock(&wil->vif_mutex); 1352 if (vif->scan_request) { 1353 cfg80211_scan_done(vif->scan_request, &info); 1354 vif->scan_request = NULL; 1355 } 1356 } 1357 1358 void wil_abort_scan_all_vifs(struct wil6210_priv *wil, bool sync) 1359 { 1360 int i; 1361 1362 lockdep_assert_held(&wil->vif_mutex); 1363 1364 for (i = 0; i < wil->max_vifs; i++) { 1365 struct wil6210_vif *vif = wil->vifs[i]; 1366 1367 if (vif) 1368 wil_abort_scan(vif, sync); 1369 } 1370 } 1371 1372 int wil_ps_update(struct wil6210_priv *wil, enum wmi_ps_profile_type ps_profile) 1373 { 1374 int rc; 1375 1376 if (!test_bit(WMI_FW_CAPABILITY_PS_CONFIG, wil->fw_capabilities)) { 1377 wil_err(wil, "set_power_mgmt not supported\n"); 1378 return -EOPNOTSUPP; 1379 } 1380 1381 rc = wmi_ps_dev_profile_cfg(wil, ps_profile); 1382 if (rc) 1383 wil_err(wil, "wmi_ps_dev_profile_cfg failed (%d)\n", rc); 1384 else 1385 wil->ps_profile = ps_profile; 1386 1387 return rc; 1388 } 1389 1390 static void wil_pre_fw_config(struct wil6210_priv *wil) 1391 { 1392 /* Mark FW as loaded from host */ 1393 wil_s(wil, RGF_USER_USAGE_6, 1); 1394 1395 /* clear any interrupts which on-card-firmware 1396 * may have set 1397 */ 1398 wil6210_clear_irq(wil); 1399 /* CAF_ICR - clear and mask */ 1400 /* it is W1C, clear by writing back same value */ 1401 wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0); 1402 wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0); 1403 /* clear PAL_UNIT_ICR (potential D0->D3 leftover) 1404 * In Talyn-MB host cannot access this register due to 1405 * access control, hence PAL_UNIT_ICR is cleared by the FW 1406 */ 1407 if (wil->hw_version < HW_VER_TALYN_MB) 1408 wil_s(wil, RGF_PAL_UNIT_ICR + offsetof(struct RGF_ICR, ICR), 1409 0); 1410 1411 if (wil->fw_calib_result > 0) { 1412 __le32 val = cpu_to_le32(wil->fw_calib_result | 1413 (CALIB_RESULT_SIGNATURE << 8)); 1414 wil_w(wil, RGF_USER_FW_CALIB_RESULT, (u32 __force)val); 1415 } 1416 } 1417 1418 static int wil_restore_vifs(struct wil6210_priv *wil) 1419 { 1420 struct wil6210_vif *vif; 1421 struct net_device *ndev; 1422 struct wireless_dev *wdev; 1423 int i, rc; 1424 1425 for (i = 0; i < wil->max_vifs; i++) { 1426 vif = wil->vifs[i]; 1427 if (!vif) 1428 continue; 1429 vif->ap_isolate = 0; 1430 if (vif->mid) { 1431 ndev = vif_to_ndev(vif); 1432 wdev = vif_to_wdev(vif); 1433 rc = wmi_port_allocate(wil, vif->mid, ndev->dev_addr, 1434 wdev->iftype); 1435 if (rc) { 1436 wil_err(wil, "fail to restore VIF %d type %d, rc %d\n", 1437 i, wdev->iftype, rc); 1438 return rc; 1439 } 1440 } 1441 } 1442 1443 return 0; 1444 } 1445 1446 /* 1447 * We reset all the structures, and we reset the UMAC. 1448 * After calling this routine, you're expected to reload 1449 * the firmware. 1450 */ 1451 int wil_reset(struct wil6210_priv *wil, bool load_fw) 1452 { 1453 int rc, i; 1454 unsigned long status_flags = BIT(wil_status_resetting); 1455 int no_flash; 1456 struct wil6210_vif *vif; 1457 1458 wil_dbg_misc(wil, "reset\n"); 1459 1460 WARN_ON(!mutex_is_locked(&wil->mutex)); 1461 WARN_ON(test_bit(wil_status_napi_en, wil->status)); 1462 1463 if (debug_fw) { 1464 static const u8 mac[ETH_ALEN] = { 1465 0x00, 0xde, 0xad, 0x12, 0x34, 0x56, 1466 }; 1467 struct net_device *ndev = wil->main_ndev; 1468 1469 ether_addr_copy(ndev->perm_addr, mac); 1470 ether_addr_copy(ndev->dev_addr, ndev->perm_addr); 1471 return 0; 1472 } 1473 1474 if (wil->hw_version == HW_VER_UNKNOWN) 1475 return -ENODEV; 1476 1477 if (test_bit(WIL_PLATFORM_CAPA_T_PWR_ON_0, wil->platform_capa)) { 1478 wil_dbg_misc(wil, "Notify FW to set T_POWER_ON=0\n"); 1479 wil_s(wil, RGF_USER_USAGE_8, BIT_USER_SUPPORT_T_POWER_ON_0); 1480 } 1481 1482 if (test_bit(WIL_PLATFORM_CAPA_EXT_CLK, wil->platform_capa)) { 1483 wil_dbg_misc(wil, "Notify FW on ext clock configuration\n"); 1484 wil_s(wil, RGF_USER_USAGE_8, BIT_USER_EXT_CLK); 1485 } 1486 1487 if (wil->platform_ops.notify) { 1488 rc = wil->platform_ops.notify(wil->platform_handle, 1489 WIL_PLATFORM_EVT_PRE_RESET); 1490 if (rc) 1491 wil_err(wil, "PRE_RESET platform notify failed, rc %d\n", 1492 rc); 1493 } 1494 1495 set_bit(wil_status_resetting, wil->status); 1496 if (test_bit(wil_status_collecting_dumps, wil->status)) { 1497 /* Device collects crash dump, cancel the reset. 1498 * following crash dump collection, reset would take place. 1499 */ 1500 wil_dbg_misc(wil, "reject reset while collecting crash dump\n"); 1501 rc = -EBUSY; 1502 goto out; 1503 } 1504 1505 mutex_lock(&wil->vif_mutex); 1506 wil_abort_scan_all_vifs(wil, false); 1507 mutex_unlock(&wil->vif_mutex); 1508 1509 for (i = 0; i < wil->max_vifs; i++) { 1510 vif = wil->vifs[i]; 1511 if (vif) { 1512 cancel_work_sync(&vif->disconnect_worker); 1513 wil6210_disconnect(vif, NULL, 1514 WLAN_REASON_DEAUTH_LEAVING, false); 1515 } 1516 } 1517 wil_bcast_fini_all(wil); 1518 1519 /* Disable device led before reset*/ 1520 wmi_led_cfg(wil, false); 1521 1522 /* prevent NAPI from being scheduled and prevent wmi commands */ 1523 mutex_lock(&wil->wmi_mutex); 1524 if (test_bit(wil_status_suspending, wil->status)) 1525 status_flags |= BIT(wil_status_suspending); 1526 bitmap_and(wil->status, wil->status, &status_flags, 1527 wil_status_last); 1528 wil_dbg_misc(wil, "wil->status (0x%lx)\n", *wil->status); 1529 mutex_unlock(&wil->wmi_mutex); 1530 1531 wil_mask_irq(wil); 1532 1533 wmi_event_flush(wil); 1534 1535 flush_workqueue(wil->wq_service); 1536 flush_workqueue(wil->wmi_wq); 1537 1538 no_flash = test_bit(hw_capa_no_flash, wil->hw_capa); 1539 if (!no_flash) 1540 wil_bl_crash_info(wil, false); 1541 wil_disable_irq(wil); 1542 rc = wil_target_reset(wil, no_flash); 1543 wil6210_clear_irq(wil); 1544 wil_enable_irq(wil); 1545 wil->txrx_ops.rx_fini(wil); 1546 wil->txrx_ops.tx_fini(wil); 1547 if (rc) { 1548 if (!no_flash) 1549 wil_bl_crash_info(wil, true); 1550 goto out; 1551 } 1552 1553 if (no_flash) { 1554 rc = wil_get_otp_info(wil); 1555 } else { 1556 rc = wil_get_bl_info(wil); 1557 if (rc == -EAGAIN && !load_fw) 1558 /* ignore RF error if not going up */ 1559 rc = 0; 1560 } 1561 if (rc) 1562 goto out; 1563 1564 wil_set_oob_mode(wil, oob_mode); 1565 if (load_fw) { 1566 char board_file[WIL_BOARD_FILE_MAX_NAMELEN]; 1567 1568 if (wil->secured_boot) { 1569 wil_err(wil, "secured boot is not supported\n"); 1570 return -ENOTSUPP; 1571 } 1572 1573 board_file[0] = '\0'; 1574 wil_get_board_file(wil, board_file, sizeof(board_file)); 1575 wil_info(wil, "Use firmware <%s> + board <%s>\n", 1576 wil->wil_fw_name, board_file); 1577 1578 if (!no_flash) 1579 wil_bl_prepare_halt(wil); 1580 1581 wil_halt_cpu(wil); 1582 memset(wil->fw_version, 0, sizeof(wil->fw_version)); 1583 /* Loading f/w from the file */ 1584 rc = wil_request_firmware(wil, wil->wil_fw_name, true); 1585 if (rc) 1586 goto out; 1587 if (wil->brd_file_addr) 1588 rc = wil_request_board(wil, board_file); 1589 else 1590 rc = wil_request_firmware(wil, board_file, true); 1591 if (rc) 1592 goto out; 1593 1594 wil_pre_fw_config(wil); 1595 wil_release_cpu(wil); 1596 } 1597 1598 /* init after reset */ 1599 reinit_completion(&wil->wmi_ready); 1600 reinit_completion(&wil->wmi_call); 1601 reinit_completion(&wil->halp.comp); 1602 1603 clear_bit(wil_status_resetting, wil->status); 1604 1605 if (load_fw) { 1606 wil_unmask_irq(wil); 1607 1608 /* we just started MAC, wait for FW ready */ 1609 rc = wil_wait_for_fw_ready(wil); 1610 if (rc) 1611 return rc; 1612 1613 /* check FW is responsive */ 1614 rc = wmi_echo(wil); 1615 if (rc) { 1616 wil_err(wil, "wmi_echo failed, rc %d\n", rc); 1617 return rc; 1618 } 1619 1620 wil->txrx_ops.configure_interrupt_moderation(wil); 1621 1622 /* Enable OFU rdy valid bug fix, to prevent hang in oful34_rx 1623 * while there is back-pressure from Host during RX 1624 */ 1625 if (wil->hw_version >= HW_VER_TALYN_MB) 1626 wil_s(wil, RGF_DMA_MISC_CTL, 1627 BIT_OFUL34_RDY_VALID_BUG_FIX_EN); 1628 1629 rc = wil_restore_vifs(wil); 1630 if (rc) { 1631 wil_err(wil, "failed to restore vifs, rc %d\n", rc); 1632 return rc; 1633 } 1634 1635 wil_collect_fw_info(wil); 1636 1637 if (wil->ps_profile != WMI_PS_PROFILE_TYPE_DEFAULT) 1638 wil_ps_update(wil, wil->ps_profile); 1639 1640 if (wil->platform_ops.notify) { 1641 rc = wil->platform_ops.notify(wil->platform_handle, 1642 WIL_PLATFORM_EVT_FW_RDY); 1643 if (rc) { 1644 wil_err(wil, "FW_RDY notify failed, rc %d\n", 1645 rc); 1646 rc = 0; 1647 } 1648 } 1649 } 1650 1651 return rc; 1652 1653 out: 1654 clear_bit(wil_status_resetting, wil->status); 1655 return rc; 1656 } 1657 1658 void wil_fw_error_recovery(struct wil6210_priv *wil) 1659 { 1660 wil_dbg_misc(wil, "starting fw error recovery\n"); 1661 1662 if (test_bit(wil_status_resetting, wil->status)) { 1663 wil_info(wil, "Reset already in progress\n"); 1664 return; 1665 } 1666 1667 wil->recovery_state = fw_recovery_pending; 1668 schedule_work(&wil->fw_error_worker); 1669 } 1670 1671 int __wil_up(struct wil6210_priv *wil) 1672 { 1673 struct net_device *ndev = wil->main_ndev; 1674 struct wireless_dev *wdev = ndev->ieee80211_ptr; 1675 int rc; 1676 1677 WARN_ON(!mutex_is_locked(&wil->mutex)); 1678 1679 rc = wil_reset(wil, true); 1680 if (rc) 1681 return rc; 1682 1683 /* Rx RING. After MAC and beacon */ 1684 rc = wil->txrx_ops.rx_init(wil, 1 << rx_ring_order); 1685 if (rc) 1686 return rc; 1687 1688 rc = wil->txrx_ops.tx_init(wil); 1689 if (rc) 1690 return rc; 1691 1692 switch (wdev->iftype) { 1693 case NL80211_IFTYPE_STATION: 1694 wil_dbg_misc(wil, "type: STATION\n"); 1695 ndev->type = ARPHRD_ETHER; 1696 break; 1697 case NL80211_IFTYPE_AP: 1698 wil_dbg_misc(wil, "type: AP\n"); 1699 ndev->type = ARPHRD_ETHER; 1700 break; 1701 case NL80211_IFTYPE_P2P_CLIENT: 1702 wil_dbg_misc(wil, "type: P2P_CLIENT\n"); 1703 ndev->type = ARPHRD_ETHER; 1704 break; 1705 case NL80211_IFTYPE_P2P_GO: 1706 wil_dbg_misc(wil, "type: P2P_GO\n"); 1707 ndev->type = ARPHRD_ETHER; 1708 break; 1709 case NL80211_IFTYPE_MONITOR: 1710 wil_dbg_misc(wil, "type: Monitor\n"); 1711 ndev->type = ARPHRD_IEEE80211_RADIOTAP; 1712 /* ARPHRD_IEEE80211 or ARPHRD_IEEE80211_RADIOTAP ? */ 1713 break; 1714 default: 1715 return -EOPNOTSUPP; 1716 } 1717 1718 /* MAC address - pre-requisite for other commands */ 1719 wmi_set_mac_address(wil, ndev->dev_addr); 1720 1721 wil_dbg_misc(wil, "NAPI enable\n"); 1722 napi_enable(&wil->napi_rx); 1723 napi_enable(&wil->napi_tx); 1724 set_bit(wil_status_napi_en, wil->status); 1725 1726 wil6210_bus_request(wil, WIL_DEFAULT_BUS_REQUEST_KBPS); 1727 1728 return 0; 1729 } 1730 1731 int wil_up(struct wil6210_priv *wil) 1732 { 1733 int rc; 1734 1735 wil_dbg_misc(wil, "up\n"); 1736 1737 mutex_lock(&wil->mutex); 1738 rc = __wil_up(wil); 1739 mutex_unlock(&wil->mutex); 1740 1741 return rc; 1742 } 1743 1744 int __wil_down(struct wil6210_priv *wil) 1745 { 1746 WARN_ON(!mutex_is_locked(&wil->mutex)); 1747 1748 set_bit(wil_status_resetting, wil->status); 1749 1750 wil6210_bus_request(wil, 0); 1751 1752 wil_disable_irq(wil); 1753 if (test_and_clear_bit(wil_status_napi_en, wil->status)) { 1754 napi_disable(&wil->napi_rx); 1755 napi_disable(&wil->napi_tx); 1756 wil_dbg_misc(wil, "NAPI disable\n"); 1757 } 1758 wil_enable_irq(wil); 1759 1760 mutex_lock(&wil->vif_mutex); 1761 wil_p2p_stop_radio_operations(wil); 1762 wil_abort_scan_all_vifs(wil, false); 1763 mutex_unlock(&wil->vif_mutex); 1764 1765 return wil_reset(wil, false); 1766 } 1767 1768 int wil_down(struct wil6210_priv *wil) 1769 { 1770 int rc; 1771 1772 wil_dbg_misc(wil, "down\n"); 1773 1774 wil_set_recovery_state(wil, fw_recovery_idle); 1775 mutex_lock(&wil->mutex); 1776 rc = __wil_down(wil); 1777 mutex_unlock(&wil->mutex); 1778 1779 return rc; 1780 } 1781 1782 int wil_find_cid(struct wil6210_priv *wil, u8 mid, const u8 *mac) 1783 { 1784 int i; 1785 int rc = -ENOENT; 1786 1787 for (i = 0; i < ARRAY_SIZE(wil->sta); i++) { 1788 if (wil->sta[i].mid == mid && 1789 wil->sta[i].status != wil_sta_unused && 1790 ether_addr_equal(wil->sta[i].addr, mac)) { 1791 rc = i; 1792 break; 1793 } 1794 } 1795 1796 return rc; 1797 } 1798 1799 void wil_halp_vote(struct wil6210_priv *wil) 1800 { 1801 unsigned long rc; 1802 unsigned long to_jiffies = msecs_to_jiffies(WAIT_FOR_HALP_VOTE_MS); 1803 1804 mutex_lock(&wil->halp.lock); 1805 1806 wil_dbg_irq(wil, "halp_vote: start, HALP ref_cnt (%d)\n", 1807 wil->halp.ref_cnt); 1808 1809 if (++wil->halp.ref_cnt == 1) { 1810 reinit_completion(&wil->halp.comp); 1811 wil6210_set_halp(wil); 1812 rc = wait_for_completion_timeout(&wil->halp.comp, to_jiffies); 1813 if (!rc) { 1814 wil_err(wil, "HALP vote timed out\n"); 1815 /* Mask HALP as done in case the interrupt is raised */ 1816 wil6210_mask_halp(wil); 1817 } else { 1818 wil_dbg_irq(wil, 1819 "halp_vote: HALP vote completed after %d ms\n", 1820 jiffies_to_msecs(to_jiffies - rc)); 1821 } 1822 } 1823 1824 wil_dbg_irq(wil, "halp_vote: end, HALP ref_cnt (%d)\n", 1825 wil->halp.ref_cnt); 1826 1827 mutex_unlock(&wil->halp.lock); 1828 } 1829 1830 void wil_halp_unvote(struct wil6210_priv *wil) 1831 { 1832 WARN_ON(wil->halp.ref_cnt == 0); 1833 1834 mutex_lock(&wil->halp.lock); 1835 1836 wil_dbg_irq(wil, "halp_unvote: start, HALP ref_cnt (%d)\n", 1837 wil->halp.ref_cnt); 1838 1839 if (--wil->halp.ref_cnt == 0) { 1840 wil6210_clear_halp(wil); 1841 wil_dbg_irq(wil, "HALP unvote\n"); 1842 } 1843 1844 wil_dbg_irq(wil, "halp_unvote:end, HALP ref_cnt (%d)\n", 1845 wil->halp.ref_cnt); 1846 1847 mutex_unlock(&wil->halp.lock); 1848 } 1849 1850 void wil_init_txrx_ops(struct wil6210_priv *wil) 1851 { 1852 if (wil->use_enhanced_dma_hw) 1853 wil_init_txrx_ops_edma(wil); 1854 else 1855 wil_init_txrx_ops_legacy_dma(wil); 1856 } 1857