1 /* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _WCN36XX_H_ 18 #define _WCN36XX_H_ 19 20 #include <linux/completion.h> 21 #include <linux/in6.h> 22 #include <linux/printk.h> 23 #include <linux/spinlock.h> 24 #include <net/mac80211.h> 25 26 #include "hal.h" 27 #include "smd.h" 28 #include "txrx.h" 29 #include "dxe.h" 30 #include "pmc.h" 31 #include "debug.h" 32 33 #define WLAN_NV_FILE "wlan/prima/WCNSS_qcom_wlan_nv.bin" 34 #define WCN36XX_AGGR_BUFFER_SIZE 64 35 36 extern unsigned int wcn36xx_dbg_mask; 37 38 enum wcn36xx_debug_mask { 39 WCN36XX_DBG_DXE = 0x00000001, 40 WCN36XX_DBG_DXE_DUMP = 0x00000002, 41 WCN36XX_DBG_SMD = 0x00000004, 42 WCN36XX_DBG_SMD_DUMP = 0x00000008, 43 WCN36XX_DBG_RX = 0x00000010, 44 WCN36XX_DBG_RX_DUMP = 0x00000020, 45 WCN36XX_DBG_TX = 0x00000040, 46 WCN36XX_DBG_TX_DUMP = 0x00000080, 47 WCN36XX_DBG_HAL = 0x00000100, 48 WCN36XX_DBG_HAL_DUMP = 0x00000200, 49 WCN36XX_DBG_MAC = 0x00000400, 50 WCN36XX_DBG_BEACON = 0x00000800, 51 WCN36XX_DBG_BEACON_DUMP = 0x00001000, 52 WCN36XX_DBG_PMC = 0x00002000, 53 WCN36XX_DBG_PMC_DUMP = 0x00004000, 54 WCN36XX_DBG_TESTMODE = 0x00008000, 55 WCN36XX_DBG_TESTMODE_DUMP = 0x00010000, 56 WCN36XX_DBG_ANY = 0xffffffff, 57 }; 58 59 #define wcn36xx_err(fmt, arg...) \ 60 printk(KERN_ERR pr_fmt("ERROR " fmt), ##arg) 61 62 #define wcn36xx_warn(fmt, arg...) \ 63 printk(KERN_WARNING pr_fmt("WARNING " fmt), ##arg) 64 65 #define wcn36xx_info(fmt, arg...) \ 66 printk(KERN_INFO pr_fmt(fmt), ##arg) 67 68 #define wcn36xx_dbg(mask, fmt, arg...) do { \ 69 if (wcn36xx_dbg_mask & mask) \ 70 printk(KERN_DEBUG pr_fmt(fmt), ##arg); \ 71 } while (0) 72 73 #define wcn36xx_dbg_dump(mask, prefix_str, buf, len) do { \ 74 if (wcn36xx_dbg_mask & mask) \ 75 print_hex_dump(KERN_DEBUG, pr_fmt(prefix_str), \ 76 DUMP_PREFIX_OFFSET, 32, 1, \ 77 buf, len, false); \ 78 } while (0) 79 80 enum wcn36xx_ampdu_state { 81 WCN36XX_AMPDU_NONE, 82 WCN36XX_AMPDU_INIT, 83 WCN36XX_AMPDU_START, 84 WCN36XX_AMPDU_OPERATIONAL, 85 }; 86 87 #define HW_VALUE_PHY_SHIFT 8 88 #define HW_VALUE_PHY(hw_value) ((hw_value) >> HW_VALUE_PHY_SHIFT) 89 #define HW_VALUE_CHANNEL(hw_value) ((hw_value) & 0xFF) 90 #define WCN36XX_HW_CHANNEL(__wcn)\ 91 HW_VALUE_CHANNEL(__wcn->hw->conf.chandef.chan->hw_value) 92 #define WCN36XX_BAND(__wcn) (__wcn->hw->conf.chandef.chan->band) 93 #define WCN36XX_CENTER_FREQ(__wcn) (__wcn->hw->conf.chandef.chan->center_freq) 94 #define WCN36XX_LISTEN_INTERVAL(__wcn) (__wcn->hw->conf.listen_interval) 95 #define WCN36XX_FLAGS(__wcn) (__wcn->hw->flags) 96 #define WCN36XX_MAX_POWER(__wcn) (__wcn->hw->conf.chandef.chan->max_power) 97 98 #define RF_UNKNOWN 0x0000 99 #define RF_IRIS_WCN3620 0x3620 100 #define RF_IRIS_WCN3680 0x3680 101 102 static inline void buff_to_be(u32 *buf, size_t len) 103 { 104 int i; 105 for (i = 0; i < len; i++) 106 buf[i] = cpu_to_be32(buf[i]); 107 } 108 109 struct nv_data { 110 int is_valid; 111 u8 table; 112 }; 113 114 /** 115 * struct wcn36xx_vif - holds VIF related fields 116 * 117 * @bss_index: bss_index is initially set to 0xFF. bss_index is received from 118 * HW after first config_bss call and must be used in delete_bss and 119 * enter/exit_bmps. 120 */ 121 struct wcn36xx_vif { 122 struct list_head list; 123 u8 dtim_period; 124 enum ani_ed_type encrypt_type; 125 bool is_joining; 126 bool sta_assoc; 127 struct wcn36xx_hal_mac_ssid ssid; 128 enum wcn36xx_hal_bss_type bss_type; 129 130 /* Power management */ 131 bool allow_bmps; 132 enum wcn36xx_power_state pw_state; 133 134 u8 bss_index; 135 /* Returned from WCN36XX_HAL_ADD_STA_SELF_RSP */ 136 u8 self_sta_index; 137 u8 self_dpu_desc_index; 138 u8 self_ucast_dpu_sign; 139 140 #if IS_ENABLED(CONFIG_IPV6) 141 /* IPv6 addresses for WoWLAN */ 142 struct in6_addr target_ipv6_addrs[WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX]; 143 unsigned long tentative_addrs[BITS_TO_LONGS(WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX)]; 144 int num_target_ipv6_addrs; 145 #endif 146 /* WoWLAN GTK rekey data */ 147 struct { 148 u8 kck[NL80211_KCK_LEN], kek[NL80211_KEK_LEN]; 149 __le64 replay_ctr; 150 bool valid; 151 } rekey_data; 152 153 struct list_head sta_list; 154 }; 155 156 /** 157 * struct wcn36xx_sta - holds STA related fields 158 * 159 * @tid: traffic ID that is used during AMPDU and in TX BD. 160 * @sta_index: STA index is returned from HW after config_sta call and is 161 * used in both SMD channel and TX BD. 162 * @dpu_desc_index: DPU descriptor index is returned from HW after config_sta 163 * call and is used in TX BD. 164 * @bss_sta_index: STA index is returned from HW after config_bss call and is 165 * used in both SMD channel and TX BD. See table bellow when it is used. 166 * @bss_dpu_desc_index: DPU descriptor index is returned from HW after 167 * config_bss call and is used in TX BD. 168 * ______________________________________________ 169 * | | STA | AP | 170 * |______________|_____________|_______________| 171 * | TX BD |bss_sta_index| sta_index | 172 * |______________|_____________|_______________| 173 * |all SMD calls |bss_sta_index| sta_index | 174 * |______________|_____________|_______________| 175 * |smd_delete_sta| sta_index | sta_index | 176 * |______________|_____________|_______________| 177 */ 178 struct wcn36xx_sta { 179 struct list_head list; 180 struct wcn36xx_vif *vif; 181 u16 aid; 182 u16 tid; 183 u8 sta_index; 184 u8 dpu_desc_index; 185 u8 ucast_dpu_sign; 186 u8 bss_sta_index; 187 u8 bss_dpu_desc_index; 188 bool is_data_encrypted; 189 /* Rates */ 190 struct wcn36xx_hal_supported_rates_v1 supported_rates; 191 192 spinlock_t ampdu_lock; /* protects next two fields */ 193 enum wcn36xx_ampdu_state ampdu_state[16]; 194 int non_agg_frame_ct; 195 }; 196 struct wcn36xx_dxe_ch; 197 struct wcn36xx { 198 struct ieee80211_hw *hw; 199 struct device *dev; 200 struct list_head vif_list; 201 202 const struct firmware *nv; 203 204 u8 fw_revision; 205 u8 fw_version; 206 u8 fw_minor; 207 u8 fw_major; 208 u32 fw_feat_caps[WCN36XX_HAL_CAPS_SIZE]; 209 bool is_pronto; 210 211 /* extra byte for the NULL termination */ 212 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH + 1]; 213 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH + 1]; 214 215 bool first_boot; 216 217 /* IRQs */ 218 int tx_irq; 219 int rx_irq; 220 void __iomem *ccu_base; 221 void __iomem *dxe_base; 222 223 struct rpmsg_endpoint *smd_channel; 224 225 struct qcom_smem_state *tx_enable_state; 226 unsigned tx_enable_state_bit; 227 struct qcom_smem_state *tx_rings_empty_state; 228 unsigned tx_rings_empty_state_bit; 229 230 /* prevents concurrent FW reconfiguration */ 231 struct mutex conf_mutex; 232 233 /* 234 * smd_buf must be protected with smd_mutex to garantee 235 * that all messages are sent one after another 236 */ 237 u8 *hal_buf; 238 size_t hal_rsp_len; 239 struct mutex hal_mutex; 240 struct completion hal_rsp_compl; 241 struct workqueue_struct *hal_ind_wq; 242 struct work_struct hal_ind_work; 243 spinlock_t hal_ind_lock; 244 struct list_head hal_ind_queue; 245 246 struct cfg80211_scan_request *scan_req; 247 bool sw_scan; 248 u8 sw_scan_opchannel; 249 struct ieee80211_vif *sw_scan_vif; 250 struct mutex scan_lock; 251 bool scan_aborted; 252 253 /* DXE channels */ 254 struct wcn36xx_dxe_ch dxe_tx_l_ch; /* TX low */ 255 struct wcn36xx_dxe_ch dxe_tx_h_ch; /* TX high */ 256 struct wcn36xx_dxe_ch dxe_rx_l_ch; /* RX low */ 257 struct wcn36xx_dxe_ch dxe_rx_h_ch; /* RX high */ 258 259 /* For synchronization of DXE resources from BH, IRQ and WQ contexts */ 260 spinlock_t dxe_lock; 261 bool queues_stopped; 262 263 /* Memory pools */ 264 struct wcn36xx_dxe_mem_pool mgmt_mem_pool; 265 struct wcn36xx_dxe_mem_pool data_mem_pool; 266 267 struct sk_buff *tx_ack_skb; 268 struct timer_list tx_ack_timer; 269 270 /* RF module */ 271 unsigned rf_id; 272 273 #ifdef CONFIG_WCN36XX_DEBUGFS 274 /* Debug file system entry */ 275 struct wcn36xx_dfs_entry dfs; 276 #endif /* CONFIG_WCN36XX_DEBUGFS */ 277 278 }; 279 280 static inline bool wcn36xx_is_fw_version(struct wcn36xx *wcn, 281 u8 major, 282 u8 minor, 283 u8 version, 284 u8 revision) 285 { 286 return (wcn->fw_major == major && 287 wcn->fw_minor == minor && 288 wcn->fw_version == version && 289 wcn->fw_revision == revision); 290 } 291 void wcn36xx_set_default_rates(struct wcn36xx_hal_supported_rates *rates); 292 void wcn36xx_set_default_rates_v1(struct wcn36xx_hal_supported_rates_v1 *rates); 293 294 static inline 295 struct ieee80211_sta *wcn36xx_priv_to_sta(struct wcn36xx_sta *sta_priv) 296 { 297 return container_of((void *)sta_priv, struct ieee80211_sta, drv_priv); 298 } 299 300 static inline 301 struct wcn36xx_vif *wcn36xx_vif_to_priv(struct ieee80211_vif *vif) 302 { 303 return (struct wcn36xx_vif *) vif->drv_priv; 304 } 305 306 static inline 307 struct ieee80211_vif *wcn36xx_priv_to_vif(struct wcn36xx_vif *vif_priv) 308 { 309 return container_of((void *) vif_priv, struct ieee80211_vif, drv_priv); 310 } 311 312 static inline 313 struct wcn36xx_sta *wcn36xx_sta_to_priv(struct ieee80211_sta *sta) 314 { 315 return (struct wcn36xx_sta *)sta->drv_priv; 316 } 317 318 #endif /* _WCN36XX_H_ */ 319