1 /* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _TXRX_H_ 18 #define _TXRX_H_ 19 20 #include <linux/etherdevice.h> 21 #include "wcn36xx.h" 22 23 /* TODO describe all properties */ 24 #define WCN36XX_802_11_HEADER_LEN 24 25 #define WCN36XX_BMU_WQ_TX 25 26 #define WCN36XX_TID 7 27 /* broadcast wq ID */ 28 #define WCN36XX_TX_B_WQ_ID 0xA 29 #define WCN36XX_TX_U_WQ_ID 0x9 30 /* bd_rate */ 31 #define WCN36XX_BD_RATE_DATA 0 32 #define WCN36XX_BD_RATE_MGMT 2 33 #define WCN36XX_BD_RATE_CTRL 3 34 35 struct wcn36xx_pdu { 36 u32 dpu_fb:8; 37 u32 adu_fb:8; 38 u32 pdu_id:16; 39 40 /* 0x04*/ 41 u32 tail_pdu_idx:16; 42 u32 head_pdu_idx:16; 43 44 /* 0x08*/ 45 u32 pdu_count:7; 46 u32 mpdu_data_off:9; 47 u32 mpdu_header_off:8; 48 u32 mpdu_header_len:8; 49 50 /* 0x0c*/ 51 u32 reserved4:8; 52 u32 tid:4; 53 u32 reserved3:4; 54 u32 mpdu_len:16; 55 }; 56 57 struct wcn36xx_rx_bd { 58 u32 bdt:2; 59 u32 ft:1; 60 u32 dpu_ne:1; 61 u32 rx_key_id:3; 62 u32 ub:1; 63 u32 rmf:1; 64 u32 uma_bypass:1; 65 u32 csr11:1; 66 u32 reserved0:1; 67 u32 scan_learn:1; 68 u32 rx_ch:4; 69 u32 rtsf:1; 70 u32 bsf:1; 71 u32 a2hf:1; 72 u32 st_auf:1; 73 u32 dpu_sign:3; 74 u32 dpu_rf:8; 75 76 struct wcn36xx_pdu pdu; 77 78 /* 0x14*/ 79 u32 addr3:8; 80 u32 addr2:8; 81 u32 addr1:8; 82 u32 dpu_desc_idx:8; 83 84 /* 0x18*/ 85 u32 rxp_flags:23; 86 u32 rate_id:9; 87 88 u32 phy_stat0; 89 u32 phy_stat1; 90 91 /* 0x24 */ 92 u32 rx_times; 93 94 u32 pmi_cmd[6]; 95 96 /* 0x40 */ 97 u32 reserved7:4; 98 u32 reorder_slot_id:6; 99 u32 reorder_fwd_id:6; 100 u32 reserved6:12; 101 u32 reorder_code:4; 102 103 /* 0x44 */ 104 u32 exp_seq_num:12; 105 u32 cur_seq_num:12; 106 u32 fr_type_subtype:8; 107 108 /* 0x48 */ 109 u32 msdu_size:16; 110 u32 sub_fr_id:4; 111 u32 proc_order:4; 112 u32 reserved9:4; 113 u32 aef:1; 114 u32 lsf:1; 115 u32 esf:1; 116 u32 asf:1; 117 }; 118 119 struct wcn36xx_tx_bd { 120 u32 bdt:2; 121 u32 ft:1; 122 u32 dpu_ne:1; 123 u32 fw_tx_comp:1; 124 u32 tx_comp:1; 125 u32 reserved1:1; 126 u32 ub:1; 127 u32 rmf:1; 128 u32 reserved0:12; 129 u32 dpu_sign:3; 130 u32 dpu_rf:8; 131 132 struct wcn36xx_pdu pdu; 133 134 /* 0x14*/ 135 u32 reserved5:7; 136 u32 queue_id:5; 137 u32 bd_rate:2; 138 u32 ack_policy:2; 139 u32 sta_index:8; 140 u32 dpu_desc_idx:8; 141 142 u32 tx_bd_sign; 143 u32 reserved6; 144 u32 dxe_start_time; 145 u32 dxe_end_time; 146 147 /*u32 tcp_udp_start_off:10; 148 u32 header_cks:16; 149 u32 reserved7:6;*/ 150 }; 151 152 struct wcn36xx_sta; 153 struct wcn36xx; 154 155 int wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb); 156 int wcn36xx_start_tx(struct wcn36xx *wcn, 157 struct wcn36xx_sta *sta_priv, 158 struct sk_buff *skb); 159 160 #endif /* _TXRX_H_ */ 161