1 /* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* DXE - DMA transfer engine 18 * we have 2 channels(High prio and Low prio) for TX and 2 channels for RX. 19 * through low channels data packets are transfered 20 * through high channels managment packets are transfered 21 */ 22 23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25 #include <linux/interrupt.h> 26 #include <linux/soc/qcom/smem_state.h> 27 #include "wcn36xx.h" 28 #include "txrx.h" 29 30 void *wcn36xx_dxe_get_next_bd(struct wcn36xx *wcn, bool is_low) 31 { 32 struct wcn36xx_dxe_ch *ch = is_low ? 33 &wcn->dxe_tx_l_ch : 34 &wcn->dxe_tx_h_ch; 35 36 return ch->head_blk_ctl->bd_cpu_addr; 37 } 38 39 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data) 40 { 41 wcn36xx_dbg(WCN36XX_DBG_DXE, 42 "wcn36xx_ccu_write_register: addr=%x, data=%x\n", 43 addr, data); 44 45 writel(data, wcn->ccu_base + addr); 46 } 47 48 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data) 49 { 50 wcn36xx_dbg(WCN36XX_DBG_DXE, 51 "wcn36xx_dxe_write_register: addr=%x, data=%x\n", 52 addr, data); 53 54 writel(data, wcn->dxe_base + addr); 55 } 56 57 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data) 58 { 59 *data = readl(wcn->dxe_base + addr); 60 61 wcn36xx_dbg(WCN36XX_DBG_DXE, 62 "wcn36xx_dxe_read_register: addr=%x, data=%x\n", 63 addr, *data); 64 } 65 66 static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch) 67 { 68 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next; 69 int i; 70 71 for (i = 0; i < ch->desc_num && ctl; i++) { 72 next = ctl->next; 73 kfree(ctl); 74 ctl = next; 75 } 76 } 77 78 static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch) 79 { 80 struct wcn36xx_dxe_ctl *prev_ctl = NULL; 81 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 82 int i; 83 84 spin_lock_init(&ch->lock); 85 for (i = 0; i < ch->desc_num; i++) { 86 cur_ctl = kzalloc(sizeof(*cur_ctl), GFP_KERNEL); 87 if (!cur_ctl) 88 goto out_fail; 89 90 spin_lock_init(&cur_ctl->skb_lock); 91 cur_ctl->ctl_blk_order = i; 92 if (i == 0) { 93 ch->head_blk_ctl = cur_ctl; 94 ch->tail_blk_ctl = cur_ctl; 95 } else if (ch->desc_num - 1 == i) { 96 prev_ctl->next = cur_ctl; 97 cur_ctl->next = ch->head_blk_ctl; 98 } else { 99 prev_ctl->next = cur_ctl; 100 } 101 prev_ctl = cur_ctl; 102 } 103 104 return 0; 105 106 out_fail: 107 wcn36xx_dxe_free_ctl_block(ch); 108 return -ENOMEM; 109 } 110 111 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn) 112 { 113 int ret; 114 115 wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L; 116 wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H; 117 wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L; 118 wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H; 119 120 wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L; 121 wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H; 122 wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L; 123 wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H; 124 125 wcn->dxe_tx_l_ch.dxe_wq = WCN36XX_DXE_WQ_TX_L; 126 wcn->dxe_tx_h_ch.dxe_wq = WCN36XX_DXE_WQ_TX_H; 127 128 wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD; 129 wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD; 130 131 wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB; 132 wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB; 133 134 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L; 135 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H; 136 137 wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L; 138 wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H; 139 140 /* DXE control block allocation */ 141 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch); 142 if (ret) 143 goto out_err; 144 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch); 145 if (ret) 146 goto out_err; 147 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch); 148 if (ret) 149 goto out_err; 150 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch); 151 if (ret) 152 goto out_err; 153 154 /* Initialize SMSM state Clear TX Enable RING EMPTY STATE */ 155 ret = qcom_smem_state_update_bits(wcn->tx_enable_state, 156 WCN36XX_SMSM_WLAN_TX_ENABLE | 157 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY, 158 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY); 159 if (ret) 160 goto out_err; 161 162 return 0; 163 164 out_err: 165 wcn36xx_err("Failed to allocate DXE control blocks\n"); 166 wcn36xx_dxe_free_ctl_blks(wcn); 167 return -ENOMEM; 168 } 169 170 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn) 171 { 172 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch); 173 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch); 174 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch); 175 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch); 176 } 177 178 static int wcn36xx_dxe_init_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 179 { 180 struct wcn36xx_dxe_desc *cur_dxe = NULL; 181 struct wcn36xx_dxe_desc *prev_dxe = NULL; 182 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 183 size_t size; 184 int i; 185 186 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 187 wcn_ch->cpu_addr = dma_alloc_coherent(dev, size, &wcn_ch->dma_addr, 188 GFP_KERNEL); 189 if (!wcn_ch->cpu_addr) 190 return -ENOMEM; 191 192 memset(wcn_ch->cpu_addr, 0, size); 193 194 cur_dxe = (struct wcn36xx_dxe_desc *)wcn_ch->cpu_addr; 195 cur_ctl = wcn_ch->head_blk_ctl; 196 197 for (i = 0; i < wcn_ch->desc_num; i++) { 198 cur_ctl->desc = cur_dxe; 199 cur_ctl->desc_phy_addr = wcn_ch->dma_addr + 200 i * sizeof(struct wcn36xx_dxe_desc); 201 202 switch (wcn_ch->ch_type) { 203 case WCN36XX_DXE_CH_TX_L: 204 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_L; 205 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L; 206 break; 207 case WCN36XX_DXE_CH_TX_H: 208 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_H; 209 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H; 210 break; 211 case WCN36XX_DXE_CH_RX_L: 212 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_L; 213 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_L; 214 break; 215 case WCN36XX_DXE_CH_RX_H: 216 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_H; 217 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_H; 218 break; 219 } 220 if (0 == i) { 221 cur_dxe->phy_next_l = 0; 222 } else if ((0 < i) && (i < wcn_ch->desc_num - 1)) { 223 prev_dxe->phy_next_l = 224 cur_ctl->desc_phy_addr; 225 } else if (i == (wcn_ch->desc_num - 1)) { 226 prev_dxe->phy_next_l = 227 cur_ctl->desc_phy_addr; 228 cur_dxe->phy_next_l = 229 wcn_ch->head_blk_ctl->desc_phy_addr; 230 } 231 cur_ctl = cur_ctl->next; 232 prev_dxe = cur_dxe; 233 cur_dxe++; 234 } 235 236 return 0; 237 } 238 239 static void wcn36xx_dxe_deinit_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 240 { 241 size_t size; 242 243 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 244 dma_free_coherent(dev, size,wcn_ch->cpu_addr, wcn_ch->dma_addr); 245 } 246 247 static void wcn36xx_dxe_init_tx_bd(struct wcn36xx_dxe_ch *ch, 248 struct wcn36xx_dxe_mem_pool *pool) 249 { 250 int i, chunk_size = pool->chunk_size; 251 dma_addr_t bd_phy_addr = pool->phy_addr; 252 void *bd_cpu_addr = pool->virt_addr; 253 struct wcn36xx_dxe_ctl *cur = ch->head_blk_ctl; 254 255 for (i = 0; i < ch->desc_num; i++) { 256 /* Only every second dxe needs a bd pointer, 257 the other will point to the skb data */ 258 if (!(i & 1)) { 259 cur->bd_phy_addr = bd_phy_addr; 260 cur->bd_cpu_addr = bd_cpu_addr; 261 bd_phy_addr += chunk_size; 262 bd_cpu_addr += chunk_size; 263 } else { 264 cur->bd_phy_addr = 0; 265 cur->bd_cpu_addr = NULL; 266 } 267 cur = cur->next; 268 } 269 } 270 271 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch) 272 { 273 int reg_data = 0; 274 275 wcn36xx_dxe_read_register(wcn, 276 WCN36XX_DXE_INT_MASK_REG, 277 ®_data); 278 279 reg_data |= wcn_ch; 280 281 wcn36xx_dxe_write_register(wcn, 282 WCN36XX_DXE_INT_MASK_REG, 283 (int)reg_data); 284 return 0; 285 } 286 287 static int wcn36xx_dxe_fill_skb(struct device *dev, struct wcn36xx_dxe_ctl *ctl) 288 { 289 struct wcn36xx_dxe_desc *dxe = ctl->desc; 290 struct sk_buff *skb; 291 292 skb = alloc_skb(WCN36XX_PKT_SIZE, GFP_ATOMIC); 293 if (skb == NULL) 294 return -ENOMEM; 295 296 dxe->dst_addr_l = dma_map_single(dev, 297 skb_tail_pointer(skb), 298 WCN36XX_PKT_SIZE, 299 DMA_FROM_DEVICE); 300 if (dma_mapping_error(dev, dxe->dst_addr_l)) { 301 dev_err(dev, "unable to map skb\n"); 302 kfree_skb(skb); 303 return -ENOMEM; 304 } 305 ctl->skb = skb; 306 307 return 0; 308 } 309 310 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn, 311 struct wcn36xx_dxe_ch *wcn_ch) 312 { 313 int i; 314 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 315 316 cur_ctl = wcn_ch->head_blk_ctl; 317 318 for (i = 0; i < wcn_ch->desc_num; i++) { 319 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl); 320 cur_ctl = cur_ctl->next; 321 } 322 323 return 0; 324 } 325 326 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn, 327 struct wcn36xx_dxe_ch *wcn_ch) 328 { 329 struct wcn36xx_dxe_ctl *cur = wcn_ch->head_blk_ctl; 330 int i; 331 332 for (i = 0; i < wcn_ch->desc_num; i++) { 333 kfree_skb(cur->skb); 334 cur = cur->next; 335 } 336 } 337 338 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status) 339 { 340 struct ieee80211_tx_info *info; 341 struct sk_buff *skb; 342 unsigned long flags; 343 344 spin_lock_irqsave(&wcn->dxe_lock, flags); 345 skb = wcn->tx_ack_skb; 346 wcn->tx_ack_skb = NULL; 347 spin_unlock_irqrestore(&wcn->dxe_lock, flags); 348 349 if (!skb) { 350 wcn36xx_warn("Spurious TX complete indication\n"); 351 return; 352 } 353 354 info = IEEE80211_SKB_CB(skb); 355 356 if (status == 1) 357 info->flags |= IEEE80211_TX_STAT_ACK; 358 359 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ack status: %d\n", status); 360 361 ieee80211_tx_status_irqsafe(wcn->hw, skb); 362 ieee80211_wake_queues(wcn->hw); 363 } 364 365 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch) 366 { 367 struct wcn36xx_dxe_ctl *ctl; 368 struct ieee80211_tx_info *info; 369 unsigned long flags; 370 371 /* 372 * Make at least one loop of do-while because in case ring is 373 * completely full head and tail are pointing to the same element 374 * and while-do will not make any cycles. 375 */ 376 spin_lock_irqsave(&ch->lock, flags); 377 ctl = ch->tail_blk_ctl; 378 do { 379 if (ctl->desc->ctrl & WCN36XX_DXE_CTRL_VALID_MASK) 380 break; 381 if (ctl->skb) { 382 dma_unmap_single(wcn->dev, ctl->desc->src_addr_l, 383 ctl->skb->len, DMA_TO_DEVICE); 384 info = IEEE80211_SKB_CB(ctl->skb); 385 if (!(info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)) { 386 /* Keep frame until TX status comes */ 387 ieee80211_free_txskb(wcn->hw, ctl->skb); 388 } 389 spin_lock(&ctl->skb_lock); 390 if (wcn->queues_stopped) { 391 wcn->queues_stopped = false; 392 ieee80211_wake_queues(wcn->hw); 393 } 394 spin_unlock(&ctl->skb_lock); 395 396 ctl->skb = NULL; 397 } 398 ctl = ctl->next; 399 } while (ctl != ch->head_blk_ctl && 400 !(ctl->desc->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)); 401 402 ch->tail_blk_ctl = ctl; 403 spin_unlock_irqrestore(&ch->lock, flags); 404 } 405 406 static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev) 407 { 408 struct wcn36xx *wcn = (struct wcn36xx *)dev; 409 int int_src, int_reason; 410 411 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 412 413 if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) { 414 wcn36xx_dxe_read_register(wcn, 415 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H, 416 &int_reason); 417 418 /* TODO: Check int_reason */ 419 420 wcn36xx_dxe_write_register(wcn, 421 WCN36XX_DXE_0_INT_CLR, 422 WCN36XX_INT_MASK_CHAN_TX_H); 423 424 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR, 425 WCN36XX_INT_MASK_CHAN_TX_H); 426 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n"); 427 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch); 428 } 429 430 if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) { 431 wcn36xx_dxe_read_register(wcn, 432 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L, 433 &int_reason); 434 /* TODO: Check int_reason */ 435 436 wcn36xx_dxe_write_register(wcn, 437 WCN36XX_DXE_0_INT_CLR, 438 WCN36XX_INT_MASK_CHAN_TX_L); 439 440 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR, 441 WCN36XX_INT_MASK_CHAN_TX_L); 442 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n"); 443 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch); 444 } 445 446 return IRQ_HANDLED; 447 } 448 449 static irqreturn_t wcn36xx_irq_rx_ready(int irq, void *dev) 450 { 451 struct wcn36xx *wcn = (struct wcn36xx *)dev; 452 453 disable_irq_nosync(wcn->rx_irq); 454 wcn36xx_dxe_rx_frame(wcn); 455 enable_irq(wcn->rx_irq); 456 return IRQ_HANDLED; 457 } 458 459 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn) 460 { 461 int ret; 462 463 ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete, 464 IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn); 465 if (ret) { 466 wcn36xx_err("failed to alloc tx irq\n"); 467 goto out_err; 468 } 469 470 ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH, 471 "wcn36xx_rx", wcn); 472 if (ret) { 473 wcn36xx_err("failed to alloc rx irq\n"); 474 goto out_txirq; 475 } 476 477 enable_irq_wake(wcn->rx_irq); 478 479 return 0; 480 481 out_txirq: 482 free_irq(wcn->tx_irq, wcn); 483 out_err: 484 return ret; 485 486 } 487 488 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, 489 struct wcn36xx_dxe_ch *ch) 490 { 491 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl; 492 struct wcn36xx_dxe_desc *dxe = ctl->desc; 493 dma_addr_t dma_addr; 494 struct sk_buff *skb; 495 int ret = 0, int_mask; 496 u32 value; 497 498 if (ch->ch_type == WCN36XX_DXE_CH_RX_L) { 499 value = WCN36XX_DXE_CTRL_RX_L; 500 int_mask = WCN36XX_DXE_INT_CH1_MASK; 501 } else { 502 value = WCN36XX_DXE_CTRL_RX_H; 503 int_mask = WCN36XX_DXE_INT_CH3_MASK; 504 } 505 506 while (!(dxe->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) { 507 skb = ctl->skb; 508 dma_addr = dxe->dst_addr_l; 509 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl); 510 if (0 == ret) { 511 /* new skb allocation ok. Use the new one and queue 512 * the old one to network system. 513 */ 514 dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE, 515 DMA_FROM_DEVICE); 516 wcn36xx_rx_skb(wcn, skb); 517 } /* else keep old skb not submitted and use it for rx DMA */ 518 519 dxe->ctrl = value; 520 ctl = ctl->next; 521 dxe = ctl->desc; 522 } 523 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, int_mask); 524 525 ch->head_blk_ctl = ctl; 526 return 0; 527 } 528 529 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn) 530 { 531 int int_src; 532 533 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 534 535 /* RX_LOW_PRI */ 536 if (int_src & WCN36XX_DXE_INT_CH1_MASK) { 537 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, 538 WCN36XX_DXE_INT_CH1_MASK); 539 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_l_ch)); 540 } 541 542 /* RX_HIGH_PRI */ 543 if (int_src & WCN36XX_DXE_INT_CH3_MASK) { 544 /* Clean up all the INT within this channel */ 545 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, 546 WCN36XX_DXE_INT_CH3_MASK); 547 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_h_ch)); 548 } 549 550 if (!int_src) 551 wcn36xx_warn("No DXE interrupt pending\n"); 552 } 553 554 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn) 555 { 556 size_t s; 557 void *cpu_addr; 558 559 /* Allocate BD headers for MGMT frames */ 560 561 /* Where this come from ask QC */ 562 wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 563 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 564 565 s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H; 566 cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->mgmt_mem_pool.phy_addr, 567 GFP_KERNEL); 568 if (!cpu_addr) 569 goto out_err; 570 571 wcn->mgmt_mem_pool.virt_addr = cpu_addr; 572 memset(cpu_addr, 0, s); 573 574 /* Allocate BD headers for DATA frames */ 575 576 /* Where this come from ask QC */ 577 wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 578 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 579 580 s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L; 581 cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->data_mem_pool.phy_addr, 582 GFP_KERNEL); 583 if (!cpu_addr) 584 goto out_err; 585 586 wcn->data_mem_pool.virt_addr = cpu_addr; 587 memset(cpu_addr, 0, s); 588 589 return 0; 590 591 out_err: 592 wcn36xx_dxe_free_mem_pools(wcn); 593 wcn36xx_err("Failed to allocate BD mempool\n"); 594 return -ENOMEM; 595 } 596 597 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn) 598 { 599 if (wcn->mgmt_mem_pool.virt_addr) 600 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size * 601 WCN36XX_DXE_CH_DESC_NUMB_TX_H, 602 wcn->mgmt_mem_pool.virt_addr, 603 wcn->mgmt_mem_pool.phy_addr); 604 605 if (wcn->data_mem_pool.virt_addr) { 606 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size * 607 WCN36XX_DXE_CH_DESC_NUMB_TX_L, 608 wcn->data_mem_pool.virt_addr, 609 wcn->data_mem_pool.phy_addr); 610 } 611 } 612 613 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, 614 struct wcn36xx_vif *vif_priv, 615 struct sk_buff *skb, 616 bool is_low) 617 { 618 struct wcn36xx_dxe_ctl *ctl = NULL; 619 struct wcn36xx_dxe_desc *desc = NULL; 620 struct wcn36xx_dxe_ch *ch = NULL; 621 unsigned long flags; 622 int ret; 623 624 ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch; 625 626 spin_lock_irqsave(&ch->lock, flags); 627 ctl = ch->head_blk_ctl; 628 629 spin_lock(&ctl->next->skb_lock); 630 631 /* 632 * If skb is not null that means that we reached the tail of the ring 633 * hence ring is full. Stop queues to let mac80211 back off until ring 634 * has an empty slot again. 635 */ 636 if (NULL != ctl->next->skb) { 637 ieee80211_stop_queues(wcn->hw); 638 wcn->queues_stopped = true; 639 spin_unlock(&ctl->next->skb_lock); 640 spin_unlock_irqrestore(&ch->lock, flags); 641 return -EBUSY; 642 } 643 spin_unlock(&ctl->next->skb_lock); 644 645 ctl->skb = NULL; 646 desc = ctl->desc; 647 648 /* Set source address of the BD we send */ 649 desc->src_addr_l = ctl->bd_phy_addr; 650 651 desc->dst_addr_l = ch->dxe_wq; 652 desc->fr_len = sizeof(struct wcn36xx_tx_bd); 653 desc->ctrl = ch->ctrl_bd; 654 655 wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n"); 656 657 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ", 658 (char *)desc, sizeof(*desc)); 659 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, 660 "BD >>> ", (char *)ctl->bd_cpu_addr, 661 sizeof(struct wcn36xx_tx_bd)); 662 663 /* Set source address of the SKB we send */ 664 ctl = ctl->next; 665 ctl->skb = skb; 666 desc = ctl->desc; 667 if (ctl->bd_cpu_addr) { 668 wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n"); 669 ret = -EINVAL; 670 goto unlock; 671 } 672 673 desc->src_addr_l = dma_map_single(wcn->dev, 674 ctl->skb->data, 675 ctl->skb->len, 676 DMA_TO_DEVICE); 677 678 desc->dst_addr_l = ch->dxe_wq; 679 desc->fr_len = ctl->skb->len; 680 681 /* set dxe descriptor to VALID */ 682 desc->ctrl = ch->ctrl_skb; 683 684 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ", 685 (char *)desc, sizeof(*desc)); 686 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ", 687 (char *)ctl->skb->data, ctl->skb->len); 688 689 /* Move the head of the ring to the next empty descriptor */ 690 ch->head_blk_ctl = ctl->next; 691 692 /* 693 * When connected and trying to send data frame chip can be in sleep 694 * mode and writing to the register will not wake up the chip. Instead 695 * notify chip about new frame through SMSM bus. 696 */ 697 if (is_low && vif_priv->pw_state == WCN36XX_BMPS) { 698 qcom_smem_state_update_bits(wcn->tx_rings_empty_state, 699 WCN36XX_SMSM_WLAN_TX_ENABLE, 700 WCN36XX_SMSM_WLAN_TX_ENABLE); 701 } else { 702 /* indicate End Of Packet and generate interrupt on descriptor 703 * done. 704 */ 705 wcn36xx_dxe_write_register(wcn, 706 ch->reg_ctrl, ch->def_ctrl); 707 } 708 709 ret = 0; 710 unlock: 711 spin_unlock_irqrestore(&ch->lock, flags); 712 return ret; 713 } 714 715 int wcn36xx_dxe_init(struct wcn36xx *wcn) 716 { 717 int reg_data = 0, ret; 718 719 reg_data = WCN36XX_DXE_REG_RESET; 720 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data); 721 722 /* Select channels for rx avail and xfer done interrupts... */ 723 reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 | 724 WCN36XX_DXE_INT_CH0_MASK | WCN36XX_DXE_INT_CH4_MASK; 725 if (wcn->is_pronto) 726 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data); 727 else 728 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data); 729 730 /***************************************/ 731 /* Init descriptors for TX LOW channel */ 732 /***************************************/ 733 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_l_ch); 734 if (ret) { 735 dev_err(wcn->dev, "Error allocating descriptor\n"); 736 return ret; 737 } 738 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool); 739 740 /* Write channel head to a NEXT register */ 741 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L, 742 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr); 743 744 /* Program DMA destination addr for TX LOW */ 745 wcn36xx_dxe_write_register(wcn, 746 WCN36XX_DXE_CH_DEST_ADDR_TX_L, 747 WCN36XX_DXE_WQ_TX_L); 748 749 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 750 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L); 751 752 /***************************************/ 753 /* Init descriptors for TX HIGH channel */ 754 /***************************************/ 755 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_h_ch); 756 if (ret) { 757 dev_err(wcn->dev, "Error allocating descriptor\n"); 758 goto out_err_txh_ch; 759 } 760 761 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool); 762 763 /* Write channel head to a NEXT register */ 764 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H, 765 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr); 766 767 /* Program DMA destination addr for TX HIGH */ 768 wcn36xx_dxe_write_register(wcn, 769 WCN36XX_DXE_CH_DEST_ADDR_TX_H, 770 WCN36XX_DXE_WQ_TX_H); 771 772 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 773 774 /* Enable channel interrupts */ 775 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H); 776 777 /***************************************/ 778 /* Init descriptors for RX LOW channel */ 779 /***************************************/ 780 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_l_ch); 781 if (ret) { 782 dev_err(wcn->dev, "Error allocating descriptor\n"); 783 goto out_err_rxl_ch; 784 } 785 786 787 /* For RX we need to preallocated buffers */ 788 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch); 789 790 /* Write channel head to a NEXT register */ 791 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L, 792 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr); 793 794 /* Write DMA source address */ 795 wcn36xx_dxe_write_register(wcn, 796 WCN36XX_DXE_CH_SRC_ADDR_RX_L, 797 WCN36XX_DXE_WQ_RX_L); 798 799 /* Program preallocated destination address */ 800 wcn36xx_dxe_write_register(wcn, 801 WCN36XX_DXE_CH_DEST_ADDR_RX_L, 802 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l); 803 804 /* Enable default control registers */ 805 wcn36xx_dxe_write_register(wcn, 806 WCN36XX_DXE_REG_CTL_RX_L, 807 WCN36XX_DXE_CH_DEFAULT_CTL_RX_L); 808 809 /* Enable channel interrupts */ 810 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L); 811 812 /***************************************/ 813 /* Init descriptors for RX HIGH channel */ 814 /***************************************/ 815 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_h_ch); 816 if (ret) { 817 dev_err(wcn->dev, "Error allocating descriptor\n"); 818 goto out_err_rxh_ch; 819 } 820 821 /* For RX we need to prealocat buffers */ 822 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch); 823 824 /* Write chanel head to a NEXT register */ 825 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H, 826 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr); 827 828 /* Write DMA source address */ 829 wcn36xx_dxe_write_register(wcn, 830 WCN36XX_DXE_CH_SRC_ADDR_RX_H, 831 WCN36XX_DXE_WQ_RX_H); 832 833 /* Program preallocated destination address */ 834 wcn36xx_dxe_write_register(wcn, 835 WCN36XX_DXE_CH_DEST_ADDR_RX_H, 836 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l); 837 838 /* Enable default control registers */ 839 wcn36xx_dxe_write_register(wcn, 840 WCN36XX_DXE_REG_CTL_RX_H, 841 WCN36XX_DXE_CH_DEFAULT_CTL_RX_H); 842 843 /* Enable channel interrupts */ 844 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H); 845 846 ret = wcn36xx_dxe_request_irqs(wcn); 847 if (ret < 0) 848 goto out_err_irq; 849 850 return 0; 851 852 out_err_irq: 853 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch); 854 out_err_rxh_ch: 855 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch); 856 out_err_rxl_ch: 857 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch); 858 out_err_txh_ch: 859 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch); 860 861 return ret; 862 } 863 864 void wcn36xx_dxe_deinit(struct wcn36xx *wcn) 865 { 866 free_irq(wcn->tx_irq, wcn); 867 free_irq(wcn->rx_irq, wcn); 868 869 if (wcn->tx_ack_skb) { 870 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb); 871 wcn->tx_ack_skb = NULL; 872 } 873 874 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch); 875 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch); 876 } 877