1 /* 2 * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /* DXE - DMA transfer engine 18 * we have 2 channels(High prio and Low prio) for TX and 2 channels for RX. 19 * through low channels data packets are transfered 20 * through high channels managment packets are transfered 21 */ 22 23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25 #include <linux/interrupt.h> 26 #include <linux/soc/qcom/smem_state.h> 27 #include "wcn36xx.h" 28 #include "txrx.h" 29 30 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data) 31 { 32 wcn36xx_dbg(WCN36XX_DBG_DXE, 33 "wcn36xx_ccu_write_register: addr=%x, data=%x\n", 34 addr, data); 35 36 writel(data, wcn->ccu_base + addr); 37 } 38 39 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data) 40 { 41 wcn36xx_dbg(WCN36XX_DBG_DXE, 42 "wcn36xx_dxe_write_register: addr=%x, data=%x\n", 43 addr, data); 44 45 writel(data, wcn->dxe_base + addr); 46 } 47 48 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data) 49 { 50 *data = readl(wcn->dxe_base + addr); 51 52 wcn36xx_dbg(WCN36XX_DBG_DXE, 53 "wcn36xx_dxe_read_register: addr=%x, data=%x\n", 54 addr, *data); 55 } 56 57 static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch) 58 { 59 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next; 60 int i; 61 62 for (i = 0; i < ch->desc_num && ctl; i++) { 63 next = ctl->next; 64 kfree(ctl); 65 ctl = next; 66 } 67 } 68 69 static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch) 70 { 71 struct wcn36xx_dxe_ctl *prev_ctl = NULL; 72 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 73 int i; 74 75 spin_lock_init(&ch->lock); 76 for (i = 0; i < ch->desc_num; i++) { 77 cur_ctl = kzalloc(sizeof(*cur_ctl), GFP_KERNEL); 78 if (!cur_ctl) 79 goto out_fail; 80 81 cur_ctl->ctl_blk_order = i; 82 if (i == 0) { 83 ch->head_blk_ctl = cur_ctl; 84 ch->tail_blk_ctl = cur_ctl; 85 } else if (ch->desc_num - 1 == i) { 86 prev_ctl->next = cur_ctl; 87 cur_ctl->next = ch->head_blk_ctl; 88 } else { 89 prev_ctl->next = cur_ctl; 90 } 91 prev_ctl = cur_ctl; 92 } 93 94 return 0; 95 96 out_fail: 97 wcn36xx_dxe_free_ctl_block(ch); 98 return -ENOMEM; 99 } 100 101 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn) 102 { 103 int ret; 104 105 wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L; 106 wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H; 107 wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L; 108 wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H; 109 110 wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L; 111 wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H; 112 wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L; 113 wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H; 114 115 wcn->dxe_tx_l_ch.dxe_wq = WCN36XX_DXE_WQ_TX_L; 116 wcn->dxe_tx_h_ch.dxe_wq = WCN36XX_DXE_WQ_TX_H; 117 118 wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD; 119 wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD; 120 121 wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB; 122 wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB; 123 124 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L; 125 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H; 126 127 wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L; 128 wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H; 129 130 /* DXE control block allocation */ 131 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch); 132 if (ret) 133 goto out_err; 134 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch); 135 if (ret) 136 goto out_err; 137 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch); 138 if (ret) 139 goto out_err; 140 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch); 141 if (ret) 142 goto out_err; 143 144 /* Initialize SMSM state Clear TX Enable RING EMPTY STATE */ 145 ret = qcom_smem_state_update_bits(wcn->tx_enable_state, 146 WCN36XX_SMSM_WLAN_TX_ENABLE | 147 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY, 148 WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY); 149 if (ret) 150 goto out_err; 151 152 return 0; 153 154 out_err: 155 wcn36xx_err("Failed to allocate DXE control blocks\n"); 156 wcn36xx_dxe_free_ctl_blks(wcn); 157 return -ENOMEM; 158 } 159 160 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn) 161 { 162 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch); 163 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch); 164 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch); 165 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch); 166 } 167 168 static int wcn36xx_dxe_init_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 169 { 170 struct wcn36xx_dxe_desc *cur_dxe = NULL; 171 struct wcn36xx_dxe_desc *prev_dxe = NULL; 172 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 173 size_t size; 174 int i; 175 176 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 177 wcn_ch->cpu_addr = dma_alloc_coherent(dev, size, &wcn_ch->dma_addr, 178 GFP_KERNEL); 179 if (!wcn_ch->cpu_addr) 180 return -ENOMEM; 181 182 memset(wcn_ch->cpu_addr, 0, size); 183 184 cur_dxe = (struct wcn36xx_dxe_desc *)wcn_ch->cpu_addr; 185 cur_ctl = wcn_ch->head_blk_ctl; 186 187 for (i = 0; i < wcn_ch->desc_num; i++) { 188 cur_ctl->desc = cur_dxe; 189 cur_ctl->desc_phy_addr = wcn_ch->dma_addr + 190 i * sizeof(struct wcn36xx_dxe_desc); 191 192 switch (wcn_ch->ch_type) { 193 case WCN36XX_DXE_CH_TX_L: 194 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_L; 195 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L; 196 break; 197 case WCN36XX_DXE_CH_TX_H: 198 cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_H; 199 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H; 200 break; 201 case WCN36XX_DXE_CH_RX_L: 202 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_L; 203 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_L; 204 break; 205 case WCN36XX_DXE_CH_RX_H: 206 cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_H; 207 cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_H; 208 break; 209 } 210 if (0 == i) { 211 cur_dxe->phy_next_l = 0; 212 } else if ((0 < i) && (i < wcn_ch->desc_num - 1)) { 213 prev_dxe->phy_next_l = 214 cur_ctl->desc_phy_addr; 215 } else if (i == (wcn_ch->desc_num - 1)) { 216 prev_dxe->phy_next_l = 217 cur_ctl->desc_phy_addr; 218 cur_dxe->phy_next_l = 219 wcn_ch->head_blk_ctl->desc_phy_addr; 220 } 221 cur_ctl = cur_ctl->next; 222 prev_dxe = cur_dxe; 223 cur_dxe++; 224 } 225 226 return 0; 227 } 228 229 static void wcn36xx_dxe_deinit_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch) 230 { 231 size_t size; 232 233 size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc); 234 dma_free_coherent(dev, size,wcn_ch->cpu_addr, wcn_ch->dma_addr); 235 } 236 237 static void wcn36xx_dxe_init_tx_bd(struct wcn36xx_dxe_ch *ch, 238 struct wcn36xx_dxe_mem_pool *pool) 239 { 240 int i, chunk_size = pool->chunk_size; 241 dma_addr_t bd_phy_addr = pool->phy_addr; 242 void *bd_cpu_addr = pool->virt_addr; 243 struct wcn36xx_dxe_ctl *cur = ch->head_blk_ctl; 244 245 for (i = 0; i < ch->desc_num; i++) { 246 /* Only every second dxe needs a bd pointer, 247 the other will point to the skb data */ 248 if (!(i & 1)) { 249 cur->bd_phy_addr = bd_phy_addr; 250 cur->bd_cpu_addr = bd_cpu_addr; 251 bd_phy_addr += chunk_size; 252 bd_cpu_addr += chunk_size; 253 } else { 254 cur->bd_phy_addr = 0; 255 cur->bd_cpu_addr = NULL; 256 } 257 cur = cur->next; 258 } 259 } 260 261 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch) 262 { 263 int reg_data = 0; 264 265 wcn36xx_dxe_read_register(wcn, 266 WCN36XX_DXE_INT_MASK_REG, 267 ®_data); 268 269 reg_data |= wcn_ch; 270 271 wcn36xx_dxe_write_register(wcn, 272 WCN36XX_DXE_INT_MASK_REG, 273 (int)reg_data); 274 return 0; 275 } 276 277 static int wcn36xx_dxe_fill_skb(struct device *dev, 278 struct wcn36xx_dxe_ctl *ctl, 279 gfp_t gfp) 280 { 281 struct wcn36xx_dxe_desc *dxe = ctl->desc; 282 struct sk_buff *skb; 283 284 skb = alloc_skb(WCN36XX_PKT_SIZE, gfp); 285 if (skb == NULL) 286 return -ENOMEM; 287 288 dxe->dst_addr_l = dma_map_single(dev, 289 skb_tail_pointer(skb), 290 WCN36XX_PKT_SIZE, 291 DMA_FROM_DEVICE); 292 if (dma_mapping_error(dev, dxe->dst_addr_l)) { 293 dev_err(dev, "unable to map skb\n"); 294 kfree_skb(skb); 295 return -ENOMEM; 296 } 297 ctl->skb = skb; 298 299 return 0; 300 } 301 302 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn, 303 struct wcn36xx_dxe_ch *wcn_ch) 304 { 305 int i; 306 struct wcn36xx_dxe_ctl *cur_ctl = NULL; 307 308 cur_ctl = wcn_ch->head_blk_ctl; 309 310 for (i = 0; i < wcn_ch->desc_num; i++) { 311 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL); 312 cur_ctl = cur_ctl->next; 313 } 314 315 return 0; 316 } 317 318 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn, 319 struct wcn36xx_dxe_ch *wcn_ch) 320 { 321 struct wcn36xx_dxe_ctl *cur = wcn_ch->head_blk_ctl; 322 int i; 323 324 for (i = 0; i < wcn_ch->desc_num; i++) { 325 kfree_skb(cur->skb); 326 cur = cur->next; 327 } 328 } 329 330 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status) 331 { 332 struct ieee80211_tx_info *info; 333 struct sk_buff *skb; 334 unsigned long flags; 335 336 spin_lock_irqsave(&wcn->dxe_lock, flags); 337 skb = wcn->tx_ack_skb; 338 wcn->tx_ack_skb = NULL; 339 spin_unlock_irqrestore(&wcn->dxe_lock, flags); 340 341 if (!skb) { 342 wcn36xx_warn("Spurious TX complete indication\n"); 343 return; 344 } 345 346 info = IEEE80211_SKB_CB(skb); 347 348 if (status == 1) 349 info->flags |= IEEE80211_TX_STAT_ACK; 350 351 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ack status: %d\n", status); 352 353 ieee80211_tx_status_irqsafe(wcn->hw, skb); 354 ieee80211_wake_queues(wcn->hw); 355 } 356 357 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch) 358 { 359 struct wcn36xx_dxe_ctl *ctl; 360 struct ieee80211_tx_info *info; 361 unsigned long flags; 362 363 /* 364 * Make at least one loop of do-while because in case ring is 365 * completely full head and tail are pointing to the same element 366 * and while-do will not make any cycles. 367 */ 368 spin_lock_irqsave(&ch->lock, flags); 369 ctl = ch->tail_blk_ctl; 370 do { 371 if (READ_ONCE(ctl->desc->ctrl) & WCN36xx_DXE_CTRL_VLD) 372 break; 373 if (ctl->skb) { 374 dma_unmap_single(wcn->dev, ctl->desc->src_addr_l, 375 ctl->skb->len, DMA_TO_DEVICE); 376 info = IEEE80211_SKB_CB(ctl->skb); 377 if (!(info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)) { 378 /* Keep frame until TX status comes */ 379 ieee80211_free_txskb(wcn->hw, ctl->skb); 380 } 381 382 if (wcn->queues_stopped) { 383 wcn->queues_stopped = false; 384 ieee80211_wake_queues(wcn->hw); 385 } 386 387 ctl->skb = NULL; 388 } 389 ctl = ctl->next; 390 } while (ctl != ch->head_blk_ctl); 391 392 ch->tail_blk_ctl = ctl; 393 spin_unlock_irqrestore(&ch->lock, flags); 394 } 395 396 static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev) 397 { 398 struct wcn36xx *wcn = (struct wcn36xx *)dev; 399 int int_src, int_reason; 400 401 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 402 403 if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) { 404 wcn36xx_dxe_read_register(wcn, 405 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H, 406 &int_reason); 407 408 wcn36xx_dxe_write_register(wcn, 409 WCN36XX_DXE_0_INT_CLR, 410 WCN36XX_INT_MASK_CHAN_TX_H); 411 412 if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) { 413 wcn36xx_dxe_write_register(wcn, 414 WCN36XX_DXE_0_INT_ERR_CLR, 415 WCN36XX_INT_MASK_CHAN_TX_H); 416 417 wcn36xx_err("DXE IRQ reported error: 0x%x in high TX channel\n", 418 int_src); 419 } 420 421 if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) { 422 wcn36xx_dxe_write_register(wcn, 423 WCN36XX_DXE_0_INT_DONE_CLR, 424 WCN36XX_INT_MASK_CHAN_TX_H); 425 } 426 427 if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) { 428 wcn36xx_dxe_write_register(wcn, 429 WCN36XX_DXE_0_INT_ED_CLR, 430 WCN36XX_INT_MASK_CHAN_TX_H); 431 } 432 433 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n"); 434 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch); 435 } 436 437 if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) { 438 wcn36xx_dxe_read_register(wcn, 439 WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L, 440 &int_reason); 441 442 wcn36xx_dxe_write_register(wcn, 443 WCN36XX_DXE_0_INT_CLR, 444 WCN36XX_INT_MASK_CHAN_TX_L); 445 446 447 if (int_reason & WCN36XX_CH_STAT_INT_ERR_MASK ) { 448 wcn36xx_dxe_write_register(wcn, 449 WCN36XX_DXE_0_INT_ERR_CLR, 450 WCN36XX_INT_MASK_CHAN_TX_L); 451 452 wcn36xx_err("DXE IRQ reported error: 0x%x in low TX channel\n", 453 int_src); 454 } 455 456 if (int_reason & WCN36XX_CH_STAT_INT_DONE_MASK) { 457 wcn36xx_dxe_write_register(wcn, 458 WCN36XX_DXE_0_INT_DONE_CLR, 459 WCN36XX_INT_MASK_CHAN_TX_L); 460 } 461 462 if (int_reason & WCN36XX_CH_STAT_INT_ED_MASK) { 463 wcn36xx_dxe_write_register(wcn, 464 WCN36XX_DXE_0_INT_ED_CLR, 465 WCN36XX_INT_MASK_CHAN_TX_L); 466 } 467 468 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n"); 469 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch); 470 } 471 472 return IRQ_HANDLED; 473 } 474 475 static irqreturn_t wcn36xx_irq_rx_ready(int irq, void *dev) 476 { 477 struct wcn36xx *wcn = (struct wcn36xx *)dev; 478 479 disable_irq_nosync(wcn->rx_irq); 480 wcn36xx_dxe_rx_frame(wcn); 481 enable_irq(wcn->rx_irq); 482 return IRQ_HANDLED; 483 } 484 485 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn) 486 { 487 int ret; 488 489 ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete, 490 IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn); 491 if (ret) { 492 wcn36xx_err("failed to alloc tx irq\n"); 493 goto out_err; 494 } 495 496 ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH, 497 "wcn36xx_rx", wcn); 498 if (ret) { 499 wcn36xx_err("failed to alloc rx irq\n"); 500 goto out_txirq; 501 } 502 503 enable_irq_wake(wcn->rx_irq); 504 505 return 0; 506 507 out_txirq: 508 free_irq(wcn->tx_irq, wcn); 509 out_err: 510 return ret; 511 512 } 513 514 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn, 515 struct wcn36xx_dxe_ch *ch) 516 { 517 struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl; 518 struct wcn36xx_dxe_desc *dxe = ctl->desc; 519 dma_addr_t dma_addr; 520 struct sk_buff *skb; 521 int ret = 0, int_mask; 522 u32 value; 523 524 if (ch->ch_type == WCN36XX_DXE_CH_RX_L) { 525 value = WCN36XX_DXE_CTRL_RX_L; 526 int_mask = WCN36XX_DXE_INT_CH1_MASK; 527 } else { 528 value = WCN36XX_DXE_CTRL_RX_H; 529 int_mask = WCN36XX_DXE_INT_CH3_MASK; 530 } 531 532 while (!(READ_ONCE(dxe->ctrl) & WCN36xx_DXE_CTRL_VLD)) { 533 skb = ctl->skb; 534 dma_addr = dxe->dst_addr_l; 535 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC); 536 if (0 == ret) { 537 /* new skb allocation ok. Use the new one and queue 538 * the old one to network system. 539 */ 540 dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE, 541 DMA_FROM_DEVICE); 542 wcn36xx_rx_skb(wcn, skb); 543 } /* else keep old skb not submitted and use it for rx DMA */ 544 545 dxe->ctrl = value; 546 ctl = ctl->next; 547 dxe = ctl->desc; 548 } 549 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, int_mask); 550 551 ch->head_blk_ctl = ctl; 552 return 0; 553 } 554 555 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn) 556 { 557 int int_src; 558 559 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src); 560 561 /* RX_LOW_PRI */ 562 if (int_src & WCN36XX_DXE_INT_CH1_MASK) { 563 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, 564 WCN36XX_DXE_INT_CH1_MASK); 565 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_l_ch)); 566 } 567 568 /* RX_HIGH_PRI */ 569 if (int_src & WCN36XX_DXE_INT_CH3_MASK) { 570 /* Clean up all the INT within this channel */ 571 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, 572 WCN36XX_DXE_INT_CH3_MASK); 573 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_h_ch)); 574 } 575 576 if (!int_src) 577 wcn36xx_warn("No DXE interrupt pending\n"); 578 } 579 580 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn) 581 { 582 size_t s; 583 void *cpu_addr; 584 585 /* Allocate BD headers for MGMT frames */ 586 587 /* Where this come from ask QC */ 588 wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 589 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 590 591 s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H; 592 cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->mgmt_mem_pool.phy_addr, 593 GFP_KERNEL); 594 if (!cpu_addr) 595 goto out_err; 596 597 wcn->mgmt_mem_pool.virt_addr = cpu_addr; 598 memset(cpu_addr, 0, s); 599 600 /* Allocate BD headers for DATA frames */ 601 602 /* Where this come from ask QC */ 603 wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE + 604 16 - (WCN36XX_BD_CHUNK_SIZE % 8); 605 606 s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L; 607 cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->data_mem_pool.phy_addr, 608 GFP_KERNEL); 609 if (!cpu_addr) 610 goto out_err; 611 612 wcn->data_mem_pool.virt_addr = cpu_addr; 613 memset(cpu_addr, 0, s); 614 615 return 0; 616 617 out_err: 618 wcn36xx_dxe_free_mem_pools(wcn); 619 wcn36xx_err("Failed to allocate BD mempool\n"); 620 return -ENOMEM; 621 } 622 623 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn) 624 { 625 if (wcn->mgmt_mem_pool.virt_addr) 626 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size * 627 WCN36XX_DXE_CH_DESC_NUMB_TX_H, 628 wcn->mgmt_mem_pool.virt_addr, 629 wcn->mgmt_mem_pool.phy_addr); 630 631 if (wcn->data_mem_pool.virt_addr) { 632 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size * 633 WCN36XX_DXE_CH_DESC_NUMB_TX_L, 634 wcn->data_mem_pool.virt_addr, 635 wcn->data_mem_pool.phy_addr); 636 } 637 } 638 639 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn, 640 struct wcn36xx_vif *vif_priv, 641 struct wcn36xx_tx_bd *bd, 642 struct sk_buff *skb, 643 bool is_low) 644 { 645 struct wcn36xx_dxe_ctl *ctl = NULL; 646 struct wcn36xx_dxe_desc *desc = NULL; 647 struct wcn36xx_dxe_ch *ch = NULL; 648 unsigned long flags; 649 int ret; 650 651 ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch; 652 653 spin_lock_irqsave(&ch->lock, flags); 654 ctl = ch->head_blk_ctl; 655 656 /* 657 * If skb is not null that means that we reached the tail of the ring 658 * hence ring is full. Stop queues to let mac80211 back off until ring 659 * has an empty slot again. 660 */ 661 if (NULL != ctl->next->skb) { 662 ieee80211_stop_queues(wcn->hw); 663 wcn->queues_stopped = true; 664 spin_unlock_irqrestore(&ch->lock, flags); 665 return -EBUSY; 666 } 667 668 ctl->skb = NULL; 669 desc = ctl->desc; 670 671 /* write buffer descriptor */ 672 memcpy(ctl->bd_cpu_addr, bd, sizeof(*bd)); 673 674 /* Set source address of the BD we send */ 675 desc->src_addr_l = ctl->bd_phy_addr; 676 677 desc->dst_addr_l = ch->dxe_wq; 678 desc->fr_len = sizeof(struct wcn36xx_tx_bd); 679 desc->ctrl = ch->ctrl_bd; 680 681 wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n"); 682 683 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ", 684 (char *)desc, sizeof(*desc)); 685 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, 686 "BD >>> ", (char *)ctl->bd_cpu_addr, 687 sizeof(struct wcn36xx_tx_bd)); 688 689 /* Set source address of the SKB we send */ 690 ctl = ctl->next; 691 desc = ctl->desc; 692 if (ctl->bd_cpu_addr) { 693 wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n"); 694 ret = -EINVAL; 695 goto unlock; 696 } 697 698 desc->src_addr_l = dma_map_single(wcn->dev, 699 skb->data, 700 skb->len, 701 DMA_TO_DEVICE); 702 if (dma_mapping_error(wcn->dev, desc->src_addr_l)) { 703 dev_err(wcn->dev, "unable to DMA map src_addr_l\n"); 704 ret = -ENOMEM; 705 goto unlock; 706 } 707 708 ctl->skb = skb; 709 desc->dst_addr_l = ch->dxe_wq; 710 desc->fr_len = ctl->skb->len; 711 712 /* set dxe descriptor to VALID */ 713 desc->ctrl = ch->ctrl_skb; 714 715 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ", 716 (char *)desc, sizeof(*desc)); 717 wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB >>> ", 718 (char *)ctl->skb->data, ctl->skb->len); 719 720 /* Move the head of the ring to the next empty descriptor */ 721 ch->head_blk_ctl = ctl->next; 722 723 /* 724 * When connected and trying to send data frame chip can be in sleep 725 * mode and writing to the register will not wake up the chip. Instead 726 * notify chip about new frame through SMSM bus. 727 */ 728 if (is_low && vif_priv->pw_state == WCN36XX_BMPS) { 729 qcom_smem_state_update_bits(wcn->tx_rings_empty_state, 730 WCN36XX_SMSM_WLAN_TX_ENABLE, 731 WCN36XX_SMSM_WLAN_TX_ENABLE); 732 } else { 733 /* indicate End Of Packet and generate interrupt on descriptor 734 * done. 735 */ 736 wcn36xx_dxe_write_register(wcn, 737 ch->reg_ctrl, ch->def_ctrl); 738 } 739 740 ret = 0; 741 unlock: 742 spin_unlock_irqrestore(&ch->lock, flags); 743 return ret; 744 } 745 746 int wcn36xx_dxe_init(struct wcn36xx *wcn) 747 { 748 int reg_data = 0, ret; 749 750 reg_data = WCN36XX_DXE_REG_RESET; 751 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data); 752 753 /* Select channels for rx avail and xfer done interrupts... */ 754 reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 | 755 WCN36XX_DXE_INT_CH0_MASK | WCN36XX_DXE_INT_CH4_MASK; 756 if (wcn->is_pronto) 757 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data); 758 else 759 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data); 760 761 /***************************************/ 762 /* Init descriptors for TX LOW channel */ 763 /***************************************/ 764 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_l_ch); 765 if (ret) { 766 dev_err(wcn->dev, "Error allocating descriptor\n"); 767 return ret; 768 } 769 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool); 770 771 /* Write channel head to a NEXT register */ 772 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L, 773 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr); 774 775 /* Program DMA destination addr for TX LOW */ 776 wcn36xx_dxe_write_register(wcn, 777 WCN36XX_DXE_CH_DEST_ADDR_TX_L, 778 WCN36XX_DXE_WQ_TX_L); 779 780 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 781 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L); 782 783 /***************************************/ 784 /* Init descriptors for TX HIGH channel */ 785 /***************************************/ 786 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_h_ch); 787 if (ret) { 788 dev_err(wcn->dev, "Error allocating descriptor\n"); 789 goto out_err_txh_ch; 790 } 791 792 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool); 793 794 /* Write channel head to a NEXT register */ 795 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H, 796 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr); 797 798 /* Program DMA destination addr for TX HIGH */ 799 wcn36xx_dxe_write_register(wcn, 800 WCN36XX_DXE_CH_DEST_ADDR_TX_H, 801 WCN36XX_DXE_WQ_TX_H); 802 803 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data); 804 805 /* Enable channel interrupts */ 806 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H); 807 808 /***************************************/ 809 /* Init descriptors for RX LOW channel */ 810 /***************************************/ 811 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_l_ch); 812 if (ret) { 813 dev_err(wcn->dev, "Error allocating descriptor\n"); 814 goto out_err_rxl_ch; 815 } 816 817 818 /* For RX we need to preallocated buffers */ 819 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch); 820 821 /* Write channel head to a NEXT register */ 822 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L, 823 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr); 824 825 /* Write DMA source address */ 826 wcn36xx_dxe_write_register(wcn, 827 WCN36XX_DXE_CH_SRC_ADDR_RX_L, 828 WCN36XX_DXE_WQ_RX_L); 829 830 /* Program preallocated destination address */ 831 wcn36xx_dxe_write_register(wcn, 832 WCN36XX_DXE_CH_DEST_ADDR_RX_L, 833 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l); 834 835 /* Enable default control registers */ 836 wcn36xx_dxe_write_register(wcn, 837 WCN36XX_DXE_REG_CTL_RX_L, 838 WCN36XX_DXE_CH_DEFAULT_CTL_RX_L); 839 840 /* Enable channel interrupts */ 841 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L); 842 843 /***************************************/ 844 /* Init descriptors for RX HIGH channel */ 845 /***************************************/ 846 ret = wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_h_ch); 847 if (ret) { 848 dev_err(wcn->dev, "Error allocating descriptor\n"); 849 goto out_err_rxh_ch; 850 } 851 852 /* For RX we need to prealocat buffers */ 853 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch); 854 855 /* Write chanel head to a NEXT register */ 856 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H, 857 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr); 858 859 /* Write DMA source address */ 860 wcn36xx_dxe_write_register(wcn, 861 WCN36XX_DXE_CH_SRC_ADDR_RX_H, 862 WCN36XX_DXE_WQ_RX_H); 863 864 /* Program preallocated destination address */ 865 wcn36xx_dxe_write_register(wcn, 866 WCN36XX_DXE_CH_DEST_ADDR_RX_H, 867 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l); 868 869 /* Enable default control registers */ 870 wcn36xx_dxe_write_register(wcn, 871 WCN36XX_DXE_REG_CTL_RX_H, 872 WCN36XX_DXE_CH_DEFAULT_CTL_RX_H); 873 874 /* Enable channel interrupts */ 875 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H); 876 877 ret = wcn36xx_dxe_request_irqs(wcn); 878 if (ret < 0) 879 goto out_err_irq; 880 881 return 0; 882 883 out_err_irq: 884 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch); 885 out_err_rxh_ch: 886 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch); 887 out_err_rxl_ch: 888 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch); 889 out_err_txh_ch: 890 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch); 891 892 return ret; 893 } 894 895 void wcn36xx_dxe_deinit(struct wcn36xx *wcn) 896 { 897 free_irq(wcn->tx_irq, wcn); 898 free_irq(wcn->rx_irq, wcn); 899 900 if (wcn->tx_ack_skb) { 901 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb); 902 wcn->tx_ack_skb = NULL; 903 } 904 905 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch); 906 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch); 907 } 908