1 /*
2  * Shared Atheros AR9170 Header
3  *
4  * Register map, hardware-specific definitions
5  *
6  * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7  * Copyright 2009, 2010, Christian Lamparter <chunkeey@googlemail.com>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; see the file COPYING.  If not, see
20  * http://www.gnu.org/licenses/.
21  *
22  * This file incorporates work covered by the following copyright and
23  * permission notice:
24  *    Copyright (c) 2007-2008 Atheros Communications, Inc.
25  *
26  *    Permission to use, copy, modify, and/or distribute this software for any
27  *    purpose with or without fee is hereby granted, provided that the above
28  *    copyright notice and this permission notice appear in all copies.
29  *
30  *    THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31  *    WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32  *    MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33  *    ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34  *    WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35  *    ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36  *    OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37  */
38 
39 #ifndef __CARL9170_SHARED_HW_H
40 #define __CARL9170_SHARED_HW_H
41 
42 /* High Speed UART */
43 #define	AR9170_UART_REG_BASE			0x1c0000
44 
45 /* Definitions of interrupt registers */
46 #define	AR9170_UART_REG_RX_BUFFER		(AR9170_UART_REG_BASE + 0x000)
47 #define	AR9170_UART_REG_TX_HOLDING		(AR9170_UART_REG_BASE + 0x004)
48 #define	AR9170_UART_REG_FIFO_CONTROL		(AR9170_UART_REG_BASE + 0x010)
49 #define		AR9170_UART_FIFO_CTRL_RESET_RX_FIFO	0x02
50 #define		AR9170_UART_FIFO_CTRL_RESET_TX_FIFO	0x04
51 
52 #define	AR9170_UART_REG_LINE_CONTROL		(AR9170_UART_REG_BASE + 0x014)
53 #define	AR9170_UART_REG_MODEM_CONTROL		(AR9170_UART_REG_BASE + 0x018)
54 #define		AR9170_UART_MODEM_CTRL_DTR_BIT		0x01
55 #define		AR9170_UART_MODEM_CTRL_RTS_BIT		0x02
56 #define		AR9170_UART_MODEM_CTRL_INTERNAL_LOOP_BACK	0x10
57 #define		AR9170_UART_MODEM_CTRL_AUTO_RTS		0x20
58 #define		AR9170_UART_MODEM_CTRL_AUTO_CTR		0x40
59 
60 #define	AR9170_UART_REG_LINE_STATUS		(AR9170_UART_REG_BASE + 0x01c)
61 #define		AR9170_UART_LINE_STS_RX_DATA_READY	0x01
62 #define		AR9170_UART_LINE_STS_RX_BUFFER_OVERRUN	0x02
63 #define		AR9170_UART_LINE_STS_RX_BREAK_IND	0x10
64 #define		AR9170_UART_LINE_STS_TX_FIFO_NEAR_EMPTY	0x20
65 #define		AR9170_UART_LINE_STS_TRANSMITTER_EMPTY	0x40
66 
67 #define	AR9170_UART_REG_MODEM_STATUS		(AR9170_UART_REG_BASE + 0x020)
68 #define		AR9170_UART_MODEM_STS_CTS_CHANGE	0x01
69 #define		AR9170_UART_MODEM_STS_DSR_CHANGE	0x02
70 #define		AR9170_UART_MODEM_STS_DCD_CHANGE	0x08
71 #define		AR9170_UART_MODEM_STS_CTS_COMPL		0x10
72 #define		AR9170_UART_MODEM_STS_DSR_COMPL		0x20
73 #define		AR9170_UART_MODEM_STS_DCD_COMPL		0x80
74 
75 #define	AR9170_UART_REG_SCRATCH			(AR9170_UART_REG_BASE + 0x024)
76 #define	AR9170_UART_REG_DIVISOR_LSB		(AR9170_UART_REG_BASE + 0x028)
77 #define	AR9170_UART_REG_DIVISOR_MSB		(AR9170_UART_REG_BASE + 0x02c)
78 #define	AR9170_UART_REG_WORD_RX_BUFFER		(AR9170_UART_REG_BASE + 0x034)
79 #define	AR9170_UART_REG_WORD_TX_HOLDING		(AR9170_UART_REG_BASE + 0x038)
80 #define	AR9170_UART_REG_FIFO_COUNT		(AR9170_UART_REG_BASE + 0x03c)
81 #define	AR9170_UART_REG_REMAINDER		(AR9170_UART_REG_BASE + 0x04c)
82 
83 /* Timer */
84 #define	AR9170_TIMER_REG_BASE			0x1c1000
85 
86 #define	AR9170_TIMER_REG_WATCH_DOG		(AR9170_TIMER_REG_BASE + 0x000)
87 #define	AR9170_TIMER_REG_TIMER0			(AR9170_TIMER_REG_BASE + 0x010)
88 #define	AR9170_TIMER_REG_TIMER1			(AR9170_TIMER_REG_BASE + 0x014)
89 #define	AR9170_TIMER_REG_TIMER2			(AR9170_TIMER_REG_BASE + 0x018)
90 #define	AR9170_TIMER_REG_TIMER3			(AR9170_TIMER_REG_BASE + 0x01c)
91 #define	AR9170_TIMER_REG_TIMER4			(AR9170_TIMER_REG_BASE + 0x020)
92 #define	AR9170_TIMER_REG_CONTROL		(AR9170_TIMER_REG_BASE + 0x024)
93 #define		AR9170_TIMER_CTRL_DISABLE_CLOCK		0x100
94 
95 #define	AR9170_TIMER_REG_INTERRUPT		(AR9170_TIMER_REG_BASE + 0x028)
96 #define		AR9170_TIMER_INT_TIMER0			0x001
97 #define		AR9170_TIMER_INT_TIMER1			0x002
98 #define		AR9170_TIMER_INT_TIMER2			0x004
99 #define		AR9170_TIMER_INT_TIMER3			0x008
100 #define		AR9170_TIMER_INT_TIMER4			0x010
101 #define		AR9170_TIMER_INT_TICK_TIMER		0x100
102 
103 #define	AR9170_TIMER_REG_TICK_TIMER		(AR9170_TIMER_REG_BASE + 0x030)
104 #define	AR9170_TIMER_REG_CLOCK_LOW		(AR9170_TIMER_REG_BASE + 0x040)
105 #define	AR9170_TIMER_REG_CLOCK_HIGH		(AR9170_TIMER_REG_BASE + 0x044)
106 
107 #define	AR9170_MAC_REG_BASE			0x1c3000
108 
109 #define	AR9170_MAC_REG_POWER_STATE_CTRL		(AR9170_MAC_REG_BASE + 0x500)
110 #define		AR9170_MAC_POWER_STATE_CTRL_RESET	0x20
111 
112 #define	AR9170_MAC_REG_MAC_POWER_STATE_CTRL	(AR9170_MAC_REG_BASE + 0x50c)
113 
114 #define	AR9170_MAC_REG_INT_CTRL			(AR9170_MAC_REG_BASE + 0x510)
115 #define		AR9170_MAC_INT_TXC			BIT(0)
116 #define		AR9170_MAC_INT_RXC			BIT(1)
117 #define		AR9170_MAC_INT_RETRY_FAIL		BIT(2)
118 #define		AR9170_MAC_INT_WAKEUP			BIT(3)
119 #define		AR9170_MAC_INT_ATIM			BIT(4)
120 #define		AR9170_MAC_INT_DTIM			BIT(5)
121 #define		AR9170_MAC_INT_CFG_BCN			BIT(6)
122 #define		AR9170_MAC_INT_ABORT			BIT(7)
123 #define		AR9170_MAC_INT_QOS			BIT(8)
124 #define		AR9170_MAC_INT_MIMO_PS			BIT(9)
125 #define		AR9170_MAC_INT_KEY_GEN			BIT(10)
126 #define		AR9170_MAC_INT_DECRY_NOUSER		BIT(11)
127 #define		AR9170_MAC_INT_RADAR			BIT(12)
128 #define		AR9170_MAC_INT_QUIET_FRAME		BIT(13)
129 #define		AR9170_MAC_INT_PRETBTT			BIT(14)
130 
131 #define	AR9170_MAC_REG_TSF_L			(AR9170_MAC_REG_BASE + 0x514)
132 #define	AR9170_MAC_REG_TSF_H			(AR9170_MAC_REG_BASE + 0x518)
133 
134 #define	AR9170_MAC_REG_ATIM_WINDOW		(AR9170_MAC_REG_BASE + 0x51c)
135 #define		AR9170_MAC_ATIM_PERIOD_S		0
136 #define		AR9170_MAC_ATIM_PERIOD			0x0000ffff
137 
138 #define	AR9170_MAC_REG_BCN_PERIOD		(AR9170_MAC_REG_BASE + 0x520)
139 #define		AR9170_MAC_BCN_PERIOD_S			0
140 #define		AR9170_MAC_BCN_PERIOD			0x0000ffff
141 #define		AR9170_MAC_BCN_DTIM_S			16
142 #define		AR9170_MAC_BCN_DTIM			0x00ff0000
143 #define		AR9170_MAC_BCN_AP_MODE			BIT(24)
144 #define		AR9170_MAC_BCN_IBSS_MODE		BIT(25)
145 #define		AR9170_MAC_BCN_PWR_MGT			BIT(26)
146 #define		AR9170_MAC_BCN_STA_PS			BIT(27)
147 
148 #define	AR9170_MAC_REG_PRETBTT			(AR9170_MAC_REG_BASE + 0x524)
149 #define		AR9170_MAC_PRETBTT_S			0
150 #define		AR9170_MAC_PRETBTT			0x0000ffff
151 #define		AR9170_MAC_PRETBTT2_S			16
152 #define		AR9170_MAC_PRETBTT2			0xffff0000
153 
154 #define	AR9170_MAC_REG_MAC_ADDR_L		(AR9170_MAC_REG_BASE + 0x610)
155 #define	AR9170_MAC_REG_MAC_ADDR_H		(AR9170_MAC_REG_BASE + 0x614)
156 #define	AR9170_MAC_REG_BSSID_L			(AR9170_MAC_REG_BASE + 0x618)
157 #define	AR9170_MAC_REG_BSSID_H			(AR9170_MAC_REG_BASE + 0x61c)
158 
159 #define	AR9170_MAC_REG_GROUP_HASH_TBL_L		(AR9170_MAC_REG_BASE + 0x624)
160 #define	AR9170_MAC_REG_GROUP_HASH_TBL_H		(AR9170_MAC_REG_BASE + 0x628)
161 
162 #define	AR9170_MAC_REG_RX_TIMEOUT		(AR9170_MAC_REG_BASE + 0x62c)
163 
164 #define	AR9170_MAC_REG_BASIC_RATE		(AR9170_MAC_REG_BASE + 0x630)
165 #define	AR9170_MAC_REG_MANDATORY_RATE		(AR9170_MAC_REG_BASE + 0x634)
166 #define	AR9170_MAC_REG_RTS_CTS_RATE		(AR9170_MAC_REG_BASE + 0x638)
167 #define	AR9170_MAC_REG_BACKOFF_PROTECT		(AR9170_MAC_REG_BASE + 0x63c)
168 #define	AR9170_MAC_REG_RX_THRESHOLD		(AR9170_MAC_REG_BASE + 0x640)
169 #define	AR9170_MAC_REG_AFTER_PNP		(AR9170_MAC_REG_BASE + 0x648)
170 #define	AR9170_MAC_REG_RX_PE_DELAY		(AR9170_MAC_REG_BASE + 0x64c)
171 
172 #define	AR9170_MAC_REG_DYNAMIC_SIFS_ACK		(AR9170_MAC_REG_BASE + 0x658)
173 #define	AR9170_MAC_REG_SNIFFER			(AR9170_MAC_REG_BASE + 0x674)
174 #define		AR9170_MAC_SNIFFER_ENABLE_PROMISC	BIT(0)
175 #define		AR9170_MAC_SNIFFER_DEFAULTS		0x02000000
176 #define	AR9170_MAC_REG_ENCRYPTION		(AR9170_MAC_REG_BASE + 0x678)
177 #define		AR9170_MAC_ENCRYPTION_RX_SOFTWARE	BIT(3)
178 #define		AR9170_MAC_ENCRYPTION_DEFAULTS		0x70
179 
180 #define	AR9170_MAC_REG_MISC_680			(AR9170_MAC_REG_BASE + 0x680)
181 #define	AR9170_MAC_REG_MISC_684			(AR9170_MAC_REG_BASE + 0x684)
182 #define	AR9170_MAC_REG_TX_UNDERRUN		(AR9170_MAC_REG_BASE + 0x688)
183 
184 #define	AR9170_MAC_REG_FRAMETYPE_FILTER		(AR9170_MAC_REG_BASE + 0x68c)
185 #define		AR9170_MAC_FTF_ASSOC_REQ		BIT(0)
186 #define		AR9170_MAC_FTF_ASSOC_RESP		BIT(1)
187 #define		AR9170_MAC_FTF_REASSOC_REQ		BIT(2)
188 #define		AR9170_MAC_FTF_REASSOC_RESP		BIT(3)
189 #define		AR9170_MAC_FTF_PRB_REQ			BIT(4)
190 #define		AR9170_MAC_FTF_PRB_RESP			BIT(5)
191 #define		AR9170_MAC_FTF_BIT6			BIT(6)
192 #define		AR9170_MAC_FTF_BIT7			BIT(7)
193 #define		AR9170_MAC_FTF_BEACON			BIT(8)
194 #define		AR9170_MAC_FTF_ATIM			BIT(9)
195 #define		AR9170_MAC_FTF_DEASSOC			BIT(10)
196 #define		AR9170_MAC_FTF_AUTH			BIT(11)
197 #define		AR9170_MAC_FTF_DEAUTH			BIT(12)
198 #define		AR9170_MAC_FTF_BIT13			BIT(13)
199 #define		AR9170_MAC_FTF_BIT14			BIT(14)
200 #define		AR9170_MAC_FTF_BIT15			BIT(15)
201 #define		AR9170_MAC_FTF_BAR			BIT(24)
202 #define		AR9170_MAC_FTF_BA			BIT(25)
203 #define		AR9170_MAC_FTF_PSPOLL			BIT(26)
204 #define		AR9170_MAC_FTF_RTS			BIT(27)
205 #define		AR9170_MAC_FTF_CTS			BIT(28)
206 #define		AR9170_MAC_FTF_ACK			BIT(29)
207 #define		AR9170_MAC_FTF_CFE			BIT(30)
208 #define		AR9170_MAC_FTF_CFE_ACK			BIT(31)
209 #define		AR9170_MAC_FTF_DEFAULTS			0x0500ffff
210 #define		AR9170_MAC_FTF_MONITOR			0xff00ffff
211 
212 #define	AR9170_MAC_REG_ACK_EXTENSION		(AR9170_MAC_REG_BASE + 0x690)
213 #define	AR9170_MAC_REG_ACK_TPC			(AR9170_MAC_REG_BASE + 0x694)
214 #define	AR9170_MAC_REG_EIFS_AND_SIFS		(AR9170_MAC_REG_BASE + 0x698)
215 #define	AR9170_MAC_REG_RX_TIMEOUT_COUNT		(AR9170_MAC_REG_BASE + 0x69c)
216 #define	AR9170_MAC_REG_RX_TOTAL			(AR9170_MAC_REG_BASE + 0x6a0)
217 #define	AR9170_MAC_REG_RX_CRC32			(AR9170_MAC_REG_BASE + 0x6a4)
218 #define	AR9170_MAC_REG_RX_CRC16			(AR9170_MAC_REG_BASE + 0x6a8)
219 #define	AR9170_MAC_REG_RX_ERR_DECRYPTION_UNI	(AR9170_MAC_REG_BASE + 0x6ac)
220 #define	AR9170_MAC_REG_RX_OVERRUN		(AR9170_MAC_REG_BASE + 0x6b0)
221 #define	AR9170_MAC_REG_RX_ERR_DECRYPTION_MUL	(AR9170_MAC_REG_BASE + 0x6bc)
222 #define AR9170_MAC_REG_TX_BLOCKACKS		(AR9170_MAC_REG_BASE + 0x6c0)
223 #define AR9170_MAC_REG_NAV_COUNT		(AR9170_MAC_REG_BASE + 0x6c4)
224 #define AR9170_MAC_REG_BACKOFF_STATUS		(AR9170_MAC_REG_BASE + 0x6c8)
225 #define	AR9170_MAC_REG_TX_RETRY			(AR9170_MAC_REG_BASE + 0x6cc)
226 
227 #define AR9170_MAC_REG_TX_COMPLETE		(AR9170_MAC_REG_BASE + 0x6d4)
228 
229 #define	AR9170_MAC_REG_CHANNEL_BUSY		(AR9170_MAC_REG_BASE + 0x6e8)
230 #define	AR9170_MAC_REG_EXT_BUSY			(AR9170_MAC_REG_BASE + 0x6ec)
231 
232 #define	AR9170_MAC_REG_SLOT_TIME		(AR9170_MAC_REG_BASE + 0x6f0)
233 #define	AR9170_MAC_REG_TX_TOTAL			(AR9170_MAC_REG_BASE + 0x6f4)
234 #define AR9170_MAC_REG_ACK_FC			(AR9170_MAC_REG_BASE + 0x6f8)
235 
236 #define	AR9170_MAC_REG_CAM_MODE			(AR9170_MAC_REG_BASE + 0x700)
237 #define		AR9170_MAC_CAM_IBSS			0xe0
238 #define		AR9170_MAC_CAM_AP			0xa1
239 #define		AR9170_MAC_CAM_STA			0x2
240 #define		AR9170_MAC_CAM_AP_WDS			0x3
241 #define		AR9170_MAC_CAM_DEFAULTS			(0xf << 24)
242 #define		AR9170_MAC_CAM_HOST_PENDING		0x80000000
243 
244 #define	AR9170_MAC_REG_CAM_ROLL_CALL_TBL_L	(AR9170_MAC_REG_BASE + 0x704)
245 #define	AR9170_MAC_REG_CAM_ROLL_CALL_TBL_H	(AR9170_MAC_REG_BASE + 0x708)
246 
247 #define	AR9170_MAC_REG_CAM_ADDR			(AR9170_MAC_REG_BASE + 0x70c)
248 #define		AR9170_MAC_CAM_ADDR_WRITE		0x80000000
249 #define	AR9170_MAC_REG_CAM_DATA0		(AR9170_MAC_REG_BASE + 0x720)
250 #define	AR9170_MAC_REG_CAM_DATA1		(AR9170_MAC_REG_BASE + 0x724)
251 #define	AR9170_MAC_REG_CAM_DATA2		(AR9170_MAC_REG_BASE + 0x728)
252 #define	AR9170_MAC_REG_CAM_DATA3		(AR9170_MAC_REG_BASE + 0x72c)
253 
254 #define	AR9170_MAC_REG_CAM_DBG0			(AR9170_MAC_REG_BASE + 0x730)
255 #define	AR9170_MAC_REG_CAM_DBG1			(AR9170_MAC_REG_BASE + 0x734)
256 #define	AR9170_MAC_REG_CAM_DBG2			(AR9170_MAC_REG_BASE + 0x738)
257 #define	AR9170_MAC_REG_CAM_STATE		(AR9170_MAC_REG_BASE + 0x73c)
258 #define		AR9170_MAC_CAM_STATE_READ_PENDING	0x40000000
259 #define		AR9170_MAC_CAM_STATE_WRITE_PENDING	0x80000000
260 
261 #define	AR9170_MAC_REG_CAM_TXKEY		(AR9170_MAC_REG_BASE + 0x740)
262 #define	AR9170_MAC_REG_CAM_RXKEY		(AR9170_MAC_REG_BASE + 0x750)
263 
264 #define	AR9170_MAC_REG_CAM_TX_ENC_TYPE		(AR9170_MAC_REG_BASE + 0x760)
265 #define	AR9170_MAC_REG_CAM_RX_ENC_TYPE		(AR9170_MAC_REG_BASE + 0x770)
266 #define	AR9170_MAC_REG_CAM_TX_SERACH_HIT	(AR9170_MAC_REG_BASE + 0x780)
267 #define	AR9170_MAC_REG_CAM_RX_SERACH_HIT	(AR9170_MAC_REG_BASE + 0x790)
268 
269 #define	AR9170_MAC_REG_AC0_CW			(AR9170_MAC_REG_BASE + 0xb00)
270 #define	AR9170_MAC_REG_AC1_CW			(AR9170_MAC_REG_BASE + 0xb04)
271 #define	AR9170_MAC_REG_AC2_CW			(AR9170_MAC_REG_BASE + 0xb08)
272 #define	AR9170_MAC_REG_AC3_CW			(AR9170_MAC_REG_BASE + 0xb0c)
273 #define	AR9170_MAC_REG_AC4_CW			(AR9170_MAC_REG_BASE + 0xb10)
274 #define	AR9170_MAC_REG_AC2_AC1_AC0_AIFS		(AR9170_MAC_REG_BASE + 0xb14)
275 #define	AR9170_MAC_REG_AC4_AC3_AC2_AIFS		(AR9170_MAC_REG_BASE + 0xb18)
276 #define AR9170_MAC_REG_TXOP_ACK_EXTENSION	(AR9170_MAC_REG_BASE + 0xb1c)
277 #define AR9170_MAC_REG_TXOP_ACK_INTERVAL	(AR9170_MAC_REG_BASE + 0xb20)
278 #define AR9170_MAC_REG_CONTENTION_POINT		(AR9170_MAC_REG_BASE + 0xb24)
279 #define	AR9170_MAC_REG_RETRY_MAX		(AR9170_MAC_REG_BASE + 0xb28)
280 #define AR9170_MAC_REG_TID_CFACK_CFEND_RATE	(AR9170_MAC_REG_BASE + 0xb2c)
281 #define	AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND	(AR9170_MAC_REG_BASE + 0xb30)
282 #define AR9170_MAC_REG_TKIP_TSC			(AR9170_MAC_REG_BASE + 0xb34)
283 #define AR9170_MAC_REG_TXOP_DURATION		(AR9170_MAC_REG_BASE + 0xb38)
284 #define AR9170_MAC_REG_TX_QOS_THRESHOLD		(AR9170_MAC_REG_BASE + 0xb3c)
285 #define	AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA	(AR9170_MAC_REG_BASE + 0xb40)
286 #define		AR9170_MAC_VIRTUAL_CCA_Q0		BIT(15)
287 #define		AR9170_MAC_VIRTUAL_CCA_Q1		BIT(16)
288 #define		AR9170_MAC_VIRTUAL_CCA_Q2		BIT(17)
289 #define		AR9170_MAC_VIRTUAL_CCA_Q3		BIT(18)
290 #define		AR9170_MAC_VIRTUAL_CCA_Q4		BIT(19)
291 #define		AR9170_MAC_VIRTUAL_CCA_ALL		(0xf8000)
292 
293 #define	AR9170_MAC_REG_AC1_AC0_TXOP		(AR9170_MAC_REG_BASE + 0xb44)
294 #define	AR9170_MAC_REG_AC3_AC2_TXOP		(AR9170_MAC_REG_BASE + 0xb48)
295 
296 #define	AR9170_MAC_REG_AMPDU_COUNT		(AR9170_MAC_REG_BASE + 0xb88)
297 #define	AR9170_MAC_REG_MPDU_COUNT		(AR9170_MAC_REG_BASE + 0xb8c)
298 
299 #define	AR9170_MAC_REG_AMPDU_FACTOR		(AR9170_MAC_REG_BASE + 0xb9c)
300 #define		AR9170_MAC_AMPDU_FACTOR			0x7f0000
301 #define		AR9170_MAC_AMPDU_FACTOR_S		16
302 #define	AR9170_MAC_REG_AMPDU_DENSITY		(AR9170_MAC_REG_BASE + 0xba0)
303 #define		AR9170_MAC_AMPDU_DENSITY		0x7
304 #define		AR9170_MAC_AMPDU_DENSITY_S		0
305 
306 #define	AR9170_MAC_REG_FCS_SELECT		(AR9170_MAC_REG_BASE + 0xbb0)
307 #define		AR9170_MAC_FCS_SWFCS			0x1
308 #define		AR9170_MAC_FCS_FIFO_PROT		0x4
309 
310 #define	AR9170_MAC_REG_RTS_CTS_TPC		(AR9170_MAC_REG_BASE + 0xbb4)
311 #define AR9170_MAC_REG_CFEND_QOSNULL_TPC	(AR9170_MAC_REG_BASE + 0xbb8)
312 
313 #define	AR9170_MAC_REG_ACK_TABLE		(AR9170_MAC_REG_BASE + 0xc00)
314 #define AR9170_MAC_REG_RX_CONTROL		(AR9170_MAC_REG_BASE + 0xc40)
315 #define		AR9170_MAC_RX_CTRL_DEAGG		0x1
316 #define		AR9170_MAC_RX_CTRL_SHORT_FILTER		0x2
317 #define		AR9170_MAC_RX_CTRL_SA_DA_SEARCH		0x20
318 #define		AR9170_MAC_RX_CTRL_PASS_TO_HOST		BIT(28)
319 #define		AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER	BIT(30)
320 
321 #define AR9170_MAC_REG_RX_CONTROL_1		(AR9170_MAC_REG_BASE + 0xc44)
322 
323 #define	AR9170_MAC_REG_AMPDU_RX_THRESH		(AR9170_MAC_REG_BASE + 0xc50)
324 
325 #define	AR9170_MAC_REG_RX_MPDU			(AR9170_MAC_REG_BASE + 0xca0)
326 #define	AR9170_MAC_REG_RX_DROPPED_MPDU		(AR9170_MAC_REG_BASE + 0xca4)
327 #define	AR9170_MAC_REG_RX_DEL_MPDU		(AR9170_MAC_REG_BASE + 0xca8)
328 #define	AR9170_MAC_REG_RX_PHY_MISC_ERROR	(AR9170_MAC_REG_BASE + 0xcac)
329 #define	AR9170_MAC_REG_RX_PHY_XR_ERROR		(AR9170_MAC_REG_BASE + 0xcb0)
330 #define	AR9170_MAC_REG_RX_PHY_OFDM_ERROR	(AR9170_MAC_REG_BASE + 0xcb4)
331 #define	AR9170_MAC_REG_RX_PHY_CCK_ERROR		(AR9170_MAC_REG_BASE + 0xcb8)
332 #define	AR9170_MAC_REG_RX_PHY_HT_ERROR		(AR9170_MAC_REG_BASE + 0xcbc)
333 #define	AR9170_MAC_REG_RX_PHY_TOTAL		(AR9170_MAC_REG_BASE + 0xcc0)
334 
335 #define	AR9170_MAC_REG_DMA_TXQ_ADDR		(AR9170_MAC_REG_BASE + 0xd00)
336 #define	AR9170_MAC_REG_DMA_TXQ_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd04)
337 #define	AR9170_MAC_REG_DMA_TXQ0_ADDR		(AR9170_MAC_REG_BASE + 0xd00)
338 #define	AR9170_MAC_REG_DMA_TXQ0_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd04)
339 #define	AR9170_MAC_REG_DMA_TXQ1_ADDR		(AR9170_MAC_REG_BASE + 0xd08)
340 #define	AR9170_MAC_REG_DMA_TXQ1_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd0c)
341 #define	AR9170_MAC_REG_DMA_TXQ2_ADDR		(AR9170_MAC_REG_BASE + 0xd10)
342 #define	AR9170_MAC_REG_DMA_TXQ2_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd14)
343 #define	AR9170_MAC_REG_DMA_TXQ3_ADDR		(AR9170_MAC_REG_BASE + 0xd18)
344 #define	AR9170_MAC_REG_DMA_TXQ3_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd1c)
345 #define	AR9170_MAC_REG_DMA_TXQ4_ADDR		(AR9170_MAC_REG_BASE + 0xd20)
346 #define	AR9170_MAC_REG_DMA_TXQ4_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd24)
347 #define	AR9170_MAC_REG_DMA_RXQ_ADDR		(AR9170_MAC_REG_BASE + 0xd28)
348 #define	AR9170_MAC_REG_DMA_RXQ_CURR_ADDR	(AR9170_MAC_REG_BASE + 0xd2c)
349 
350 #define	AR9170_MAC_REG_DMA_TRIGGER		(AR9170_MAC_REG_BASE + 0xd30)
351 #define		AR9170_DMA_TRIGGER_TXQ0			BIT(0)
352 #define		AR9170_DMA_TRIGGER_TXQ1			BIT(1)
353 #define		AR9170_DMA_TRIGGER_TXQ2			BIT(2)
354 #define		AR9170_DMA_TRIGGER_TXQ3			BIT(3)
355 #define		AR9170_DMA_TRIGGER_TXQ4			BIT(4)
356 #define		AR9170_DMA_TRIGGER_RXQ			BIT(8)
357 
358 #define AR9170_MAC_REG_DMA_WLAN_STATUS		(AR9170_MAC_REG_BASE + 0xd38)
359 #define	AR9170_MAC_REG_DMA_STATUS		(AR9170_MAC_REG_BASE + 0xd3c)
360 
361 #define	AR9170_MAC_REG_TXRX_MPI			(AR9170_MAC_REG_BASE + 0xd7c)
362 #define		AR9170_MAC_TXRX_MPI_TX_MPI_MASK		0x0000000f
363 #define		AR9170_MAC_TXRX_MPI_TX_TO_MASK		0x0000fff0
364 #define		AR9170_MAC_TXRX_MPI_RX_MPI_MASK		0x000f0000
365 #define		AR9170_MAC_TXRX_MPI_RX_TO_MASK		0xfff00000
366 
367 #define	AR9170_MAC_REG_BCN_ADDR			(AR9170_MAC_REG_BASE + 0xd84)
368 #define	AR9170_MAC_REG_BCN_LENGTH		(AR9170_MAC_REG_BASE + 0xd88)
369 #define		AR9170_MAC_BCN_LENGTH_MAX		256
370 
371 #define AR9170_MAC_REG_BCN_STATUS		(AR9170_MAC_REG_BASE + 0xd8c)
372 
373 #define	AR9170_MAC_REG_BCN_PLCP			(AR9170_MAC_REG_BASE + 0xd90)
374 #define	AR9170_MAC_REG_BCN_CTRL			(AR9170_MAC_REG_BASE + 0xd94)
375 #define		AR9170_BCN_CTRL_READY			0x01
376 #define		AR9170_BCN_CTRL_LOCK			0x02
377 
378 #define AR9170_MAC_REG_BCN_CURR_ADDR		(AR9170_MAC_REG_BASE + 0xd98)
379 #define	AR9170_MAC_REG_BCN_COUNT		(AR9170_MAC_REG_BASE + 0xd9c)
380 
381 
382 #define	AR9170_MAC_REG_BCN_HT1			(AR9170_MAC_REG_BASE + 0xda0)
383 #define	AR9170_MAC_REG_BCN_HT2			(AR9170_MAC_REG_BASE + 0xda4)
384 
385 #define	AR9170_MAC_REG_DMA_TXQX_ADDR_CURR	(AR9170_MAC_REG_BASE + 0xdc0)
386 
387 /* Random number generator */
388 #define	AR9170_RAND_REG_BASE			0x1d0000
389 
390 #define	AR9170_RAND_REG_NUM			(AR9170_RAND_REG_BASE + 0x000)
391 #define	AR9170_RAND_REG_MODE			(AR9170_RAND_REG_BASE + 0x004)
392 #define		AR9170_RAND_MODE_MANUAL			0x000
393 #define		AR9170_RAND_MODE_FREE			0x001
394 
395 /* GPIO */
396 #define	AR9170_GPIO_REG_BASE			0x1d0100
397 #define	AR9170_GPIO_REG_PORT_TYPE		(AR9170_GPIO_REG_BASE + 0x000)
398 #define	AR9170_GPIO_REG_PORT_DATA		(AR9170_GPIO_REG_BASE + 0x004)
399 #define		AR9170_GPIO_PORT_LED_0			1
400 #define		AR9170_GPIO_PORT_LED_1			2
401 /* WPS Button GPIO for TP-Link TL-WN821N */
402 #define		AR9170_GPIO_PORT_WPS_BUTTON_PRESSED	4
403 
404 /* Memory Controller */
405 #define	AR9170_MC_REG_BASE			0x1d1000
406 
407 #define	AR9170_MC_REG_FLASH_WAIT_STATE		(AR9170_MC_REG_BASE + 0x000)
408 #define	AR9170_MC_REG_SEEPROM_WP0		(AR9170_MC_REG_BASE + 0x400)
409 #define	AR9170_MC_REG_SEEPROM_WP1		(AR9170_MC_REG_BASE + 0x404)
410 #define	AR9170_MC_REG_SEEPROM_WP2		(AR9170_MC_REG_BASE + 0x408)
411 
412 /* Interrupt Controller */
413 #define	AR9170_MAX_INT_SRC			9
414 #define	AR9170_INT_REG_BASE			0x1d2000
415 
416 #define	AR9170_INT_REG_FLAG			(AR9170_INT_REG_BASE + 0x000)
417 #define	AR9170_INT_REG_FIQ_MASK			(AR9170_INT_REG_BASE + 0x004)
418 #define	AR9170_INT_REG_IRQ_MASK			(AR9170_INT_REG_BASE + 0x008)
419 /* INT_REG_FLAG, INT_REG_FIQ_MASK and INT_REG_IRQ_MASK */
420 #define		AR9170_INT_FLAG_WLAN			0x001
421 #define		AR9170_INT_FLAG_PTAB_BIT		0x002
422 #define		AR9170_INT_FLAG_SE_BIT			0x004
423 #define		AR9170_INT_FLAG_UART_BIT		0x008
424 #define		AR9170_INT_FLAG_TIMER_BIT		0x010
425 #define		AR9170_INT_FLAG_EXT_BIT			0x020
426 #define		AR9170_INT_FLAG_SW_BIT			0x040
427 #define		AR9170_INT_FLAG_USB_BIT			0x080
428 #define		AR9170_INT_FLAG_ETHERNET_BIT		0x100
429 
430 #define	AR9170_INT_REG_PRIORITY1		(AR9170_INT_REG_BASE + 0x00c)
431 #define	AR9170_INT_REG_PRIORITY2		(AR9170_INT_REG_BASE + 0x010)
432 #define	AR9170_INT_REG_PRIORITY3		(AR9170_INT_REG_BASE + 0x014)
433 #define	AR9170_INT_REG_EXT_INT_CONTROL		(AR9170_INT_REG_BASE + 0x018)
434 #define	AR9170_INT_REG_SW_INT_CONTROL		(AR9170_INT_REG_BASE + 0x01c)
435 #define		AR9170_INT_SW_INT_ENABLE		0x1
436 
437 #define	AR9170_INT_REG_FIQ_ENCODE		(AR9170_INT_REG_BASE + 0x020)
438 #define	AR9170_INT_INT_IRQ_ENCODE		(AR9170_INT_REG_BASE + 0x024)
439 
440 /* Power Management */
441 #define	AR9170_PWR_REG_BASE			0x1d4000
442 
443 #define AR9170_PWR_REG_POWER_STATE		(AR9170_PWR_REG_BASE + 0x000)
444 
445 #define	AR9170_PWR_REG_RESET			(AR9170_PWR_REG_BASE + 0x004)
446 #define		AR9170_PWR_RESET_COMMIT_RESET_MASK	BIT(0)
447 #define		AR9170_PWR_RESET_WLAN_MASK		BIT(1)
448 #define		AR9170_PWR_RESET_DMA_MASK		BIT(2)
449 #define		AR9170_PWR_RESET_BRIDGE_MASK		BIT(3)
450 #define		AR9170_PWR_RESET_AHB_MASK		BIT(9)
451 #define		AR9170_PWR_RESET_BB_WARM_RESET		BIT(10)
452 #define		AR9170_PWR_RESET_BB_COLD_RESET		BIT(11)
453 #define		AR9170_PWR_RESET_ADDA_CLK_COLD_RESET	BIT(12)
454 #define		AR9170_PWR_RESET_PLL			BIT(13)
455 #define		AR9170_PWR_RESET_USB_PLL		BIT(14)
456 
457 #define	AR9170_PWR_REG_CLOCK_SEL		(AR9170_PWR_REG_BASE + 0x008)
458 #define		AR9170_PWR_CLK_AHB_40MHZ		0
459 #define		AR9170_PWR_CLK_AHB_20_22MHZ		1
460 #define		AR9170_PWR_CLK_AHB_40_44MHZ		2
461 #define		AR9170_PWR_CLK_AHB_80_88MHZ		3
462 #define		AR9170_PWR_CLK_DAC_160_INV_DLY		0x70
463 
464 #define	AR9170_PWR_REG_CHIP_REVISION		(AR9170_PWR_REG_BASE + 0x010)
465 #define AR9170_PWR_REG_PLL_ADDAC		(AR9170_PWR_REG_BASE + 0x014)
466 #define	AR9170_PWR_REG_WATCH_DOG_MAGIC		(AR9170_PWR_REG_BASE + 0x020)
467 
468 /* Faraday USB Controller */
469 #define	AR9170_USB_REG_BASE			0x1e1000
470 
471 #define	AR9170_USB_REG_MAIN_CTRL		(AR9170_USB_REG_BASE + 0x000)
472 #define		AR9170_USB_MAIN_CTRL_REMOTE_WAKEUP	BIT(0)
473 #define		AR9170_USB_MAIN_CTRL_ENABLE_GLOBAL_INT	BIT(2)
474 #define		AR9170_USB_MAIN_CTRL_HIGHSPEED		BIT(6)
475 
476 #define	AR9170_USB_REG_DEVICE_ADDRESS		(AR9170_USB_REG_BASE + 0x001)
477 #define		AR9170_USB_DEVICE_ADDRESS_CONFIGURE	BIT(7)
478 
479 #define	AR9170_USB_REG_TEST			(AR9170_USB_REG_BASE + 0x002)
480 #define	AR9170_USB_REG_PHY_TEST_SELECT		(AR9170_USB_REG_BASE + 0x008)
481 #define	AR9170_USB_REG_CX_CONFIG_STATUS		(AR9170_USB_REG_BASE + 0x00b)
482 #define	AR9170_USB_REG_EP0_DATA			(AR9170_USB_REG_BASE + 0x00c)
483 #define	AR9170_USB_REG_EP0_DATA1		(AR9170_USB_REG_BASE + 0x00c)
484 #define	AR9170_USB_REG_EP0_DATA2		(AR9170_USB_REG_BASE + 0x00d)
485 
486 #define	AR9170_USB_REG_INTR_MASK_BYTE_0		(AR9170_USB_REG_BASE + 0x011)
487 #define	AR9170_USB_REG_INTR_MASK_BYTE_1		(AR9170_USB_REG_BASE + 0x012)
488 #define	AR9170_USB_REG_INTR_MASK_BYTE_2		(AR9170_USB_REG_BASE + 0x013)
489 #define	AR9170_USB_REG_INTR_MASK_BYTE_3		(AR9170_USB_REG_BASE + 0x014)
490 #define	AR9170_USB_REG_INTR_MASK_BYTE_4		(AR9170_USB_REG_BASE + 0x015)
491 #define		AR9170_USB_INTR_DISABLE_OUT_INT		(BIT(7) | BIT(6))
492 
493 #define	AR9170_USB_REG_INTR_MASK_BYTE_5		(AR9170_USB_REG_BASE + 0x016)
494 #define	AR9170_USB_REG_INTR_MASK_BYTE_6		(AR9170_USB_REG_BASE + 0x017)
495 #define		AR9170_USB_INTR_DISABLE_IN_INT		BIT(6)
496 
497 #define	AR9170_USB_REG_INTR_MASK_BYTE_7		(AR9170_USB_REG_BASE + 0x018)
498 
499 #define	AR9170_USB_REG_INTR_GROUP		(AR9170_USB_REG_BASE + 0x020)
500 
501 #define	AR9170_USB_REG_INTR_SOURCE_0		(AR9170_USB_REG_BASE + 0x021)
502 #define	AR9170_USB_REG_INTR_SOURCE_1		(AR9170_USB_REG_BASE + 0x022)
503 #define	AR9170_USB_REG_INTR_SOURCE_2		(AR9170_USB_REG_BASE + 0x023)
504 #define	AR9170_USB_REG_INTR_SOURCE_3		(AR9170_USB_REG_BASE + 0x024)
505 #define	AR9170_USB_REG_INTR_SOURCE_4		(AR9170_USB_REG_BASE + 0x025)
506 #define	AR9170_USB_REG_INTR_SOURCE_5		(AR9170_USB_REG_BASE + 0x026)
507 #define	AR9170_USB_REG_INTR_SOURCE_6		(AR9170_USB_REG_BASE + 0x027)
508 #define	AR9170_USB_REG_INTR_SOURCE_7		(AR9170_USB_REG_BASE + 0x028)
509 
510 #define	AR9170_USB_REG_EP_MAP			(AR9170_USB_REG_BASE + 0x030)
511 #define	AR9170_USB_REG_EP1_MAP			(AR9170_USB_REG_BASE + 0x030)
512 #define	AR9170_USB_REG_EP2_MAP			(AR9170_USB_REG_BASE + 0x031)
513 #define	AR9170_USB_REG_EP3_MAP			(AR9170_USB_REG_BASE + 0x032)
514 #define	AR9170_USB_REG_EP4_MAP			(AR9170_USB_REG_BASE + 0x033)
515 #define	AR9170_USB_REG_EP5_MAP			(AR9170_USB_REG_BASE + 0x034)
516 #define	AR9170_USB_REG_EP6_MAP			(AR9170_USB_REG_BASE + 0x035)
517 #define	AR9170_USB_REG_EP7_MAP			(AR9170_USB_REG_BASE + 0x036)
518 #define	AR9170_USB_REG_EP8_MAP			(AR9170_USB_REG_BASE + 0x037)
519 #define	AR9170_USB_REG_EP9_MAP			(AR9170_USB_REG_BASE + 0x038)
520 #define	AR9170_USB_REG_EP10_MAP			(AR9170_USB_REG_BASE + 0x039)
521 
522 #define	AR9170_USB_REG_EP_IN_MAX_SIZE_HIGH	(AR9170_USB_REG_BASE + 0x03f)
523 #define		AR9170_USB_EP_IN_TOGGLE			0x10
524 
525 #define	AR9170_USB_REG_EP_IN_MAX_SIZE_LOW	(AR9170_USB_REG_BASE + 0x03e)
526 
527 #define	AR9170_USB_REG_EP_OUT_MAX_SIZE_HIGH	(AR9170_USB_REG_BASE + 0x05f)
528 #define		AR9170_USB_EP_OUT_TOGGLE		0x10
529 
530 #define	AR9170_USB_REG_EP_OUT_MAX_SIZE_LOW	(AR9170_USB_REG_BASE + 0x05e)
531 
532 #define	AR9170_USB_REG_EP3_BYTE_COUNT_HIGH	(AR9170_USB_REG_BASE + 0x0ae)
533 #define	AR9170_USB_REG_EP3_BYTE_COUNT_LOW	(AR9170_USB_REG_BASE + 0x0be)
534 #define	AR9170_USB_REG_EP4_BYTE_COUNT_HIGH	(AR9170_USB_REG_BASE + 0x0af)
535 #define	AR9170_USB_REG_EP4_BYTE_COUNT_LOW	(AR9170_USB_REG_BASE + 0x0bf)
536 
537 #define	AR9170_USB_REG_FIFO_MAP			(AR9170_USB_REG_BASE + 0x080)
538 #define	AR9170_USB_REG_FIFO0_MAP		(AR9170_USB_REG_BASE + 0x080)
539 #define	AR9170_USB_REG_FIFO1_MAP		(AR9170_USB_REG_BASE + 0x081)
540 #define	AR9170_USB_REG_FIFO2_MAP		(AR9170_USB_REG_BASE + 0x082)
541 #define	AR9170_USB_REG_FIFO3_MAP		(AR9170_USB_REG_BASE + 0x083)
542 #define	AR9170_USB_REG_FIFO4_MAP		(AR9170_USB_REG_BASE + 0x084)
543 #define	AR9170_USB_REG_FIFO5_MAP		(AR9170_USB_REG_BASE + 0x085)
544 #define	AR9170_USB_REG_FIFO6_MAP		(AR9170_USB_REG_BASE + 0x086)
545 #define	AR9170_USB_REG_FIFO7_MAP		(AR9170_USB_REG_BASE + 0x087)
546 #define	AR9170_USB_REG_FIFO8_MAP		(AR9170_USB_REG_BASE + 0x088)
547 #define	AR9170_USB_REG_FIFO9_MAP		(AR9170_USB_REG_BASE + 0x089)
548 
549 #define	AR9170_USB_REG_FIFO_CONFIG		(AR9170_USB_REG_BASE + 0x090)
550 #define	AR9170_USB_REG_FIFO0_CONFIG		(AR9170_USB_REG_BASE + 0x090)
551 #define	AR9170_USB_REG_FIFO1_CONFIG		(AR9170_USB_REG_BASE + 0x091)
552 #define	AR9170_USB_REG_FIFO2_CONFIG		(AR9170_USB_REG_BASE + 0x092)
553 #define	AR9170_USB_REG_FIFO3_CONFIG		(AR9170_USB_REG_BASE + 0x093)
554 #define	AR9170_USB_REG_FIFO4_CONFIG		(AR9170_USB_REG_BASE + 0x094)
555 #define	AR9170_USB_REG_FIFO5_CONFIG		(AR9170_USB_REG_BASE + 0x095)
556 #define	AR9170_USB_REG_FIFO6_CONFIG		(AR9170_USB_REG_BASE + 0x096)
557 #define	AR9170_USB_REG_FIFO7_CONFIG		(AR9170_USB_REG_BASE + 0x097)
558 #define	AR9170_USB_REG_FIFO8_CONFIG		(AR9170_USB_REG_BASE + 0x098)
559 #define	AR9170_USB_REG_FIFO9_CONFIG		(AR9170_USB_REG_BASE + 0x099)
560 
561 #define	AR9170_USB_REG_EP3_DATA			(AR9170_USB_REG_BASE + 0x0f8)
562 #define	AR9170_USB_REG_EP4_DATA			(AR9170_USB_REG_BASE + 0x0fc)
563 
564 #define	AR9170_USB_REG_FIFO_SIZE		(AR9170_USB_REG_BASE + 0x100)
565 #define	AR9170_USB_REG_DMA_CTL			(AR9170_USB_REG_BASE + 0x108)
566 #define		AR9170_USB_DMA_CTL_ENABLE_TO_DEVICE	BIT(0)
567 #define		AR9170_USB_DMA_CTL_ENABLE_FROM_DEVICE	BIT(1)
568 #define		AR9170_USB_DMA_CTL_HIGH_SPEED		BIT(2)
569 #define		AR9170_USB_DMA_CTL_UP_PACKET_MODE	BIT(3)
570 #define		AR9170_USB_DMA_CTL_UP_STREAM_S		4
571 #define		AR9170_USB_DMA_CTL_UP_STREAM		(BIT(4) | BIT(5))
572 #define		AR9170_USB_DMA_CTL_UP_STREAM_4K		(0)
573 #define		AR9170_USB_DMA_CTL_UP_STREAM_8K		BIT(4)
574 #define		AR9170_USB_DMA_CTL_UP_STREAM_16K	BIT(5)
575 #define		AR9170_USB_DMA_CTL_UP_STREAM_32K	(BIT(4) | BIT(5))
576 #define		AR9170_USB_DMA_CTL_DOWN_STREAM		BIT(6)
577 
578 #define	AR9170_USB_REG_DMA_STATUS		(AR9170_USB_REG_BASE + 0x10c)
579 #define		AR9170_USB_DMA_STATUS_UP_IDLE		BIT(8)
580 #define		AR9170_USB_DMA_STATUS_DN_IDLE		BIT(16)
581 
582 #define	AR9170_USB_REG_MAX_AGG_UPLOAD		(AR9170_USB_REG_BASE + 0x110)
583 #define	AR9170_USB_REG_UPLOAD_TIME_CTL		(AR9170_USB_REG_BASE + 0x114)
584 #define	AR9170_USB_REG_CBUS_CTRL		(AR9170_USB_REG_BASE + 0x1f0)
585 #define		AR9170_USB_CBUS_CTRL_BUFFER_END		(BIT(1))
586 
587 /* PCI/USB to AHB Bridge */
588 #define	AR9170_PTA_REG_BASE			0x1e2000
589 
590 #define	AR9170_PTA_REG_CMD			(AR9170_PTA_REG_BASE + 0x000)
591 #define	AR9170_PTA_REG_PARAM1			(AR9170_PTA_REG_BASE + 0x004)
592 #define	AR9170_PTA_REG_PARAM2			(AR9170_PTA_REG_BASE + 0x008)
593 #define	AR9170_PTA_REG_PARAM3			(AR9170_PTA_REG_BASE + 0x00c)
594 #define	AR9170_PTA_REG_RSP			(AR9170_PTA_REG_BASE + 0x010)
595 #define	AR9170_PTA_REG_STATUS1			(AR9170_PTA_REG_BASE + 0x014)
596 #define	AR9170_PTA_REG_STATUS2			(AR9170_PTA_REG_BASE + 0x018)
597 #define	AR9170_PTA_REG_STATUS3			(AR9170_PTA_REG_BASE + 0x01c)
598 #define	AR9170_PTA_REG_AHB_INT_FLAG		(AR9170_PTA_REG_BASE + 0x020)
599 #define	AR9170_PTA_REG_AHB_INT_MASK		(AR9170_PTA_REG_BASE + 0x024)
600 #define	AR9170_PTA_REG_AHB_INT_ACK		(AR9170_PTA_REG_BASE + 0x028)
601 #define	AR9170_PTA_REG_AHB_SCRATCH1		(AR9170_PTA_REG_BASE + 0x030)
602 #define	AR9170_PTA_REG_AHB_SCRATCH2		(AR9170_PTA_REG_BASE + 0x034)
603 #define	AR9170_PTA_REG_AHB_SCRATCH3		(AR9170_PTA_REG_BASE + 0x038)
604 #define	AR9170_PTA_REG_AHB_SCRATCH4		(AR9170_PTA_REG_BASE + 0x03c)
605 
606 #define	AR9170_PTA_REG_SHARE_MEM_CTRL		(AR9170_PTA_REG_BASE + 0x124)
607 
608 /*
609  * PCI to AHB Bridge
610  */
611 
612 #define	AR9170_PTA_REG_INT_FLAG			(AR9170_PTA_REG_BASE + 0x100)
613 #define		AR9170_PTA_INT_FLAG_DN			0x01
614 #define		AR9170_PTA_INT_FLAG_UP			0x02
615 #define		AR9170_PTA_INT_FLAG_CMD			0x04
616 
617 #define	AR9170_PTA_REG_INT_MASK			(AR9170_PTA_REG_BASE + 0x104)
618 #define	AR9170_PTA_REG_DN_DMA_ADDRL		(AR9170_PTA_REG_BASE + 0x108)
619 #define	AR9170_PTA_REG_DN_DMA_ADDRH		(AR9170_PTA_REG_BASE + 0x10c)
620 #define	AR9170_PTA_REG_UP_DMA_ADDRL		(AR9170_PTA_REG_BASE + 0x110)
621 #define	AR9170_PTA_REG_UP_DMA_ADDRH		(AR9170_PTA_REG_BASE + 0x114)
622 #define	AR9170_PTA_REG_DN_PEND_TIME		(AR9170_PTA_REG_BASE + 0x118)
623 #define	AR9170_PTA_REG_UP_PEND_TIME		(AR9170_PTA_REG_BASE + 0x11c)
624 #define	AR9170_PTA_REG_CONTROL			(AR9170_PTA_REG_BASE + 0x120)
625 #define		AR9170_PTA_CTRL_4_BEAT_BURST		0x00
626 #define		AR9170_PTA_CTRL_8_BEAT_BURST		0x01
627 #define		AR9170_PTA_CTRL_16_BEAT_BURST		0x02
628 #define		AR9170_PTA_CTRL_LOOPBACK_MODE		0x10
629 
630 #define	AR9170_PTA_REG_MEM_CTRL			(AR9170_PTA_REG_BASE + 0x124)
631 #define	AR9170_PTA_REG_MEM_ADDR			(AR9170_PTA_REG_BASE + 0x128)
632 #define	AR9170_PTA_REG_DN_DMA_TRIGGER		(AR9170_PTA_REG_BASE + 0x12c)
633 #define	AR9170_PTA_REG_UP_DMA_TRIGGER		(AR9170_PTA_REG_BASE + 0x130)
634 #define	AR9170_PTA_REG_DMA_STATUS		(AR9170_PTA_REG_BASE + 0x134)
635 #define	AR9170_PTA_REG_DN_CURR_ADDRL		(AR9170_PTA_REG_BASE + 0x138)
636 #define	AR9170_PTA_REG_DN_CURR_ADDRH		(AR9170_PTA_REG_BASE + 0x13c)
637 #define	AR9170_PTA_REG_UP_CURR_ADDRL		(AR9170_PTA_REG_BASE + 0x140)
638 #define	AR9170_PTA_REG_UP_CURR_ADDRH		(AR9170_PTA_REG_BASE + 0x144)
639 #define	AR9170_PTA_REG_DMA_MODE_CTRL		(AR9170_PTA_REG_BASE + 0x148)
640 #define		AR9170_PTA_DMA_MODE_CTRL_RESET		BIT(0)
641 #define		AR9170_PTA_DMA_MODE_CTRL_DISABLE_USB	BIT(1)
642 
643 /* Protocol Controller Module */
644 #define	AR9170_MAC_REG_PC_REG_BASE		(AR9170_MAC_REG_BASE + 0xe00)
645 
646 
647 #define	AR9170_NUM_LEDS				2
648 
649 /* CAM */
650 #define	AR9170_CAM_MAX_USER			64
651 #define	AR9170_CAM_MAX_KEY_LENGTH		16
652 
653 #define AR9170_SRAM_OFFSET		0x100000
654 #define AR9170_SRAM_SIZE		0x18000
655 
656 #define AR9170_PRAM_OFFSET		0x200000
657 #define AR9170_PRAM_SIZE		0x8000
658 
659 enum cpu_clock {
660 	AHB_STATIC_40MHZ = 0,
661 	AHB_GMODE_22MHZ = 1,
662 	AHB_AMODE_20MHZ = 1,
663 	AHB_GMODE_44MHZ = 2,
664 	AHB_AMODE_40MHZ = 2,
665 	AHB_GMODE_88MHZ = 3,
666 	AHB_AMODE_80MHZ = 3
667 };
668 
669 /* USB endpoints */
670 enum ar9170_usb_ep {
671 	/*
672 	 * Control EP is always EP 0 (USB SPEC)
673 	 *
674 	 * The weird thing is: the original firmware has a few
675 	 * comments that suggest that the actual EP numbers
676 	 * are in the 1 to 10 range?!
677 	 */
678 	AR9170_USB_EP_CTRL		= 0,
679 
680 	AR9170_USB_EP_TX,
681 	AR9170_USB_EP_RX,
682 	AR9170_USB_EP_IRQ,
683 	AR9170_USB_EP_CMD,
684 	AR9170_USB_NUM_EXTRA_EP		= 4,
685 
686 	__AR9170_USB_NUM_EP,
687 
688 	__AR9170_USB_NUM_MAX_EP		= 10
689 };
690 
691 enum ar9170_usb_fifo {
692 	__AR9170_USB_NUM_MAX_FIFO	= 10
693 };
694 
695 enum ar9170_tx_queues {
696 	AR9170_TXQ0	= 0,
697 	AR9170_TXQ1,
698 	AR9170_TXQ2,
699 	AR9170_TXQ3,
700 	AR9170_TXQ_SPECIAL,
701 
702 	/* keep last */
703 	__AR9170_NUM_TX_QUEUES = 5
704 };
705 
706 #define	AR9170_TX_STREAM_TAG		0x697e
707 #define	AR9170_RX_STREAM_TAG		0x4e00
708 #define	AR9170_RX_STREAM_MAX_SIZE	0xffff
709 
710 struct ar9170_stream {
711 	__le16 length;
712 	__le16 tag;
713 
714 	u8 payload[0];
715 } __packed __aligned(4);
716 #define AR9170_STREAM_LEN				4
717 
718 #define AR9170_MAX_ACKTABLE_ENTRIES			8
719 #define AR9170_MAX_VIRTUAL_MAC				7
720 
721 #define	AR9170_USB_EP_CTRL_MAX				64
722 #define	AR9170_USB_EP_TX_MAX				512
723 #define	AR9170_USB_EP_RX_MAX				512
724 #define	AR9170_USB_EP_IRQ_MAX				64
725 #define	AR9170_USB_EP_CMD_MAX				64
726 
727 /* Trigger PRETBTT interrupt 6 Kus earlier */
728 #define CARL9170_PRETBTT_KUS				6
729 
730 #define	AR5416_MAX_RATE_POWER				63
731 
732 #define SET_VAL(reg, value, newvalue)					\
733 	(value = ((value) & ~reg) | (((newvalue) << reg##_S) & reg))
734 
735 #define SET_CONSTVAL(reg, newvalue)					\
736 	(((newvalue) << reg##_S) & reg)
737 
738 #define MOD_VAL(reg, value, newvalue)					\
739 	(((value) & ~reg) | (((newvalue) << reg##_S) & reg))
740 
741 #define GET_VAL(reg, value)						\
742 	(((value) & reg) >> reg##_S)
743 
744 #endif	/* __CARL9170_SHARED_HW_H */
745