1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "ath9k.h" 18 19 #define BITS_PER_BYTE 8 20 #define OFDM_PLCP_BITS 22 21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 23 #define L_STF 8 24 #define L_LTF 8 25 #define L_SIG 4 26 #define HT_SIG 8 27 #define HT_STF 4 28 #define HT_LTF(_ns) (4 * (_ns)) 29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 33 34 #define OFDM_SIFS_TIME 16 35 36 static u32 bits_per_symbol[][2] = { 37 /* 20MHz 40MHz */ 38 { 26, 54 }, /* 0: BPSK */ 39 { 52, 108 }, /* 1: QPSK 1/2 */ 40 { 78, 162 }, /* 2: QPSK 3/4 */ 41 { 104, 216 }, /* 3: 16-QAM 1/2 */ 42 { 156, 324 }, /* 4: 16-QAM 3/4 */ 43 { 208, 432 }, /* 5: 64-QAM 2/3 */ 44 { 234, 486 }, /* 6: 64-QAM 3/4 */ 45 { 260, 540 }, /* 7: 64-QAM 5/6 */ 46 { 52, 108 }, /* 8: BPSK */ 47 { 104, 216 }, /* 9: QPSK 1/2 */ 48 { 156, 324 }, /* 10: QPSK 3/4 */ 49 { 208, 432 }, /* 11: 16-QAM 1/2 */ 50 { 312, 648 }, /* 12: 16-QAM 3/4 */ 51 { 416, 864 }, /* 13: 64-QAM 2/3 */ 52 { 468, 972 }, /* 14: 64-QAM 3/4 */ 53 { 520, 1080 }, /* 15: 64-QAM 5/6 */ 54 }; 55 56 #define IS_HT_RATE(_rate) ((_rate) & 0x80) 57 58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 59 struct ath_atx_tid *tid, 60 struct list_head *bf_head); 61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_txq *txq, 63 struct list_head *bf_q, 64 int txok, int sendbar); 65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 66 struct list_head *head); 67 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); 68 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, 69 int txok); 70 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 71 int nbad, int txok, bool update_rc); 72 73 /*********************/ 74 /* Aggregation logic */ 75 /*********************/ 76 77 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) 78 { 79 struct ath_atx_ac *ac = tid->ac; 80 81 if (tid->paused) 82 return; 83 84 if (tid->sched) 85 return; 86 87 tid->sched = true; 88 list_add_tail(&tid->list, &ac->tid_q); 89 90 if (ac->sched) 91 return; 92 93 ac->sched = true; 94 list_add_tail(&ac->list, &txq->axq_acq); 95 } 96 97 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 98 { 99 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 100 101 spin_lock_bh(&txq->axq_lock); 102 tid->paused++; 103 spin_unlock_bh(&txq->axq_lock); 104 } 105 106 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 107 { 108 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 109 110 ASSERT(tid->paused > 0); 111 spin_lock_bh(&txq->axq_lock); 112 113 tid->paused--; 114 115 if (tid->paused > 0) 116 goto unlock; 117 118 if (list_empty(&tid->buf_q)) 119 goto unlock; 120 121 ath_tx_queue_tid(txq, tid); 122 ath_txq_schedule(sc, txq); 123 unlock: 124 spin_unlock_bh(&txq->axq_lock); 125 } 126 127 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 128 { 129 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 130 struct ath_buf *bf; 131 struct list_head bf_head; 132 INIT_LIST_HEAD(&bf_head); 133 134 ASSERT(tid->paused > 0); 135 spin_lock_bh(&txq->axq_lock); 136 137 tid->paused--; 138 139 if (tid->paused > 0) { 140 spin_unlock_bh(&txq->axq_lock); 141 return; 142 } 143 144 while (!list_empty(&tid->buf_q)) { 145 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 146 ASSERT(!bf_isretried(bf)); 147 list_move_tail(&bf->list, &bf_head); 148 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 149 } 150 151 spin_unlock_bh(&txq->axq_lock); 152 } 153 154 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 155 int seqno) 156 { 157 int index, cindex; 158 159 index = ATH_BA_INDEX(tid->seq_start, seqno); 160 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 161 162 tid->tx_buf[cindex] = NULL; 163 164 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { 165 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 166 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 167 } 168 } 169 170 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 171 struct ath_buf *bf) 172 { 173 int index, cindex; 174 175 if (bf_isretried(bf)) 176 return; 177 178 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); 179 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 180 181 ASSERT(tid->tx_buf[cindex] == NULL); 182 tid->tx_buf[cindex] = bf; 183 184 if (index >= ((tid->baw_tail - tid->baw_head) & 185 (ATH_TID_MAX_BUFS - 1))) { 186 tid->baw_tail = cindex; 187 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 188 } 189 } 190 191 /* 192 * TODO: For frame(s) that are in the retry state, we will reuse the 193 * sequence number(s) without setting the retry bit. The 194 * alternative is to give up on these and BAR the receiver's window 195 * forward. 196 */ 197 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 198 struct ath_atx_tid *tid) 199 200 { 201 struct ath_buf *bf; 202 struct list_head bf_head; 203 INIT_LIST_HEAD(&bf_head); 204 205 for (;;) { 206 if (list_empty(&tid->buf_q)) 207 break; 208 209 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 210 list_move_tail(&bf->list, &bf_head); 211 212 if (bf_isretried(bf)) 213 ath_tx_update_baw(sc, tid, bf->bf_seqno); 214 215 spin_unlock(&txq->axq_lock); 216 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); 217 spin_lock(&txq->axq_lock); 218 } 219 220 tid->seq_next = tid->seq_start; 221 tid->baw_tail = tid->baw_head; 222 } 223 224 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 225 struct ath_buf *bf) 226 { 227 struct sk_buff *skb; 228 struct ieee80211_hdr *hdr; 229 230 bf->bf_state.bf_type |= BUF_RETRY; 231 bf->bf_retries++; 232 TX_STAT_INC(txq->axq_qnum, a_retries); 233 234 skb = bf->bf_mpdu; 235 hdr = (struct ieee80211_hdr *)skb->data; 236 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 237 } 238 239 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 240 { 241 struct ath_buf *tbf; 242 243 spin_lock_bh(&sc->tx.txbuflock); 244 if (WARN_ON(list_empty(&sc->tx.txbuf))) { 245 spin_unlock_bh(&sc->tx.txbuflock); 246 return NULL; 247 } 248 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 249 list_del(&tbf->list); 250 spin_unlock_bh(&sc->tx.txbuflock); 251 252 ATH_TXBUF_RESET(tbf); 253 254 tbf->bf_mpdu = bf->bf_mpdu; 255 tbf->bf_buf_addr = bf->bf_buf_addr; 256 *(tbf->bf_desc) = *(bf->bf_desc); 257 tbf->bf_state = bf->bf_state; 258 tbf->bf_dmacontext = bf->bf_dmacontext; 259 260 return tbf; 261 } 262 263 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 264 struct ath_buf *bf, struct list_head *bf_q, 265 int txok) 266 { 267 struct ath_node *an = NULL; 268 struct sk_buff *skb; 269 struct ieee80211_sta *sta; 270 struct ieee80211_hdr *hdr; 271 struct ath_atx_tid *tid = NULL; 272 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 273 struct ath_desc *ds = bf_last->bf_desc; 274 struct list_head bf_head, bf_pending; 275 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; 276 u32 ba[WME_BA_BMP_SIZE >> 5]; 277 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 278 bool rc_update = true; 279 280 skb = bf->bf_mpdu; 281 hdr = (struct ieee80211_hdr *)skb->data; 282 283 rcu_read_lock(); 284 285 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 286 if (!sta) { 287 rcu_read_unlock(); 288 return; 289 } 290 291 an = (struct ath_node *)sta->drv_priv; 292 tid = ATH_AN_2_TID(an, bf->bf_tidno); 293 294 isaggr = bf_isaggr(bf); 295 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 296 297 if (isaggr && txok) { 298 if (ATH_DS_TX_BA(ds)) { 299 seq_st = ATH_DS_BA_SEQ(ds); 300 memcpy(ba, ATH_DS_BA_BITMAP(ds), 301 WME_BA_BMP_SIZE >> 3); 302 } else { 303 /* 304 * AR5416 can become deaf/mute when BA 305 * issue happens. Chip needs to be reset. 306 * But AP code may have sychronization issues 307 * when perform internal reset in this routine. 308 * Only enable reset in STA mode for now. 309 */ 310 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 311 needreset = 1; 312 } 313 } 314 315 INIT_LIST_HEAD(&bf_pending); 316 INIT_LIST_HEAD(&bf_head); 317 318 nbad = ath_tx_num_badfrms(sc, bf, txok); 319 while (bf) { 320 txfail = txpending = 0; 321 bf_next = bf->bf_next; 322 323 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { 324 /* transmit completion, subframe is 325 * acked by block ack */ 326 acked_cnt++; 327 } else if (!isaggr && txok) { 328 /* transmit completion */ 329 acked_cnt++; 330 } else { 331 if (!(tid->state & AGGR_CLEANUP) && 332 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { 333 if (bf->bf_retries < ATH_MAX_SW_RETRIES) { 334 ath_tx_set_retry(sc, txq, bf); 335 txpending = 1; 336 } else { 337 bf->bf_state.bf_type |= BUF_XRETRY; 338 txfail = 1; 339 sendbar = 1; 340 txfail_cnt++; 341 } 342 } else { 343 /* 344 * cleanup in progress, just fail 345 * the un-acked sub-frames 346 */ 347 txfail = 1; 348 } 349 } 350 351 if (bf_next == NULL) { 352 /* 353 * Make sure the last desc is reclaimed if it 354 * not a holding desc. 355 */ 356 if (!bf_last->bf_stale) 357 list_move_tail(&bf->list, &bf_head); 358 else 359 INIT_LIST_HEAD(&bf_head); 360 } else { 361 ASSERT(!list_empty(bf_q)); 362 list_move_tail(&bf->list, &bf_head); 363 } 364 365 if (!txpending) { 366 /* 367 * complete the acked-ones/xretried ones; update 368 * block-ack window 369 */ 370 spin_lock_bh(&txq->axq_lock); 371 ath_tx_update_baw(sc, tid, bf->bf_seqno); 372 spin_unlock_bh(&txq->axq_lock); 373 374 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 375 ath_tx_rc_status(bf, ds, nbad, txok, true); 376 rc_update = false; 377 } else { 378 ath_tx_rc_status(bf, ds, nbad, txok, false); 379 } 380 381 ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar); 382 } else { 383 /* retry the un-acked ones */ 384 if (bf->bf_next == NULL && bf_last->bf_stale) { 385 struct ath_buf *tbf; 386 387 tbf = ath_clone_txbuf(sc, bf_last); 388 /* 389 * Update tx baw and complete the frame with 390 * failed status if we run out of tx buf 391 */ 392 if (!tbf) { 393 spin_lock_bh(&txq->axq_lock); 394 ath_tx_update_baw(sc, tid, 395 bf->bf_seqno); 396 spin_unlock_bh(&txq->axq_lock); 397 398 bf->bf_state.bf_type |= BUF_XRETRY; 399 ath_tx_rc_status(bf, ds, nbad, 400 0, false); 401 ath_tx_complete_buf(sc, bf, txq, 402 &bf_head, 0, 0); 403 break; 404 } 405 406 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); 407 list_add_tail(&tbf->list, &bf_head); 408 } else { 409 /* 410 * Clear descriptor status words for 411 * software retry 412 */ 413 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); 414 } 415 416 /* 417 * Put this buffer to the temporary pending 418 * queue to retain ordering 419 */ 420 list_splice_tail_init(&bf_head, &bf_pending); 421 } 422 423 bf = bf_next; 424 } 425 426 if (tid->state & AGGR_CLEANUP) { 427 if (tid->baw_head == tid->baw_tail) { 428 tid->state &= ~AGGR_ADDBA_COMPLETE; 429 tid->state &= ~AGGR_CLEANUP; 430 431 /* send buffered frames as singles */ 432 ath_tx_flush_tid(sc, tid); 433 } 434 rcu_read_unlock(); 435 return; 436 } 437 438 /* prepend un-acked frames to the beginning of the pending frame queue */ 439 if (!list_empty(&bf_pending)) { 440 spin_lock_bh(&txq->axq_lock); 441 list_splice(&bf_pending, &tid->buf_q); 442 ath_tx_queue_tid(txq, tid); 443 spin_unlock_bh(&txq->axq_lock); 444 } 445 446 rcu_read_unlock(); 447 448 if (needreset) 449 ath_reset(sc, false); 450 } 451 452 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 453 struct ath_atx_tid *tid) 454 { 455 const struct ath_rate_table *rate_table = sc->cur_rate_table; 456 struct sk_buff *skb; 457 struct ieee80211_tx_info *tx_info; 458 struct ieee80211_tx_rate *rates; 459 struct ath_tx_info_priv *tx_info_priv; 460 u32 max_4ms_framelen, frmlen; 461 u16 aggr_limit, legacy = 0; 462 int i; 463 464 skb = bf->bf_mpdu; 465 tx_info = IEEE80211_SKB_CB(skb); 466 rates = tx_info->control.rates; 467 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; 468 469 /* 470 * Find the lowest frame length among the rate series that will have a 471 * 4ms transmit duration. 472 * TODO - TXOP limit needs to be considered. 473 */ 474 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 475 476 for (i = 0; i < 4; i++) { 477 if (rates[i].count) { 478 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { 479 legacy = 1; 480 break; 481 } 482 483 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; 484 max_4ms_framelen = min(max_4ms_framelen, frmlen); 485 } 486 } 487 488 /* 489 * limit aggregate size by the minimum rate if rate selected is 490 * not a probe rate, if rate selected is a probe rate then 491 * avoid aggregation of this packet. 492 */ 493 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 494 return 0; 495 496 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) 497 aggr_limit = min((max_4ms_framelen * 3) / 8, 498 (u32)ATH_AMPDU_LIMIT_MAX); 499 else 500 aggr_limit = min(max_4ms_framelen, 501 (u32)ATH_AMPDU_LIMIT_MAX); 502 503 /* 504 * h/w can accept aggregates upto 16 bit lengths (65535). 505 * The IE, however can hold upto 65536, which shows up here 506 * as zero. Ignore 65536 since we are constrained by hw. 507 */ 508 if (tid->an->maxampdu) 509 aggr_limit = min(aggr_limit, tid->an->maxampdu); 510 511 return aggr_limit; 512 } 513 514 /* 515 * Returns the number of delimiters to be added to 516 * meet the minimum required mpdudensity. 517 */ 518 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 519 struct ath_buf *bf, u16 frmlen) 520 { 521 const struct ath_rate_table *rt = sc->cur_rate_table; 522 struct sk_buff *skb = bf->bf_mpdu; 523 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 524 u32 nsymbits, nsymbols; 525 u16 minlen; 526 u8 rc, flags, rix; 527 int width, half_gi, ndelim, mindelim; 528 529 /* Select standard number of delimiters based on frame length alone */ 530 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 531 532 /* 533 * If encryption enabled, hardware requires some more padding between 534 * subframes. 535 * TODO - this could be improved to be dependent on the rate. 536 * The hardware can keep up at lower rates, but not higher rates 537 */ 538 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) 539 ndelim += ATH_AGGR_ENCRYPTDELIM; 540 541 /* 542 * Convert desired mpdu density from microeconds to bytes based 543 * on highest rate in rate series (i.e. first rate) to determine 544 * required minimum length for subframe. Take into account 545 * whether high rate is 20 or 40Mhz and half or full GI. 546 * 547 * If there is no mpdu density restriction, no further calculation 548 * is needed. 549 */ 550 551 if (tid->an->mpdudensity == 0) 552 return ndelim; 553 554 rix = tx_info->control.rates[0].idx; 555 flags = tx_info->control.rates[0].flags; 556 rc = rt->info[rix].ratecode; 557 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 558 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 559 560 if (half_gi) 561 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 562 else 563 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 564 565 if (nsymbols == 0) 566 nsymbols = 1; 567 568 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 569 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 570 571 if (frmlen < minlen) { 572 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 573 ndelim = max(mindelim, ndelim); 574 } 575 576 return ndelim; 577 } 578 579 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 580 struct ath_txq *txq, 581 struct ath_atx_tid *tid, 582 struct list_head *bf_q) 583 { 584 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 585 struct ath_buf *bf, *bf_first, *bf_prev = NULL; 586 int rl = 0, nframes = 0, ndelim, prev_al = 0; 587 u16 aggr_limit = 0, al = 0, bpad = 0, 588 al_delta, h_baw = tid->baw_size / 2; 589 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 590 591 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); 592 593 do { 594 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 595 596 /* do not step over block-ack window */ 597 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { 598 status = ATH_AGGR_BAW_CLOSED; 599 break; 600 } 601 602 if (!rl) { 603 aggr_limit = ath_lookup_rate(sc, bf, tid); 604 rl = 1; 605 } 606 607 /* do not exceed aggregation limit */ 608 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; 609 610 if (nframes && 611 (aggr_limit < (al + bpad + al_delta + prev_al))) { 612 status = ATH_AGGR_LIMITED; 613 break; 614 } 615 616 /* do not exceed subframe limit */ 617 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { 618 status = ATH_AGGR_LIMITED; 619 break; 620 } 621 nframes++; 622 623 /* add padding for previous frame to aggregation length */ 624 al += bpad + al_delta; 625 626 /* 627 * Get the delimiters needed to meet the MPDU 628 * density for this node. 629 */ 630 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); 631 bpad = PADBYTES(al_delta) + (ndelim << 2); 632 633 bf->bf_next = NULL; 634 bf->bf_desc->ds_link = 0; 635 636 /* link buffers of this frame to the aggregate */ 637 ath_tx_addto_baw(sc, tid, bf); 638 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); 639 list_move_tail(&bf->list, bf_q); 640 if (bf_prev) { 641 bf_prev->bf_next = bf; 642 bf_prev->bf_desc->ds_link = bf->bf_daddr; 643 } 644 bf_prev = bf; 645 646 } while (!list_empty(&tid->buf_q)); 647 648 bf_first->bf_al = al; 649 bf_first->bf_nframes = nframes; 650 651 return status; 652 #undef PADBYTES 653 } 654 655 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 656 struct ath_atx_tid *tid) 657 { 658 struct ath_buf *bf; 659 enum ATH_AGGR_STATUS status; 660 struct list_head bf_q; 661 662 do { 663 if (list_empty(&tid->buf_q)) 664 return; 665 666 INIT_LIST_HEAD(&bf_q); 667 668 status = ath_tx_form_aggr(sc, txq, tid, &bf_q); 669 670 /* 671 * no frames picked up to be aggregated; 672 * block-ack window is not open. 673 */ 674 if (list_empty(&bf_q)) 675 break; 676 677 bf = list_first_entry(&bf_q, struct ath_buf, list); 678 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 679 680 /* if only one frame, send as non-aggregate */ 681 if (bf->bf_nframes == 1) { 682 bf->bf_state.bf_type &= ~BUF_AGGR; 683 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); 684 ath_buf_set_rate(sc, bf); 685 ath_tx_txqaddbuf(sc, txq, &bf_q); 686 continue; 687 } 688 689 /* setup first desc of aggregate */ 690 bf->bf_state.bf_type |= BUF_AGGR; 691 ath_buf_set_rate(sc, bf); 692 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); 693 694 /* anchor last desc of aggregate */ 695 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 696 697 txq->axq_aggr_depth++; 698 ath_tx_txqaddbuf(sc, txq, &bf_q); 699 TX_STAT_INC(txq->axq_qnum, a_aggr); 700 701 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && 702 status != ATH_AGGR_BAW_CLOSED); 703 } 704 705 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 706 u16 tid, u16 *ssn) 707 { 708 struct ath_atx_tid *txtid; 709 struct ath_node *an; 710 711 an = (struct ath_node *)sta->drv_priv; 712 txtid = ATH_AN_2_TID(an, tid); 713 txtid->state |= AGGR_ADDBA_PROGRESS; 714 ath_tx_pause_tid(sc, txtid); 715 *ssn = txtid->seq_start; 716 } 717 718 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 719 { 720 struct ath_node *an = (struct ath_node *)sta->drv_priv; 721 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 722 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; 723 struct ath_buf *bf; 724 struct list_head bf_head; 725 INIT_LIST_HEAD(&bf_head); 726 727 if (txtid->state & AGGR_CLEANUP) 728 return; 729 730 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 731 txtid->state &= ~AGGR_ADDBA_PROGRESS; 732 return; 733 } 734 735 ath_tx_pause_tid(sc, txtid); 736 737 /* drop all software retried frames and mark this TID */ 738 spin_lock_bh(&txq->axq_lock); 739 while (!list_empty(&txtid->buf_q)) { 740 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); 741 if (!bf_isretried(bf)) { 742 /* 743 * NB: it's based on the assumption that 744 * software retried frame will always stay 745 * at the head of software queue. 746 */ 747 break; 748 } 749 list_move_tail(&bf->list, &bf_head); 750 ath_tx_update_baw(sc, txtid, bf->bf_seqno); 751 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); 752 } 753 spin_unlock_bh(&txq->axq_lock); 754 755 if (txtid->baw_head != txtid->baw_tail) { 756 txtid->state |= AGGR_CLEANUP; 757 } else { 758 txtid->state &= ~AGGR_ADDBA_COMPLETE; 759 ath_tx_flush_tid(sc, txtid); 760 } 761 } 762 763 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 764 { 765 struct ath_atx_tid *txtid; 766 struct ath_node *an; 767 768 an = (struct ath_node *)sta->drv_priv; 769 770 if (sc->sc_flags & SC_OP_TXAGGR) { 771 txtid = ATH_AN_2_TID(an, tid); 772 txtid->baw_size = 773 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 774 txtid->state |= AGGR_ADDBA_COMPLETE; 775 txtid->state &= ~AGGR_ADDBA_PROGRESS; 776 ath_tx_resume_tid(sc, txtid); 777 } 778 } 779 780 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) 781 { 782 struct ath_atx_tid *txtid; 783 784 if (!(sc->sc_flags & SC_OP_TXAGGR)) 785 return false; 786 787 txtid = ATH_AN_2_TID(an, tidno); 788 789 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) 790 return true; 791 return false; 792 } 793 794 /********************/ 795 /* Queue Management */ 796 /********************/ 797 798 static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 799 struct ath_txq *txq) 800 { 801 struct ath_atx_ac *ac, *ac_tmp; 802 struct ath_atx_tid *tid, *tid_tmp; 803 804 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 805 list_del(&ac->list); 806 ac->sched = false; 807 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { 808 list_del(&tid->list); 809 tid->sched = false; 810 ath_tid_drain(sc, txq, tid); 811 } 812 } 813 } 814 815 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 816 { 817 struct ath_hw *ah = sc->sc_ah; 818 struct ath9k_tx_queue_info qi; 819 int qnum; 820 821 memset(&qi, 0, sizeof(qi)); 822 qi.tqi_subtype = subtype; 823 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 824 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 825 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 826 qi.tqi_physCompBuf = 0; 827 828 /* 829 * Enable interrupts only for EOL and DESC conditions. 830 * We mark tx descriptors to receive a DESC interrupt 831 * when a tx queue gets deep; otherwise waiting for the 832 * EOL to reap descriptors. Note that this is done to 833 * reduce interrupt load and this only defers reaping 834 * descriptors, never transmitting frames. Aside from 835 * reducing interrupts this also permits more concurrency. 836 * The only potential downside is if the tx queue backs 837 * up in which case the top half of the kernel may backup 838 * due to a lack of tx descriptors. 839 * 840 * The UAPSD queue is an exception, since we take a desc- 841 * based intr on the EOSP frames. 842 */ 843 if (qtype == ATH9K_TX_QUEUE_UAPSD) 844 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 845 else 846 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 847 TXQ_FLAG_TXDESCINT_ENABLE; 848 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 849 if (qnum == -1) { 850 /* 851 * NB: don't print a message, this happens 852 * normally on parts with too few tx queues 853 */ 854 return NULL; 855 } 856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 857 DPRINTF(sc, ATH_DBG_FATAL, 858 "qnum %u out of range, max %u!\n", 859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 860 ath9k_hw_releasetxqueue(ah, qnum); 861 return NULL; 862 } 863 if (!ATH_TXQ_SETUP(sc, qnum)) { 864 struct ath_txq *txq = &sc->tx.txq[qnum]; 865 866 txq->axq_qnum = qnum; 867 txq->axq_link = NULL; 868 INIT_LIST_HEAD(&txq->axq_q); 869 INIT_LIST_HEAD(&txq->axq_acq); 870 spin_lock_init(&txq->axq_lock); 871 txq->axq_depth = 0; 872 txq->axq_aggr_depth = 0; 873 txq->axq_linkbuf = NULL; 874 txq->axq_tx_inprogress = false; 875 sc->tx.txqsetup |= 1<<qnum; 876 } 877 return &sc->tx.txq[qnum]; 878 } 879 880 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) 881 { 882 int qnum; 883 884 switch (qtype) { 885 case ATH9K_TX_QUEUE_DATA: 886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 887 DPRINTF(sc, ATH_DBG_FATAL, 888 "HAL AC %u out of range, max %zu!\n", 889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 890 return -1; 891 } 892 qnum = sc->tx.hwq_map[haltype]; 893 break; 894 case ATH9K_TX_QUEUE_BEACON: 895 qnum = sc->beacon.beaconq; 896 break; 897 case ATH9K_TX_QUEUE_CAB: 898 qnum = sc->beacon.cabq->axq_qnum; 899 break; 900 default: 901 qnum = -1; 902 } 903 return qnum; 904 } 905 906 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) 907 { 908 struct ath_txq *txq = NULL; 909 int qnum; 910 911 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 912 txq = &sc->tx.txq[qnum]; 913 914 spin_lock_bh(&txq->axq_lock); 915 916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 917 DPRINTF(sc, ATH_DBG_XMIT, 918 "TX queue: %d is full, depth: %d\n", 919 qnum, txq->axq_depth); 920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 921 txq->stopped = 1; 922 spin_unlock_bh(&txq->axq_lock); 923 return NULL; 924 } 925 926 spin_unlock_bh(&txq->axq_lock); 927 928 return txq; 929 } 930 931 int ath_txq_update(struct ath_softc *sc, int qnum, 932 struct ath9k_tx_queue_info *qinfo) 933 { 934 struct ath_hw *ah = sc->sc_ah; 935 int error = 0; 936 struct ath9k_tx_queue_info qi; 937 938 if (qnum == sc->beacon.beaconq) { 939 /* 940 * XXX: for beacon queue, we just save the parameter. 941 * It will be picked up by ath_beaconq_config when 942 * it's necessary. 943 */ 944 sc->beacon.beacon_qi = *qinfo; 945 return 0; 946 } 947 948 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); 949 950 ath9k_hw_get_txq_props(ah, qnum, &qi); 951 qi.tqi_aifs = qinfo->tqi_aifs; 952 qi.tqi_cwmin = qinfo->tqi_cwmin; 953 qi.tqi_cwmax = qinfo->tqi_cwmax; 954 qi.tqi_burstTime = qinfo->tqi_burstTime; 955 qi.tqi_readyTime = qinfo->tqi_readyTime; 956 957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 958 DPRINTF(sc, ATH_DBG_FATAL, 959 "Unable to update hardware queue %u!\n", qnum); 960 error = -EIO; 961 } else { 962 ath9k_hw_resettxqueue(ah, qnum); 963 } 964 965 return error; 966 } 967 968 int ath_cabq_update(struct ath_softc *sc) 969 { 970 struct ath9k_tx_queue_info qi; 971 int qnum = sc->beacon.cabq->axq_qnum; 972 973 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 974 /* 975 * Ensure the readytime % is within the bounds. 976 */ 977 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) 978 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; 979 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) 980 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; 981 982 qi.tqi_readyTime = (sc->beacon_interval * 983 sc->config.cabqReadytime) / 100; 984 ath_txq_update(sc, qnum, &qi); 985 986 return 0; 987 } 988 989 /* 990 * Drain a given TX queue (could be Beacon or Data) 991 * 992 * This assumes output has been stopped and 993 * we do not need to block ath_tx_tasklet. 994 */ 995 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) 996 { 997 struct ath_buf *bf, *lastbf; 998 struct list_head bf_head; 999 1000 INIT_LIST_HEAD(&bf_head); 1001 1002 for (;;) { 1003 spin_lock_bh(&txq->axq_lock); 1004 1005 if (list_empty(&txq->axq_q)) { 1006 txq->axq_link = NULL; 1007 txq->axq_linkbuf = NULL; 1008 spin_unlock_bh(&txq->axq_lock); 1009 break; 1010 } 1011 1012 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 1013 1014 if (bf->bf_stale) { 1015 list_del(&bf->list); 1016 spin_unlock_bh(&txq->axq_lock); 1017 1018 spin_lock_bh(&sc->tx.txbuflock); 1019 list_add_tail(&bf->list, &sc->tx.txbuf); 1020 spin_unlock_bh(&sc->tx.txbuflock); 1021 continue; 1022 } 1023 1024 lastbf = bf->bf_lastbf; 1025 if (!retry_tx) 1026 lastbf->bf_desc->ds_txstat.ts_flags = 1027 ATH9K_TX_SW_ABORTED; 1028 1029 /* remove ath_buf's of the same mpdu from txq */ 1030 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); 1031 txq->axq_depth--; 1032 1033 spin_unlock_bh(&txq->axq_lock); 1034 1035 if (bf_isampdu(bf)) 1036 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); 1037 else 1038 ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); 1039 } 1040 1041 spin_lock_bh(&txq->axq_lock); 1042 txq->axq_tx_inprogress = false; 1043 spin_unlock_bh(&txq->axq_lock); 1044 1045 /* flush any pending frames if aggregation is enabled */ 1046 if (sc->sc_flags & SC_OP_TXAGGR) { 1047 if (!retry_tx) { 1048 spin_lock_bh(&txq->axq_lock); 1049 ath_txq_drain_pending_buffers(sc, txq); 1050 spin_unlock_bh(&txq->axq_lock); 1051 } 1052 } 1053 } 1054 1055 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1056 { 1057 struct ath_hw *ah = sc->sc_ah; 1058 struct ath_txq *txq; 1059 int i, npend = 0; 1060 1061 if (sc->sc_flags & SC_OP_INVALID) 1062 return; 1063 1064 /* Stop beacon queue */ 1065 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1066 1067 /* Stop data queues */ 1068 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1069 if (ATH_TXQ_SETUP(sc, i)) { 1070 txq = &sc->tx.txq[i]; 1071 ath9k_hw_stoptxdma(ah, txq->axq_qnum); 1072 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); 1073 } 1074 } 1075 1076 if (npend) { 1077 int r; 1078 1079 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1080 1081 spin_lock_bh(&sc->sc_resetlock); 1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1083 if (r) 1084 DPRINTF(sc, ATH_DBG_FATAL, 1085 "Unable to reset hardware; reset status %d\n", 1086 r); 1087 spin_unlock_bh(&sc->sc_resetlock); 1088 } 1089 1090 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1091 if (ATH_TXQ_SETUP(sc, i)) 1092 ath_draintxq(sc, &sc->tx.txq[i], retry_tx); 1093 } 1094 } 1095 1096 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1097 { 1098 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1099 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1100 } 1101 1102 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1103 { 1104 struct ath_atx_ac *ac; 1105 struct ath_atx_tid *tid; 1106 1107 if (list_empty(&txq->axq_acq)) 1108 return; 1109 1110 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); 1111 list_del(&ac->list); 1112 ac->sched = false; 1113 1114 do { 1115 if (list_empty(&ac->tid_q)) 1116 return; 1117 1118 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); 1119 list_del(&tid->list); 1120 tid->sched = false; 1121 1122 if (tid->paused) 1123 continue; 1124 1125 ath_tx_sched_aggr(sc, txq, tid); 1126 1127 /* 1128 * add tid to round-robin queue if more frames 1129 * are pending for the tid 1130 */ 1131 if (!list_empty(&tid->buf_q)) 1132 ath_tx_queue_tid(txq, tid); 1133 1134 break; 1135 } while (!list_empty(&ac->tid_q)); 1136 1137 if (!list_empty(&ac->tid_q)) { 1138 if (!ac->sched) { 1139 ac->sched = true; 1140 list_add_tail(&ac->list, &txq->axq_acq); 1141 } 1142 } 1143 } 1144 1145 int ath_tx_setup(struct ath_softc *sc, int haltype) 1146 { 1147 struct ath_txq *txq; 1148 1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1150 DPRINTF(sc, ATH_DBG_FATAL, 1151 "HAL AC %u out of range, max %zu!\n", 1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1153 return 0; 1154 } 1155 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); 1156 if (txq != NULL) { 1157 sc->tx.hwq_map[haltype] = txq->axq_qnum; 1158 return 1; 1159 } else 1160 return 0; 1161 } 1162 1163 /***********/ 1164 /* TX, DMA */ 1165 /***********/ 1166 1167 /* 1168 * Insert a chain of ath_buf (descriptors) on a txq and 1169 * assume the descriptors are already chained together by caller. 1170 */ 1171 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1172 struct list_head *head) 1173 { 1174 struct ath_hw *ah = sc->sc_ah; 1175 struct ath_buf *bf; 1176 1177 /* 1178 * Insert the frame on the outbound list and 1179 * pass it on to the hardware. 1180 */ 1181 1182 if (list_empty(head)) 1183 return; 1184 1185 bf = list_first_entry(head, struct ath_buf, list); 1186 1187 list_splice_tail_init(head, &txq->axq_q); 1188 txq->axq_depth++; 1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); 1190 1191 DPRINTF(sc, ATH_DBG_QUEUE, 1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1193 1194 if (txq->axq_link == NULL) { 1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1196 DPRINTF(sc, ATH_DBG_XMIT, 1197 "TXDP[%u] = %llx (%p)\n", 1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1199 } else { 1200 *txq->axq_link = bf->bf_daddr; 1201 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1202 txq->axq_qnum, txq->axq_link, 1203 ito64(bf->bf_daddr), bf->bf_desc); 1204 } 1205 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1206 ath9k_hw_txstart(ah, txq->axq_qnum); 1207 } 1208 1209 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 1210 { 1211 struct ath_buf *bf = NULL; 1212 1213 spin_lock_bh(&sc->tx.txbuflock); 1214 1215 if (unlikely(list_empty(&sc->tx.txbuf))) { 1216 spin_unlock_bh(&sc->tx.txbuflock); 1217 return NULL; 1218 } 1219 1220 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 1221 list_del(&bf->list); 1222 1223 spin_unlock_bh(&sc->tx.txbuflock); 1224 1225 return bf; 1226 } 1227 1228 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1229 struct list_head *bf_head, 1230 struct ath_tx_control *txctl) 1231 { 1232 struct ath_buf *bf; 1233 1234 bf = list_first_entry(bf_head, struct ath_buf, list); 1235 bf->bf_state.bf_type |= BUF_AMPDU; 1236 TX_STAT_INC(txctl->txq->axq_qnum, a_queued); 1237 1238 /* 1239 * Do not queue to h/w when any of the following conditions is true: 1240 * - there are pending frames in software queue 1241 * - the TID is currently paused for ADDBA/BAR request 1242 * - seqno is not within block-ack window 1243 * - h/w queue depth exceeds low water mark 1244 */ 1245 if (!list_empty(&tid->buf_q) || tid->paused || 1246 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || 1247 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { 1248 /* 1249 * Add this frame to software queue for scheduling later 1250 * for aggregation. 1251 */ 1252 list_move_tail(&bf->list, &tid->buf_q); 1253 ath_tx_queue_tid(txctl->txq, tid); 1254 return; 1255 } 1256 1257 /* Add sub-frame to BAW */ 1258 ath_tx_addto_baw(sc, tid, bf); 1259 1260 /* Queue to h/w without aggregation */ 1261 bf->bf_nframes = 1; 1262 bf->bf_lastbf = bf; 1263 ath_buf_set_rate(sc, bf); 1264 ath_tx_txqaddbuf(sc, txctl->txq, bf_head); 1265 } 1266 1267 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 1268 struct ath_atx_tid *tid, 1269 struct list_head *bf_head) 1270 { 1271 struct ath_buf *bf; 1272 1273 bf = list_first_entry(bf_head, struct ath_buf, list); 1274 bf->bf_state.bf_type &= ~BUF_AMPDU; 1275 1276 /* update starting sequence number for subsequent ADDBA request */ 1277 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 1278 1279 bf->bf_nframes = 1; 1280 bf->bf_lastbf = bf; 1281 ath_buf_set_rate(sc, bf); 1282 ath_tx_txqaddbuf(sc, txq, bf_head); 1283 TX_STAT_INC(txq->axq_qnum, queued); 1284 } 1285 1286 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1287 struct list_head *bf_head) 1288 { 1289 struct ath_buf *bf; 1290 1291 bf = list_first_entry(bf_head, struct ath_buf, list); 1292 1293 bf->bf_lastbf = bf; 1294 bf->bf_nframes = 1; 1295 ath_buf_set_rate(sc, bf); 1296 ath_tx_txqaddbuf(sc, txq, bf_head); 1297 TX_STAT_INC(txq->axq_qnum, queued); 1298 } 1299 1300 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1301 { 1302 struct ieee80211_hdr *hdr; 1303 enum ath9k_pkt_type htype; 1304 __le16 fc; 1305 1306 hdr = (struct ieee80211_hdr *)skb->data; 1307 fc = hdr->frame_control; 1308 1309 if (ieee80211_is_beacon(fc)) 1310 htype = ATH9K_PKT_TYPE_BEACON; 1311 else if (ieee80211_is_probe_resp(fc)) 1312 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1313 else if (ieee80211_is_atim(fc)) 1314 htype = ATH9K_PKT_TYPE_ATIM; 1315 else if (ieee80211_is_pspoll(fc)) 1316 htype = ATH9K_PKT_TYPE_PSPOLL; 1317 else 1318 htype = ATH9K_PKT_TYPE_NORMAL; 1319 1320 return htype; 1321 } 1322 1323 static bool is_pae(struct sk_buff *skb) 1324 { 1325 struct ieee80211_hdr *hdr; 1326 __le16 fc; 1327 1328 hdr = (struct ieee80211_hdr *)skb->data; 1329 fc = hdr->frame_control; 1330 1331 if (ieee80211_is_data(fc)) { 1332 if (ieee80211_is_nullfunc(fc) || 1333 /* Port Access Entity (IEEE 802.1X) */ 1334 (skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1335 return true; 1336 } 1337 } 1338 1339 return false; 1340 } 1341 1342 static int get_hw_crypto_keytype(struct sk_buff *skb) 1343 { 1344 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1345 1346 if (tx_info->control.hw_key) { 1347 if (tx_info->control.hw_key->alg == ALG_WEP) 1348 return ATH9K_KEY_TYPE_WEP; 1349 else if (tx_info->control.hw_key->alg == ALG_TKIP) 1350 return ATH9K_KEY_TYPE_TKIP; 1351 else if (tx_info->control.hw_key->alg == ALG_CCMP) 1352 return ATH9K_KEY_TYPE_AES; 1353 } 1354 1355 return ATH9K_KEY_TYPE_CLEAR; 1356 } 1357 1358 static void assign_aggr_tid_seqno(struct sk_buff *skb, 1359 struct ath_buf *bf) 1360 { 1361 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1362 struct ieee80211_hdr *hdr; 1363 struct ath_node *an; 1364 struct ath_atx_tid *tid; 1365 __le16 fc; 1366 u8 *qc; 1367 1368 if (!tx_info->control.sta) 1369 return; 1370 1371 an = (struct ath_node *)tx_info->control.sta->drv_priv; 1372 hdr = (struct ieee80211_hdr *)skb->data; 1373 fc = hdr->frame_control; 1374 1375 if (ieee80211_is_data_qos(fc)) { 1376 qc = ieee80211_get_qos_ctl(hdr); 1377 bf->bf_tidno = qc[0] & 0xf; 1378 } 1379 1380 /* 1381 * For HT capable stations, we save tidno for later use. 1382 * We also override seqno set by upper layer with the one 1383 * in tx aggregation state. 1384 * 1385 * If fragmentation is on, the sequence number is 1386 * not overridden, since it has been 1387 * incremented by the fragmentation routine. 1388 * 1389 * FIXME: check if the fragmentation threshold exceeds 1390 * IEEE80211 max. 1391 */ 1392 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1393 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << 1394 IEEE80211_SEQ_SEQ_SHIFT); 1395 bf->bf_seqno = tid->seq_next; 1396 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1397 } 1398 1399 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, 1400 struct ath_txq *txq) 1401 { 1402 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1403 int flags = 0; 1404 1405 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ 1406 flags |= ATH9K_TXDESC_INTREQ; 1407 1408 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1409 flags |= ATH9K_TXDESC_NOACK; 1410 1411 return flags; 1412 } 1413 1414 /* 1415 * rix - rate index 1416 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1417 * width - 0 for 20 MHz, 1 for 40 MHz 1418 * half_gi - to use 4us v/s 3.6 us for symbol time 1419 */ 1420 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 1421 int width, int half_gi, bool shortPreamble) 1422 { 1423 const struct ath_rate_table *rate_table = sc->cur_rate_table; 1424 u32 nbits, nsymbits, duration, nsymbols; 1425 u8 rc; 1426 int streams, pktlen; 1427 1428 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; 1429 rc = rate_table->info[rix].ratecode; 1430 1431 /* for legacy rates, use old function to compute packet duration */ 1432 if (!IS_HT_RATE(rc)) 1433 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, 1434 rix, shortPreamble); 1435 1436 /* find number of symbols: PLCP + data */ 1437 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1438 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 1439 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1440 1441 if (!half_gi) 1442 duration = SYMBOL_TIME(nsymbols); 1443 else 1444 duration = SYMBOL_TIME_HALFGI(nsymbols); 1445 1446 /* addup duration for legacy/ht training and signal fields */ 1447 streams = HT_RC_2_STREAMS(rc); 1448 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1449 1450 return duration; 1451 } 1452 1453 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1454 { 1455 const struct ath_rate_table *rt = sc->cur_rate_table; 1456 struct ath9k_11n_rate_series series[4]; 1457 struct sk_buff *skb; 1458 struct ieee80211_tx_info *tx_info; 1459 struct ieee80211_tx_rate *rates; 1460 struct ieee80211_hdr *hdr; 1461 int i, flags = 0; 1462 u8 rix = 0, ctsrate = 0; 1463 bool is_pspoll; 1464 1465 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 1466 1467 skb = bf->bf_mpdu; 1468 tx_info = IEEE80211_SKB_CB(skb); 1469 rates = tx_info->control.rates; 1470 hdr = (struct ieee80211_hdr *)skb->data; 1471 is_pspoll = ieee80211_is_pspoll(hdr->frame_control); 1472 1473 /* 1474 * We check if Short Preamble is needed for the CTS rate by 1475 * checking the BSS's global flag. 1476 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1477 */ 1478 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 1479 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | 1480 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; 1481 else 1482 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; 1483 1484 /* 1485 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. 1486 * Check the first rate in the series to decide whether RTS/CTS 1487 * or CTS-to-self has to be used. 1488 */ 1489 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) 1490 flags = ATH9K_TXDESC_CTSENA; 1491 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 1492 flags = ATH9K_TXDESC_RTSENA; 1493 1494 /* FIXME: Handle aggregation protection */ 1495 if (sc->config.ath_aggr_prot && 1496 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { 1497 flags = ATH9K_TXDESC_RTSENA; 1498 } 1499 1500 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1501 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) 1502 flags &= ~(ATH9K_TXDESC_RTSENA); 1503 1504 for (i = 0; i < 4; i++) { 1505 if (!rates[i].count || (rates[i].idx < 0)) 1506 continue; 1507 1508 rix = rates[i].idx; 1509 series[i].Tries = rates[i].count; 1510 series[i].ChSel = sc->tx_chainmask; 1511 1512 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1513 series[i].Rate = rt->info[rix].ratecode | 1514 rt->info[rix].short_preamble; 1515 else 1516 series[i].Rate = rt->info[rix].ratecode; 1517 1518 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) 1519 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1520 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1521 series[i].RateFlags |= ATH9K_RATESERIES_2040; 1522 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1523 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1524 1525 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1526 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, 1527 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), 1528 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); 1529 } 1530 1531 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1532 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 1533 bf->bf_lastbf->bf_desc, 1534 !is_pspoll, ctsrate, 1535 0, series, 4, flags); 1536 1537 if (sc->config.ath_aggr_prot && flags) 1538 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); 1539 } 1540 1541 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, 1542 struct sk_buff *skb, 1543 struct ath_tx_control *txctl) 1544 { 1545 struct ath_wiphy *aphy = hw->priv; 1546 struct ath_softc *sc = aphy->sc; 1547 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1549 struct ath_tx_info_priv *tx_info_priv; 1550 int hdrlen; 1551 __le16 fc; 1552 1553 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); 1554 if (unlikely(!tx_info_priv)) 1555 return -ENOMEM; 1556 tx_info->rate_driver_data[0] = tx_info_priv; 1557 tx_info_priv->aphy = aphy; 1558 tx_info_priv->frame_type = txctl->frame_type; 1559 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1560 fc = hdr->frame_control; 1561 1562 ATH_TXBUF_RESET(bf); 1563 1564 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); 1565 1566 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) 1567 bf->bf_state.bf_type |= BUF_HT; 1568 1569 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1570 1571 bf->bf_keytype = get_hw_crypto_keytype(skb); 1572 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { 1573 bf->bf_frmlen += tx_info->control.hw_key->icv_len; 1574 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; 1575 } else { 1576 bf->bf_keyix = ATH9K_TXKEYIX_INVALID; 1577 } 1578 1579 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) 1580 assign_aggr_tid_seqno(skb, bf); 1581 1582 bf->bf_mpdu = skb; 1583 1584 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, 1585 skb->len, DMA_TO_DEVICE); 1586 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { 1587 bf->bf_mpdu = NULL; 1588 kfree(tx_info_priv); 1589 tx_info->rate_driver_data[0] = NULL; 1590 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n"); 1591 return -ENOMEM; 1592 } 1593 1594 bf->bf_buf_addr = bf->bf_dmacontext; 1595 return 0; 1596 } 1597 1598 /* FIXME: tx power */ 1599 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, 1600 struct ath_tx_control *txctl) 1601 { 1602 struct sk_buff *skb = bf->bf_mpdu; 1603 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1604 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1605 struct ath_node *an = NULL; 1606 struct list_head bf_head; 1607 struct ath_desc *ds; 1608 struct ath_atx_tid *tid; 1609 struct ath_hw *ah = sc->sc_ah; 1610 int frm_type; 1611 __le16 fc; 1612 1613 frm_type = get_hw_packet_type(skb); 1614 fc = hdr->frame_control; 1615 1616 INIT_LIST_HEAD(&bf_head); 1617 list_add_tail(&bf->list, &bf_head); 1618 1619 ds = bf->bf_desc; 1620 ds->ds_link = 0; 1621 ds->ds_data = bf->bf_buf_addr; 1622 1623 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, 1624 bf->bf_keyix, bf->bf_keytype, bf->bf_flags); 1625 1626 ath9k_hw_filltxdesc(ah, ds, 1627 skb->len, /* segment length */ 1628 true, /* first segment */ 1629 true, /* last segment */ 1630 ds); /* first descriptor */ 1631 1632 spin_lock_bh(&txctl->txq->axq_lock); 1633 1634 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && 1635 tx_info->control.sta) { 1636 an = (struct ath_node *)tx_info->control.sta->drv_priv; 1637 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1638 1639 if (!ieee80211_is_data_qos(fc)) { 1640 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1641 goto tx_done; 1642 } 1643 1644 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1645 /* 1646 * Try aggregation if it's a unicast data frame 1647 * and the destination is HT capable. 1648 */ 1649 ath_tx_send_ampdu(sc, tid, &bf_head, txctl); 1650 } else { 1651 /* 1652 * Send this frame as regular when ADDBA 1653 * exchange is neither complete nor pending. 1654 */ 1655 ath_tx_send_ht_normal(sc, txctl->txq, 1656 tid, &bf_head); 1657 } 1658 } else { 1659 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1660 } 1661 1662 tx_done: 1663 spin_unlock_bh(&txctl->txq->axq_lock); 1664 } 1665 1666 /* Upon failure caller should free skb */ 1667 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1668 struct ath_tx_control *txctl) 1669 { 1670 struct ath_wiphy *aphy = hw->priv; 1671 struct ath_softc *sc = aphy->sc; 1672 struct ath_buf *bf; 1673 int r; 1674 1675 bf = ath_tx_get_buffer(sc); 1676 if (!bf) { 1677 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1678 return -1; 1679 } 1680 1681 r = ath_tx_setup_buffer(hw, bf, skb, txctl); 1682 if (unlikely(r)) { 1683 struct ath_txq *txq = txctl->txq; 1684 1685 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1686 1687 /* upon ath_tx_processq() this TX queue will be resumed, we 1688 * guarantee this will happen by knowing beforehand that 1689 * we will at least have to run TX completionon one buffer 1690 * on the queue */ 1691 spin_lock_bh(&txq->axq_lock); 1692 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { 1693 ieee80211_stop_queue(sc->hw, 1694 skb_get_queue_mapping(skb)); 1695 txq->stopped = 1; 1696 } 1697 spin_unlock_bh(&txq->axq_lock); 1698 1699 spin_lock_bh(&sc->tx.txbuflock); 1700 list_add_tail(&bf->list, &sc->tx.txbuf); 1701 spin_unlock_bh(&sc->tx.txbuflock); 1702 1703 return r; 1704 } 1705 1706 ath_tx_start_dma(sc, bf, txctl); 1707 1708 return 0; 1709 } 1710 1711 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) 1712 { 1713 struct ath_wiphy *aphy = hw->priv; 1714 struct ath_softc *sc = aphy->sc; 1715 int hdrlen, padsize; 1716 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1717 struct ath_tx_control txctl; 1718 1719 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1720 1721 /* 1722 * As a temporary workaround, assign seq# here; this will likely need 1723 * to be cleaned up to work better with Beacon transmission and virtual 1724 * BSSes. 1725 */ 1726 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1728 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1729 sc->tx.seq_no += 0x10; 1730 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1731 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1732 } 1733 1734 /* Add the padding after the header if this is not already done */ 1735 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1736 if (hdrlen & 3) { 1737 padsize = hdrlen % 4; 1738 if (skb_headroom(skb) < padsize) { 1739 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1740 dev_kfree_skb_any(skb); 1741 return; 1742 } 1743 skb_push(skb, padsize); 1744 memmove(skb->data, skb->data + padsize, hdrlen); 1745 } 1746 1747 txctl.txq = sc->beacon.cabq; 1748 1749 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1750 1751 if (ath_tx_start(hw, skb, &txctl) != 0) { 1752 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1753 goto exit; 1754 } 1755 1756 return; 1757 exit: 1758 dev_kfree_skb_any(skb); 1759 } 1760 1761 /*****************/ 1762 /* TX Completion */ 1763 /*****************/ 1764 1765 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1766 int tx_flags) 1767 { 1768 struct ieee80211_hw *hw = sc->hw; 1769 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1770 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1771 int hdrlen, padsize; 1772 int frame_type = ATH9K_NOT_INTERNAL; 1773 1774 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1775 1776 if (tx_info_priv) { 1777 hw = tx_info_priv->aphy->hw; 1778 frame_type = tx_info_priv->frame_type; 1779 } 1780 1781 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || 1782 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { 1783 kfree(tx_info_priv); 1784 tx_info->rate_driver_data[0] = NULL; 1785 } 1786 1787 if (tx_flags & ATH_TX_BAR) 1788 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1789 1790 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { 1791 /* Frame was ACKed */ 1792 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1793 } 1794 1795 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1796 padsize = hdrlen & 3; 1797 if (padsize && hdrlen >= 24) { 1798 /* 1799 * Remove MAC header padding before giving the frame back to 1800 * mac80211. 1801 */ 1802 memmove(skb->data + padsize, skb->data, hdrlen); 1803 skb_pull(skb, padsize); 1804 } 1805 1806 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1807 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1808 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1809 "received TX status (0x%x)\n", 1810 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1811 SC_OP_WAIT_FOR_CAB | 1812 SC_OP_WAIT_FOR_PSPOLL_DATA | 1813 SC_OP_WAIT_FOR_TX_ACK)); 1814 } 1815 1816 if (frame_type == ATH9K_NOT_INTERNAL) 1817 ieee80211_tx_status(hw, skb); 1818 else 1819 ath9k_tx_status(hw, skb); 1820 } 1821 1822 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1823 struct ath_txq *txq, 1824 struct list_head *bf_q, 1825 int txok, int sendbar) 1826 { 1827 struct sk_buff *skb = bf->bf_mpdu; 1828 unsigned long flags; 1829 int tx_flags = 0; 1830 1831 if (sendbar) 1832 tx_flags = ATH_TX_BAR; 1833 1834 if (!txok) { 1835 tx_flags |= ATH_TX_ERROR; 1836 1837 if (bf_isxretried(bf)) 1838 tx_flags |= ATH_TX_XRETRY; 1839 } 1840 1841 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); 1842 ath_tx_complete(sc, skb, tx_flags); 1843 ath_debug_stat_tx(sc, txq, bf); 1844 1845 /* 1846 * Return the list of ath_buf of this mpdu to free queue 1847 */ 1848 spin_lock_irqsave(&sc->tx.txbuflock, flags); 1849 list_splice_tail_init(bf_q, &sc->tx.txbuf); 1850 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 1851 } 1852 1853 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, 1854 int txok) 1855 { 1856 struct ath_buf *bf_last = bf->bf_lastbf; 1857 struct ath_desc *ds = bf_last->bf_desc; 1858 u16 seq_st = 0; 1859 u32 ba[WME_BA_BMP_SIZE >> 5]; 1860 int ba_index; 1861 int nbad = 0; 1862 int isaggr = 0; 1863 1864 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) 1865 return 0; 1866 1867 isaggr = bf_isaggr(bf); 1868 if (isaggr) { 1869 seq_st = ATH_DS_BA_SEQ(ds); 1870 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); 1871 } 1872 1873 while (bf) { 1874 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); 1875 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 1876 nbad++; 1877 1878 bf = bf->bf_next; 1879 } 1880 1881 return nbad; 1882 } 1883 1884 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 1885 int nbad, int txok, bool update_rc) 1886 { 1887 struct sk_buff *skb = bf->bf_mpdu; 1888 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1889 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1890 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1891 struct ieee80211_hw *hw = tx_info_priv->aphy->hw; 1892 u8 i, tx_rateindex; 1893 1894 if (txok) 1895 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; 1896 1897 tx_rateindex = ds->ds_txstat.ts_rateindex; 1898 WARN_ON(tx_rateindex >= hw->max_rates); 1899 1900 tx_info_priv->update_rc = update_rc; 1901 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) 1902 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1903 1904 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && 1905 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1906 if (ieee80211_is_data(hdr->frame_control)) { 1907 memcpy(&tx_info_priv->tx, &ds->ds_txstat, 1908 sizeof(tx_info_priv->tx)); 1909 tx_info_priv->n_frames = bf->bf_nframes; 1910 tx_info_priv->n_bad_frames = nbad; 1911 } 1912 } 1913 1914 for (i = tx_rateindex + 1; i < hw->max_rates; i++) 1915 tx_info->status.rates[i].count = 0; 1916 1917 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; 1918 } 1919 1920 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) 1921 { 1922 int qnum; 1923 1924 spin_lock_bh(&txq->axq_lock); 1925 if (txq->stopped && 1926 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { 1927 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); 1928 if (qnum != -1) { 1929 ieee80211_wake_queue(sc->hw, qnum); 1930 txq->stopped = 0; 1931 } 1932 } 1933 spin_unlock_bh(&txq->axq_lock); 1934 } 1935 1936 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1937 { 1938 struct ath_hw *ah = sc->sc_ah; 1939 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1940 struct list_head bf_head; 1941 struct ath_desc *ds; 1942 int txok; 1943 int status; 1944 1945 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1946 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1947 txq->axq_link); 1948 1949 for (;;) { 1950 spin_lock_bh(&txq->axq_lock); 1951 if (list_empty(&txq->axq_q)) { 1952 txq->axq_link = NULL; 1953 txq->axq_linkbuf = NULL; 1954 spin_unlock_bh(&txq->axq_lock); 1955 break; 1956 } 1957 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 1958 1959 /* 1960 * There is a race condition that a BH gets scheduled 1961 * after sw writes TxE and before hw re-load the last 1962 * descriptor to get the newly chained one. 1963 * Software must keep the last DONE descriptor as a 1964 * holding descriptor - software does so by marking 1965 * it with the STALE flag. 1966 */ 1967 bf_held = NULL; 1968 if (bf->bf_stale) { 1969 bf_held = bf; 1970 if (list_is_last(&bf_held->list, &txq->axq_q)) { 1971 spin_unlock_bh(&txq->axq_lock); 1972 break; 1973 } else { 1974 bf = list_entry(bf_held->list.next, 1975 struct ath_buf, list); 1976 } 1977 } 1978 1979 lastbf = bf->bf_lastbf; 1980 ds = lastbf->bf_desc; 1981 1982 status = ath9k_hw_txprocdesc(ah, ds); 1983 if (status == -EINPROGRESS) { 1984 spin_unlock_bh(&txq->axq_lock); 1985 break; 1986 } 1987 if (bf->bf_desc == txq->axq_lastdsWithCTS) 1988 txq->axq_lastdsWithCTS = NULL; 1989 if (ds == txq->axq_gatingds) 1990 txq->axq_gatingds = NULL; 1991 1992 /* 1993 * Remove ath_buf's of the same transmit unit from txq, 1994 * however leave the last descriptor back as the holding 1995 * descriptor for hw. 1996 */ 1997 lastbf->bf_stale = true; 1998 INIT_LIST_HEAD(&bf_head); 1999 if (!list_is_singular(&lastbf->list)) 2000 list_cut_position(&bf_head, 2001 &txq->axq_q, lastbf->list.prev); 2002 2003 txq->axq_depth--; 2004 if (bf_isaggr(bf)) 2005 txq->axq_aggr_depth--; 2006 2007 txok = (ds->ds_txstat.ts_status == 0); 2008 txq->axq_tx_inprogress = false; 2009 spin_unlock_bh(&txq->axq_lock); 2010 2011 if (bf_held) { 2012 spin_lock_bh(&sc->tx.txbuflock); 2013 list_move_tail(&bf_held->list, &sc->tx.txbuf); 2014 spin_unlock_bh(&sc->tx.txbuflock); 2015 } 2016 2017 if (!bf_isampdu(bf)) { 2018 /* 2019 * This frame is sent out as a single frame. 2020 * Use hardware retry status for this frame. 2021 */ 2022 bf->bf_retries = ds->ds_txstat.ts_longretry; 2023 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) 2024 bf->bf_state.bf_type |= BUF_XRETRY; 2025 ath_tx_rc_status(bf, ds, 0, txok, true); 2026 } 2027 2028 if (bf_isampdu(bf)) 2029 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); 2030 else 2031 ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0); 2032 2033 ath_wake_mac80211_queue(sc, txq); 2034 2035 spin_lock_bh(&txq->axq_lock); 2036 if (sc->sc_flags & SC_OP_TXAGGR) 2037 ath_txq_schedule(sc, txq); 2038 spin_unlock_bh(&txq->axq_lock); 2039 } 2040 } 2041 2042 static void ath_tx_complete_poll_work(struct work_struct *work) 2043 { 2044 struct ath_softc *sc = container_of(work, struct ath_softc, 2045 tx_complete_work.work); 2046 struct ath_txq *txq; 2047 int i; 2048 bool needreset = false; 2049 2050 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 2051 if (ATH_TXQ_SETUP(sc, i)) { 2052 txq = &sc->tx.txq[i]; 2053 spin_lock_bh(&txq->axq_lock); 2054 if (txq->axq_depth) { 2055 if (txq->axq_tx_inprogress) { 2056 needreset = true; 2057 spin_unlock_bh(&txq->axq_lock); 2058 break; 2059 } else { 2060 txq->axq_tx_inprogress = true; 2061 } 2062 } 2063 spin_unlock_bh(&txq->axq_lock); 2064 } 2065 2066 if (needreset) { 2067 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2068 ath_reset(sc, false); 2069 } 2070 2071 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2072 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); 2073 } 2074 2075 2076 2077 void ath_tx_tasklet(struct ath_softc *sc) 2078 { 2079 int i; 2080 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); 2081 2082 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); 2083 2084 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2085 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2086 ath_tx_processq(sc, &sc->tx.txq[i]); 2087 } 2088 } 2089 2090 /*****************/ 2091 /* Init, Cleanup */ 2092 /*****************/ 2093 2094 int ath_tx_init(struct ath_softc *sc, int nbufs) 2095 { 2096 int error = 0; 2097 2098 spin_lock_init(&sc->tx.txbuflock); 2099 2100 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2101 "tx", nbufs, 1); 2102 if (error != 0) { 2103 DPRINTF(sc, ATH_DBG_FATAL, 2104 "Failed to allocate tx descriptors: %d\n", error); 2105 goto err; 2106 } 2107 2108 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2109 "beacon", ATH_BCBUF, 1); 2110 if (error != 0) { 2111 DPRINTF(sc, ATH_DBG_FATAL, 2112 "Failed to allocate beacon descriptors: %d\n", error); 2113 goto err; 2114 } 2115 2116 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2117 2118 err: 2119 if (error != 0) 2120 ath_tx_cleanup(sc); 2121 2122 return error; 2123 } 2124 2125 void ath_tx_cleanup(struct ath_softc *sc) 2126 { 2127 if (sc->beacon.bdma.dd_desc_len != 0) 2128 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); 2129 2130 if (sc->tx.txdma.dd_desc_len != 0) 2131 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2132 } 2133 2134 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2135 { 2136 struct ath_atx_tid *tid; 2137 struct ath_atx_ac *ac; 2138 int tidno, acno; 2139 2140 for (tidno = 0, tid = &an->tid[tidno]; 2141 tidno < WME_NUM_TID; 2142 tidno++, tid++) { 2143 tid->an = an; 2144 tid->tidno = tidno; 2145 tid->seq_start = tid->seq_next = 0; 2146 tid->baw_size = WME_MAX_BA; 2147 tid->baw_head = tid->baw_tail = 0; 2148 tid->sched = false; 2149 tid->paused = false; 2150 tid->state &= ~AGGR_CLEANUP; 2151 INIT_LIST_HEAD(&tid->buf_q); 2152 acno = TID_TO_WME_AC(tidno); 2153 tid->ac = &an->ac[acno]; 2154 tid->state &= ~AGGR_ADDBA_COMPLETE; 2155 tid->state &= ~AGGR_ADDBA_PROGRESS; 2156 } 2157 2158 for (acno = 0, ac = &an->ac[acno]; 2159 acno < WME_NUM_AC; acno++, ac++) { 2160 ac->sched = false; 2161 INIT_LIST_HEAD(&ac->tid_q); 2162 2163 switch (acno) { 2164 case WME_AC_BE: 2165 ac->qnum = ath_tx_get_qnum(sc, 2166 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); 2167 break; 2168 case WME_AC_BK: 2169 ac->qnum = ath_tx_get_qnum(sc, 2170 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); 2171 break; 2172 case WME_AC_VI: 2173 ac->qnum = ath_tx_get_qnum(sc, 2174 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); 2175 break; 2176 case WME_AC_VO: 2177 ac->qnum = ath_tx_get_qnum(sc, 2178 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); 2179 break; 2180 } 2181 } 2182 } 2183 2184 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2185 { 2186 int i; 2187 struct ath_atx_ac *ac, *ac_tmp; 2188 struct ath_atx_tid *tid, *tid_tmp; 2189 struct ath_txq *txq; 2190 2191 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2192 if (ATH_TXQ_SETUP(sc, i)) { 2193 txq = &sc->tx.txq[i]; 2194 2195 spin_lock(&txq->axq_lock); 2196 2197 list_for_each_entry_safe(ac, 2198 ac_tmp, &txq->axq_acq, list) { 2199 tid = list_first_entry(&ac->tid_q, 2200 struct ath_atx_tid, list); 2201 if (tid && tid->an != an) 2202 continue; 2203 list_del(&ac->list); 2204 ac->sched = false; 2205 2206 list_for_each_entry_safe(tid, 2207 tid_tmp, &ac->tid_q, list) { 2208 list_del(&tid->list); 2209 tid->sched = false; 2210 ath_tid_drain(sc, txq, tid); 2211 tid->state &= ~AGGR_ADDBA_COMPLETE; 2212 tid->state &= ~AGGR_CLEANUP; 2213 } 2214 } 2215 2216 spin_unlock(&txq->axq_lock); 2217 } 2218 } 2219 } 2220