1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38 static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48 }; 49 50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq, 54 struct ieee80211_sta *sta); 55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 56 struct ath_txq *txq, struct list_head *bf_q, 57 struct ieee80211_sta *sta, 58 struct ath_tx_status *ts, int txok); 59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 60 struct list_head *head, bool internal); 61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_tx_status *ts, int nframes, int nbad, 63 int txok); 64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 65 int seqno); 66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 67 struct ath_txq *txq, 68 struct ath_atx_tid *tid, 69 struct sk_buff *skb); 70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 71 struct ath_tx_control *txctl); 72 73 enum { 74 MCS_HT20, 75 MCS_HT20_SGI, 76 MCS_HT40, 77 MCS_HT40_SGI, 78 }; 79 80 /*********************/ 81 /* Aggregation logic */ 82 /*********************/ 83 84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 85 { 86 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 87 struct ieee80211_sta *sta = info->status.status_driver_data[0]; 88 89 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 90 ieee80211_tx_status(hw, skb); 91 return; 92 } 93 94 if (sta) 95 ieee80211_tx_status_noskb(hw, sta, info); 96 97 dev_kfree_skb(skb); 98 } 99 100 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 101 __releases(&txq->axq_lock) 102 { 103 struct ieee80211_hw *hw = sc->hw; 104 struct sk_buff_head q; 105 struct sk_buff *skb; 106 107 __skb_queue_head_init(&q); 108 skb_queue_splice_init(&txq->complete_q, &q); 109 spin_unlock_bh(&txq->axq_lock); 110 111 while ((skb = __skb_dequeue(&q))) 112 ath_tx_status(hw, skb); 113 } 114 115 void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 116 { 117 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 118 struct ath_chanctx *ctx = avp->chanctx; 119 struct ath_acq *acq; 120 struct list_head *tid_list; 121 u8 acno = TID_TO_WME_AC(tid->tidno); 122 123 if (!ctx || !list_empty(&tid->list)) 124 return; 125 126 127 acq = &ctx->acq[acno]; 128 if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) && 129 tid->an->airtime_deficit[acno] > 0) 130 tid_list = &acq->acq_new; 131 else 132 tid_list = &acq->acq_old; 133 134 list_add_tail(&tid->list, tid_list); 135 } 136 137 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 138 { 139 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 140 struct ath_chanctx *ctx = avp->chanctx; 141 struct ath_acq *acq; 142 143 if (!ctx || !list_empty(&tid->list)) 144 return; 145 146 acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; 147 spin_lock_bh(&acq->lock); 148 __ath_tx_queue_tid(sc, tid); 149 spin_unlock_bh(&acq->lock); 150 } 151 152 153 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue) 154 { 155 struct ath_softc *sc = hw->priv; 156 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 157 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv; 158 struct ath_txq *txq = tid->txq; 159 160 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n", 161 queue->sta ? queue->sta->addr : queue->vif->addr, 162 tid->tidno); 163 164 ath_txq_lock(sc, txq); 165 166 tid->has_queued = true; 167 ath_tx_queue_tid(sc, tid); 168 ath_txq_schedule(sc, txq); 169 170 ath_txq_unlock(sc, txq); 171 } 172 173 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 174 { 175 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 176 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 177 sizeof(tx_info->rate_driver_data)); 178 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 179 } 180 181 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 182 { 183 if (!tid->an->sta) 184 return; 185 186 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 187 seqno << IEEE80211_SEQ_SEQ_SHIFT); 188 } 189 190 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 191 struct ath_buf *bf) 192 { 193 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 194 ARRAY_SIZE(bf->rates)); 195 } 196 197 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 198 struct sk_buff *skb) 199 { 200 struct ath_frame_info *fi = get_frame_info(skb); 201 int q = fi->txq; 202 203 if (q < 0) 204 return; 205 206 txq = sc->tx.txq_map[q]; 207 if (WARN_ON(--txq->pending_frames < 0)) 208 txq->pending_frames = 0; 209 210 } 211 212 static struct ath_atx_tid * 213 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 214 { 215 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 216 return ATH_AN_2_TID(an, tidno); 217 } 218 219 static struct sk_buff * 220 ath_tid_pull(struct ath_atx_tid *tid) 221 { 222 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv); 223 struct ath_softc *sc = tid->an->sc; 224 struct ieee80211_hw *hw = sc->hw; 225 struct ath_tx_control txctl = { 226 .txq = tid->txq, 227 .sta = tid->an->sta, 228 }; 229 struct sk_buff *skb; 230 struct ath_frame_info *fi; 231 int q; 232 233 if (!tid->has_queued) 234 return NULL; 235 236 skb = ieee80211_tx_dequeue(hw, txq); 237 if (!skb) { 238 tid->has_queued = false; 239 return NULL; 240 } 241 242 if (ath_tx_prepare(hw, skb, &txctl)) { 243 ieee80211_free_txskb(hw, skb); 244 return NULL; 245 } 246 247 q = skb_get_queue_mapping(skb); 248 if (tid->txq == sc->tx.txq_map[q]) { 249 fi = get_frame_info(skb); 250 fi->txq = q; 251 ++tid->txq->pending_frames; 252 } 253 254 return skb; 255 } 256 257 258 static bool ath_tid_has_buffered(struct ath_atx_tid *tid) 259 { 260 return !skb_queue_empty(&tid->retry_q) || tid->has_queued; 261 } 262 263 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) 264 { 265 struct sk_buff *skb; 266 267 skb = __skb_dequeue(&tid->retry_q); 268 if (!skb) 269 skb = ath_tid_pull(tid); 270 271 return skb; 272 } 273 274 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 275 { 276 struct ath_txq *txq = tid->txq; 277 struct sk_buff *skb; 278 struct ath_buf *bf; 279 struct list_head bf_head; 280 struct ath_tx_status ts; 281 struct ath_frame_info *fi; 282 bool sendbar = false; 283 284 INIT_LIST_HEAD(&bf_head); 285 286 memset(&ts, 0, sizeof(ts)); 287 288 while ((skb = __skb_dequeue(&tid->retry_q))) { 289 fi = get_frame_info(skb); 290 bf = fi->bf; 291 if (!bf) { 292 ath_txq_skb_done(sc, txq, skb); 293 ieee80211_free_txskb(sc->hw, skb); 294 continue; 295 } 296 297 if (fi->baw_tracked) { 298 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 299 sendbar = true; 300 } 301 302 list_add_tail(&bf->list, &bf_head); 303 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 304 } 305 306 if (sendbar) { 307 ath_txq_unlock(sc, txq); 308 ath_send_bar(tid, tid->seq_start); 309 ath_txq_lock(sc, txq); 310 } 311 } 312 313 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 314 int seqno) 315 { 316 int index, cindex; 317 318 index = ATH_BA_INDEX(tid->seq_start, seqno); 319 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 320 321 __clear_bit(cindex, tid->tx_buf); 322 323 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 324 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 325 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 326 if (tid->bar_index >= 0) 327 tid->bar_index--; 328 } 329 } 330 331 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 332 struct ath_buf *bf) 333 { 334 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 335 u16 seqno = bf->bf_state.seqno; 336 int index, cindex; 337 338 index = ATH_BA_INDEX(tid->seq_start, seqno); 339 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 340 __set_bit(cindex, tid->tx_buf); 341 fi->baw_tracked = 1; 342 343 if (index >= ((tid->baw_tail - tid->baw_head) & 344 (ATH_TID_MAX_BUFS - 1))) { 345 tid->baw_tail = cindex; 346 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 347 } 348 } 349 350 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 351 struct ath_atx_tid *tid) 352 353 { 354 struct sk_buff *skb; 355 struct ath_buf *bf; 356 struct list_head bf_head; 357 struct ath_tx_status ts; 358 struct ath_frame_info *fi; 359 360 memset(&ts, 0, sizeof(ts)); 361 INIT_LIST_HEAD(&bf_head); 362 363 while ((skb = ath_tid_dequeue(tid))) { 364 fi = get_frame_info(skb); 365 bf = fi->bf; 366 367 if (!bf) { 368 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); 369 continue; 370 } 371 372 list_add_tail(&bf->list, &bf_head); 373 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 374 } 375 } 376 377 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 378 struct sk_buff *skb, int count) 379 { 380 struct ath_frame_info *fi = get_frame_info(skb); 381 struct ath_buf *bf = fi->bf; 382 struct ieee80211_hdr *hdr; 383 int prev = fi->retries; 384 385 TX_STAT_INC(txq->axq_qnum, a_retries); 386 fi->retries += count; 387 388 if (prev > 0) 389 return; 390 391 hdr = (struct ieee80211_hdr *)skb->data; 392 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 393 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 394 sizeof(*hdr), DMA_TO_DEVICE); 395 } 396 397 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 398 { 399 struct ath_buf *bf = NULL; 400 401 spin_lock_bh(&sc->tx.txbuflock); 402 403 if (unlikely(list_empty(&sc->tx.txbuf))) { 404 spin_unlock_bh(&sc->tx.txbuflock); 405 return NULL; 406 } 407 408 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 409 list_del(&bf->list); 410 411 spin_unlock_bh(&sc->tx.txbuflock); 412 413 return bf; 414 } 415 416 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 417 { 418 spin_lock_bh(&sc->tx.txbuflock); 419 list_add_tail(&bf->list, &sc->tx.txbuf); 420 spin_unlock_bh(&sc->tx.txbuflock); 421 } 422 423 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 424 { 425 struct ath_buf *tbf; 426 427 tbf = ath_tx_get_buffer(sc); 428 if (WARN_ON(!tbf)) 429 return NULL; 430 431 ATH_TXBUF_RESET(tbf); 432 433 tbf->bf_mpdu = bf->bf_mpdu; 434 tbf->bf_buf_addr = bf->bf_buf_addr; 435 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 436 tbf->bf_state = bf->bf_state; 437 tbf->bf_state.stale = false; 438 439 return tbf; 440 } 441 442 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 443 struct ath_tx_status *ts, int txok, 444 int *nframes, int *nbad) 445 { 446 struct ath_frame_info *fi; 447 u16 seq_st = 0; 448 u32 ba[WME_BA_BMP_SIZE >> 5]; 449 int ba_index; 450 int isaggr = 0; 451 452 *nbad = 0; 453 *nframes = 0; 454 455 isaggr = bf_isaggr(bf); 456 if (isaggr) { 457 seq_st = ts->ts_seqnum; 458 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 459 } 460 461 while (bf) { 462 fi = get_frame_info(bf->bf_mpdu); 463 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 464 465 (*nframes)++; 466 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 467 (*nbad)++; 468 469 bf = bf->bf_next; 470 } 471 } 472 473 474 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 475 struct ath_buf *bf, struct list_head *bf_q, 476 struct ieee80211_sta *sta, 477 struct ath_atx_tid *tid, 478 struct ath_tx_status *ts, int txok) 479 { 480 struct ath_node *an = NULL; 481 struct sk_buff *skb; 482 struct ieee80211_hdr *hdr; 483 struct ieee80211_tx_info *tx_info; 484 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 485 struct list_head bf_head; 486 struct sk_buff_head bf_pending; 487 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 488 u32 ba[WME_BA_BMP_SIZE >> 5]; 489 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 490 bool rc_update = true, isba; 491 struct ieee80211_tx_rate rates[4]; 492 struct ath_frame_info *fi; 493 int nframes; 494 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 495 int i, retries; 496 int bar_index = -1; 497 498 skb = bf->bf_mpdu; 499 hdr = (struct ieee80211_hdr *)skb->data; 500 501 tx_info = IEEE80211_SKB_CB(skb); 502 503 memcpy(rates, bf->rates, sizeof(rates)); 504 505 retries = ts->ts_longretry + 1; 506 for (i = 0; i < ts->ts_rateindex; i++) 507 retries += rates[i].count; 508 509 if (!sta) { 510 INIT_LIST_HEAD(&bf_head); 511 while (bf) { 512 bf_next = bf->bf_next; 513 514 if (!bf->bf_state.stale || bf_next != NULL) 515 list_move_tail(&bf->list, &bf_head); 516 517 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); 518 519 bf = bf_next; 520 } 521 return; 522 } 523 524 an = (struct ath_node *)sta->drv_priv; 525 seq_first = tid->seq_start; 526 isba = ts->ts_flags & ATH9K_TX_BA; 527 528 /* 529 * The hardware occasionally sends a tx status for the wrong TID. 530 * In this case, the BA status cannot be considered valid and all 531 * subframes need to be retransmitted 532 * 533 * Only BlockAcks have a TID and therefore normal Acks cannot be 534 * checked 535 */ 536 if (isba && tid->tidno != ts->tid) 537 txok = false; 538 539 isaggr = bf_isaggr(bf); 540 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 541 542 if (isaggr && txok) { 543 if (ts->ts_flags & ATH9K_TX_BA) { 544 seq_st = ts->ts_seqnum; 545 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 546 } else { 547 /* 548 * AR5416 can become deaf/mute when BA 549 * issue happens. Chip needs to be reset. 550 * But AP code may have sychronization issues 551 * when perform internal reset in this routine. 552 * Only enable reset in STA mode for now. 553 */ 554 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 555 needreset = 1; 556 } 557 } 558 559 __skb_queue_head_init(&bf_pending); 560 561 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 562 while (bf) { 563 u16 seqno = bf->bf_state.seqno; 564 565 txfail = txpending = sendbar = 0; 566 bf_next = bf->bf_next; 567 568 skb = bf->bf_mpdu; 569 tx_info = IEEE80211_SKB_CB(skb); 570 fi = get_frame_info(skb); 571 572 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 573 !tid->active) { 574 /* 575 * Outside of the current BlockAck window, 576 * maybe part of a previous session 577 */ 578 txfail = 1; 579 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 580 /* transmit completion, subframe is 581 * acked by block ack */ 582 acked_cnt++; 583 } else if (!isaggr && txok) { 584 /* transmit completion */ 585 acked_cnt++; 586 } else if (flush) { 587 txpending = 1; 588 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 589 if (txok || !an->sleeping) 590 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 591 retries); 592 593 txpending = 1; 594 } else { 595 txfail = 1; 596 txfail_cnt++; 597 bar_index = max_t(int, bar_index, 598 ATH_BA_INDEX(seq_first, seqno)); 599 } 600 601 /* 602 * Make sure the last desc is reclaimed if it 603 * not a holding desc. 604 */ 605 INIT_LIST_HEAD(&bf_head); 606 if (bf_next != NULL || !bf_last->bf_state.stale) 607 list_move_tail(&bf->list, &bf_head); 608 609 if (!txpending) { 610 /* 611 * complete the acked-ones/xretried ones; update 612 * block-ack window 613 */ 614 ath_tx_update_baw(sc, tid, seqno); 615 616 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 617 memcpy(tx_info->control.rates, rates, sizeof(rates)); 618 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 619 rc_update = false; 620 if (bf == bf->bf_lastbf) 621 ath_dynack_sample_tx_ts(sc->sc_ah, 622 bf->bf_mpdu, 623 ts); 624 } 625 626 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, 627 !txfail); 628 } else { 629 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 630 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 631 ieee80211_sta_eosp(sta); 632 } 633 /* retry the un-acked ones */ 634 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 635 struct ath_buf *tbf; 636 637 tbf = ath_clone_txbuf(sc, bf_last); 638 /* 639 * Update tx baw and complete the 640 * frame with failed status if we 641 * run out of tx buf. 642 */ 643 if (!tbf) { 644 ath_tx_update_baw(sc, tid, seqno); 645 646 ath_tx_complete_buf(sc, bf, txq, 647 &bf_head, NULL, ts, 648 0); 649 bar_index = max_t(int, bar_index, 650 ATH_BA_INDEX(seq_first, seqno)); 651 break; 652 } 653 654 fi->bf = tbf; 655 } 656 657 /* 658 * Put this buffer to the temporary pending 659 * queue to retain ordering 660 */ 661 __skb_queue_tail(&bf_pending, skb); 662 } 663 664 bf = bf_next; 665 } 666 667 /* prepend un-acked frames to the beginning of the pending frame queue */ 668 if (!skb_queue_empty(&bf_pending)) { 669 if (an->sleeping) 670 ieee80211_sta_set_buffered(sta, tid->tidno, true); 671 672 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 673 if (!an->sleeping) { 674 ath_tx_queue_tid(sc, tid); 675 676 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 677 tid->clear_ps_filter = true; 678 } 679 } 680 681 if (bar_index >= 0) { 682 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 683 684 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 685 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 686 687 ath_txq_unlock(sc, txq); 688 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 689 ath_txq_lock(sc, txq); 690 } 691 692 if (needreset) 693 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 694 } 695 696 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 697 { 698 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 699 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 700 } 701 702 static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_txq *txq, 703 struct ath_buf *bf, struct ath_tx_status *ts) 704 { 705 struct ath_node *an; 706 struct ath_acq *acq = &sc->cur_chan->acq[txq->mac80211_qnum]; 707 struct sk_buff *skb; 708 struct ieee80211_hdr *hdr; 709 struct ieee80211_hw *hw = sc->hw; 710 struct ieee80211_tx_rate rates[4]; 711 struct ieee80211_sta *sta; 712 int i; 713 u32 airtime = 0; 714 715 skb = bf->bf_mpdu; 716 if(!skb) 717 return; 718 719 hdr = (struct ieee80211_hdr *)skb->data; 720 memcpy(rates, bf->rates, sizeof(rates)); 721 722 rcu_read_lock(); 723 724 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 725 if(!sta) 726 goto exit; 727 728 729 an = (struct ath_node *) sta->drv_priv; 730 731 airtime += ts->duration * (ts->ts_longretry + 1); 732 733 for(i=0; i < ts->ts_rateindex; i++) 734 airtime += ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i) * rates[i].count; 735 736 if (!!(sc->airtime_flags & AIRTIME_USE_TX)) { 737 spin_lock_bh(&acq->lock); 738 an->airtime_deficit[txq->mac80211_qnum] -= airtime; 739 if (an->airtime_deficit[txq->mac80211_qnum] <= 0) 740 __ath_tx_queue_tid(sc, ath_get_skb_tid(sc, an, skb)); 741 spin_unlock_bh(&acq->lock); 742 } 743 ath_debug_airtime(sc, an, 0, airtime); 744 745 exit: 746 rcu_read_unlock(); 747 } 748 749 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 750 struct ath_tx_status *ts, struct ath_buf *bf, 751 struct list_head *bf_head) 752 { 753 struct ieee80211_hw *hw = sc->hw; 754 struct ieee80211_tx_info *info; 755 struct ieee80211_sta *sta; 756 struct ieee80211_hdr *hdr; 757 struct ath_atx_tid *tid = NULL; 758 bool txok, flush; 759 760 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 761 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 762 txq->axq_tx_inprogress = false; 763 764 txq->axq_depth--; 765 if (bf_is_ampdu_not_probing(bf)) 766 txq->axq_ampdu_depth--; 767 768 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 769 ts->ts_rateindex); 770 ath_tx_count_airtime(sc, txq, bf, ts); 771 772 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 773 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 774 if (sta) { 775 struct ath_node *an = (struct ath_node *)sta->drv_priv; 776 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu); 777 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 778 tid->clear_ps_filter = true; 779 } 780 781 if (!bf_isampdu(bf)) { 782 if (!flush) { 783 info = IEEE80211_SKB_CB(bf->bf_mpdu); 784 memcpy(info->control.rates, bf->rates, 785 sizeof(info->control.rates)); 786 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 787 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); 788 } 789 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); 790 } else 791 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); 792 793 if (!flush) 794 ath_txq_schedule(sc, txq); 795 } 796 797 static bool ath_lookup_legacy(struct ath_buf *bf) 798 { 799 struct sk_buff *skb; 800 struct ieee80211_tx_info *tx_info; 801 struct ieee80211_tx_rate *rates; 802 int i; 803 804 skb = bf->bf_mpdu; 805 tx_info = IEEE80211_SKB_CB(skb); 806 rates = tx_info->control.rates; 807 808 for (i = 0; i < 4; i++) { 809 if (!rates[i].count || rates[i].idx < 0) 810 break; 811 812 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 813 return true; 814 } 815 816 return false; 817 } 818 819 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 820 struct ath_atx_tid *tid) 821 { 822 struct sk_buff *skb; 823 struct ieee80211_tx_info *tx_info; 824 struct ieee80211_tx_rate *rates; 825 u32 max_4ms_framelen, frmlen; 826 u16 aggr_limit, bt_aggr_limit, legacy = 0; 827 int q = tid->txq->mac80211_qnum; 828 int i; 829 830 skb = bf->bf_mpdu; 831 tx_info = IEEE80211_SKB_CB(skb); 832 rates = bf->rates; 833 834 /* 835 * Find the lowest frame length among the rate series that will have a 836 * 4ms (or TXOP limited) transmit duration. 837 */ 838 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 839 840 for (i = 0; i < 4; i++) { 841 int modeidx; 842 843 if (!rates[i].count) 844 continue; 845 846 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 847 legacy = 1; 848 break; 849 } 850 851 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 852 modeidx = MCS_HT40; 853 else 854 modeidx = MCS_HT20; 855 856 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 857 modeidx++; 858 859 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 860 max_4ms_framelen = min(max_4ms_framelen, frmlen); 861 } 862 863 /* 864 * limit aggregate size by the minimum rate if rate selected is 865 * not a probe rate, if rate selected is a probe rate then 866 * avoid aggregation of this packet. 867 */ 868 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 869 return 0; 870 871 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 872 873 /* 874 * Override the default aggregation limit for BTCOEX. 875 */ 876 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 877 if (bt_aggr_limit) 878 aggr_limit = bt_aggr_limit; 879 880 if (tid->an->maxampdu) 881 aggr_limit = min(aggr_limit, tid->an->maxampdu); 882 883 return aggr_limit; 884 } 885 886 /* 887 * Returns the number of delimiters to be added to 888 * meet the minimum required mpdudensity. 889 */ 890 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 891 struct ath_buf *bf, u16 frmlen, 892 bool first_subfrm) 893 { 894 #define FIRST_DESC_NDELIMS 60 895 u32 nsymbits, nsymbols; 896 u16 minlen; 897 u8 flags, rix; 898 int width, streams, half_gi, ndelim, mindelim; 899 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 900 901 /* Select standard number of delimiters based on frame length alone */ 902 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 903 904 /* 905 * If encryption enabled, hardware requires some more padding between 906 * subframes. 907 * TODO - this could be improved to be dependent on the rate. 908 * The hardware can keep up at lower rates, but not higher rates 909 */ 910 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 911 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 912 ndelim += ATH_AGGR_ENCRYPTDELIM; 913 914 /* 915 * Add delimiter when using RTS/CTS with aggregation 916 * and non enterprise AR9003 card 917 */ 918 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 919 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 920 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 921 922 /* 923 * Convert desired mpdu density from microeconds to bytes based 924 * on highest rate in rate series (i.e. first rate) to determine 925 * required minimum length for subframe. Take into account 926 * whether high rate is 20 or 40Mhz and half or full GI. 927 * 928 * If there is no mpdu density restriction, no further calculation 929 * is needed. 930 */ 931 932 if (tid->an->mpdudensity == 0) 933 return ndelim; 934 935 rix = bf->rates[0].idx; 936 flags = bf->rates[0].flags; 937 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 938 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 939 940 if (half_gi) 941 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 942 else 943 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 944 945 if (nsymbols == 0) 946 nsymbols = 1; 947 948 streams = HT_RC_2_STREAMS(rix); 949 nsymbits = bits_per_symbol[rix % 8][width] * streams; 950 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 951 952 if (frmlen < minlen) { 953 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 954 ndelim = max(mindelim, ndelim); 955 } 956 957 return ndelim; 958 } 959 960 static struct ath_buf * 961 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 962 struct ath_atx_tid *tid) 963 { 964 struct ieee80211_tx_info *tx_info; 965 struct ath_frame_info *fi; 966 struct sk_buff *skb, *first_skb = NULL; 967 struct ath_buf *bf; 968 u16 seqno; 969 970 while (1) { 971 skb = ath_tid_dequeue(tid); 972 if (!skb) 973 break; 974 975 fi = get_frame_info(skb); 976 bf = fi->bf; 977 if (!fi->bf) 978 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 979 else 980 bf->bf_state.stale = false; 981 982 if (!bf) { 983 ath_txq_skb_done(sc, txq, skb); 984 ieee80211_free_txskb(sc->hw, skb); 985 continue; 986 } 987 988 bf->bf_next = NULL; 989 bf->bf_lastbf = bf; 990 991 tx_info = IEEE80211_SKB_CB(skb); 992 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 993 994 /* 995 * No aggregation session is running, but there may be frames 996 * from a previous session or a failed attempt in the queue. 997 * Send them out as normal data frames 998 */ 999 if (!tid->active) 1000 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 1001 1002 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 1003 bf->bf_state.bf_type = 0; 1004 return bf; 1005 } 1006 1007 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 1008 seqno = bf->bf_state.seqno; 1009 1010 /* do not step over block-ack window */ 1011 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 1012 __skb_queue_tail(&tid->retry_q, skb); 1013 1014 /* If there are other skbs in the retry q, they are 1015 * probably within the BAW, so loop immediately to get 1016 * one of them. Otherwise the queue can get stuck. */ 1017 if (!skb_queue_is_first(&tid->retry_q, skb) && 1018 !WARN_ON(skb == first_skb)) { 1019 if(!first_skb) /* infinite loop prevention */ 1020 first_skb = skb; 1021 continue; 1022 } 1023 break; 1024 } 1025 1026 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 1027 struct ath_tx_status ts = {}; 1028 struct list_head bf_head; 1029 1030 INIT_LIST_HEAD(&bf_head); 1031 list_add(&bf->list, &bf_head); 1032 ath_tx_update_baw(sc, tid, seqno); 1033 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 1034 continue; 1035 } 1036 1037 return bf; 1038 } 1039 1040 return NULL; 1041 } 1042 1043 static int 1044 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 1045 struct ath_atx_tid *tid, struct list_head *bf_q, 1046 struct ath_buf *bf_first) 1047 { 1048 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 1049 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1050 int nframes = 0, ndelim; 1051 u16 aggr_limit = 0, al = 0, bpad = 0, 1052 al_delta, h_baw = tid->baw_size / 2; 1053 struct ieee80211_tx_info *tx_info; 1054 struct ath_frame_info *fi; 1055 struct sk_buff *skb; 1056 1057 1058 bf = bf_first; 1059 aggr_limit = ath_lookup_rate(sc, bf, tid); 1060 1061 while (bf) 1062 { 1063 skb = bf->bf_mpdu; 1064 fi = get_frame_info(skb); 1065 1066 /* do not exceed aggregation limit */ 1067 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 1068 if (nframes) { 1069 if (aggr_limit < al + bpad + al_delta || 1070 ath_lookup_legacy(bf) || nframes >= h_baw) 1071 goto stop; 1072 1073 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1074 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 1075 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 1076 goto stop; 1077 } 1078 1079 /* add padding for previous frame to aggregation length */ 1080 al += bpad + al_delta; 1081 1082 /* 1083 * Get the delimiters needed to meet the MPDU 1084 * density for this node. 1085 */ 1086 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 1087 !nframes); 1088 bpad = PADBYTES(al_delta) + (ndelim << 2); 1089 1090 nframes++; 1091 bf->bf_next = NULL; 1092 1093 /* link buffers of this frame to the aggregate */ 1094 if (!fi->baw_tracked) 1095 ath_tx_addto_baw(sc, tid, bf); 1096 bf->bf_state.ndelim = ndelim; 1097 1098 list_add_tail(&bf->list, bf_q); 1099 if (bf_prev) 1100 bf_prev->bf_next = bf; 1101 1102 bf_prev = bf; 1103 1104 bf = ath_tx_get_tid_subframe(sc, txq, tid); 1105 } 1106 goto finish; 1107 stop: 1108 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1109 finish: 1110 bf = bf_first; 1111 bf->bf_lastbf = bf_prev; 1112 1113 if (bf == bf_prev) { 1114 al = get_frame_info(bf->bf_mpdu)->framelen; 1115 bf->bf_state.bf_type = BUF_AMPDU; 1116 } else { 1117 TX_STAT_INC(txq->axq_qnum, a_aggr); 1118 } 1119 1120 return al; 1121 #undef PADBYTES 1122 } 1123 1124 /* 1125 * rix - rate index 1126 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1127 * width - 0 for 20 MHz, 1 for 40 MHz 1128 * half_gi - to use 4us v/s 3.6 us for symbol time 1129 */ 1130 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1131 int width, int half_gi, bool shortPreamble) 1132 { 1133 u32 nbits, nsymbits, duration, nsymbols; 1134 int streams; 1135 1136 /* find number of symbols: PLCP + data */ 1137 streams = HT_RC_2_STREAMS(rix); 1138 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1139 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1140 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1141 1142 if (!half_gi) 1143 duration = SYMBOL_TIME(nsymbols); 1144 else 1145 duration = SYMBOL_TIME_HALFGI(nsymbols); 1146 1147 /* addup duration for legacy/ht training and signal fields */ 1148 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1149 1150 return duration; 1151 } 1152 1153 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1154 { 1155 int streams = HT_RC_2_STREAMS(mcs); 1156 int symbols, bits; 1157 int bytes = 0; 1158 1159 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1160 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1161 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1162 bits -= OFDM_PLCP_BITS; 1163 bytes = bits / 8; 1164 if (bytes > 65532) 1165 bytes = 65532; 1166 1167 return bytes; 1168 } 1169 1170 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1171 { 1172 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1173 int mcs; 1174 1175 /* 4ms is the default (and maximum) duration */ 1176 if (!txop || txop > 4096) 1177 txop = 4096; 1178 1179 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1180 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1181 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1182 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1183 for (mcs = 0; mcs < 32; mcs++) { 1184 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1185 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1186 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1187 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1188 } 1189 } 1190 1191 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1192 u8 rateidx, bool is_40, bool is_cck) 1193 { 1194 u8 max_power; 1195 struct sk_buff *skb; 1196 struct ath_frame_info *fi; 1197 struct ieee80211_tx_info *info; 1198 struct ath_hw *ah = sc->sc_ah; 1199 1200 if (sc->tx99_state || !ah->tpc_enabled) 1201 return MAX_RATE_POWER; 1202 1203 skb = bf->bf_mpdu; 1204 fi = get_frame_info(skb); 1205 info = IEEE80211_SKB_CB(skb); 1206 1207 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1208 int txpower = fi->tx_power; 1209 1210 if (is_40) { 1211 u8 power_ht40delta; 1212 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1213 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah); 1214 1215 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) { 1216 bool is_2ghz; 1217 struct modal_eep_header *pmodal; 1218 1219 is_2ghz = info->band == NL80211_BAND_2GHZ; 1220 pmodal = &eep->modalHeader[is_2ghz]; 1221 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1222 } else { 1223 power_ht40delta = 2; 1224 } 1225 txpower += power_ht40delta; 1226 } 1227 1228 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1229 AR_SREV_9271(ah)) { 1230 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1231 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1232 s8 power_offset; 1233 1234 power_offset = ah->eep_ops->get_eeprom(ah, 1235 EEP_PWR_TABLE_OFFSET); 1236 txpower -= 2 * power_offset; 1237 } 1238 1239 if (OLC_FOR_AR9280_20_LATER && is_cck) 1240 txpower -= 2; 1241 1242 txpower = max(txpower, 0); 1243 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1244 1245 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1246 * max_power is set to 0, frames are transmitted at max 1247 * TX power 1248 */ 1249 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1250 max_power = 1; 1251 } else if (!bf->bf_state.bfs_paprd) { 1252 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) 1253 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1254 fi->tx_power); 1255 else 1256 max_power = min_t(u8, ah->tx_power[rateidx], 1257 fi->tx_power); 1258 } else { 1259 max_power = ah->paprd_training_power; 1260 } 1261 1262 return max_power; 1263 } 1264 1265 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1266 struct ath_tx_info *info, int len, bool rts) 1267 { 1268 struct ath_hw *ah = sc->sc_ah; 1269 struct ath_common *common = ath9k_hw_common(ah); 1270 struct sk_buff *skb; 1271 struct ieee80211_tx_info *tx_info; 1272 struct ieee80211_tx_rate *rates; 1273 const struct ieee80211_rate *rate; 1274 struct ieee80211_hdr *hdr; 1275 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1276 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1277 int i; 1278 u8 rix = 0; 1279 1280 skb = bf->bf_mpdu; 1281 tx_info = IEEE80211_SKB_CB(skb); 1282 rates = bf->rates; 1283 hdr = (struct ieee80211_hdr *)skb->data; 1284 1285 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1286 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1287 info->rtscts_rate = fi->rtscts_rate; 1288 1289 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1290 bool is_40, is_sgi, is_sp, is_cck; 1291 int phy; 1292 1293 if (!rates[i].count || (rates[i].idx < 0)) 1294 continue; 1295 1296 rix = rates[i].idx; 1297 info->rates[i].Tries = rates[i].count; 1298 1299 /* 1300 * Handle RTS threshold for unaggregated HT frames. 1301 */ 1302 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1303 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1304 unlikely(rts_thresh != (u32) -1)) { 1305 if (!rts_thresh || (len > rts_thresh)) 1306 rts = true; 1307 } 1308 1309 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1310 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1311 info->flags |= ATH9K_TXDESC_RTSENA; 1312 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1313 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1314 info->flags |= ATH9K_TXDESC_CTSENA; 1315 } 1316 1317 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1318 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1319 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1320 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1321 1322 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1323 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1324 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1325 1326 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1327 /* MCS rates */ 1328 info->rates[i].Rate = rix | 0x80; 1329 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1330 ah->txchainmask, info->rates[i].Rate); 1331 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1332 is_40, is_sgi, is_sp); 1333 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1334 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1335 1336 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1337 is_40, false); 1338 continue; 1339 } 1340 1341 /* legacy rates */ 1342 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1343 if ((tx_info->band == NL80211_BAND_2GHZ) && 1344 !(rate->flags & IEEE80211_RATE_ERP_G)) 1345 phy = WLAN_RC_PHY_CCK; 1346 else 1347 phy = WLAN_RC_PHY_OFDM; 1348 1349 info->rates[i].Rate = rate->hw_value; 1350 if (rate->hw_value_short) { 1351 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1352 info->rates[i].Rate |= rate->hw_value_short; 1353 } else { 1354 is_sp = false; 1355 } 1356 1357 if (bf->bf_state.bfs_paprd) 1358 info->rates[i].ChSel = ah->txchainmask; 1359 else 1360 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1361 ah->txchainmask, info->rates[i].Rate); 1362 1363 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1364 phy, rate->bitrate * 100, len, rix, is_sp); 1365 1366 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1367 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1368 is_cck); 1369 } 1370 1371 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1372 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1373 info->flags &= ~ATH9K_TXDESC_RTSENA; 1374 1375 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1376 if (info->flags & ATH9K_TXDESC_RTSENA) 1377 info->flags &= ~ATH9K_TXDESC_CTSENA; 1378 } 1379 1380 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1381 { 1382 struct ieee80211_hdr *hdr; 1383 enum ath9k_pkt_type htype; 1384 __le16 fc; 1385 1386 hdr = (struct ieee80211_hdr *)skb->data; 1387 fc = hdr->frame_control; 1388 1389 if (ieee80211_is_beacon(fc)) 1390 htype = ATH9K_PKT_TYPE_BEACON; 1391 else if (ieee80211_is_probe_resp(fc)) 1392 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1393 else if (ieee80211_is_atim(fc)) 1394 htype = ATH9K_PKT_TYPE_ATIM; 1395 else if (ieee80211_is_pspoll(fc)) 1396 htype = ATH9K_PKT_TYPE_PSPOLL; 1397 else 1398 htype = ATH9K_PKT_TYPE_NORMAL; 1399 1400 return htype; 1401 } 1402 1403 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1404 struct ath_txq *txq, int len) 1405 { 1406 struct ath_hw *ah = sc->sc_ah; 1407 struct ath_buf *bf_first = NULL; 1408 struct ath_tx_info info; 1409 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1410 bool rts = false; 1411 1412 memset(&info, 0, sizeof(info)); 1413 info.is_first = true; 1414 info.is_last = true; 1415 info.qcu = txq->axq_qnum; 1416 1417 while (bf) { 1418 struct sk_buff *skb = bf->bf_mpdu; 1419 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1420 struct ath_frame_info *fi = get_frame_info(skb); 1421 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1422 1423 info.type = get_hw_packet_type(skb); 1424 if (bf->bf_next) 1425 info.link = bf->bf_next->bf_daddr; 1426 else 1427 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1428 1429 if (!bf_first) { 1430 bf_first = bf; 1431 1432 if (!sc->tx99_state) 1433 info.flags = ATH9K_TXDESC_INTREQ; 1434 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1435 txq == sc->tx.uapsdq) 1436 info.flags |= ATH9K_TXDESC_CLRDMASK; 1437 1438 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1439 info.flags |= ATH9K_TXDESC_NOACK; 1440 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1441 info.flags |= ATH9K_TXDESC_LDPC; 1442 1443 if (bf->bf_state.bfs_paprd) 1444 info.flags |= (u32) bf->bf_state.bfs_paprd << 1445 ATH9K_TXDESC_PAPRD_S; 1446 1447 /* 1448 * mac80211 doesn't handle RTS threshold for HT because 1449 * the decision has to be taken based on AMPDU length 1450 * and aggregation is done entirely inside ath9k. 1451 * Set the RTS/CTS flag for the first subframe based 1452 * on the threshold. 1453 */ 1454 if (aggr && (bf == bf_first) && 1455 unlikely(rts_thresh != (u32) -1)) { 1456 /* 1457 * "len" is the size of the entire AMPDU. 1458 */ 1459 if (!rts_thresh || (len > rts_thresh)) 1460 rts = true; 1461 } 1462 1463 if (!aggr) 1464 len = fi->framelen; 1465 1466 ath_buf_set_rate(sc, bf, &info, len, rts); 1467 } 1468 1469 info.buf_addr[0] = bf->bf_buf_addr; 1470 info.buf_len[0] = skb->len; 1471 info.pkt_len = fi->framelen; 1472 info.keyix = fi->keyix; 1473 info.keytype = fi->keytype; 1474 1475 if (aggr) { 1476 if (bf == bf_first) 1477 info.aggr = AGGR_BUF_FIRST; 1478 else if (bf == bf_first->bf_lastbf) 1479 info.aggr = AGGR_BUF_LAST; 1480 else 1481 info.aggr = AGGR_BUF_MIDDLE; 1482 1483 info.ndelim = bf->bf_state.ndelim; 1484 info.aggr_len = len; 1485 } 1486 1487 if (bf == bf_first->bf_lastbf) 1488 bf_first = NULL; 1489 1490 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1491 bf = bf->bf_next; 1492 } 1493 } 1494 1495 static void 1496 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1497 struct ath_atx_tid *tid, struct list_head *bf_q, 1498 struct ath_buf *bf_first) 1499 { 1500 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1501 int nframes = 0; 1502 1503 do { 1504 struct ieee80211_tx_info *tx_info; 1505 1506 nframes++; 1507 list_add_tail(&bf->list, bf_q); 1508 if (bf_prev) 1509 bf_prev->bf_next = bf; 1510 bf_prev = bf; 1511 1512 if (nframes >= 2) 1513 break; 1514 1515 bf = ath_tx_get_tid_subframe(sc, txq, tid); 1516 if (!bf) 1517 break; 1518 1519 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1520 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1521 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1522 break; 1523 } 1524 1525 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1526 } while (1); 1527 } 1528 1529 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1530 struct ath_atx_tid *tid) 1531 { 1532 struct ath_buf *bf; 1533 struct ieee80211_tx_info *tx_info; 1534 struct list_head bf_q; 1535 int aggr_len = 0; 1536 bool aggr; 1537 1538 if (!ath_tid_has_buffered(tid)) 1539 return false; 1540 1541 INIT_LIST_HEAD(&bf_q); 1542 1543 bf = ath_tx_get_tid_subframe(sc, txq, tid); 1544 if (!bf) 1545 return false; 1546 1547 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1548 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1549 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1550 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1551 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1552 return false; 1553 } 1554 1555 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1556 if (aggr) 1557 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf); 1558 else 1559 ath_tx_form_burst(sc, txq, tid, &bf_q, bf); 1560 1561 if (list_empty(&bf_q)) 1562 return false; 1563 1564 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1565 tid->clear_ps_filter = false; 1566 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1567 } 1568 1569 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1570 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1571 return true; 1572 } 1573 1574 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1575 u16 tid, u16 *ssn) 1576 { 1577 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1578 struct ath_atx_tid *txtid; 1579 struct ath_txq *txq; 1580 struct ath_node *an; 1581 u8 density; 1582 1583 ath_dbg(common, XMIT, "%s called\n", __func__); 1584 1585 an = (struct ath_node *)sta->drv_priv; 1586 txtid = ATH_AN_2_TID(an, tid); 1587 txq = txtid->txq; 1588 1589 ath_txq_lock(sc, txq); 1590 1591 /* update ampdu factor/density, they may have changed. This may happen 1592 * in HT IBSS when a beacon with HT-info is received after the station 1593 * has already been added. 1594 */ 1595 if (sta->ht_cap.ht_supported) { 1596 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1597 sta->ht_cap.ampdu_factor)) - 1; 1598 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1599 an->mpdudensity = density; 1600 } 1601 1602 txtid->active = true; 1603 *ssn = txtid->seq_start = txtid->seq_next; 1604 txtid->bar_index = -1; 1605 1606 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1607 txtid->baw_head = txtid->baw_tail = 0; 1608 1609 ath_txq_unlock_complete(sc, txq); 1610 1611 return 0; 1612 } 1613 1614 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1615 { 1616 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1617 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1618 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1619 struct ath_txq *txq = txtid->txq; 1620 1621 ath_dbg(common, XMIT, "%s called\n", __func__); 1622 1623 ath_txq_lock(sc, txq); 1624 txtid->active = false; 1625 ath_tx_flush_tid(sc, txtid); 1626 ath_txq_unlock_complete(sc, txq); 1627 } 1628 1629 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1630 struct ath_node *an) 1631 { 1632 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1633 struct ath_atx_tid *tid; 1634 struct ath_txq *txq; 1635 int tidno; 1636 1637 ath_dbg(common, XMIT, "%s called\n", __func__); 1638 1639 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1640 tid = ath_node_to_tid(an, tidno); 1641 txq = tid->txq; 1642 1643 ath_txq_lock(sc, txq); 1644 1645 if (list_empty(&tid->list)) { 1646 ath_txq_unlock(sc, txq); 1647 continue; 1648 } 1649 1650 if (!skb_queue_empty(&tid->retry_q)) 1651 ieee80211_sta_set_buffered(sta, tid->tidno, true); 1652 1653 list_del_init(&tid->list); 1654 1655 ath_txq_unlock(sc, txq); 1656 } 1657 } 1658 1659 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1660 { 1661 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1662 struct ath_atx_tid *tid; 1663 struct ath_txq *txq; 1664 int tidno; 1665 1666 ath_dbg(common, XMIT, "%s called\n", __func__); 1667 1668 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1669 tid = ath_node_to_tid(an, tidno); 1670 txq = tid->txq; 1671 1672 ath_txq_lock(sc, txq); 1673 tid->clear_ps_filter = true; 1674 if (ath_tid_has_buffered(tid)) { 1675 ath_tx_queue_tid(sc, tid); 1676 ath_txq_schedule(sc, txq); 1677 } 1678 ath_txq_unlock_complete(sc, txq); 1679 } 1680 } 1681 1682 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1683 struct ieee80211_sta *sta, 1684 u16 tids, int nframes, 1685 enum ieee80211_frame_release_type reason, 1686 bool more_data) 1687 { 1688 struct ath_softc *sc = hw->priv; 1689 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1690 struct ath_txq *txq = sc->tx.uapsdq; 1691 struct ieee80211_tx_info *info; 1692 struct list_head bf_q; 1693 struct ath_buf *bf_tail = NULL, *bf; 1694 int sent = 0; 1695 int i; 1696 1697 INIT_LIST_HEAD(&bf_q); 1698 for (i = 0; tids && nframes; i++, tids >>= 1) { 1699 struct ath_atx_tid *tid; 1700 1701 if (!(tids & 1)) 1702 continue; 1703 1704 tid = ATH_AN_2_TID(an, i); 1705 1706 ath_txq_lock(sc, tid->txq); 1707 while (nframes > 0) { 1708 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid); 1709 if (!bf) 1710 break; 1711 1712 list_add_tail(&bf->list, &bf_q); 1713 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1714 if (bf_isampdu(bf)) { 1715 ath_tx_addto_baw(sc, tid, bf); 1716 bf->bf_state.bf_type &= ~BUF_AGGR; 1717 } 1718 if (bf_tail) 1719 bf_tail->bf_next = bf; 1720 1721 bf_tail = bf; 1722 nframes--; 1723 sent++; 1724 TX_STAT_INC(txq->axq_qnum, a_queued_hw); 1725 1726 if (an->sta && skb_queue_empty(&tid->retry_q)) 1727 ieee80211_sta_set_buffered(an->sta, i, false); 1728 } 1729 ath_txq_unlock_complete(sc, tid->txq); 1730 } 1731 1732 if (list_empty(&bf_q)) 1733 return; 1734 1735 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1736 info->flags |= IEEE80211_TX_STATUS_EOSP; 1737 1738 bf = list_first_entry(&bf_q, struct ath_buf, list); 1739 ath_txq_lock(sc, txq); 1740 ath_tx_fill_desc(sc, bf, txq, 0); 1741 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1742 ath_txq_unlock(sc, txq); 1743 } 1744 1745 /********************/ 1746 /* Queue Management */ 1747 /********************/ 1748 1749 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1750 { 1751 struct ath_hw *ah = sc->sc_ah; 1752 struct ath9k_tx_queue_info qi; 1753 static const int subtype_txq_to_hwq[] = { 1754 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1755 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1756 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1757 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1758 }; 1759 int axq_qnum, i; 1760 1761 memset(&qi, 0, sizeof(qi)); 1762 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1763 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1764 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1765 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1766 qi.tqi_physCompBuf = 0; 1767 1768 /* 1769 * Enable interrupts only for EOL and DESC conditions. 1770 * We mark tx descriptors to receive a DESC interrupt 1771 * when a tx queue gets deep; otherwise waiting for the 1772 * EOL to reap descriptors. Note that this is done to 1773 * reduce interrupt load and this only defers reaping 1774 * descriptors, never transmitting frames. Aside from 1775 * reducing interrupts this also permits more concurrency. 1776 * The only potential downside is if the tx queue backs 1777 * up in which case the top half of the kernel may backup 1778 * due to a lack of tx descriptors. 1779 * 1780 * The UAPSD queue is an exception, since we take a desc- 1781 * based intr on the EOSP frames. 1782 */ 1783 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1784 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1785 } else { 1786 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1787 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1788 else 1789 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1790 TXQ_FLAG_TXDESCINT_ENABLE; 1791 } 1792 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1793 if (axq_qnum == -1) { 1794 /* 1795 * NB: don't print a message, this happens 1796 * normally on parts with too few tx queues 1797 */ 1798 return NULL; 1799 } 1800 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1801 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1802 1803 txq->axq_qnum = axq_qnum; 1804 txq->mac80211_qnum = -1; 1805 txq->axq_link = NULL; 1806 __skb_queue_head_init(&txq->complete_q); 1807 INIT_LIST_HEAD(&txq->axq_q); 1808 spin_lock_init(&txq->axq_lock); 1809 txq->axq_depth = 0; 1810 txq->axq_ampdu_depth = 0; 1811 txq->axq_tx_inprogress = false; 1812 sc->tx.txqsetup |= 1<<axq_qnum; 1813 1814 txq->txq_headidx = txq->txq_tailidx = 0; 1815 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1816 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1817 } 1818 return &sc->tx.txq[axq_qnum]; 1819 } 1820 1821 int ath_txq_update(struct ath_softc *sc, int qnum, 1822 struct ath9k_tx_queue_info *qinfo) 1823 { 1824 struct ath_hw *ah = sc->sc_ah; 1825 int error = 0; 1826 struct ath9k_tx_queue_info qi; 1827 1828 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1829 1830 ath9k_hw_get_txq_props(ah, qnum, &qi); 1831 qi.tqi_aifs = qinfo->tqi_aifs; 1832 qi.tqi_cwmin = qinfo->tqi_cwmin; 1833 qi.tqi_cwmax = qinfo->tqi_cwmax; 1834 qi.tqi_burstTime = qinfo->tqi_burstTime; 1835 qi.tqi_readyTime = qinfo->tqi_readyTime; 1836 1837 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1838 ath_err(ath9k_hw_common(sc->sc_ah), 1839 "Unable to update hardware queue %u!\n", qnum); 1840 error = -EIO; 1841 } else { 1842 ath9k_hw_resettxqueue(ah, qnum); 1843 } 1844 1845 return error; 1846 } 1847 1848 int ath_cabq_update(struct ath_softc *sc) 1849 { 1850 struct ath9k_tx_queue_info qi; 1851 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1852 int qnum = sc->beacon.cabq->axq_qnum; 1853 1854 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1855 1856 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1857 ATH_CABQ_READY_TIME) / 100; 1858 ath_txq_update(sc, qnum, &qi); 1859 1860 return 0; 1861 } 1862 1863 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1864 struct list_head *list) 1865 { 1866 struct ath_buf *bf, *lastbf; 1867 struct list_head bf_head; 1868 struct ath_tx_status ts; 1869 1870 memset(&ts, 0, sizeof(ts)); 1871 ts.ts_status = ATH9K_TX_FLUSH; 1872 INIT_LIST_HEAD(&bf_head); 1873 1874 while (!list_empty(list)) { 1875 bf = list_first_entry(list, struct ath_buf, list); 1876 1877 if (bf->bf_state.stale) { 1878 list_del(&bf->list); 1879 1880 ath_tx_return_buffer(sc, bf); 1881 continue; 1882 } 1883 1884 lastbf = bf->bf_lastbf; 1885 list_cut_position(&bf_head, list, &lastbf->list); 1886 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1887 } 1888 } 1889 1890 /* 1891 * Drain a given TX queue (could be Beacon or Data) 1892 * 1893 * This assumes output has been stopped and 1894 * we do not need to block ath_tx_tasklet. 1895 */ 1896 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1897 { 1898 rcu_read_lock(); 1899 ath_txq_lock(sc, txq); 1900 1901 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1902 int idx = txq->txq_tailidx; 1903 1904 while (!list_empty(&txq->txq_fifo[idx])) { 1905 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1906 1907 INCR(idx, ATH_TXFIFO_DEPTH); 1908 } 1909 txq->txq_tailidx = idx; 1910 } 1911 1912 txq->axq_link = NULL; 1913 txq->axq_tx_inprogress = false; 1914 ath_drain_txq_list(sc, txq, &txq->axq_q); 1915 1916 ath_txq_unlock_complete(sc, txq); 1917 rcu_read_unlock(); 1918 } 1919 1920 bool ath_drain_all_txq(struct ath_softc *sc) 1921 { 1922 struct ath_hw *ah = sc->sc_ah; 1923 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1924 struct ath_txq *txq; 1925 int i; 1926 u32 npend = 0; 1927 1928 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1929 return true; 1930 1931 ath9k_hw_abort_tx_dma(ah); 1932 1933 /* Check if any queue remains active */ 1934 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1935 if (!ATH_TXQ_SETUP(sc, i)) 1936 continue; 1937 1938 if (!sc->tx.txq[i].axq_depth) 1939 continue; 1940 1941 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1942 npend |= BIT(i); 1943 } 1944 1945 if (npend) { 1946 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1947 ath_dbg(common, RESET, 1948 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1949 } 1950 1951 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1952 if (!ATH_TXQ_SETUP(sc, i)) 1953 continue; 1954 1955 txq = &sc->tx.txq[i]; 1956 ath_draintxq(sc, txq); 1957 } 1958 1959 return !npend; 1960 } 1961 1962 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1963 { 1964 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1965 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1966 } 1967 1968 /* For each acq entry, for each tid, try to schedule packets 1969 * for transmit until ampdu_depth has reached min Q depth. 1970 */ 1971 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1972 { 1973 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1974 struct ath_atx_tid *tid; 1975 struct list_head *tid_list; 1976 struct ath_acq *acq; 1977 bool active = AIRTIME_ACTIVE(sc->airtime_flags); 1978 1979 if (txq->mac80211_qnum < 0) 1980 return; 1981 1982 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1983 return; 1984 1985 spin_lock_bh(&sc->chan_lock); 1986 rcu_read_lock(); 1987 acq = &sc->cur_chan->acq[txq->mac80211_qnum]; 1988 1989 if (sc->cur_chan->stopped) 1990 goto out; 1991 1992 begin: 1993 tid_list = &acq->acq_new; 1994 if (list_empty(tid_list)) { 1995 tid_list = &acq->acq_old; 1996 if (list_empty(tid_list)) 1997 goto out; 1998 } 1999 tid = list_first_entry(tid_list, struct ath_atx_tid, list); 2000 2001 if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) { 2002 spin_lock_bh(&acq->lock); 2003 tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM; 2004 list_move_tail(&tid->list, &acq->acq_old); 2005 spin_unlock_bh(&acq->lock); 2006 goto begin; 2007 } 2008 2009 if (!ath_tid_has_buffered(tid)) { 2010 spin_lock_bh(&acq->lock); 2011 if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old)) 2012 list_move_tail(&tid->list, &acq->acq_old); 2013 else { 2014 list_del_init(&tid->list); 2015 } 2016 spin_unlock_bh(&acq->lock); 2017 goto begin; 2018 } 2019 2020 2021 /* 2022 * If we succeed in scheduling something, immediately restart to make 2023 * sure we keep the HW busy. 2024 */ 2025 if(ath_tx_sched_aggr(sc, txq, tid)) { 2026 if (!active) { 2027 spin_lock_bh(&acq->lock); 2028 list_move_tail(&tid->list, &acq->acq_old); 2029 spin_unlock_bh(&acq->lock); 2030 } 2031 goto begin; 2032 } 2033 2034 out: 2035 rcu_read_unlock(); 2036 spin_unlock_bh(&sc->chan_lock); 2037 } 2038 2039 void ath_txq_schedule_all(struct ath_softc *sc) 2040 { 2041 struct ath_txq *txq; 2042 int i; 2043 2044 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2045 txq = sc->tx.txq_map[i]; 2046 2047 spin_lock_bh(&txq->axq_lock); 2048 ath_txq_schedule(sc, txq); 2049 spin_unlock_bh(&txq->axq_lock); 2050 } 2051 } 2052 2053 /***********/ 2054 /* TX, DMA */ 2055 /***********/ 2056 2057 /* 2058 * Insert a chain of ath_buf (descriptors) on a txq and 2059 * assume the descriptors are already chained together by caller. 2060 */ 2061 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2062 struct list_head *head, bool internal) 2063 { 2064 struct ath_hw *ah = sc->sc_ah; 2065 struct ath_common *common = ath9k_hw_common(ah); 2066 struct ath_buf *bf, *bf_last; 2067 bool puttxbuf = false; 2068 bool edma; 2069 2070 /* 2071 * Insert the frame on the outbound list and 2072 * pass it on to the hardware. 2073 */ 2074 2075 if (list_empty(head)) 2076 return; 2077 2078 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2079 bf = list_first_entry(head, struct ath_buf, list); 2080 bf_last = list_entry(head->prev, struct ath_buf, list); 2081 2082 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2083 txq->axq_qnum, txq->axq_depth); 2084 2085 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2086 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2087 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2088 puttxbuf = true; 2089 } else { 2090 list_splice_tail_init(head, &txq->axq_q); 2091 2092 if (txq->axq_link) { 2093 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2094 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2095 txq->axq_qnum, txq->axq_link, 2096 ito64(bf->bf_daddr), bf->bf_desc); 2097 } else if (!edma) 2098 puttxbuf = true; 2099 2100 txq->axq_link = bf_last->bf_desc; 2101 } 2102 2103 if (puttxbuf) { 2104 TX_STAT_INC(txq->axq_qnum, puttxbuf); 2105 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2106 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2107 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2108 } 2109 2110 if (!edma || sc->tx99_state) { 2111 TX_STAT_INC(txq->axq_qnum, txstart); 2112 ath9k_hw_txstart(ah, txq->axq_qnum); 2113 } 2114 2115 if (!internal) { 2116 while (bf) { 2117 txq->axq_depth++; 2118 if (bf_is_ampdu_not_probing(bf)) 2119 txq->axq_ampdu_depth++; 2120 2121 bf_last = bf->bf_lastbf; 2122 bf = bf_last->bf_next; 2123 bf_last->bf_next = NULL; 2124 } 2125 } 2126 } 2127 2128 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2129 struct ath_atx_tid *tid, struct sk_buff *skb) 2130 { 2131 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2132 struct ath_frame_info *fi = get_frame_info(skb); 2133 struct list_head bf_head; 2134 struct ath_buf *bf = fi->bf; 2135 2136 INIT_LIST_HEAD(&bf_head); 2137 list_add_tail(&bf->list, &bf_head); 2138 bf->bf_state.bf_type = 0; 2139 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2140 bf->bf_state.bf_type = BUF_AMPDU; 2141 ath_tx_addto_baw(sc, tid, bf); 2142 } 2143 2144 bf->bf_next = NULL; 2145 bf->bf_lastbf = bf; 2146 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2147 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2148 TX_STAT_INC(txq->axq_qnum, queued); 2149 } 2150 2151 static void setup_frame_info(struct ieee80211_hw *hw, 2152 struct ieee80211_sta *sta, 2153 struct sk_buff *skb, 2154 int framelen) 2155 { 2156 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2157 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2158 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2159 const struct ieee80211_rate *rate; 2160 struct ath_frame_info *fi = get_frame_info(skb); 2161 struct ath_node *an = NULL; 2162 enum ath9k_key_type keytype; 2163 bool short_preamble = false; 2164 u8 txpower; 2165 2166 /* 2167 * We check if Short Preamble is needed for the CTS rate by 2168 * checking the BSS's global flag. 2169 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2170 */ 2171 if (tx_info->control.vif && 2172 tx_info->control.vif->bss_conf.use_short_preamble) 2173 short_preamble = true; 2174 2175 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2176 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2177 2178 if (sta) 2179 an = (struct ath_node *) sta->drv_priv; 2180 2181 if (tx_info->control.vif) { 2182 struct ieee80211_vif *vif = tx_info->control.vif; 2183 2184 txpower = 2 * vif->bss_conf.txpower; 2185 } else { 2186 struct ath_softc *sc = hw->priv; 2187 2188 txpower = sc->cur_chan->cur_txpower; 2189 } 2190 2191 memset(fi, 0, sizeof(*fi)); 2192 fi->txq = -1; 2193 if (hw_key) 2194 fi->keyix = hw_key->hw_key_idx; 2195 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2196 fi->keyix = an->ps_key; 2197 else 2198 fi->keyix = ATH9K_TXKEYIX_INVALID; 2199 fi->keytype = keytype; 2200 fi->framelen = framelen; 2201 fi->tx_power = txpower; 2202 2203 if (!rate) 2204 return; 2205 fi->rtscts_rate = rate->hw_value; 2206 if (short_preamble) 2207 fi->rtscts_rate |= rate->hw_value_short; 2208 } 2209 2210 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2211 { 2212 struct ath_hw *ah = sc->sc_ah; 2213 struct ath9k_channel *curchan = ah->curchan; 2214 2215 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2216 (chainmask == 0x7) && (rate < 0x90)) 2217 return 0x3; 2218 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2219 IS_CCK_RATE(rate)) 2220 return 0x2; 2221 else 2222 return chainmask; 2223 } 2224 2225 /* 2226 * Assign a descriptor (and sequence number if necessary, 2227 * and map buffer for DMA. Frees skb on error 2228 */ 2229 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2230 struct ath_txq *txq, 2231 struct ath_atx_tid *tid, 2232 struct sk_buff *skb) 2233 { 2234 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2235 struct ath_frame_info *fi = get_frame_info(skb); 2236 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2237 struct ath_buf *bf; 2238 int fragno; 2239 u16 seqno; 2240 2241 bf = ath_tx_get_buffer(sc); 2242 if (!bf) { 2243 ath_dbg(common, XMIT, "TX buffers are full\n"); 2244 return NULL; 2245 } 2246 2247 ATH_TXBUF_RESET(bf); 2248 2249 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2250 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2251 seqno = tid->seq_next; 2252 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2253 2254 if (fragno) 2255 hdr->seq_ctrl |= cpu_to_le16(fragno); 2256 2257 if (!ieee80211_has_morefrags(hdr->frame_control)) 2258 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2259 2260 bf->bf_state.seqno = seqno; 2261 } 2262 2263 bf->bf_mpdu = skb; 2264 2265 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2266 skb->len, DMA_TO_DEVICE); 2267 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2268 bf->bf_mpdu = NULL; 2269 bf->bf_buf_addr = 0; 2270 ath_err(ath9k_hw_common(sc->sc_ah), 2271 "dma_mapping_error() on TX\n"); 2272 ath_tx_return_buffer(sc, bf); 2273 return NULL; 2274 } 2275 2276 fi->bf = bf; 2277 2278 return bf; 2279 } 2280 2281 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2282 { 2283 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2284 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2285 struct ieee80211_vif *vif = info->control.vif; 2286 struct ath_vif *avp; 2287 2288 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2289 return; 2290 2291 if (!vif) 2292 return; 2293 2294 avp = (struct ath_vif *)vif->drv_priv; 2295 2296 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2297 avp->seq_no += 0x10; 2298 2299 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2300 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2301 } 2302 2303 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2304 struct ath_tx_control *txctl) 2305 { 2306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2307 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2308 struct ieee80211_sta *sta = txctl->sta; 2309 struct ieee80211_vif *vif = info->control.vif; 2310 struct ath_vif *avp; 2311 struct ath_softc *sc = hw->priv; 2312 int frmlen = skb->len + FCS_LEN; 2313 int padpos, padsize; 2314 2315 /* NOTE: sta can be NULL according to net/mac80211.h */ 2316 if (sta) 2317 txctl->an = (struct ath_node *)sta->drv_priv; 2318 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2319 avp = (void *)vif->drv_priv; 2320 txctl->an = &avp->mcast_node; 2321 } 2322 2323 if (info->control.hw_key) 2324 frmlen += info->control.hw_key->icv_len; 2325 2326 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2327 2328 if ((vif && vif->type != NL80211_IFTYPE_AP && 2329 vif->type != NL80211_IFTYPE_AP_VLAN) || 2330 !ieee80211_is_data(hdr->frame_control)) 2331 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2332 2333 /* Add the padding after the header if this is not already done */ 2334 padpos = ieee80211_hdrlen(hdr->frame_control); 2335 padsize = padpos & 3; 2336 if (padsize && skb->len > padpos) { 2337 if (skb_headroom(skb) < padsize) 2338 return -ENOMEM; 2339 2340 skb_push(skb, padsize); 2341 memmove(skb->data, skb->data + padsize, padpos); 2342 } 2343 2344 setup_frame_info(hw, sta, skb, frmlen); 2345 return 0; 2346 } 2347 2348 2349 /* Upon failure caller should free skb */ 2350 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2351 struct ath_tx_control *txctl) 2352 { 2353 struct ieee80211_hdr *hdr; 2354 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2355 struct ieee80211_sta *sta = txctl->sta; 2356 struct ieee80211_vif *vif = info->control.vif; 2357 struct ath_frame_info *fi = get_frame_info(skb); 2358 struct ath_vif *avp = NULL; 2359 struct ath_softc *sc = hw->priv; 2360 struct ath_txq *txq = txctl->txq; 2361 struct ath_atx_tid *tid = NULL; 2362 struct ath_node *an = NULL; 2363 struct ath_buf *bf; 2364 bool ps_resp; 2365 int q, ret; 2366 2367 if (vif) 2368 avp = (void *)vif->drv_priv; 2369 2370 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2371 2372 ret = ath_tx_prepare(hw, skb, txctl); 2373 if (ret) 2374 return ret; 2375 2376 hdr = (struct ieee80211_hdr *) skb->data; 2377 /* 2378 * At this point, the vif, hw_key and sta pointers in the tx control 2379 * info are no longer valid (overwritten by the ath_frame_info data. 2380 */ 2381 2382 q = skb_get_queue_mapping(skb); 2383 2384 if (ps_resp) 2385 txq = sc->tx.uapsdq; 2386 2387 if (txctl->sta) { 2388 an = (struct ath_node *) sta->drv_priv; 2389 tid = ath_get_skb_tid(sc, an, skb); 2390 } 2391 2392 ath_txq_lock(sc, txq); 2393 if (txq == sc->tx.txq_map[q]) { 2394 fi->txq = q; 2395 ++txq->pending_frames; 2396 } 2397 2398 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2399 if (!bf) { 2400 ath_txq_skb_done(sc, txq, skb); 2401 if (txctl->paprd) 2402 dev_kfree_skb_any(skb); 2403 else 2404 ieee80211_free_txskb(sc->hw, skb); 2405 goto out; 2406 } 2407 2408 bf->bf_state.bfs_paprd = txctl->paprd; 2409 2410 if (txctl->paprd) 2411 bf->bf_state.bfs_paprd_timestamp = jiffies; 2412 2413 ath_set_rates(vif, sta, bf); 2414 ath_tx_send_normal(sc, txq, tid, skb); 2415 2416 out: 2417 ath_txq_unlock(sc, txq); 2418 2419 return 0; 2420 } 2421 2422 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2423 struct sk_buff *skb) 2424 { 2425 struct ath_softc *sc = hw->priv; 2426 struct ath_tx_control txctl = { 2427 .txq = sc->beacon.cabq 2428 }; 2429 struct ath_tx_info info = {}; 2430 struct ieee80211_hdr *hdr; 2431 struct ath_buf *bf_tail = NULL; 2432 struct ath_buf *bf; 2433 LIST_HEAD(bf_q); 2434 int duration = 0; 2435 int max_duration; 2436 2437 max_duration = 2438 sc->cur_chan->beacon.beacon_interval * 1000 * 2439 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2440 2441 do { 2442 struct ath_frame_info *fi = get_frame_info(skb); 2443 2444 if (ath_tx_prepare(hw, skb, &txctl)) 2445 break; 2446 2447 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2448 if (!bf) 2449 break; 2450 2451 bf->bf_lastbf = bf; 2452 ath_set_rates(vif, NULL, bf); 2453 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2454 duration += info.rates[0].PktDuration; 2455 if (bf_tail) 2456 bf_tail->bf_next = bf; 2457 2458 list_add_tail(&bf->list, &bf_q); 2459 bf_tail = bf; 2460 skb = NULL; 2461 2462 if (duration > max_duration) 2463 break; 2464 2465 skb = ieee80211_get_buffered_bc(hw, vif); 2466 } while(skb); 2467 2468 if (skb) 2469 ieee80211_free_txskb(hw, skb); 2470 2471 if (list_empty(&bf_q)) 2472 return; 2473 2474 bf = list_first_entry(&bf_q, struct ath_buf, list); 2475 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 2476 2477 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) { 2478 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA); 2479 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 2480 sizeof(*hdr), DMA_TO_DEVICE); 2481 } 2482 2483 ath_txq_lock(sc, txctl.txq); 2484 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2485 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2486 TX_STAT_INC(txctl.txq->axq_qnum, queued); 2487 ath_txq_unlock(sc, txctl.txq); 2488 } 2489 2490 /*****************/ 2491 /* TX Completion */ 2492 /*****************/ 2493 2494 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2495 int tx_flags, struct ath_txq *txq, 2496 struct ieee80211_sta *sta) 2497 { 2498 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2499 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2500 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2501 int padpos, padsize; 2502 unsigned long flags; 2503 2504 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2505 2506 if (sc->sc_ah->caldata) 2507 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2508 2509 if (!(tx_flags & ATH_TX_ERROR)) { 2510 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2511 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2512 else 2513 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2514 } 2515 2516 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 2517 padpos = ieee80211_hdrlen(hdr->frame_control); 2518 padsize = padpos & 3; 2519 if (padsize && skb->len>padpos+padsize) { 2520 /* 2521 * Remove MAC header padding before giving the frame back to 2522 * mac80211. 2523 */ 2524 memmove(skb->data + padsize, skb->data, padpos); 2525 skb_pull(skb, padsize); 2526 } 2527 } 2528 2529 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2530 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2531 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2532 ath_dbg(common, PS, 2533 "Going back to sleep after having received TX status (0x%lx)\n", 2534 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2535 PS_WAIT_FOR_CAB | 2536 PS_WAIT_FOR_PSPOLL_DATA | 2537 PS_WAIT_FOR_TX_ACK)); 2538 } 2539 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2540 2541 ath_txq_skb_done(sc, txq, skb); 2542 tx_info->status.status_driver_data[0] = sta; 2543 __skb_queue_tail(&txq->complete_q, skb); 2544 } 2545 2546 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2547 struct ath_txq *txq, struct list_head *bf_q, 2548 struct ieee80211_sta *sta, 2549 struct ath_tx_status *ts, int txok) 2550 { 2551 struct sk_buff *skb = bf->bf_mpdu; 2552 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2553 unsigned long flags; 2554 int tx_flags = 0; 2555 2556 if (!txok) 2557 tx_flags |= ATH_TX_ERROR; 2558 2559 if (ts->ts_status & ATH9K_TXERR_FILT) 2560 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2561 2562 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2563 bf->bf_buf_addr = 0; 2564 if (sc->tx99_state) 2565 goto skip_tx_complete; 2566 2567 if (bf->bf_state.bfs_paprd) { 2568 if (time_after(jiffies, 2569 bf->bf_state.bfs_paprd_timestamp + 2570 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2571 dev_kfree_skb_any(skb); 2572 else 2573 complete(&sc->paprd_complete); 2574 } else { 2575 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2576 ath_tx_complete(sc, skb, tx_flags, txq, sta); 2577 } 2578 skip_tx_complete: 2579 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2580 * accidentally reference it later. 2581 */ 2582 bf->bf_mpdu = NULL; 2583 2584 /* 2585 * Return the list of ath_buf of this mpdu to free queue 2586 */ 2587 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2588 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2589 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2590 } 2591 2592 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2593 struct ath_tx_status *ts, int nframes, int nbad, 2594 int txok) 2595 { 2596 struct sk_buff *skb = bf->bf_mpdu; 2597 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2598 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2599 struct ieee80211_hw *hw = sc->hw; 2600 struct ath_hw *ah = sc->sc_ah; 2601 u8 i, tx_rateindex; 2602 2603 if (txok) 2604 tx_info->status.ack_signal = ts->ts_rssi; 2605 2606 tx_rateindex = ts->ts_rateindex; 2607 WARN_ON(tx_rateindex >= hw->max_rates); 2608 2609 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2610 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2611 2612 BUG_ON(nbad > nframes); 2613 } 2614 tx_info->status.ampdu_len = nframes; 2615 tx_info->status.ampdu_ack_len = nframes - nbad; 2616 2617 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2618 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2619 /* 2620 * If an underrun error is seen assume it as an excessive 2621 * retry only if max frame trigger level has been reached 2622 * (2 KB for single stream, and 4 KB for dual stream). 2623 * Adjust the long retry as if the frame was tried 2624 * hw->max_rate_tries times to affect how rate control updates 2625 * PER for the failed rate. 2626 * In case of congestion on the bus penalizing this type of 2627 * underruns should help hardware actually transmit new frames 2628 * successfully by eventually preferring slower rates. 2629 * This itself should also alleviate congestion on the bus. 2630 */ 2631 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2632 ATH9K_TX_DELIM_UNDERRUN)) && 2633 ieee80211_is_data(hdr->frame_control) && 2634 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2635 tx_info->status.rates[tx_rateindex].count = 2636 hw->max_rate_tries; 2637 } 2638 2639 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2640 tx_info->status.rates[i].count = 0; 2641 tx_info->status.rates[i].idx = -1; 2642 } 2643 2644 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2645 } 2646 2647 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2648 { 2649 struct ath_hw *ah = sc->sc_ah; 2650 struct ath_common *common = ath9k_hw_common(ah); 2651 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2652 struct list_head bf_head; 2653 struct ath_desc *ds; 2654 struct ath_tx_status ts; 2655 int status; 2656 2657 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2658 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2659 txq->axq_link); 2660 2661 ath_txq_lock(sc, txq); 2662 for (;;) { 2663 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2664 break; 2665 2666 if (list_empty(&txq->axq_q)) { 2667 txq->axq_link = NULL; 2668 ath_txq_schedule(sc, txq); 2669 break; 2670 } 2671 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2672 2673 /* 2674 * There is a race condition that a BH gets scheduled 2675 * after sw writes TxE and before hw re-load the last 2676 * descriptor to get the newly chained one. 2677 * Software must keep the last DONE descriptor as a 2678 * holding descriptor - software does so by marking 2679 * it with the STALE flag. 2680 */ 2681 bf_held = NULL; 2682 if (bf->bf_state.stale) { 2683 bf_held = bf; 2684 if (list_is_last(&bf_held->list, &txq->axq_q)) 2685 break; 2686 2687 bf = list_entry(bf_held->list.next, struct ath_buf, 2688 list); 2689 } 2690 2691 lastbf = bf->bf_lastbf; 2692 ds = lastbf->bf_desc; 2693 2694 memset(&ts, 0, sizeof(ts)); 2695 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2696 if (status == -EINPROGRESS) 2697 break; 2698 2699 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2700 2701 /* 2702 * Remove ath_buf's of the same transmit unit from txq, 2703 * however leave the last descriptor back as the holding 2704 * descriptor for hw. 2705 */ 2706 lastbf->bf_state.stale = true; 2707 INIT_LIST_HEAD(&bf_head); 2708 if (!list_is_singular(&lastbf->list)) 2709 list_cut_position(&bf_head, 2710 &txq->axq_q, lastbf->list.prev); 2711 2712 if (bf_held) { 2713 list_del(&bf_held->list); 2714 ath_tx_return_buffer(sc, bf_held); 2715 } 2716 2717 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2718 } 2719 ath_txq_unlock_complete(sc, txq); 2720 } 2721 2722 void ath_tx_tasklet(struct ath_softc *sc) 2723 { 2724 struct ath_hw *ah = sc->sc_ah; 2725 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2726 int i; 2727 2728 rcu_read_lock(); 2729 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2730 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2731 ath_tx_processq(sc, &sc->tx.txq[i]); 2732 } 2733 rcu_read_unlock(); 2734 } 2735 2736 void ath_tx_edma_tasklet(struct ath_softc *sc) 2737 { 2738 struct ath_tx_status ts; 2739 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2740 struct ath_hw *ah = sc->sc_ah; 2741 struct ath_txq *txq; 2742 struct ath_buf *bf, *lastbf; 2743 struct list_head bf_head; 2744 struct list_head *fifo_list; 2745 int status; 2746 2747 rcu_read_lock(); 2748 for (;;) { 2749 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2750 break; 2751 2752 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2753 if (status == -EINPROGRESS) 2754 break; 2755 if (status == -EIO) { 2756 ath_dbg(common, XMIT, "Error processing tx status\n"); 2757 break; 2758 } 2759 2760 /* Process beacon completions separately */ 2761 if (ts.qid == sc->beacon.beaconq) { 2762 sc->beacon.tx_processed = true; 2763 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2764 2765 if (ath9k_is_chanctx_enabled()) { 2766 ath_chanctx_event(sc, NULL, 2767 ATH_CHANCTX_EVENT_BEACON_SENT); 2768 } 2769 2770 ath9k_csa_update(sc); 2771 continue; 2772 } 2773 2774 txq = &sc->tx.txq[ts.qid]; 2775 2776 ath_txq_lock(sc, txq); 2777 2778 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2779 2780 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2781 if (list_empty(fifo_list)) { 2782 ath_txq_unlock(sc, txq); 2783 break; 2784 } 2785 2786 bf = list_first_entry(fifo_list, struct ath_buf, list); 2787 if (bf->bf_state.stale) { 2788 list_del(&bf->list); 2789 ath_tx_return_buffer(sc, bf); 2790 bf = list_first_entry(fifo_list, struct ath_buf, list); 2791 } 2792 2793 lastbf = bf->bf_lastbf; 2794 2795 INIT_LIST_HEAD(&bf_head); 2796 if (list_is_last(&lastbf->list, fifo_list)) { 2797 list_splice_tail_init(fifo_list, &bf_head); 2798 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2799 2800 if (!list_empty(&txq->axq_q)) { 2801 struct list_head bf_q; 2802 2803 INIT_LIST_HEAD(&bf_q); 2804 txq->axq_link = NULL; 2805 list_splice_tail_init(&txq->axq_q, &bf_q); 2806 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2807 } 2808 } else { 2809 lastbf->bf_state.stale = true; 2810 if (bf != lastbf) 2811 list_cut_position(&bf_head, fifo_list, 2812 lastbf->list.prev); 2813 } 2814 2815 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2816 ath_txq_unlock_complete(sc, txq); 2817 } 2818 rcu_read_unlock(); 2819 } 2820 2821 /*****************/ 2822 /* Init, Cleanup */ 2823 /*****************/ 2824 2825 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2826 { 2827 struct ath_descdma *dd = &sc->txsdma; 2828 u8 txs_len = sc->sc_ah->caps.txs_len; 2829 2830 dd->dd_desc_len = size * txs_len; 2831 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2832 &dd->dd_desc_paddr, GFP_KERNEL); 2833 if (!dd->dd_desc) 2834 return -ENOMEM; 2835 2836 return 0; 2837 } 2838 2839 static int ath_tx_edma_init(struct ath_softc *sc) 2840 { 2841 int err; 2842 2843 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2844 if (!err) 2845 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2846 sc->txsdma.dd_desc_paddr, 2847 ATH_TXSTATUS_RING_SIZE); 2848 2849 return err; 2850 } 2851 2852 int ath_tx_init(struct ath_softc *sc, int nbufs) 2853 { 2854 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2855 int error = 0; 2856 2857 spin_lock_init(&sc->tx.txbuflock); 2858 2859 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2860 "tx", nbufs, 1, 1); 2861 if (error != 0) { 2862 ath_err(common, 2863 "Failed to allocate tx descriptors: %d\n", error); 2864 return error; 2865 } 2866 2867 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2868 "beacon", ATH_BCBUF, 1, 1); 2869 if (error != 0) { 2870 ath_err(common, 2871 "Failed to allocate beacon descriptors: %d\n", error); 2872 return error; 2873 } 2874 2875 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2876 2877 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2878 error = ath_tx_edma_init(sc); 2879 2880 return error; 2881 } 2882 2883 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2884 { 2885 struct ath_atx_tid *tid; 2886 int tidno, acno; 2887 2888 for (acno = 0; acno < IEEE80211_NUM_ACS; acno++) 2889 an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM; 2890 2891 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2892 tid = ath_node_to_tid(an, tidno); 2893 tid->an = an; 2894 tid->tidno = tidno; 2895 tid->seq_start = tid->seq_next = 0; 2896 tid->baw_size = WME_MAX_BA; 2897 tid->baw_head = tid->baw_tail = 0; 2898 tid->active = false; 2899 tid->clear_ps_filter = true; 2900 tid->has_queued = false; 2901 __skb_queue_head_init(&tid->retry_q); 2902 INIT_LIST_HEAD(&tid->list); 2903 acno = TID_TO_WME_AC(tidno); 2904 tid->txq = sc->tx.txq_map[acno]; 2905 2906 if (!an->sta) 2907 break; /* just one multicast ath_atx_tid */ 2908 } 2909 } 2910 2911 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2912 { 2913 struct ath_atx_tid *tid; 2914 struct ath_txq *txq; 2915 int tidno; 2916 2917 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2918 tid = ath_node_to_tid(an, tidno); 2919 txq = tid->txq; 2920 2921 ath_txq_lock(sc, txq); 2922 2923 if (!list_empty(&tid->list)) 2924 list_del_init(&tid->list); 2925 2926 ath_tid_drain(sc, txq, tid); 2927 tid->active = false; 2928 2929 ath_txq_unlock(sc, txq); 2930 2931 if (!an->sta) 2932 break; /* just one multicast ath_atx_tid */ 2933 } 2934 } 2935 2936 #ifdef CONFIG_ATH9K_TX99 2937 2938 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2939 struct ath_tx_control *txctl) 2940 { 2941 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2942 struct ath_frame_info *fi = get_frame_info(skb); 2943 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2944 struct ath_buf *bf; 2945 int padpos, padsize; 2946 2947 padpos = ieee80211_hdrlen(hdr->frame_control); 2948 padsize = padpos & 3; 2949 2950 if (padsize && skb->len > padpos) { 2951 if (skb_headroom(skb) < padsize) { 2952 ath_dbg(common, XMIT, 2953 "tx99 padding failed\n"); 2954 return -EINVAL; 2955 } 2956 2957 skb_push(skb, padsize); 2958 memmove(skb->data, skb->data + padsize, padpos); 2959 } 2960 2961 fi->keyix = ATH9K_TXKEYIX_INVALID; 2962 fi->framelen = skb->len + FCS_LEN; 2963 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2964 2965 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2966 if (!bf) { 2967 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2968 return -EINVAL; 2969 } 2970 2971 ath_set_rates(sc->tx99_vif, NULL, bf); 2972 2973 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2974 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2975 2976 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2977 2978 return 0; 2979 } 2980 2981 #endif /* CONFIG_ATH9K_TX99 */ 2982