1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "ath9k.h" 18 #include "ar9003_mac.h" 19 20 #define BITS_PER_BYTE 8 21 #define OFDM_PLCP_BITS 22 22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f) 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 34 35 #define OFDM_SIFS_TIME 16 36 37 static u16 bits_per_symbol[][2] = { 38 /* 20MHz 40MHz */ 39 { 26, 54 }, /* 0: BPSK */ 40 { 52, 108 }, /* 1: QPSK 1/2 */ 41 { 78, 162 }, /* 2: QPSK 3/4 */ 42 { 104, 216 }, /* 3: 16-QAM 1/2 */ 43 { 156, 324 }, /* 4: 16-QAM 3/4 */ 44 { 208, 432 }, /* 5: 64-QAM 2/3 */ 45 { 234, 486 }, /* 6: 64-QAM 3/4 */ 46 { 260, 540 }, /* 7: 64-QAM 5/6 */ 47 }; 48 49 #define IS_HT_RATE(_rate) ((_rate) & 0x80) 50 51 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 52 struct ath_atx_tid *tid, 53 struct list_head *bf_head); 54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 55 struct ath_txq *txq, struct list_head *bf_q, 56 struct ath_tx_status *ts, int txok, int sendbar); 57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 58 struct list_head *head); 59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len); 60 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, 61 int nframes, int nbad, int txok, bool update_rc); 62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 63 int seqno); 64 65 enum { 66 MCS_HT20, 67 MCS_HT20_SGI, 68 MCS_HT40, 69 MCS_HT40_SGI, 70 }; 71 72 static int ath_max_4ms_framelen[4][32] = { 73 [MCS_HT20] = { 74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172, 75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280, 76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532, 77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532, 78 }, 79 [MCS_HT20_SGI] = { 80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744, 81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532, 82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532, 83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532, 84 }, 85 [MCS_HT40] = { 86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532, 87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532, 88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532, 89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532, 90 }, 91 [MCS_HT40_SGI] = { 92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532, 93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532, 94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532, 95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532, 96 } 97 }; 98 99 /*********************/ 100 /* Aggregation logic */ 101 /*********************/ 102 103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) 104 { 105 struct ath_atx_ac *ac = tid->ac; 106 107 if (tid->paused) 108 return; 109 110 if (tid->sched) 111 return; 112 113 tid->sched = true; 114 list_add_tail(&tid->list, &ac->tid_q); 115 116 if (ac->sched) 117 return; 118 119 ac->sched = true; 120 list_add_tail(&ac->list, &txq->axq_acq); 121 } 122 123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 124 { 125 struct ath_txq *txq = tid->ac->txq; 126 127 WARN_ON(!tid->paused); 128 129 spin_lock_bh(&txq->axq_lock); 130 tid->paused = false; 131 132 if (list_empty(&tid->buf_q)) 133 goto unlock; 134 135 ath_tx_queue_tid(txq, tid); 136 ath_txq_schedule(sc, txq); 137 unlock: 138 spin_unlock_bh(&txq->axq_lock); 139 } 140 141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 142 { 143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 144 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 145 sizeof(tx_info->rate_driver_data)); 146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 147 } 148 149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 150 { 151 struct ath_txq *txq = tid->ac->txq; 152 struct ath_buf *bf; 153 struct list_head bf_head; 154 struct ath_tx_status ts; 155 struct ath_frame_info *fi; 156 157 INIT_LIST_HEAD(&bf_head); 158 159 memset(&ts, 0, sizeof(ts)); 160 spin_lock_bh(&txq->axq_lock); 161 162 while (!list_empty(&tid->buf_q)) { 163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 164 list_move_tail(&bf->list, &bf_head); 165 166 spin_unlock_bh(&txq->axq_lock); 167 fi = get_frame_info(bf->bf_mpdu); 168 if (fi->retries) { 169 ath_tx_update_baw(sc, tid, fi->seqno); 170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 171 } else { 172 ath_tx_send_normal(sc, txq, tid, &bf_head); 173 } 174 spin_lock_bh(&txq->axq_lock); 175 } 176 177 spin_unlock_bh(&txq->axq_lock); 178 } 179 180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 181 int seqno) 182 { 183 int index, cindex; 184 185 index = ATH_BA_INDEX(tid->seq_start, seqno); 186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 187 188 __clear_bit(cindex, tid->tx_buf); 189 190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 191 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 192 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 193 } 194 } 195 196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 197 u16 seqno) 198 { 199 int index, cindex; 200 201 index = ATH_BA_INDEX(tid->seq_start, seqno); 202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 203 __set_bit(cindex, tid->tx_buf); 204 205 if (index >= ((tid->baw_tail - tid->baw_head) & 206 (ATH_TID_MAX_BUFS - 1))) { 207 tid->baw_tail = cindex; 208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 209 } 210 } 211 212 /* 213 * TODO: For frame(s) that are in the retry state, we will reuse the 214 * sequence number(s) without setting the retry bit. The 215 * alternative is to give up on these and BAR the receiver's window 216 * forward. 217 */ 218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 219 struct ath_atx_tid *tid) 220 221 { 222 struct ath_buf *bf; 223 struct list_head bf_head; 224 struct ath_tx_status ts; 225 struct ath_frame_info *fi; 226 227 memset(&ts, 0, sizeof(ts)); 228 INIT_LIST_HEAD(&bf_head); 229 230 for (;;) { 231 if (list_empty(&tid->buf_q)) 232 break; 233 234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 235 list_move_tail(&bf->list, &bf_head); 236 237 fi = get_frame_info(bf->bf_mpdu); 238 if (fi->retries) 239 ath_tx_update_baw(sc, tid, fi->seqno); 240 241 spin_unlock(&txq->axq_lock); 242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 243 spin_lock(&txq->axq_lock); 244 } 245 246 tid->seq_next = tid->seq_start; 247 tid->baw_tail = tid->baw_head; 248 } 249 250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 251 struct sk_buff *skb) 252 { 253 struct ath_frame_info *fi = get_frame_info(skb); 254 struct ieee80211_hdr *hdr; 255 256 TX_STAT_INC(txq->axq_qnum, a_retries); 257 if (fi->retries++ > 0) 258 return; 259 260 hdr = (struct ieee80211_hdr *)skb->data; 261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 262 } 263 264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 265 { 266 struct ath_buf *bf = NULL; 267 268 spin_lock_bh(&sc->tx.txbuflock); 269 270 if (unlikely(list_empty(&sc->tx.txbuf))) { 271 spin_unlock_bh(&sc->tx.txbuflock); 272 return NULL; 273 } 274 275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 276 list_del(&bf->list); 277 278 spin_unlock_bh(&sc->tx.txbuflock); 279 280 return bf; 281 } 282 283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 284 { 285 spin_lock_bh(&sc->tx.txbuflock); 286 list_add_tail(&bf->list, &sc->tx.txbuf); 287 spin_unlock_bh(&sc->tx.txbuflock); 288 } 289 290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 291 { 292 struct ath_buf *tbf; 293 294 tbf = ath_tx_get_buffer(sc); 295 if (WARN_ON(!tbf)) 296 return NULL; 297 298 ATH_TXBUF_RESET(tbf); 299 300 tbf->aphy = bf->aphy; 301 tbf->bf_mpdu = bf->bf_mpdu; 302 tbf->bf_buf_addr = bf->bf_buf_addr; 303 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 304 tbf->bf_state = bf->bf_state; 305 306 return tbf; 307 } 308 309 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 310 struct ath_tx_status *ts, int txok, 311 int *nframes, int *nbad) 312 { 313 struct ath_frame_info *fi; 314 u16 seq_st = 0; 315 u32 ba[WME_BA_BMP_SIZE >> 5]; 316 int ba_index; 317 int isaggr = 0; 318 319 *nbad = 0; 320 *nframes = 0; 321 322 isaggr = bf_isaggr(bf); 323 if (isaggr) { 324 seq_st = ts->ts_seqnum; 325 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 326 } 327 328 while (bf) { 329 fi = get_frame_info(bf->bf_mpdu); 330 ba_index = ATH_BA_INDEX(seq_st, fi->seqno); 331 332 (*nframes)++; 333 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 334 (*nbad)++; 335 336 bf = bf->bf_next; 337 } 338 } 339 340 341 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 342 struct ath_buf *bf, struct list_head *bf_q, 343 struct ath_tx_status *ts, int txok, bool retry) 344 { 345 struct ath_node *an = NULL; 346 struct sk_buff *skb; 347 struct ieee80211_sta *sta; 348 struct ieee80211_hw *hw; 349 struct ieee80211_hdr *hdr; 350 struct ieee80211_tx_info *tx_info; 351 struct ath_atx_tid *tid = NULL; 352 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 353 struct list_head bf_head, bf_pending; 354 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; 355 u32 ba[WME_BA_BMP_SIZE >> 5]; 356 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 357 bool rc_update = true; 358 struct ieee80211_tx_rate rates[4]; 359 struct ath_frame_info *fi; 360 int nframes; 361 u8 tidno; 362 363 skb = bf->bf_mpdu; 364 hdr = (struct ieee80211_hdr *)skb->data; 365 366 tx_info = IEEE80211_SKB_CB(skb); 367 hw = bf->aphy->hw; 368 369 memcpy(rates, tx_info->control.rates, sizeof(rates)); 370 371 rcu_read_lock(); 372 373 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 374 if (!sta) { 375 rcu_read_unlock(); 376 377 INIT_LIST_HEAD(&bf_head); 378 while (bf) { 379 bf_next = bf->bf_next; 380 381 bf->bf_state.bf_type |= BUF_XRETRY; 382 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) || 383 !bf->bf_stale || bf_next != NULL) 384 list_move_tail(&bf->list, &bf_head); 385 386 ath_tx_rc_status(bf, ts, 1, 1, 0, false); 387 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 388 0, 0); 389 390 bf = bf_next; 391 } 392 return; 393 } 394 395 an = (struct ath_node *)sta->drv_priv; 396 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; 397 tid = ATH_AN_2_TID(an, tidno); 398 399 /* 400 * The hardware occasionally sends a tx status for the wrong TID. 401 * In this case, the BA status cannot be considered valid and all 402 * subframes need to be retransmitted 403 */ 404 if (tidno != ts->tid) 405 txok = false; 406 407 isaggr = bf_isaggr(bf); 408 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 409 410 if (isaggr && txok) { 411 if (ts->ts_flags & ATH9K_TX_BA) { 412 seq_st = ts->ts_seqnum; 413 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 414 } else { 415 /* 416 * AR5416 can become deaf/mute when BA 417 * issue happens. Chip needs to be reset. 418 * But AP code may have sychronization issues 419 * when perform internal reset in this routine. 420 * Only enable reset in STA mode for now. 421 */ 422 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 423 needreset = 1; 424 } 425 } 426 427 INIT_LIST_HEAD(&bf_pending); 428 INIT_LIST_HEAD(&bf_head); 429 430 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 431 while (bf) { 432 txfail = txpending = 0; 433 bf_next = bf->bf_next; 434 435 skb = bf->bf_mpdu; 436 tx_info = IEEE80211_SKB_CB(skb); 437 fi = get_frame_info(skb); 438 439 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) { 440 /* transmit completion, subframe is 441 * acked by block ack */ 442 acked_cnt++; 443 } else if (!isaggr && txok) { 444 /* transmit completion */ 445 acked_cnt++; 446 } else { 447 if (!(tid->state & AGGR_CLEANUP) && retry) { 448 if (fi->retries < ATH_MAX_SW_RETRIES) { 449 ath_tx_set_retry(sc, txq, bf->bf_mpdu); 450 txpending = 1; 451 } else { 452 bf->bf_state.bf_type |= BUF_XRETRY; 453 txfail = 1; 454 sendbar = 1; 455 txfail_cnt++; 456 } 457 } else { 458 /* 459 * cleanup in progress, just fail 460 * the un-acked sub-frames 461 */ 462 txfail = 1; 463 } 464 } 465 466 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 467 bf_next == NULL) { 468 /* 469 * Make sure the last desc is reclaimed if it 470 * not a holding desc. 471 */ 472 if (!bf_last->bf_stale) 473 list_move_tail(&bf->list, &bf_head); 474 else 475 INIT_LIST_HEAD(&bf_head); 476 } else { 477 BUG_ON(list_empty(bf_q)); 478 list_move_tail(&bf->list, &bf_head); 479 } 480 481 if (!txpending || (tid->state & AGGR_CLEANUP)) { 482 /* 483 * complete the acked-ones/xretried ones; update 484 * block-ack window 485 */ 486 spin_lock_bh(&txq->axq_lock); 487 ath_tx_update_baw(sc, tid, fi->seqno); 488 spin_unlock_bh(&txq->axq_lock); 489 490 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 491 memcpy(tx_info->control.rates, rates, sizeof(rates)); 492 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true); 493 rc_update = false; 494 } else { 495 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false); 496 } 497 498 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 499 !txfail, sendbar); 500 } else { 501 /* retry the un-acked ones */ 502 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) { 503 if (bf->bf_next == NULL && bf_last->bf_stale) { 504 struct ath_buf *tbf; 505 506 tbf = ath_clone_txbuf(sc, bf_last); 507 /* 508 * Update tx baw and complete the 509 * frame with failed status if we 510 * run out of tx buf. 511 */ 512 if (!tbf) { 513 spin_lock_bh(&txq->axq_lock); 514 ath_tx_update_baw(sc, tid, fi->seqno); 515 spin_unlock_bh(&txq->axq_lock); 516 517 bf->bf_state.bf_type |= 518 BUF_XRETRY; 519 ath_tx_rc_status(bf, ts, nframes, 520 nbad, 0, false); 521 ath_tx_complete_buf(sc, bf, txq, 522 &bf_head, 523 ts, 0, 0); 524 break; 525 } 526 527 ath9k_hw_cleartxdesc(sc->sc_ah, 528 tbf->bf_desc); 529 list_add_tail(&tbf->list, &bf_head); 530 } else { 531 /* 532 * Clear descriptor status words for 533 * software retry 534 */ 535 ath9k_hw_cleartxdesc(sc->sc_ah, 536 bf->bf_desc); 537 } 538 } 539 540 /* 541 * Put this buffer to the temporary pending 542 * queue to retain ordering 543 */ 544 list_splice_tail_init(&bf_head, &bf_pending); 545 } 546 547 bf = bf_next; 548 } 549 550 /* prepend un-acked frames to the beginning of the pending frame queue */ 551 if (!list_empty(&bf_pending)) { 552 spin_lock_bh(&txq->axq_lock); 553 list_splice(&bf_pending, &tid->buf_q); 554 ath_tx_queue_tid(txq, tid); 555 spin_unlock_bh(&txq->axq_lock); 556 } 557 558 if (tid->state & AGGR_CLEANUP) { 559 ath_tx_flush_tid(sc, tid); 560 561 if (tid->baw_head == tid->baw_tail) { 562 tid->state &= ~AGGR_ADDBA_COMPLETE; 563 tid->state &= ~AGGR_CLEANUP; 564 } 565 } 566 567 rcu_read_unlock(); 568 569 if (needreset) 570 ath_reset(sc, false); 571 } 572 573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 574 struct ath_atx_tid *tid) 575 { 576 struct sk_buff *skb; 577 struct ieee80211_tx_info *tx_info; 578 struct ieee80211_tx_rate *rates; 579 u32 max_4ms_framelen, frmlen; 580 u16 aggr_limit, legacy = 0; 581 int i; 582 583 skb = bf->bf_mpdu; 584 tx_info = IEEE80211_SKB_CB(skb); 585 rates = tx_info->control.rates; 586 587 /* 588 * Find the lowest frame length among the rate series that will have a 589 * 4ms transmit duration. 590 * TODO - TXOP limit needs to be considered. 591 */ 592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 593 594 for (i = 0; i < 4; i++) { 595 if (rates[i].count) { 596 int modeidx; 597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 598 legacy = 1; 599 break; 600 } 601 602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 603 modeidx = MCS_HT40; 604 else 605 modeidx = MCS_HT20; 606 607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 608 modeidx++; 609 610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; 611 max_4ms_framelen = min(max_4ms_framelen, frmlen); 612 } 613 } 614 615 /* 616 * limit aggregate size by the minimum rate if rate selected is 617 * not a probe rate, if rate selected is a probe rate then 618 * avoid aggregation of this packet. 619 */ 620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 621 return 0; 622 623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) 624 aggr_limit = min((max_4ms_framelen * 3) / 8, 625 (u32)ATH_AMPDU_LIMIT_MAX); 626 else 627 aggr_limit = min(max_4ms_framelen, 628 (u32)ATH_AMPDU_LIMIT_MAX); 629 630 /* 631 * h/w can accept aggregates upto 16 bit lengths (65535). 632 * The IE, however can hold upto 65536, which shows up here 633 * as zero. Ignore 65536 since we are constrained by hw. 634 */ 635 if (tid->an->maxampdu) 636 aggr_limit = min(aggr_limit, tid->an->maxampdu); 637 638 return aggr_limit; 639 } 640 641 /* 642 * Returns the number of delimiters to be added to 643 * meet the minimum required mpdudensity. 644 */ 645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 646 struct ath_buf *bf, u16 frmlen) 647 { 648 struct sk_buff *skb = bf->bf_mpdu; 649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 650 u32 nsymbits, nsymbols; 651 u16 minlen; 652 u8 flags, rix; 653 int width, streams, half_gi, ndelim, mindelim; 654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 655 656 /* Select standard number of delimiters based on frame length alone */ 657 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 658 659 /* 660 * If encryption enabled, hardware requires some more padding between 661 * subframes. 662 * TODO - this could be improved to be dependent on the rate. 663 * The hardware can keep up at lower rates, but not higher rates 664 */ 665 if (fi->keyix != ATH9K_TXKEYIX_INVALID) 666 ndelim += ATH_AGGR_ENCRYPTDELIM; 667 668 /* 669 * Convert desired mpdu density from microeconds to bytes based 670 * on highest rate in rate series (i.e. first rate) to determine 671 * required minimum length for subframe. Take into account 672 * whether high rate is 20 or 40Mhz and half or full GI. 673 * 674 * If there is no mpdu density restriction, no further calculation 675 * is needed. 676 */ 677 678 if (tid->an->mpdudensity == 0) 679 return ndelim; 680 681 rix = tx_info->control.rates[0].idx; 682 flags = tx_info->control.rates[0].flags; 683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 685 686 if (half_gi) 687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 688 else 689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 690 691 if (nsymbols == 0) 692 nsymbols = 1; 693 694 streams = HT_RC_2_STREAMS(rix); 695 nsymbits = bits_per_symbol[rix % 8][width] * streams; 696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 697 698 if (frmlen < minlen) { 699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 700 ndelim = max(mindelim, ndelim); 701 } 702 703 return ndelim; 704 } 705 706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 707 struct ath_txq *txq, 708 struct ath_atx_tid *tid, 709 struct list_head *bf_q, 710 int *aggr_len) 711 { 712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 713 struct ath_buf *bf, *bf_first, *bf_prev = NULL; 714 int rl = 0, nframes = 0, ndelim, prev_al = 0; 715 u16 aggr_limit = 0, al = 0, bpad = 0, 716 al_delta, h_baw = tid->baw_size / 2; 717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 718 struct ieee80211_tx_info *tx_info; 719 struct ath_frame_info *fi; 720 721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); 722 723 do { 724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 725 fi = get_frame_info(bf->bf_mpdu); 726 727 /* do not step over block-ack window */ 728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) { 729 status = ATH_AGGR_BAW_CLOSED; 730 break; 731 } 732 733 if (!rl) { 734 aggr_limit = ath_lookup_rate(sc, bf, tid); 735 rl = 1; 736 } 737 738 /* do not exceed aggregation limit */ 739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 740 741 if (nframes && 742 (aggr_limit < (al + bpad + al_delta + prev_al))) { 743 status = ATH_AGGR_LIMITED; 744 break; 745 } 746 747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS))) 750 break; 751 752 /* do not exceed subframe limit */ 753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { 754 status = ATH_AGGR_LIMITED; 755 break; 756 } 757 nframes++; 758 759 /* add padding for previous frame to aggregation length */ 760 al += bpad + al_delta; 761 762 /* 763 * Get the delimiters needed to meet the MPDU 764 * density for this node. 765 */ 766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen); 767 bpad = PADBYTES(al_delta) + (ndelim << 2); 768 769 bf->bf_next = NULL; 770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); 771 772 /* link buffers of this frame to the aggregate */ 773 if (!fi->retries) 774 ath_tx_addto_baw(sc, tid, fi->seqno); 775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); 776 list_move_tail(&bf->list, bf_q); 777 if (bf_prev) { 778 bf_prev->bf_next = bf; 779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc, 780 bf->bf_daddr); 781 } 782 bf_prev = bf; 783 784 } while (!list_empty(&tid->buf_q)); 785 786 *aggr_len = al; 787 788 return status; 789 #undef PADBYTES 790 } 791 792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 793 struct ath_atx_tid *tid) 794 { 795 struct ath_buf *bf; 796 enum ATH_AGGR_STATUS status; 797 struct ath_frame_info *fi; 798 struct list_head bf_q; 799 int aggr_len; 800 801 do { 802 if (list_empty(&tid->buf_q)) 803 return; 804 805 INIT_LIST_HEAD(&bf_q); 806 807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len); 808 809 /* 810 * no frames picked up to be aggregated; 811 * block-ack window is not open. 812 */ 813 if (list_empty(&bf_q)) 814 break; 815 816 bf = list_first_entry(&bf_q, struct ath_buf, list); 817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 818 819 /* if only one frame, send as non-aggregate */ 820 if (bf == bf->bf_lastbf) { 821 fi = get_frame_info(bf->bf_mpdu); 822 823 bf->bf_state.bf_type &= ~BUF_AGGR; 824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); 825 ath_buf_set_rate(sc, bf, fi->framelen); 826 ath_tx_txqaddbuf(sc, txq, &bf_q); 827 continue; 828 } 829 830 /* setup first desc of aggregate */ 831 bf->bf_state.bf_type |= BUF_AGGR; 832 ath_buf_set_rate(sc, bf, aggr_len); 833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len); 834 835 /* anchor last desc of aggregate */ 836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 837 838 ath_tx_txqaddbuf(sc, txq, &bf_q); 839 TX_STAT_INC(txq->axq_qnum, a_aggr); 840 841 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && 842 status != ATH_AGGR_BAW_CLOSED); 843 } 844 845 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 846 u16 tid, u16 *ssn) 847 { 848 struct ath_atx_tid *txtid; 849 struct ath_node *an; 850 851 an = (struct ath_node *)sta->drv_priv; 852 txtid = ATH_AN_2_TID(an, tid); 853 854 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) 855 return -EAGAIN; 856 857 txtid->state |= AGGR_ADDBA_PROGRESS; 858 txtid->paused = true; 859 *ssn = txtid->seq_start; 860 861 return 0; 862 } 863 864 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 865 { 866 struct ath_node *an = (struct ath_node *)sta->drv_priv; 867 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 868 struct ath_txq *txq = txtid->ac->txq; 869 870 if (txtid->state & AGGR_CLEANUP) 871 return; 872 873 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 874 txtid->state &= ~AGGR_ADDBA_PROGRESS; 875 return; 876 } 877 878 spin_lock_bh(&txq->axq_lock); 879 txtid->paused = true; 880 881 /* 882 * If frames are still being transmitted for this TID, they will be 883 * cleaned up during tx completion. To prevent race conditions, this 884 * TID can only be reused after all in-progress subframes have been 885 * completed. 886 */ 887 if (txtid->baw_head != txtid->baw_tail) 888 txtid->state |= AGGR_CLEANUP; 889 else 890 txtid->state &= ~AGGR_ADDBA_COMPLETE; 891 spin_unlock_bh(&txq->axq_lock); 892 893 ath_tx_flush_tid(sc, txtid); 894 } 895 896 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 897 { 898 struct ath_atx_tid *txtid; 899 struct ath_node *an; 900 901 an = (struct ath_node *)sta->drv_priv; 902 903 if (sc->sc_flags & SC_OP_TXAGGR) { 904 txtid = ATH_AN_2_TID(an, tid); 905 txtid->baw_size = 906 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 907 txtid->state |= AGGR_ADDBA_COMPLETE; 908 txtid->state &= ~AGGR_ADDBA_PROGRESS; 909 ath_tx_resume_tid(sc, txtid); 910 } 911 } 912 913 /********************/ 914 /* Queue Management */ 915 /********************/ 916 917 static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 918 struct ath_txq *txq) 919 { 920 struct ath_atx_ac *ac, *ac_tmp; 921 struct ath_atx_tid *tid, *tid_tmp; 922 923 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 924 list_del(&ac->list); 925 ac->sched = false; 926 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { 927 list_del(&tid->list); 928 tid->sched = false; 929 ath_tid_drain(sc, txq, tid); 930 } 931 } 932 } 933 934 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 935 { 936 struct ath_hw *ah = sc->sc_ah; 937 struct ath_common *common = ath9k_hw_common(ah); 938 struct ath9k_tx_queue_info qi; 939 static const int subtype_txq_to_hwq[] = { 940 [WME_AC_BE] = ATH_TXQ_AC_BE, 941 [WME_AC_BK] = ATH_TXQ_AC_BK, 942 [WME_AC_VI] = ATH_TXQ_AC_VI, 943 [WME_AC_VO] = ATH_TXQ_AC_VO, 944 }; 945 int qnum, i; 946 947 memset(&qi, 0, sizeof(qi)); 948 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 949 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 950 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 951 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 952 qi.tqi_physCompBuf = 0; 953 954 /* 955 * Enable interrupts only for EOL and DESC conditions. 956 * We mark tx descriptors to receive a DESC interrupt 957 * when a tx queue gets deep; otherwise waiting for the 958 * EOL to reap descriptors. Note that this is done to 959 * reduce interrupt load and this only defers reaping 960 * descriptors, never transmitting frames. Aside from 961 * reducing interrupts this also permits more concurrency. 962 * The only potential downside is if the tx queue backs 963 * up in which case the top half of the kernel may backup 964 * due to a lack of tx descriptors. 965 * 966 * The UAPSD queue is an exception, since we take a desc- 967 * based intr on the EOSP frames. 968 */ 969 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 970 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE | 971 TXQ_FLAG_TXERRINT_ENABLE; 972 } else { 973 if (qtype == ATH9K_TX_QUEUE_UAPSD) 974 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 975 else 976 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 977 TXQ_FLAG_TXDESCINT_ENABLE; 978 } 979 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 980 if (qnum == -1) { 981 /* 982 * NB: don't print a message, this happens 983 * normally on parts with too few tx queues 984 */ 985 return NULL; 986 } 987 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 988 ath_err(common, "qnum %u out of range, max %zu!\n", 989 qnum, ARRAY_SIZE(sc->tx.txq)); 990 ath9k_hw_releasetxqueue(ah, qnum); 991 return NULL; 992 } 993 if (!ATH_TXQ_SETUP(sc, qnum)) { 994 struct ath_txq *txq = &sc->tx.txq[qnum]; 995 996 txq->axq_qnum = qnum; 997 txq->axq_link = NULL; 998 INIT_LIST_HEAD(&txq->axq_q); 999 INIT_LIST_HEAD(&txq->axq_acq); 1000 spin_lock_init(&txq->axq_lock); 1001 txq->axq_depth = 0; 1002 txq->axq_ampdu_depth = 0; 1003 txq->axq_tx_inprogress = false; 1004 sc->tx.txqsetup |= 1<<qnum; 1005 1006 txq->txq_headidx = txq->txq_tailidx = 0; 1007 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1008 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1009 INIT_LIST_HEAD(&txq->txq_fifo_pending); 1010 } 1011 return &sc->tx.txq[qnum]; 1012 } 1013 1014 int ath_txq_update(struct ath_softc *sc, int qnum, 1015 struct ath9k_tx_queue_info *qinfo) 1016 { 1017 struct ath_hw *ah = sc->sc_ah; 1018 int error = 0; 1019 struct ath9k_tx_queue_info qi; 1020 1021 if (qnum == sc->beacon.beaconq) { 1022 /* 1023 * XXX: for beacon queue, we just save the parameter. 1024 * It will be picked up by ath_beaconq_config when 1025 * it's necessary. 1026 */ 1027 sc->beacon.beacon_qi = *qinfo; 1028 return 0; 1029 } 1030 1031 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1032 1033 ath9k_hw_get_txq_props(ah, qnum, &qi); 1034 qi.tqi_aifs = qinfo->tqi_aifs; 1035 qi.tqi_cwmin = qinfo->tqi_cwmin; 1036 qi.tqi_cwmax = qinfo->tqi_cwmax; 1037 qi.tqi_burstTime = qinfo->tqi_burstTime; 1038 qi.tqi_readyTime = qinfo->tqi_readyTime; 1039 1040 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1041 ath_err(ath9k_hw_common(sc->sc_ah), 1042 "Unable to update hardware queue %u!\n", qnum); 1043 error = -EIO; 1044 } else { 1045 ath9k_hw_resettxqueue(ah, qnum); 1046 } 1047 1048 return error; 1049 } 1050 1051 int ath_cabq_update(struct ath_softc *sc) 1052 { 1053 struct ath9k_tx_queue_info qi; 1054 int qnum = sc->beacon.cabq->axq_qnum; 1055 1056 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1057 /* 1058 * Ensure the readytime % is within the bounds. 1059 */ 1060 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) 1061 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; 1062 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) 1063 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; 1064 1065 qi.tqi_readyTime = (sc->beacon_interval * 1066 sc->config.cabqReadytime) / 100; 1067 ath_txq_update(sc, qnum, &qi); 1068 1069 return 0; 1070 } 1071 1072 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 1073 { 1074 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 1075 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1076 } 1077 1078 /* 1079 * Drain a given TX queue (could be Beacon or Data) 1080 * 1081 * This assumes output has been stopped and 1082 * we do not need to block ath_tx_tasklet. 1083 */ 1084 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) 1085 { 1086 struct ath_buf *bf, *lastbf; 1087 struct list_head bf_head; 1088 struct ath_tx_status ts; 1089 1090 memset(&ts, 0, sizeof(ts)); 1091 INIT_LIST_HEAD(&bf_head); 1092 1093 for (;;) { 1094 spin_lock_bh(&txq->axq_lock); 1095 1096 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1097 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 1098 txq->txq_headidx = txq->txq_tailidx = 0; 1099 spin_unlock_bh(&txq->axq_lock); 1100 break; 1101 } else { 1102 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], 1103 struct ath_buf, list); 1104 } 1105 } else { 1106 if (list_empty(&txq->axq_q)) { 1107 txq->axq_link = NULL; 1108 spin_unlock_bh(&txq->axq_lock); 1109 break; 1110 } 1111 bf = list_first_entry(&txq->axq_q, struct ath_buf, 1112 list); 1113 1114 if (bf->bf_stale) { 1115 list_del(&bf->list); 1116 spin_unlock_bh(&txq->axq_lock); 1117 1118 ath_tx_return_buffer(sc, bf); 1119 continue; 1120 } 1121 } 1122 1123 lastbf = bf->bf_lastbf; 1124 1125 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1126 list_cut_position(&bf_head, 1127 &txq->txq_fifo[txq->txq_tailidx], 1128 &lastbf->list); 1129 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 1130 } else { 1131 /* remove ath_buf's of the same mpdu from txq */ 1132 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); 1133 } 1134 1135 txq->axq_depth--; 1136 if (bf_is_ampdu_not_probing(bf)) 1137 txq->axq_ampdu_depth--; 1138 spin_unlock_bh(&txq->axq_lock); 1139 1140 if (bf_isampdu(bf)) 1141 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0, 1142 retry_tx); 1143 else 1144 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); 1145 } 1146 1147 spin_lock_bh(&txq->axq_lock); 1148 txq->axq_tx_inprogress = false; 1149 spin_unlock_bh(&txq->axq_lock); 1150 1151 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1152 spin_lock_bh(&txq->axq_lock); 1153 while (!list_empty(&txq->txq_fifo_pending)) { 1154 bf = list_first_entry(&txq->txq_fifo_pending, 1155 struct ath_buf, list); 1156 list_cut_position(&bf_head, 1157 &txq->txq_fifo_pending, 1158 &bf->bf_lastbf->list); 1159 spin_unlock_bh(&txq->axq_lock); 1160 1161 if (bf_isampdu(bf)) 1162 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 1163 &ts, 0, retry_tx); 1164 else 1165 ath_tx_complete_buf(sc, bf, txq, &bf_head, 1166 &ts, 0, 0); 1167 spin_lock_bh(&txq->axq_lock); 1168 } 1169 spin_unlock_bh(&txq->axq_lock); 1170 } 1171 1172 /* flush any pending frames if aggregation is enabled */ 1173 if (sc->sc_flags & SC_OP_TXAGGR) { 1174 if (!retry_tx) { 1175 spin_lock_bh(&txq->axq_lock); 1176 ath_txq_drain_pending_buffers(sc, txq); 1177 spin_unlock_bh(&txq->axq_lock); 1178 } 1179 } 1180 } 1181 1182 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1183 { 1184 struct ath_hw *ah = sc->sc_ah; 1185 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1186 struct ath_txq *txq; 1187 int i, npend = 0; 1188 1189 if (sc->sc_flags & SC_OP_INVALID) 1190 return true; 1191 1192 /* Stop beacon queue */ 1193 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1194 1195 /* Stop data queues */ 1196 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1197 if (ATH_TXQ_SETUP(sc, i)) { 1198 txq = &sc->tx.txq[i]; 1199 ath9k_hw_stoptxdma(ah, txq->axq_qnum); 1200 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); 1201 } 1202 } 1203 1204 if (npend) 1205 ath_err(common, "Failed to stop TX DMA!\n"); 1206 1207 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1208 if (ATH_TXQ_SETUP(sc, i)) 1209 ath_draintxq(sc, &sc->tx.txq[i], retry_tx); 1210 } 1211 1212 return !npend; 1213 } 1214 1215 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1216 { 1217 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1218 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1219 } 1220 1221 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1222 { 1223 struct ath_atx_ac *ac; 1224 struct ath_atx_tid *tid; 1225 1226 if (list_empty(&txq->axq_acq)) 1227 return; 1228 1229 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); 1230 list_del(&ac->list); 1231 ac->sched = false; 1232 1233 do { 1234 if (list_empty(&ac->tid_q)) 1235 return; 1236 1237 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); 1238 list_del(&tid->list); 1239 tid->sched = false; 1240 1241 if (tid->paused) 1242 continue; 1243 1244 ath_tx_sched_aggr(sc, txq, tid); 1245 1246 /* 1247 * add tid to round-robin queue if more frames 1248 * are pending for the tid 1249 */ 1250 if (!list_empty(&tid->buf_q)) 1251 ath_tx_queue_tid(txq, tid); 1252 1253 break; 1254 } while (!list_empty(&ac->tid_q)); 1255 1256 if (!list_empty(&ac->tid_q)) { 1257 if (!ac->sched) { 1258 ac->sched = true; 1259 list_add_tail(&ac->list, &txq->axq_acq); 1260 } 1261 } 1262 } 1263 1264 /***********/ 1265 /* TX, DMA */ 1266 /***********/ 1267 1268 /* 1269 * Insert a chain of ath_buf (descriptors) on a txq and 1270 * assume the descriptors are already chained together by caller. 1271 */ 1272 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1273 struct list_head *head) 1274 { 1275 struct ath_hw *ah = sc->sc_ah; 1276 struct ath_common *common = ath9k_hw_common(ah); 1277 struct ath_buf *bf; 1278 1279 /* 1280 * Insert the frame on the outbound list and 1281 * pass it on to the hardware. 1282 */ 1283 1284 if (list_empty(head)) 1285 return; 1286 1287 bf = list_first_entry(head, struct ath_buf, list); 1288 1289 ath_dbg(common, ATH_DBG_QUEUE, 1290 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1291 1292 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1293 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) { 1294 list_splice_tail_init(head, &txq->txq_fifo_pending); 1295 return; 1296 } 1297 if (!list_empty(&txq->txq_fifo[txq->txq_headidx])) 1298 ath_dbg(common, ATH_DBG_XMIT, 1299 "Initializing tx fifo %d which is non-empty\n", 1300 txq->txq_headidx); 1301 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]); 1302 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]); 1303 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 1304 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1305 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n", 1306 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1307 } else { 1308 list_splice_tail_init(head, &txq->axq_q); 1309 1310 if (txq->axq_link == NULL) { 1311 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1312 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n", 1313 txq->axq_qnum, ito64(bf->bf_daddr), 1314 bf->bf_desc); 1315 } else { 1316 *txq->axq_link = bf->bf_daddr; 1317 ath_dbg(common, ATH_DBG_XMIT, 1318 "link[%u] (%p)=%llx (%p)\n", 1319 txq->axq_qnum, txq->axq_link, 1320 ito64(bf->bf_daddr), bf->bf_desc); 1321 } 1322 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, 1323 &txq->axq_link); 1324 ath9k_hw_txstart(ah, txq->axq_qnum); 1325 } 1326 txq->axq_depth++; 1327 if (bf_is_ampdu_not_probing(bf)) 1328 txq->axq_ampdu_depth++; 1329 } 1330 1331 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1332 struct ath_buf *bf, struct ath_tx_control *txctl) 1333 { 1334 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1335 struct list_head bf_head; 1336 1337 bf->bf_state.bf_type |= BUF_AMPDU; 1338 TX_STAT_INC(txctl->txq->axq_qnum, a_queued); 1339 1340 /* 1341 * Do not queue to h/w when any of the following conditions is true: 1342 * - there are pending frames in software queue 1343 * - the TID is currently paused for ADDBA/BAR request 1344 * - seqno is not within block-ack window 1345 * - h/w queue depth exceeds low water mark 1346 */ 1347 if (!list_empty(&tid->buf_q) || tid->paused || 1348 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) || 1349 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) { 1350 /* 1351 * Add this frame to software queue for scheduling later 1352 * for aggregation. 1353 */ 1354 list_add_tail(&bf->list, &tid->buf_q); 1355 ath_tx_queue_tid(txctl->txq, tid); 1356 return; 1357 } 1358 1359 INIT_LIST_HEAD(&bf_head); 1360 list_add(&bf->list, &bf_head); 1361 1362 /* Add sub-frame to BAW */ 1363 if (!fi->retries) 1364 ath_tx_addto_baw(sc, tid, fi->seqno); 1365 1366 /* Queue to h/w without aggregation */ 1367 bf->bf_lastbf = bf; 1368 ath_buf_set_rate(sc, bf, fi->framelen); 1369 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head); 1370 } 1371 1372 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1373 struct ath_atx_tid *tid, 1374 struct list_head *bf_head) 1375 { 1376 struct ath_frame_info *fi; 1377 struct ath_buf *bf; 1378 1379 bf = list_first_entry(bf_head, struct ath_buf, list); 1380 bf->bf_state.bf_type &= ~BUF_AMPDU; 1381 1382 /* update starting sequence number for subsequent ADDBA request */ 1383 if (tid) 1384 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 1385 1386 bf->bf_lastbf = bf; 1387 fi = get_frame_info(bf->bf_mpdu); 1388 ath_buf_set_rate(sc, bf, fi->framelen); 1389 ath_tx_txqaddbuf(sc, txq, bf_head); 1390 TX_STAT_INC(txq->axq_qnum, queued); 1391 } 1392 1393 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1394 { 1395 struct ieee80211_hdr *hdr; 1396 enum ath9k_pkt_type htype; 1397 __le16 fc; 1398 1399 hdr = (struct ieee80211_hdr *)skb->data; 1400 fc = hdr->frame_control; 1401 1402 if (ieee80211_is_beacon(fc)) 1403 htype = ATH9K_PKT_TYPE_BEACON; 1404 else if (ieee80211_is_probe_resp(fc)) 1405 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1406 else if (ieee80211_is_atim(fc)) 1407 htype = ATH9K_PKT_TYPE_ATIM; 1408 else if (ieee80211_is_pspoll(fc)) 1409 htype = ATH9K_PKT_TYPE_PSPOLL; 1410 else 1411 htype = ATH9K_PKT_TYPE_NORMAL; 1412 1413 return htype; 1414 } 1415 1416 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, 1417 int framelen) 1418 { 1419 struct ath_wiphy *aphy = hw->priv; 1420 struct ath_softc *sc = aphy->sc; 1421 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1422 struct ieee80211_sta *sta = tx_info->control.sta; 1423 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 1424 struct ieee80211_hdr *hdr; 1425 struct ath_frame_info *fi = get_frame_info(skb); 1426 struct ath_node *an; 1427 struct ath_atx_tid *tid; 1428 enum ath9k_key_type keytype; 1429 u16 seqno = 0; 1430 u8 tidno; 1431 1432 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 1433 1434 hdr = (struct ieee80211_hdr *)skb->data; 1435 if (sta && ieee80211_is_data_qos(hdr->frame_control) && 1436 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) { 1437 1438 an = (struct ath_node *) sta->drv_priv; 1439 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; 1440 1441 /* 1442 * Override seqno set by upper layer with the one 1443 * in tx aggregation state. 1444 */ 1445 tid = ATH_AN_2_TID(an, tidno); 1446 seqno = tid->seq_next; 1447 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT); 1448 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1449 } 1450 1451 memset(fi, 0, sizeof(*fi)); 1452 if (hw_key) 1453 fi->keyix = hw_key->hw_key_idx; 1454 else 1455 fi->keyix = ATH9K_TXKEYIX_INVALID; 1456 fi->keytype = keytype; 1457 fi->framelen = framelen; 1458 fi->seqno = seqno; 1459 } 1460 1461 static int setup_tx_flags(struct sk_buff *skb) 1462 { 1463 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1464 int flags = 0; 1465 1466 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ 1467 flags |= ATH9K_TXDESC_INTREQ; 1468 1469 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1470 flags |= ATH9K_TXDESC_NOACK; 1471 1472 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1473 flags |= ATH9K_TXDESC_LDPC; 1474 1475 return flags; 1476 } 1477 1478 /* 1479 * rix - rate index 1480 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1481 * width - 0 for 20 MHz, 1 for 40 MHz 1482 * half_gi - to use 4us v/s 3.6 us for symbol time 1483 */ 1484 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1485 int width, int half_gi, bool shortPreamble) 1486 { 1487 u32 nbits, nsymbits, duration, nsymbols; 1488 int streams; 1489 1490 /* find number of symbols: PLCP + data */ 1491 streams = HT_RC_2_STREAMS(rix); 1492 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1493 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1494 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1495 1496 if (!half_gi) 1497 duration = SYMBOL_TIME(nsymbols); 1498 else 1499 duration = SYMBOL_TIME_HALFGI(nsymbols); 1500 1501 /* addup duration for legacy/ht training and signal fields */ 1502 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1503 1504 return duration; 1505 } 1506 1507 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 1508 { 1509 struct ath_hw *ah = sc->sc_ah; 1510 struct ath9k_channel *curchan = ah->curchan; 1511 if ((sc->sc_flags & SC_OP_ENABLE_APM) && 1512 (curchan->channelFlags & CHANNEL_5GHZ) && 1513 (chainmask == 0x7) && (rate < 0x90)) 1514 return 0x3; 1515 else 1516 return chainmask; 1517 } 1518 1519 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len) 1520 { 1521 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1522 struct ath9k_11n_rate_series series[4]; 1523 struct sk_buff *skb; 1524 struct ieee80211_tx_info *tx_info; 1525 struct ieee80211_tx_rate *rates; 1526 const struct ieee80211_rate *rate; 1527 struct ieee80211_hdr *hdr; 1528 int i, flags = 0; 1529 u8 rix = 0, ctsrate = 0; 1530 bool is_pspoll; 1531 1532 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 1533 1534 skb = bf->bf_mpdu; 1535 tx_info = IEEE80211_SKB_CB(skb); 1536 rates = tx_info->control.rates; 1537 hdr = (struct ieee80211_hdr *)skb->data; 1538 is_pspoll = ieee80211_is_pspoll(hdr->frame_control); 1539 1540 /* 1541 * We check if Short Preamble is needed for the CTS rate by 1542 * checking the BSS's global flag. 1543 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1544 */ 1545 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); 1546 ctsrate = rate->hw_value; 1547 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 1548 ctsrate |= rate->hw_value_short; 1549 1550 for (i = 0; i < 4; i++) { 1551 bool is_40, is_sgi, is_sp; 1552 int phy; 1553 1554 if (!rates[i].count || (rates[i].idx < 0)) 1555 continue; 1556 1557 rix = rates[i].idx; 1558 series[i].Tries = rates[i].count; 1559 1560 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) || 1561 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) { 1562 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1563 flags |= ATH9K_TXDESC_RTSENA; 1564 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1565 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1566 flags |= ATH9K_TXDESC_CTSENA; 1567 } 1568 1569 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1570 series[i].RateFlags |= ATH9K_RATESERIES_2040; 1571 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1572 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1573 1574 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1575 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1576 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1577 1578 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1579 /* MCS rates */ 1580 series[i].Rate = rix | 0x80; 1581 series[i].ChSel = ath_txchainmask_reduction(sc, 1582 common->tx_chainmask, series[i].Rate); 1583 series[i].PktDuration = ath_pkt_duration(sc, rix, len, 1584 is_40, is_sgi, is_sp); 1585 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1586 series[i].RateFlags |= ATH9K_RATESERIES_STBC; 1587 continue; 1588 } 1589 1590 /* legacy rates */ 1591 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1592 !(rate->flags & IEEE80211_RATE_ERP_G)) 1593 phy = WLAN_RC_PHY_CCK; 1594 else 1595 phy = WLAN_RC_PHY_OFDM; 1596 1597 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; 1598 series[i].Rate = rate->hw_value; 1599 if (rate->hw_value_short) { 1600 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1601 series[i].Rate |= rate->hw_value_short; 1602 } else { 1603 is_sp = false; 1604 } 1605 1606 if (bf->bf_state.bfs_paprd) 1607 series[i].ChSel = common->tx_chainmask; 1608 else 1609 series[i].ChSel = ath_txchainmask_reduction(sc, 1610 common->tx_chainmask, series[i].Rate); 1611 1612 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1613 phy, rate->bitrate * 100, len, rix, is_sp); 1614 } 1615 1616 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1617 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1618 flags &= ~ATH9K_TXDESC_RTSENA; 1619 1620 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1621 if (flags & ATH9K_TXDESC_RTSENA) 1622 flags &= ~ATH9K_TXDESC_CTSENA; 1623 1624 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1625 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 1626 bf->bf_lastbf->bf_desc, 1627 !is_pspoll, ctsrate, 1628 0, series, 4, flags); 1629 1630 if (sc->config.ath_aggr_prot && flags) 1631 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); 1632 } 1633 1634 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw, 1635 struct ath_txq *txq, 1636 struct sk_buff *skb) 1637 { 1638 struct ath_wiphy *aphy = hw->priv; 1639 struct ath_softc *sc = aphy->sc; 1640 struct ath_hw *ah = sc->sc_ah; 1641 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1642 struct ath_frame_info *fi = get_frame_info(skb); 1643 struct ath_buf *bf; 1644 struct ath_desc *ds; 1645 int frm_type; 1646 1647 bf = ath_tx_get_buffer(sc); 1648 if (!bf) { 1649 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n"); 1650 return NULL; 1651 } 1652 1653 ATH_TXBUF_RESET(bf); 1654 1655 bf->aphy = aphy; 1656 bf->bf_flags = setup_tx_flags(skb); 1657 bf->bf_mpdu = skb; 1658 1659 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 1660 skb->len, DMA_TO_DEVICE); 1661 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 1662 bf->bf_mpdu = NULL; 1663 bf->bf_buf_addr = 0; 1664 ath_err(ath9k_hw_common(sc->sc_ah), 1665 "dma_mapping_error() on TX\n"); 1666 ath_tx_return_buffer(sc, bf); 1667 return NULL; 1668 } 1669 1670 frm_type = get_hw_packet_type(skb); 1671 1672 ds = bf->bf_desc; 1673 ath9k_hw_set_desc_link(ah, ds, 0); 1674 1675 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER, 1676 fi->keyix, fi->keytype, bf->bf_flags); 1677 1678 ath9k_hw_filltxdesc(ah, ds, 1679 skb->len, /* segment length */ 1680 true, /* first segment */ 1681 true, /* last segment */ 1682 ds, /* first descriptor */ 1683 bf->bf_buf_addr, 1684 txq->axq_qnum); 1685 1686 1687 return bf; 1688 } 1689 1690 /* FIXME: tx power */ 1691 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, 1692 struct ath_tx_control *txctl) 1693 { 1694 struct sk_buff *skb = bf->bf_mpdu; 1695 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1696 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1697 struct list_head bf_head; 1698 struct ath_atx_tid *tid = NULL; 1699 u8 tidno; 1700 1701 spin_lock_bh(&txctl->txq->axq_lock); 1702 1703 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) { 1704 tidno = ieee80211_get_qos_ctl(hdr)[0] & 1705 IEEE80211_QOS_CTL_TID_MASK; 1706 tid = ATH_AN_2_TID(txctl->an, tidno); 1707 1708 WARN_ON(tid->ac->txq != txctl->txq); 1709 } 1710 1711 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) { 1712 /* 1713 * Try aggregation if it's a unicast data frame 1714 * and the destination is HT capable. 1715 */ 1716 ath_tx_send_ampdu(sc, tid, bf, txctl); 1717 } else { 1718 INIT_LIST_HEAD(&bf_head); 1719 list_add_tail(&bf->list, &bf_head); 1720 1721 bf->bf_state.bfs_ftype = txctl->frame_type; 1722 bf->bf_state.bfs_paprd = txctl->paprd; 1723 1724 if (bf->bf_state.bfs_paprd) 1725 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc, 1726 bf->bf_state.bfs_paprd); 1727 1728 if (txctl->paprd) 1729 bf->bf_state.bfs_paprd_timestamp = jiffies; 1730 1731 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head); 1732 } 1733 1734 spin_unlock_bh(&txctl->txq->axq_lock); 1735 } 1736 1737 /* Upon failure caller should free skb */ 1738 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1739 struct ath_tx_control *txctl) 1740 { 1741 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1742 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1743 struct ieee80211_sta *sta = info->control.sta; 1744 struct ath_wiphy *aphy = hw->priv; 1745 struct ath_softc *sc = aphy->sc; 1746 struct ath_txq *txq = txctl->txq; 1747 struct ath_buf *bf; 1748 int padpos, padsize; 1749 int frmlen = skb->len + FCS_LEN; 1750 int q; 1751 1752 /* NOTE: sta can be NULL according to net/mac80211.h */ 1753 if (sta) 1754 txctl->an = (struct ath_node *)sta->drv_priv; 1755 1756 if (info->control.hw_key) 1757 frmlen += info->control.hw_key->icv_len; 1758 1759 /* 1760 * As a temporary workaround, assign seq# here; this will likely need 1761 * to be cleaned up to work better with Beacon transmission and virtual 1762 * BSSes. 1763 */ 1764 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1765 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1766 sc->tx.seq_no += 0x10; 1767 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1768 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1769 } 1770 1771 /* Add the padding after the header if this is not already done */ 1772 padpos = ath9k_cmn_padpos(hdr->frame_control); 1773 padsize = padpos & 3; 1774 if (padsize && skb->len > padpos) { 1775 if (skb_headroom(skb) < padsize) 1776 return -ENOMEM; 1777 1778 skb_push(skb, padsize); 1779 memmove(skb->data, skb->data + padsize, padpos); 1780 } 1781 1782 setup_frame_info(hw, skb, frmlen); 1783 1784 /* 1785 * At this point, the vif, hw_key and sta pointers in the tx control 1786 * info are no longer valid (overwritten by the ath_frame_info data. 1787 */ 1788 1789 bf = ath_tx_setup_buffer(hw, txctl->txq, skb); 1790 if (unlikely(!bf)) 1791 return -ENOMEM; 1792 1793 q = skb_get_queue_mapping(skb); 1794 spin_lock_bh(&txq->axq_lock); 1795 if (txq == sc->tx.txq_map[q] && 1796 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) { 1797 ath_mac80211_stop_queue(sc, q); 1798 txq->stopped = 1; 1799 } 1800 spin_unlock_bh(&txq->axq_lock); 1801 1802 ath_tx_start_dma(sc, bf, txctl); 1803 1804 return 0; 1805 } 1806 1807 /*****************/ 1808 /* TX Completion */ 1809 /*****************/ 1810 1811 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1812 struct ath_wiphy *aphy, int tx_flags, int ftype, 1813 struct ath_txq *txq) 1814 { 1815 struct ieee80211_hw *hw = sc->hw; 1816 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1817 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1818 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1819 int q, padpos, padsize; 1820 1821 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1822 1823 if (aphy) 1824 hw = aphy->hw; 1825 1826 if (tx_flags & ATH_TX_BAR) 1827 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1828 1829 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { 1830 /* Frame was ACKed */ 1831 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1832 } 1833 1834 padpos = ath9k_cmn_padpos(hdr->frame_control); 1835 padsize = padpos & 3; 1836 if (padsize && skb->len>padpos+padsize) { 1837 /* 1838 * Remove MAC header padding before giving the frame back to 1839 * mac80211. 1840 */ 1841 memmove(skb->data + padsize, skb->data, padpos); 1842 skb_pull(skb, padsize); 1843 } 1844 1845 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { 1846 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 1847 ath_dbg(common, ATH_DBG_PS, 1848 "Going back to sleep after having received TX status (0x%lx)\n", 1849 sc->ps_flags & (PS_WAIT_FOR_BEACON | 1850 PS_WAIT_FOR_CAB | 1851 PS_WAIT_FOR_PSPOLL_DATA | 1852 PS_WAIT_FOR_TX_ACK)); 1853 } 1854 1855 if (unlikely(ftype)) 1856 ath9k_tx_status(hw, skb, ftype); 1857 else { 1858 q = skb_get_queue_mapping(skb); 1859 if (txq == sc->tx.txq_map[q]) { 1860 spin_lock_bh(&txq->axq_lock); 1861 if (WARN_ON(--txq->pending_frames < 0)) 1862 txq->pending_frames = 0; 1863 spin_unlock_bh(&txq->axq_lock); 1864 } 1865 1866 ieee80211_tx_status(hw, skb); 1867 } 1868 } 1869 1870 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1871 struct ath_txq *txq, struct list_head *bf_q, 1872 struct ath_tx_status *ts, int txok, int sendbar) 1873 { 1874 struct sk_buff *skb = bf->bf_mpdu; 1875 unsigned long flags; 1876 int tx_flags = 0; 1877 1878 if (sendbar) 1879 tx_flags = ATH_TX_BAR; 1880 1881 if (!txok) { 1882 tx_flags |= ATH_TX_ERROR; 1883 1884 if (bf_isxretried(bf)) 1885 tx_flags |= ATH_TX_XRETRY; 1886 } 1887 1888 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 1889 bf->bf_buf_addr = 0; 1890 1891 if (bf->bf_state.bfs_paprd) { 1892 if (time_after(jiffies, 1893 bf->bf_state.bfs_paprd_timestamp + 1894 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 1895 dev_kfree_skb_any(skb); 1896 else 1897 complete(&sc->paprd_complete); 1898 } else { 1899 ath_debug_stat_tx(sc, bf, ts); 1900 ath_tx_complete(sc, skb, bf->aphy, tx_flags, 1901 bf->bf_state.bfs_ftype, txq); 1902 } 1903 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 1904 * accidentally reference it later. 1905 */ 1906 bf->bf_mpdu = NULL; 1907 1908 /* 1909 * Return the list of ath_buf of this mpdu to free queue 1910 */ 1911 spin_lock_irqsave(&sc->tx.txbuflock, flags); 1912 list_splice_tail_init(bf_q, &sc->tx.txbuf); 1913 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 1914 } 1915 1916 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, 1917 int nframes, int nbad, int txok, bool update_rc) 1918 { 1919 struct sk_buff *skb = bf->bf_mpdu; 1920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1921 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1922 struct ieee80211_hw *hw = bf->aphy->hw; 1923 struct ath_softc *sc = bf->aphy->sc; 1924 struct ath_hw *ah = sc->sc_ah; 1925 u8 i, tx_rateindex; 1926 1927 if (txok) 1928 tx_info->status.ack_signal = ts->ts_rssi; 1929 1930 tx_rateindex = ts->ts_rateindex; 1931 WARN_ON(tx_rateindex >= hw->max_rates); 1932 1933 if (ts->ts_status & ATH9K_TXERR_FILT) 1934 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1935 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) { 1936 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 1937 1938 BUG_ON(nbad > nframes); 1939 1940 tx_info->status.ampdu_len = nframes; 1941 tx_info->status.ampdu_ack_len = nframes - nbad; 1942 } 1943 1944 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 1945 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1946 /* 1947 * If an underrun error is seen assume it as an excessive 1948 * retry only if max frame trigger level has been reached 1949 * (2 KB for single stream, and 4 KB for dual stream). 1950 * Adjust the long retry as if the frame was tried 1951 * hw->max_rate_tries times to affect how rate control updates 1952 * PER for the failed rate. 1953 * In case of congestion on the bus penalizing this type of 1954 * underruns should help hardware actually transmit new frames 1955 * successfully by eventually preferring slower rates. 1956 * This itself should also alleviate congestion on the bus. 1957 */ 1958 if (ieee80211_is_data(hdr->frame_control) && 1959 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 1960 ATH9K_TX_DELIM_UNDERRUN)) && 1961 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max) 1962 tx_info->status.rates[tx_rateindex].count = 1963 hw->max_rate_tries; 1964 } 1965 1966 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 1967 tx_info->status.rates[i].count = 0; 1968 tx_info->status.rates[i].idx = -1; 1969 } 1970 1971 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 1972 } 1973 1974 static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum) 1975 { 1976 struct ath_txq *txq; 1977 1978 txq = sc->tx.txq_map[qnum]; 1979 spin_lock_bh(&txq->axq_lock); 1980 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) { 1981 if (ath_mac80211_start_queue(sc, qnum)) 1982 txq->stopped = 0; 1983 } 1984 spin_unlock_bh(&txq->axq_lock); 1985 } 1986 1987 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1988 { 1989 struct ath_hw *ah = sc->sc_ah; 1990 struct ath_common *common = ath9k_hw_common(ah); 1991 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1992 struct list_head bf_head; 1993 struct ath_desc *ds; 1994 struct ath_tx_status ts; 1995 int txok; 1996 int status; 1997 int qnum; 1998 1999 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 2000 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2001 txq->axq_link); 2002 2003 for (;;) { 2004 spin_lock_bh(&txq->axq_lock); 2005 if (list_empty(&txq->axq_q)) { 2006 txq->axq_link = NULL; 2007 spin_unlock_bh(&txq->axq_lock); 2008 break; 2009 } 2010 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2011 2012 /* 2013 * There is a race condition that a BH gets scheduled 2014 * after sw writes TxE and before hw re-load the last 2015 * descriptor to get the newly chained one. 2016 * Software must keep the last DONE descriptor as a 2017 * holding descriptor - software does so by marking 2018 * it with the STALE flag. 2019 */ 2020 bf_held = NULL; 2021 if (bf->bf_stale) { 2022 bf_held = bf; 2023 if (list_is_last(&bf_held->list, &txq->axq_q)) { 2024 spin_unlock_bh(&txq->axq_lock); 2025 break; 2026 } else { 2027 bf = list_entry(bf_held->list.next, 2028 struct ath_buf, list); 2029 } 2030 } 2031 2032 lastbf = bf->bf_lastbf; 2033 ds = lastbf->bf_desc; 2034 2035 memset(&ts, 0, sizeof(ts)); 2036 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2037 if (status == -EINPROGRESS) { 2038 spin_unlock_bh(&txq->axq_lock); 2039 break; 2040 } 2041 2042 /* 2043 * Remove ath_buf's of the same transmit unit from txq, 2044 * however leave the last descriptor back as the holding 2045 * descriptor for hw. 2046 */ 2047 lastbf->bf_stale = true; 2048 INIT_LIST_HEAD(&bf_head); 2049 if (!list_is_singular(&lastbf->list)) 2050 list_cut_position(&bf_head, 2051 &txq->axq_q, lastbf->list.prev); 2052 2053 txq->axq_depth--; 2054 txok = !(ts.ts_status & ATH9K_TXERR_MASK); 2055 txq->axq_tx_inprogress = false; 2056 if (bf_held) 2057 list_del(&bf_held->list); 2058 2059 if (bf_is_ampdu_not_probing(bf)) 2060 txq->axq_ampdu_depth--; 2061 spin_unlock_bh(&txq->axq_lock); 2062 2063 if (bf_held) 2064 ath_tx_return_buffer(sc, bf_held); 2065 2066 if (!bf_isampdu(bf)) { 2067 /* 2068 * This frame is sent out as a single frame. 2069 * Use hardware retry status for this frame. 2070 */ 2071 if (ts.ts_status & ATH9K_TXERR_XRETRY) 2072 bf->bf_state.bf_type |= BUF_XRETRY; 2073 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true); 2074 } 2075 2076 qnum = skb_get_queue_mapping(bf->bf_mpdu); 2077 2078 if (bf_isampdu(bf)) 2079 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok, 2080 true); 2081 else 2082 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0); 2083 2084 if (txq == sc->tx.txq_map[qnum]) 2085 ath_wake_mac80211_queue(sc, qnum); 2086 2087 spin_lock_bh(&txq->axq_lock); 2088 if (sc->sc_flags & SC_OP_TXAGGR) 2089 ath_txq_schedule(sc, txq); 2090 spin_unlock_bh(&txq->axq_lock); 2091 } 2092 } 2093 2094 static void ath_tx_complete_poll_work(struct work_struct *work) 2095 { 2096 struct ath_softc *sc = container_of(work, struct ath_softc, 2097 tx_complete_work.work); 2098 struct ath_txq *txq; 2099 int i; 2100 bool needreset = false; 2101 2102 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 2103 if (ATH_TXQ_SETUP(sc, i)) { 2104 txq = &sc->tx.txq[i]; 2105 spin_lock_bh(&txq->axq_lock); 2106 if (txq->axq_depth) { 2107 if (txq->axq_tx_inprogress) { 2108 needreset = true; 2109 spin_unlock_bh(&txq->axq_lock); 2110 break; 2111 } else { 2112 txq->axq_tx_inprogress = true; 2113 } 2114 } 2115 spin_unlock_bh(&txq->axq_lock); 2116 } 2117 2118 if (needreset) { 2119 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, 2120 "tx hung, resetting the chip\n"); 2121 ath_reset(sc, true); 2122 } 2123 2124 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2125 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); 2126 } 2127 2128 2129 2130 void ath_tx_tasklet(struct ath_softc *sc) 2131 { 2132 int i; 2133 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); 2134 2135 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); 2136 2137 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2138 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2139 ath_tx_processq(sc, &sc->tx.txq[i]); 2140 } 2141 } 2142 2143 void ath_tx_edma_tasklet(struct ath_softc *sc) 2144 { 2145 struct ath_tx_status txs; 2146 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2147 struct ath_hw *ah = sc->sc_ah; 2148 struct ath_txq *txq; 2149 struct ath_buf *bf, *lastbf; 2150 struct list_head bf_head; 2151 int status; 2152 int txok; 2153 int qnum; 2154 2155 for (;;) { 2156 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs); 2157 if (status == -EINPROGRESS) 2158 break; 2159 if (status == -EIO) { 2160 ath_dbg(common, ATH_DBG_XMIT, 2161 "Error processing tx status\n"); 2162 break; 2163 } 2164 2165 /* Skip beacon completions */ 2166 if (txs.qid == sc->beacon.beaconq) 2167 continue; 2168 2169 txq = &sc->tx.txq[txs.qid]; 2170 2171 spin_lock_bh(&txq->axq_lock); 2172 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2173 spin_unlock_bh(&txq->axq_lock); 2174 return; 2175 } 2176 2177 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], 2178 struct ath_buf, list); 2179 lastbf = bf->bf_lastbf; 2180 2181 INIT_LIST_HEAD(&bf_head); 2182 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], 2183 &lastbf->list); 2184 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2185 txq->axq_depth--; 2186 txq->axq_tx_inprogress = false; 2187 if (bf_is_ampdu_not_probing(bf)) 2188 txq->axq_ampdu_depth--; 2189 spin_unlock_bh(&txq->axq_lock); 2190 2191 txok = !(txs.ts_status & ATH9K_TXERR_MASK); 2192 2193 if (!bf_isampdu(bf)) { 2194 if (txs.ts_status & ATH9K_TXERR_XRETRY) 2195 bf->bf_state.bf_type |= BUF_XRETRY; 2196 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true); 2197 } 2198 2199 qnum = skb_get_queue_mapping(bf->bf_mpdu); 2200 2201 if (bf_isampdu(bf)) 2202 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, 2203 txok, true); 2204 else 2205 ath_tx_complete_buf(sc, bf, txq, &bf_head, 2206 &txs, txok, 0); 2207 2208 if (txq == sc->tx.txq_map[qnum]) 2209 ath_wake_mac80211_queue(sc, qnum); 2210 2211 spin_lock_bh(&txq->axq_lock); 2212 if (!list_empty(&txq->txq_fifo_pending)) { 2213 INIT_LIST_HEAD(&bf_head); 2214 bf = list_first_entry(&txq->txq_fifo_pending, 2215 struct ath_buf, list); 2216 list_cut_position(&bf_head, &txq->txq_fifo_pending, 2217 &bf->bf_lastbf->list); 2218 ath_tx_txqaddbuf(sc, txq, &bf_head); 2219 } else if (sc->sc_flags & SC_OP_TXAGGR) 2220 ath_txq_schedule(sc, txq); 2221 spin_unlock_bh(&txq->axq_lock); 2222 } 2223 } 2224 2225 /*****************/ 2226 /* Init, Cleanup */ 2227 /*****************/ 2228 2229 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2230 { 2231 struct ath_descdma *dd = &sc->txsdma; 2232 u8 txs_len = sc->sc_ah->caps.txs_len; 2233 2234 dd->dd_desc_len = size * txs_len; 2235 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, 2236 &dd->dd_desc_paddr, GFP_KERNEL); 2237 if (!dd->dd_desc) 2238 return -ENOMEM; 2239 2240 return 0; 2241 } 2242 2243 static int ath_tx_edma_init(struct ath_softc *sc) 2244 { 2245 int err; 2246 2247 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2248 if (!err) 2249 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2250 sc->txsdma.dd_desc_paddr, 2251 ATH_TXSTATUS_RING_SIZE); 2252 2253 return err; 2254 } 2255 2256 static void ath_tx_edma_cleanup(struct ath_softc *sc) 2257 { 2258 struct ath_descdma *dd = &sc->txsdma; 2259 2260 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, 2261 dd->dd_desc_paddr); 2262 } 2263 2264 int ath_tx_init(struct ath_softc *sc, int nbufs) 2265 { 2266 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2267 int error = 0; 2268 2269 spin_lock_init(&sc->tx.txbuflock); 2270 2271 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2272 "tx", nbufs, 1, 1); 2273 if (error != 0) { 2274 ath_err(common, 2275 "Failed to allocate tx descriptors: %d\n", error); 2276 goto err; 2277 } 2278 2279 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2280 "beacon", ATH_BCBUF, 1, 1); 2281 if (error != 0) { 2282 ath_err(common, 2283 "Failed to allocate beacon descriptors: %d\n", error); 2284 goto err; 2285 } 2286 2287 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2288 2289 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 2290 error = ath_tx_edma_init(sc); 2291 if (error) 2292 goto err; 2293 } 2294 2295 err: 2296 if (error != 0) 2297 ath_tx_cleanup(sc); 2298 2299 return error; 2300 } 2301 2302 void ath_tx_cleanup(struct ath_softc *sc) 2303 { 2304 if (sc->beacon.bdma.dd_desc_len != 0) 2305 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); 2306 2307 if (sc->tx.txdma.dd_desc_len != 0) 2308 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2309 2310 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2311 ath_tx_edma_cleanup(sc); 2312 } 2313 2314 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2315 { 2316 struct ath_atx_tid *tid; 2317 struct ath_atx_ac *ac; 2318 int tidno, acno; 2319 2320 for (tidno = 0, tid = &an->tid[tidno]; 2321 tidno < WME_NUM_TID; 2322 tidno++, tid++) { 2323 tid->an = an; 2324 tid->tidno = tidno; 2325 tid->seq_start = tid->seq_next = 0; 2326 tid->baw_size = WME_MAX_BA; 2327 tid->baw_head = tid->baw_tail = 0; 2328 tid->sched = false; 2329 tid->paused = false; 2330 tid->state &= ~AGGR_CLEANUP; 2331 INIT_LIST_HEAD(&tid->buf_q); 2332 acno = TID_TO_WME_AC(tidno); 2333 tid->ac = &an->ac[acno]; 2334 tid->state &= ~AGGR_ADDBA_COMPLETE; 2335 tid->state &= ~AGGR_ADDBA_PROGRESS; 2336 } 2337 2338 for (acno = 0, ac = &an->ac[acno]; 2339 acno < WME_NUM_AC; acno++, ac++) { 2340 ac->sched = false; 2341 ac->txq = sc->tx.txq_map[acno]; 2342 INIT_LIST_HEAD(&ac->tid_q); 2343 } 2344 } 2345 2346 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2347 { 2348 struct ath_atx_ac *ac; 2349 struct ath_atx_tid *tid; 2350 struct ath_txq *txq; 2351 int tidno; 2352 2353 for (tidno = 0, tid = &an->tid[tidno]; 2354 tidno < WME_NUM_TID; tidno++, tid++) { 2355 2356 ac = tid->ac; 2357 txq = ac->txq; 2358 2359 spin_lock_bh(&txq->axq_lock); 2360 2361 if (tid->sched) { 2362 list_del(&tid->list); 2363 tid->sched = false; 2364 } 2365 2366 if (ac->sched) { 2367 list_del(&ac->list); 2368 tid->ac->sched = false; 2369 } 2370 2371 ath_tid_drain(sc, txq, tid); 2372 tid->state &= ~AGGR_ADDBA_COMPLETE; 2373 tid->state &= ~AGGR_CLEANUP; 2374 2375 spin_unlock_bh(&txq->axq_lock); 2376 } 2377 } 2378