1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38 static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48 }; 49 50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq, 54 struct ieee80211_sta *sta); 55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 56 struct ath_txq *txq, struct list_head *bf_q, 57 struct ieee80211_sta *sta, 58 struct ath_tx_status *ts, int txok); 59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 60 struct list_head *head, bool internal); 61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_tx_status *ts, int nframes, int nbad, 63 int txok); 64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 65 int seqno); 66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 67 struct ath_txq *txq, 68 struct ath_atx_tid *tid, 69 struct sk_buff *skb); 70 71 enum { 72 MCS_HT20, 73 MCS_HT20_SGI, 74 MCS_HT40, 75 MCS_HT40_SGI, 76 }; 77 78 /*********************/ 79 /* Aggregation logic */ 80 /*********************/ 81 82 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 83 { 84 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 85 struct ieee80211_sta *sta = info->status.status_driver_data[0]; 86 87 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 88 ieee80211_tx_status(hw, skb); 89 return; 90 } 91 92 if (sta) 93 ieee80211_tx_status_noskb(hw, sta, info); 94 95 dev_kfree_skb(skb); 96 } 97 98 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 99 __acquires(&txq->axq_lock) 100 { 101 spin_lock_bh(&txq->axq_lock); 102 } 103 104 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 105 __releases(&txq->axq_lock) 106 { 107 spin_unlock_bh(&txq->axq_lock); 108 } 109 110 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 111 __releases(&txq->axq_lock) 112 { 113 struct ieee80211_hw *hw = sc->hw; 114 struct sk_buff_head q; 115 struct sk_buff *skb; 116 117 __skb_queue_head_init(&q); 118 skb_queue_splice_init(&txq->complete_q, &q); 119 spin_unlock_bh(&txq->axq_lock); 120 121 while ((skb = __skb_dequeue(&q))) 122 ath_tx_status(hw, skb); 123 } 124 125 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq, 126 struct ath_atx_tid *tid) 127 { 128 struct list_head *list; 129 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 130 struct ath_chanctx *ctx = avp->chanctx; 131 132 if (!ctx) 133 return; 134 135 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; 136 if (list_empty(&tid->list)) 137 list_add_tail(&tid->list, list); 138 } 139 140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 141 { 142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 143 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 144 sizeof(tx_info->rate_driver_data)); 145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 146 } 147 148 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 149 { 150 if (!tid->an->sta) 151 return; 152 153 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 154 seqno << IEEE80211_SEQ_SEQ_SHIFT); 155 } 156 157 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 158 struct ath_buf *bf) 159 { 160 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 161 ARRAY_SIZE(bf->rates)); 162 } 163 164 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 165 struct sk_buff *skb) 166 { 167 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 168 struct ath_frame_info *fi = get_frame_info(skb); 169 int q = fi->txq; 170 171 if (q < 0) 172 return; 173 174 txq = sc->tx.txq_map[q]; 175 if (WARN_ON(--txq->pending_frames < 0)) 176 txq->pending_frames = 0; 177 178 if (txq->stopped && 179 txq->pending_frames < sc->tx.txq_max_pending[q]) { 180 if (ath9k_is_chanctx_enabled()) 181 ieee80211_wake_queue(sc->hw, info->hw_queue); 182 else 183 ieee80211_wake_queue(sc->hw, q); 184 txq->stopped = false; 185 } 186 } 187 188 static struct ath_atx_tid * 189 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 190 { 191 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 192 return ATH_AN_2_TID(an, tidno); 193 } 194 195 static bool ath_tid_has_buffered(struct ath_atx_tid *tid) 196 { 197 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q); 198 } 199 200 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) 201 { 202 struct sk_buff *skb; 203 204 skb = __skb_dequeue(&tid->retry_q); 205 if (!skb) 206 skb = __skb_dequeue(&tid->buf_q); 207 208 return skb; 209 } 210 211 /* 212 * ath_tx_tid_change_state: 213 * - clears a-mpdu flag of previous session 214 * - force sequence number allocation to fix next BlockAck Window 215 */ 216 static void 217 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid) 218 { 219 struct ath_txq *txq = tid->txq; 220 struct ieee80211_tx_info *tx_info; 221 struct sk_buff *skb, *tskb; 222 struct ath_buf *bf; 223 struct ath_frame_info *fi; 224 225 skb_queue_walk_safe(&tid->buf_q, skb, tskb) { 226 fi = get_frame_info(skb); 227 bf = fi->bf; 228 229 tx_info = IEEE80211_SKB_CB(skb); 230 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 231 232 if (bf) 233 continue; 234 235 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 236 if (!bf) { 237 __skb_unlink(skb, &tid->buf_q); 238 ath_txq_skb_done(sc, txq, skb); 239 ieee80211_free_txskb(sc->hw, skb); 240 continue; 241 } 242 } 243 244 } 245 246 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 247 { 248 struct ath_txq *txq = tid->txq; 249 struct sk_buff *skb; 250 struct ath_buf *bf; 251 struct list_head bf_head; 252 struct ath_tx_status ts; 253 struct ath_frame_info *fi; 254 bool sendbar = false; 255 256 INIT_LIST_HEAD(&bf_head); 257 258 memset(&ts, 0, sizeof(ts)); 259 260 while ((skb = __skb_dequeue(&tid->retry_q))) { 261 fi = get_frame_info(skb); 262 bf = fi->bf; 263 if (!bf) { 264 ath_txq_skb_done(sc, txq, skb); 265 ieee80211_free_txskb(sc->hw, skb); 266 continue; 267 } 268 269 if (fi->baw_tracked) { 270 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 271 sendbar = true; 272 } 273 274 list_add_tail(&bf->list, &bf_head); 275 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 276 } 277 278 if (sendbar) { 279 ath_txq_unlock(sc, txq); 280 ath_send_bar(tid, tid->seq_start); 281 ath_txq_lock(sc, txq); 282 } 283 } 284 285 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 286 int seqno) 287 { 288 int index, cindex; 289 290 index = ATH_BA_INDEX(tid->seq_start, seqno); 291 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 292 293 __clear_bit(cindex, tid->tx_buf); 294 295 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 296 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 297 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 298 if (tid->bar_index >= 0) 299 tid->bar_index--; 300 } 301 } 302 303 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 304 struct ath_buf *bf) 305 { 306 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 307 u16 seqno = bf->bf_state.seqno; 308 int index, cindex; 309 310 index = ATH_BA_INDEX(tid->seq_start, seqno); 311 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 312 __set_bit(cindex, tid->tx_buf); 313 fi->baw_tracked = 1; 314 315 if (index >= ((tid->baw_tail - tid->baw_head) & 316 (ATH_TID_MAX_BUFS - 1))) { 317 tid->baw_tail = cindex; 318 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 319 } 320 } 321 322 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 323 struct ath_atx_tid *tid) 324 325 { 326 struct sk_buff *skb; 327 struct ath_buf *bf; 328 struct list_head bf_head; 329 struct ath_tx_status ts; 330 struct ath_frame_info *fi; 331 332 memset(&ts, 0, sizeof(ts)); 333 INIT_LIST_HEAD(&bf_head); 334 335 while ((skb = ath_tid_dequeue(tid))) { 336 fi = get_frame_info(skb); 337 bf = fi->bf; 338 339 if (!bf) { 340 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); 341 continue; 342 } 343 344 list_add_tail(&bf->list, &bf_head); 345 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 346 } 347 } 348 349 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 350 struct sk_buff *skb, int count) 351 { 352 struct ath_frame_info *fi = get_frame_info(skb); 353 struct ath_buf *bf = fi->bf; 354 struct ieee80211_hdr *hdr; 355 int prev = fi->retries; 356 357 TX_STAT_INC(txq->axq_qnum, a_retries); 358 fi->retries += count; 359 360 if (prev > 0) 361 return; 362 363 hdr = (struct ieee80211_hdr *)skb->data; 364 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 365 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 366 sizeof(*hdr), DMA_TO_DEVICE); 367 } 368 369 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 370 { 371 struct ath_buf *bf = NULL; 372 373 spin_lock_bh(&sc->tx.txbuflock); 374 375 if (unlikely(list_empty(&sc->tx.txbuf))) { 376 spin_unlock_bh(&sc->tx.txbuflock); 377 return NULL; 378 } 379 380 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 381 list_del(&bf->list); 382 383 spin_unlock_bh(&sc->tx.txbuflock); 384 385 return bf; 386 } 387 388 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 389 { 390 spin_lock_bh(&sc->tx.txbuflock); 391 list_add_tail(&bf->list, &sc->tx.txbuf); 392 spin_unlock_bh(&sc->tx.txbuflock); 393 } 394 395 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 396 { 397 struct ath_buf *tbf; 398 399 tbf = ath_tx_get_buffer(sc); 400 if (WARN_ON(!tbf)) 401 return NULL; 402 403 ATH_TXBUF_RESET(tbf); 404 405 tbf->bf_mpdu = bf->bf_mpdu; 406 tbf->bf_buf_addr = bf->bf_buf_addr; 407 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 408 tbf->bf_state = bf->bf_state; 409 tbf->bf_state.stale = false; 410 411 return tbf; 412 } 413 414 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 415 struct ath_tx_status *ts, int txok, 416 int *nframes, int *nbad) 417 { 418 struct ath_frame_info *fi; 419 u16 seq_st = 0; 420 u32 ba[WME_BA_BMP_SIZE >> 5]; 421 int ba_index; 422 int isaggr = 0; 423 424 *nbad = 0; 425 *nframes = 0; 426 427 isaggr = bf_isaggr(bf); 428 if (isaggr) { 429 seq_st = ts->ts_seqnum; 430 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 431 } 432 433 while (bf) { 434 fi = get_frame_info(bf->bf_mpdu); 435 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 436 437 (*nframes)++; 438 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 439 (*nbad)++; 440 441 bf = bf->bf_next; 442 } 443 } 444 445 446 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 447 struct ath_buf *bf, struct list_head *bf_q, 448 struct ieee80211_sta *sta, 449 struct ath_atx_tid *tid, 450 struct ath_tx_status *ts, int txok) 451 { 452 struct ath_node *an = NULL; 453 struct sk_buff *skb; 454 struct ieee80211_hdr *hdr; 455 struct ieee80211_tx_info *tx_info; 456 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 457 struct list_head bf_head; 458 struct sk_buff_head bf_pending; 459 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 460 u32 ba[WME_BA_BMP_SIZE >> 5]; 461 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 462 bool rc_update = true, isba; 463 struct ieee80211_tx_rate rates[4]; 464 struct ath_frame_info *fi; 465 int nframes; 466 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 467 int i, retries; 468 int bar_index = -1; 469 470 skb = bf->bf_mpdu; 471 hdr = (struct ieee80211_hdr *)skb->data; 472 473 tx_info = IEEE80211_SKB_CB(skb); 474 475 memcpy(rates, bf->rates, sizeof(rates)); 476 477 retries = ts->ts_longretry + 1; 478 for (i = 0; i < ts->ts_rateindex; i++) 479 retries += rates[i].count; 480 481 if (!sta) { 482 INIT_LIST_HEAD(&bf_head); 483 while (bf) { 484 bf_next = bf->bf_next; 485 486 if (!bf->bf_state.stale || bf_next != NULL) 487 list_move_tail(&bf->list, &bf_head); 488 489 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); 490 491 bf = bf_next; 492 } 493 return; 494 } 495 496 an = (struct ath_node *)sta->drv_priv; 497 seq_first = tid->seq_start; 498 isba = ts->ts_flags & ATH9K_TX_BA; 499 500 /* 501 * The hardware occasionally sends a tx status for the wrong TID. 502 * In this case, the BA status cannot be considered valid and all 503 * subframes need to be retransmitted 504 * 505 * Only BlockAcks have a TID and therefore normal Acks cannot be 506 * checked 507 */ 508 if (isba && tid->tidno != ts->tid) 509 txok = false; 510 511 isaggr = bf_isaggr(bf); 512 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 513 514 if (isaggr && txok) { 515 if (ts->ts_flags & ATH9K_TX_BA) { 516 seq_st = ts->ts_seqnum; 517 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 518 } else { 519 /* 520 * AR5416 can become deaf/mute when BA 521 * issue happens. Chip needs to be reset. 522 * But AP code may have sychronization issues 523 * when perform internal reset in this routine. 524 * Only enable reset in STA mode for now. 525 */ 526 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 527 needreset = 1; 528 } 529 } 530 531 __skb_queue_head_init(&bf_pending); 532 533 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 534 while (bf) { 535 u16 seqno = bf->bf_state.seqno; 536 537 txfail = txpending = sendbar = 0; 538 bf_next = bf->bf_next; 539 540 skb = bf->bf_mpdu; 541 tx_info = IEEE80211_SKB_CB(skb); 542 fi = get_frame_info(skb); 543 544 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 545 !tid->active) { 546 /* 547 * Outside of the current BlockAck window, 548 * maybe part of a previous session 549 */ 550 txfail = 1; 551 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 552 /* transmit completion, subframe is 553 * acked by block ack */ 554 acked_cnt++; 555 } else if (!isaggr && txok) { 556 /* transmit completion */ 557 acked_cnt++; 558 } else if (flush) { 559 txpending = 1; 560 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 561 if (txok || !an->sleeping) 562 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 563 retries); 564 565 txpending = 1; 566 } else { 567 txfail = 1; 568 txfail_cnt++; 569 bar_index = max_t(int, bar_index, 570 ATH_BA_INDEX(seq_first, seqno)); 571 } 572 573 /* 574 * Make sure the last desc is reclaimed if it 575 * not a holding desc. 576 */ 577 INIT_LIST_HEAD(&bf_head); 578 if (bf_next != NULL || !bf_last->bf_state.stale) 579 list_move_tail(&bf->list, &bf_head); 580 581 if (!txpending) { 582 /* 583 * complete the acked-ones/xretried ones; update 584 * block-ack window 585 */ 586 ath_tx_update_baw(sc, tid, seqno); 587 588 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 589 memcpy(tx_info->control.rates, rates, sizeof(rates)); 590 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 591 rc_update = false; 592 if (bf == bf->bf_lastbf) 593 ath_dynack_sample_tx_ts(sc->sc_ah, 594 bf->bf_mpdu, 595 ts); 596 } 597 598 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, 599 !txfail); 600 } else { 601 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 602 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 603 ieee80211_sta_eosp(sta); 604 } 605 /* retry the un-acked ones */ 606 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 607 struct ath_buf *tbf; 608 609 tbf = ath_clone_txbuf(sc, bf_last); 610 /* 611 * Update tx baw and complete the 612 * frame with failed status if we 613 * run out of tx buf. 614 */ 615 if (!tbf) { 616 ath_tx_update_baw(sc, tid, seqno); 617 618 ath_tx_complete_buf(sc, bf, txq, 619 &bf_head, NULL, ts, 620 0); 621 bar_index = max_t(int, bar_index, 622 ATH_BA_INDEX(seq_first, seqno)); 623 break; 624 } 625 626 fi->bf = tbf; 627 } 628 629 /* 630 * Put this buffer to the temporary pending 631 * queue to retain ordering 632 */ 633 __skb_queue_tail(&bf_pending, skb); 634 } 635 636 bf = bf_next; 637 } 638 639 /* prepend un-acked frames to the beginning of the pending frame queue */ 640 if (!skb_queue_empty(&bf_pending)) { 641 if (an->sleeping) 642 ieee80211_sta_set_buffered(sta, tid->tidno, true); 643 644 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 645 if (!an->sleeping) { 646 ath_tx_queue_tid(sc, txq, tid); 647 648 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 649 tid->clear_ps_filter = true; 650 } 651 } 652 653 if (bar_index >= 0) { 654 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 655 656 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 657 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 658 659 ath_txq_unlock(sc, txq); 660 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 661 ath_txq_lock(sc, txq); 662 } 663 664 if (needreset) 665 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 666 } 667 668 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 669 { 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 671 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 672 } 673 674 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 675 struct ath_tx_status *ts, struct ath_buf *bf, 676 struct list_head *bf_head) 677 { 678 struct ieee80211_hw *hw = sc->hw; 679 struct ieee80211_tx_info *info; 680 struct ieee80211_sta *sta; 681 struct ieee80211_hdr *hdr; 682 struct ath_atx_tid *tid = NULL; 683 bool txok, flush; 684 685 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 686 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 687 txq->axq_tx_inprogress = false; 688 689 txq->axq_depth--; 690 if (bf_is_ampdu_not_probing(bf)) 691 txq->axq_ampdu_depth--; 692 693 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 694 ts->ts_rateindex); 695 696 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 697 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 698 if (sta) { 699 struct ath_node *an = (struct ath_node *)sta->drv_priv; 700 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu); 701 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 702 tid->clear_ps_filter = true; 703 } 704 705 if (!bf_isampdu(bf)) { 706 if (!flush) { 707 info = IEEE80211_SKB_CB(bf->bf_mpdu); 708 memcpy(info->control.rates, bf->rates, 709 sizeof(info->control.rates)); 710 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 711 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); 712 } 713 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); 714 } else 715 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); 716 717 if (!flush) 718 ath_txq_schedule(sc, txq); 719 } 720 721 static bool ath_lookup_legacy(struct ath_buf *bf) 722 { 723 struct sk_buff *skb; 724 struct ieee80211_tx_info *tx_info; 725 struct ieee80211_tx_rate *rates; 726 int i; 727 728 skb = bf->bf_mpdu; 729 tx_info = IEEE80211_SKB_CB(skb); 730 rates = tx_info->control.rates; 731 732 for (i = 0; i < 4; i++) { 733 if (!rates[i].count || rates[i].idx < 0) 734 break; 735 736 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 737 return true; 738 } 739 740 return false; 741 } 742 743 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 744 struct ath_atx_tid *tid) 745 { 746 struct sk_buff *skb; 747 struct ieee80211_tx_info *tx_info; 748 struct ieee80211_tx_rate *rates; 749 u32 max_4ms_framelen, frmlen; 750 u16 aggr_limit, bt_aggr_limit, legacy = 0; 751 int q = tid->txq->mac80211_qnum; 752 int i; 753 754 skb = bf->bf_mpdu; 755 tx_info = IEEE80211_SKB_CB(skb); 756 rates = bf->rates; 757 758 /* 759 * Find the lowest frame length among the rate series that will have a 760 * 4ms (or TXOP limited) transmit duration. 761 */ 762 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 763 764 for (i = 0; i < 4; i++) { 765 int modeidx; 766 767 if (!rates[i].count) 768 continue; 769 770 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 771 legacy = 1; 772 break; 773 } 774 775 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 776 modeidx = MCS_HT40; 777 else 778 modeidx = MCS_HT20; 779 780 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 781 modeidx++; 782 783 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 784 max_4ms_framelen = min(max_4ms_framelen, frmlen); 785 } 786 787 /* 788 * limit aggregate size by the minimum rate if rate selected is 789 * not a probe rate, if rate selected is a probe rate then 790 * avoid aggregation of this packet. 791 */ 792 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 793 return 0; 794 795 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 796 797 /* 798 * Override the default aggregation limit for BTCOEX. 799 */ 800 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 801 if (bt_aggr_limit) 802 aggr_limit = bt_aggr_limit; 803 804 if (tid->an->maxampdu) 805 aggr_limit = min(aggr_limit, tid->an->maxampdu); 806 807 return aggr_limit; 808 } 809 810 /* 811 * Returns the number of delimiters to be added to 812 * meet the minimum required mpdudensity. 813 */ 814 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 815 struct ath_buf *bf, u16 frmlen, 816 bool first_subfrm) 817 { 818 #define FIRST_DESC_NDELIMS 60 819 u32 nsymbits, nsymbols; 820 u16 minlen; 821 u8 flags, rix; 822 int width, streams, half_gi, ndelim, mindelim; 823 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 824 825 /* Select standard number of delimiters based on frame length alone */ 826 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 827 828 /* 829 * If encryption enabled, hardware requires some more padding between 830 * subframes. 831 * TODO - this could be improved to be dependent on the rate. 832 * The hardware can keep up at lower rates, but not higher rates 833 */ 834 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 835 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 836 ndelim += ATH_AGGR_ENCRYPTDELIM; 837 838 /* 839 * Add delimiter when using RTS/CTS with aggregation 840 * and non enterprise AR9003 card 841 */ 842 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 843 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 844 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 845 846 /* 847 * Convert desired mpdu density from microeconds to bytes based 848 * on highest rate in rate series (i.e. first rate) to determine 849 * required minimum length for subframe. Take into account 850 * whether high rate is 20 or 40Mhz and half or full GI. 851 * 852 * If there is no mpdu density restriction, no further calculation 853 * is needed. 854 */ 855 856 if (tid->an->mpdudensity == 0) 857 return ndelim; 858 859 rix = bf->rates[0].idx; 860 flags = bf->rates[0].flags; 861 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 862 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 863 864 if (half_gi) 865 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 866 else 867 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 868 869 if (nsymbols == 0) 870 nsymbols = 1; 871 872 streams = HT_RC_2_STREAMS(rix); 873 nsymbits = bits_per_symbol[rix % 8][width] * streams; 874 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 875 876 if (frmlen < minlen) { 877 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 878 ndelim = max(mindelim, ndelim); 879 } 880 881 return ndelim; 882 } 883 884 static struct ath_buf * 885 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 886 struct ath_atx_tid *tid, struct sk_buff_head **q) 887 { 888 struct ieee80211_tx_info *tx_info; 889 struct ath_frame_info *fi; 890 struct sk_buff *skb; 891 struct ath_buf *bf; 892 u16 seqno; 893 894 while (1) { 895 *q = &tid->retry_q; 896 if (skb_queue_empty(*q)) 897 *q = &tid->buf_q; 898 899 skb = skb_peek(*q); 900 if (!skb) 901 break; 902 903 fi = get_frame_info(skb); 904 bf = fi->bf; 905 if (!fi->bf) 906 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 907 else 908 bf->bf_state.stale = false; 909 910 if (!bf) { 911 __skb_unlink(skb, *q); 912 ath_txq_skb_done(sc, txq, skb); 913 ieee80211_free_txskb(sc->hw, skb); 914 continue; 915 } 916 917 bf->bf_next = NULL; 918 bf->bf_lastbf = bf; 919 920 tx_info = IEEE80211_SKB_CB(skb); 921 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 922 923 /* 924 * No aggregation session is running, but there may be frames 925 * from a previous session or a failed attempt in the queue. 926 * Send them out as normal data frames 927 */ 928 if (!tid->active) 929 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 930 931 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 932 bf->bf_state.bf_type = 0; 933 return bf; 934 } 935 936 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 937 seqno = bf->bf_state.seqno; 938 939 /* do not step over block-ack window */ 940 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) 941 break; 942 943 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 944 struct ath_tx_status ts = {}; 945 struct list_head bf_head; 946 947 INIT_LIST_HEAD(&bf_head); 948 list_add(&bf->list, &bf_head); 949 __skb_unlink(skb, *q); 950 ath_tx_update_baw(sc, tid, seqno); 951 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 952 continue; 953 } 954 955 return bf; 956 } 957 958 return NULL; 959 } 960 961 static bool 962 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 963 struct ath_atx_tid *tid, struct list_head *bf_q, 964 struct ath_buf *bf_first, struct sk_buff_head *tid_q, 965 int *aggr_len) 966 { 967 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 968 struct ath_buf *bf = bf_first, *bf_prev = NULL; 969 int nframes = 0, ndelim; 970 u16 aggr_limit = 0, al = 0, bpad = 0, 971 al_delta, h_baw = tid->baw_size / 2; 972 struct ieee80211_tx_info *tx_info; 973 struct ath_frame_info *fi; 974 struct sk_buff *skb; 975 bool closed = false; 976 977 bf = bf_first; 978 aggr_limit = ath_lookup_rate(sc, bf, tid); 979 980 do { 981 skb = bf->bf_mpdu; 982 fi = get_frame_info(skb); 983 984 /* do not exceed aggregation limit */ 985 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 986 if (nframes) { 987 if (aggr_limit < al + bpad + al_delta || 988 ath_lookup_legacy(bf) || nframes >= h_baw) 989 break; 990 991 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 992 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 993 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 994 break; 995 } 996 997 /* add padding for previous frame to aggregation length */ 998 al += bpad + al_delta; 999 1000 /* 1001 * Get the delimiters needed to meet the MPDU 1002 * density for this node. 1003 */ 1004 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 1005 !nframes); 1006 bpad = PADBYTES(al_delta) + (ndelim << 2); 1007 1008 nframes++; 1009 bf->bf_next = NULL; 1010 1011 /* link buffers of this frame to the aggregate */ 1012 if (!fi->baw_tracked) 1013 ath_tx_addto_baw(sc, tid, bf); 1014 bf->bf_state.ndelim = ndelim; 1015 1016 __skb_unlink(skb, tid_q); 1017 list_add_tail(&bf->list, bf_q); 1018 if (bf_prev) 1019 bf_prev->bf_next = bf; 1020 1021 bf_prev = bf; 1022 1023 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1024 if (!bf) { 1025 closed = true; 1026 break; 1027 } 1028 } while (ath_tid_has_buffered(tid)); 1029 1030 bf = bf_first; 1031 bf->bf_lastbf = bf_prev; 1032 1033 if (bf == bf_prev) { 1034 al = get_frame_info(bf->bf_mpdu)->framelen; 1035 bf->bf_state.bf_type = BUF_AMPDU; 1036 } else { 1037 TX_STAT_INC(txq->axq_qnum, a_aggr); 1038 } 1039 1040 *aggr_len = al; 1041 1042 return closed; 1043 #undef PADBYTES 1044 } 1045 1046 /* 1047 * rix - rate index 1048 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1049 * width - 0 for 20 MHz, 1 for 40 MHz 1050 * half_gi - to use 4us v/s 3.6 us for symbol time 1051 */ 1052 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1053 int width, int half_gi, bool shortPreamble) 1054 { 1055 u32 nbits, nsymbits, duration, nsymbols; 1056 int streams; 1057 1058 /* find number of symbols: PLCP + data */ 1059 streams = HT_RC_2_STREAMS(rix); 1060 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1061 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1062 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1063 1064 if (!half_gi) 1065 duration = SYMBOL_TIME(nsymbols); 1066 else 1067 duration = SYMBOL_TIME_HALFGI(nsymbols); 1068 1069 /* addup duration for legacy/ht training and signal fields */ 1070 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1071 1072 return duration; 1073 } 1074 1075 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1076 { 1077 int streams = HT_RC_2_STREAMS(mcs); 1078 int symbols, bits; 1079 int bytes = 0; 1080 1081 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1082 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1083 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1084 bits -= OFDM_PLCP_BITS; 1085 bytes = bits / 8; 1086 if (bytes > 65532) 1087 bytes = 65532; 1088 1089 return bytes; 1090 } 1091 1092 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1093 { 1094 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1095 int mcs; 1096 1097 /* 4ms is the default (and maximum) duration */ 1098 if (!txop || txop > 4096) 1099 txop = 4096; 1100 1101 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1102 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1103 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1104 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1105 for (mcs = 0; mcs < 32; mcs++) { 1106 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1107 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1108 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1109 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1110 } 1111 } 1112 1113 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1114 u8 rateidx, bool is_40, bool is_cck) 1115 { 1116 u8 max_power; 1117 struct sk_buff *skb; 1118 struct ath_frame_info *fi; 1119 struct ieee80211_tx_info *info; 1120 struct ath_hw *ah = sc->sc_ah; 1121 1122 if (sc->tx99_state || !ah->tpc_enabled) 1123 return MAX_RATE_POWER; 1124 1125 skb = bf->bf_mpdu; 1126 fi = get_frame_info(skb); 1127 info = IEEE80211_SKB_CB(skb); 1128 1129 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1130 int txpower = fi->tx_power; 1131 1132 if (is_40) { 1133 u8 power_ht40delta; 1134 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1135 1136 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { 1137 bool is_2ghz; 1138 struct modal_eep_header *pmodal; 1139 1140 is_2ghz = info->band == NL80211_BAND_2GHZ; 1141 pmodal = &eep->modalHeader[is_2ghz]; 1142 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1143 } else { 1144 power_ht40delta = 2; 1145 } 1146 txpower += power_ht40delta; 1147 } 1148 1149 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1150 AR_SREV_9271(ah)) { 1151 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1152 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1153 s8 power_offset; 1154 1155 power_offset = ah->eep_ops->get_eeprom(ah, 1156 EEP_PWR_TABLE_OFFSET); 1157 txpower -= 2 * power_offset; 1158 } 1159 1160 if (OLC_FOR_AR9280_20_LATER && is_cck) 1161 txpower -= 2; 1162 1163 txpower = max(txpower, 0); 1164 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1165 1166 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1167 * max_power is set to 0, frames are transmitted at max 1168 * TX power 1169 */ 1170 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1171 max_power = 1; 1172 } else if (!bf->bf_state.bfs_paprd) { 1173 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) 1174 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1175 fi->tx_power); 1176 else 1177 max_power = min_t(u8, ah->tx_power[rateidx], 1178 fi->tx_power); 1179 } else { 1180 max_power = ah->paprd_training_power; 1181 } 1182 1183 return max_power; 1184 } 1185 1186 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1187 struct ath_tx_info *info, int len, bool rts) 1188 { 1189 struct ath_hw *ah = sc->sc_ah; 1190 struct ath_common *common = ath9k_hw_common(ah); 1191 struct sk_buff *skb; 1192 struct ieee80211_tx_info *tx_info; 1193 struct ieee80211_tx_rate *rates; 1194 const struct ieee80211_rate *rate; 1195 struct ieee80211_hdr *hdr; 1196 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1197 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1198 int i; 1199 u8 rix = 0; 1200 1201 skb = bf->bf_mpdu; 1202 tx_info = IEEE80211_SKB_CB(skb); 1203 rates = bf->rates; 1204 hdr = (struct ieee80211_hdr *)skb->data; 1205 1206 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1207 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1208 info->rtscts_rate = fi->rtscts_rate; 1209 1210 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1211 bool is_40, is_sgi, is_sp, is_cck; 1212 int phy; 1213 1214 if (!rates[i].count || (rates[i].idx < 0)) 1215 continue; 1216 1217 rix = rates[i].idx; 1218 info->rates[i].Tries = rates[i].count; 1219 1220 /* 1221 * Handle RTS threshold for unaggregated HT frames. 1222 */ 1223 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1224 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1225 unlikely(rts_thresh != (u32) -1)) { 1226 if (!rts_thresh || (len > rts_thresh)) 1227 rts = true; 1228 } 1229 1230 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1231 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1232 info->flags |= ATH9K_TXDESC_RTSENA; 1233 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1234 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1235 info->flags |= ATH9K_TXDESC_CTSENA; 1236 } 1237 1238 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1239 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1240 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1241 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1242 1243 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1244 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1245 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1246 1247 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1248 /* MCS rates */ 1249 info->rates[i].Rate = rix | 0x80; 1250 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1251 ah->txchainmask, info->rates[i].Rate); 1252 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1253 is_40, is_sgi, is_sp); 1254 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1255 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1256 1257 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1258 is_40, false); 1259 continue; 1260 } 1261 1262 /* legacy rates */ 1263 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1264 if ((tx_info->band == NL80211_BAND_2GHZ) && 1265 !(rate->flags & IEEE80211_RATE_ERP_G)) 1266 phy = WLAN_RC_PHY_CCK; 1267 else 1268 phy = WLAN_RC_PHY_OFDM; 1269 1270 info->rates[i].Rate = rate->hw_value; 1271 if (rate->hw_value_short) { 1272 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1273 info->rates[i].Rate |= rate->hw_value_short; 1274 } else { 1275 is_sp = false; 1276 } 1277 1278 if (bf->bf_state.bfs_paprd) 1279 info->rates[i].ChSel = ah->txchainmask; 1280 else 1281 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1282 ah->txchainmask, info->rates[i].Rate); 1283 1284 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1285 phy, rate->bitrate * 100, len, rix, is_sp); 1286 1287 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1288 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1289 is_cck); 1290 } 1291 1292 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1293 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1294 info->flags &= ~ATH9K_TXDESC_RTSENA; 1295 1296 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1297 if (info->flags & ATH9K_TXDESC_RTSENA) 1298 info->flags &= ~ATH9K_TXDESC_CTSENA; 1299 } 1300 1301 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1302 { 1303 struct ieee80211_hdr *hdr; 1304 enum ath9k_pkt_type htype; 1305 __le16 fc; 1306 1307 hdr = (struct ieee80211_hdr *)skb->data; 1308 fc = hdr->frame_control; 1309 1310 if (ieee80211_is_beacon(fc)) 1311 htype = ATH9K_PKT_TYPE_BEACON; 1312 else if (ieee80211_is_probe_resp(fc)) 1313 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1314 else if (ieee80211_is_atim(fc)) 1315 htype = ATH9K_PKT_TYPE_ATIM; 1316 else if (ieee80211_is_pspoll(fc)) 1317 htype = ATH9K_PKT_TYPE_PSPOLL; 1318 else 1319 htype = ATH9K_PKT_TYPE_NORMAL; 1320 1321 return htype; 1322 } 1323 1324 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1325 struct ath_txq *txq, int len) 1326 { 1327 struct ath_hw *ah = sc->sc_ah; 1328 struct ath_buf *bf_first = NULL; 1329 struct ath_tx_info info; 1330 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1331 bool rts = false; 1332 1333 memset(&info, 0, sizeof(info)); 1334 info.is_first = true; 1335 info.is_last = true; 1336 info.qcu = txq->axq_qnum; 1337 1338 while (bf) { 1339 struct sk_buff *skb = bf->bf_mpdu; 1340 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1341 struct ath_frame_info *fi = get_frame_info(skb); 1342 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1343 1344 info.type = get_hw_packet_type(skb); 1345 if (bf->bf_next) 1346 info.link = bf->bf_next->bf_daddr; 1347 else 1348 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1349 1350 if (!bf_first) { 1351 bf_first = bf; 1352 1353 if (!sc->tx99_state) 1354 info.flags = ATH9K_TXDESC_INTREQ; 1355 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1356 txq == sc->tx.uapsdq) 1357 info.flags |= ATH9K_TXDESC_CLRDMASK; 1358 1359 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1360 info.flags |= ATH9K_TXDESC_NOACK; 1361 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1362 info.flags |= ATH9K_TXDESC_LDPC; 1363 1364 if (bf->bf_state.bfs_paprd) 1365 info.flags |= (u32) bf->bf_state.bfs_paprd << 1366 ATH9K_TXDESC_PAPRD_S; 1367 1368 /* 1369 * mac80211 doesn't handle RTS threshold for HT because 1370 * the decision has to be taken based on AMPDU length 1371 * and aggregation is done entirely inside ath9k. 1372 * Set the RTS/CTS flag for the first subframe based 1373 * on the threshold. 1374 */ 1375 if (aggr && (bf == bf_first) && 1376 unlikely(rts_thresh != (u32) -1)) { 1377 /* 1378 * "len" is the size of the entire AMPDU. 1379 */ 1380 if (!rts_thresh || (len > rts_thresh)) 1381 rts = true; 1382 } 1383 1384 if (!aggr) 1385 len = fi->framelen; 1386 1387 ath_buf_set_rate(sc, bf, &info, len, rts); 1388 } 1389 1390 info.buf_addr[0] = bf->bf_buf_addr; 1391 info.buf_len[0] = skb->len; 1392 info.pkt_len = fi->framelen; 1393 info.keyix = fi->keyix; 1394 info.keytype = fi->keytype; 1395 1396 if (aggr) { 1397 if (bf == bf_first) 1398 info.aggr = AGGR_BUF_FIRST; 1399 else if (bf == bf_first->bf_lastbf) 1400 info.aggr = AGGR_BUF_LAST; 1401 else 1402 info.aggr = AGGR_BUF_MIDDLE; 1403 1404 info.ndelim = bf->bf_state.ndelim; 1405 info.aggr_len = len; 1406 } 1407 1408 if (bf == bf_first->bf_lastbf) 1409 bf_first = NULL; 1410 1411 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1412 bf = bf->bf_next; 1413 } 1414 } 1415 1416 static void 1417 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1418 struct ath_atx_tid *tid, struct list_head *bf_q, 1419 struct ath_buf *bf_first, struct sk_buff_head *tid_q) 1420 { 1421 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1422 struct sk_buff *skb; 1423 int nframes = 0; 1424 1425 do { 1426 struct ieee80211_tx_info *tx_info; 1427 skb = bf->bf_mpdu; 1428 1429 nframes++; 1430 __skb_unlink(skb, tid_q); 1431 list_add_tail(&bf->list, bf_q); 1432 if (bf_prev) 1433 bf_prev->bf_next = bf; 1434 bf_prev = bf; 1435 1436 if (nframes >= 2) 1437 break; 1438 1439 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1440 if (!bf) 1441 break; 1442 1443 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1444 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1445 break; 1446 1447 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1448 } while (1); 1449 } 1450 1451 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1452 struct ath_atx_tid *tid, bool *stop) 1453 { 1454 struct ath_buf *bf; 1455 struct ieee80211_tx_info *tx_info; 1456 struct sk_buff_head *tid_q; 1457 struct list_head bf_q; 1458 int aggr_len = 0; 1459 bool aggr, last = true; 1460 1461 if (!ath_tid_has_buffered(tid)) 1462 return false; 1463 1464 INIT_LIST_HEAD(&bf_q); 1465 1466 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1467 if (!bf) 1468 return false; 1469 1470 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1471 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1472 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1473 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1474 *stop = true; 1475 return false; 1476 } 1477 1478 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1479 if (aggr) 1480 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf, 1481 tid_q, &aggr_len); 1482 else 1483 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q); 1484 1485 if (list_empty(&bf_q)) 1486 return false; 1487 1488 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1489 tid->clear_ps_filter = false; 1490 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1491 } 1492 1493 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1494 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1495 return true; 1496 } 1497 1498 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1499 u16 tid, u16 *ssn) 1500 { 1501 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1502 struct ath_atx_tid *txtid; 1503 struct ath_txq *txq; 1504 struct ath_node *an; 1505 u8 density; 1506 1507 ath_dbg(common, XMIT, "%s called\n", __func__); 1508 1509 an = (struct ath_node *)sta->drv_priv; 1510 txtid = ATH_AN_2_TID(an, tid); 1511 txq = txtid->txq; 1512 1513 ath_txq_lock(sc, txq); 1514 1515 /* update ampdu factor/density, they may have changed. This may happen 1516 * in HT IBSS when a beacon with HT-info is received after the station 1517 * has already been added. 1518 */ 1519 if (sta->ht_cap.ht_supported) { 1520 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1521 sta->ht_cap.ampdu_factor)) - 1; 1522 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1523 an->mpdudensity = density; 1524 } 1525 1526 /* force sequence number allocation for pending frames */ 1527 ath_tx_tid_change_state(sc, txtid); 1528 1529 txtid->active = true; 1530 *ssn = txtid->seq_start = txtid->seq_next; 1531 txtid->bar_index = -1; 1532 1533 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1534 txtid->baw_head = txtid->baw_tail = 0; 1535 1536 ath_txq_unlock_complete(sc, txq); 1537 1538 return 0; 1539 } 1540 1541 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1542 { 1543 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1544 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1545 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1546 struct ath_txq *txq = txtid->txq; 1547 1548 ath_dbg(common, XMIT, "%s called\n", __func__); 1549 1550 ath_txq_lock(sc, txq); 1551 txtid->active = false; 1552 ath_tx_flush_tid(sc, txtid); 1553 ath_tx_tid_change_state(sc, txtid); 1554 ath_txq_unlock_complete(sc, txq); 1555 } 1556 1557 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1558 struct ath_node *an) 1559 { 1560 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1561 struct ath_atx_tid *tid; 1562 struct ath_txq *txq; 1563 bool buffered; 1564 int tidno; 1565 1566 ath_dbg(common, XMIT, "%s called\n", __func__); 1567 1568 for (tidno = 0, tid = &an->tid[tidno]; 1569 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1570 1571 txq = tid->txq; 1572 1573 ath_txq_lock(sc, txq); 1574 1575 if (list_empty(&tid->list)) { 1576 ath_txq_unlock(sc, txq); 1577 continue; 1578 } 1579 1580 buffered = ath_tid_has_buffered(tid); 1581 1582 list_del_init(&tid->list); 1583 1584 ath_txq_unlock(sc, txq); 1585 1586 ieee80211_sta_set_buffered(sta, tidno, buffered); 1587 } 1588 } 1589 1590 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1591 { 1592 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1593 struct ath_atx_tid *tid; 1594 struct ath_txq *txq; 1595 int tidno; 1596 1597 ath_dbg(common, XMIT, "%s called\n", __func__); 1598 1599 for (tidno = 0, tid = &an->tid[tidno]; 1600 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1601 1602 txq = tid->txq; 1603 1604 ath_txq_lock(sc, txq); 1605 tid->clear_ps_filter = true; 1606 1607 if (ath_tid_has_buffered(tid)) { 1608 ath_tx_queue_tid(sc, txq, tid); 1609 ath_txq_schedule(sc, txq); 1610 } 1611 1612 ath_txq_unlock_complete(sc, txq); 1613 } 1614 } 1615 1616 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, 1617 u16 tidno) 1618 { 1619 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1620 struct ath_atx_tid *tid; 1621 struct ath_node *an; 1622 struct ath_txq *txq; 1623 1624 ath_dbg(common, XMIT, "%s called\n", __func__); 1625 1626 an = (struct ath_node *)sta->drv_priv; 1627 tid = ATH_AN_2_TID(an, tidno); 1628 txq = tid->txq; 1629 1630 ath_txq_lock(sc, txq); 1631 1632 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1633 1634 if (ath_tid_has_buffered(tid)) { 1635 ath_tx_queue_tid(sc, txq, tid); 1636 ath_txq_schedule(sc, txq); 1637 } 1638 1639 ath_txq_unlock_complete(sc, txq); 1640 } 1641 1642 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1643 struct ieee80211_sta *sta, 1644 u16 tids, int nframes, 1645 enum ieee80211_frame_release_type reason, 1646 bool more_data) 1647 { 1648 struct ath_softc *sc = hw->priv; 1649 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1650 struct ath_txq *txq = sc->tx.uapsdq; 1651 struct ieee80211_tx_info *info; 1652 struct list_head bf_q; 1653 struct ath_buf *bf_tail = NULL, *bf; 1654 struct sk_buff_head *tid_q; 1655 int sent = 0; 1656 int i; 1657 1658 INIT_LIST_HEAD(&bf_q); 1659 for (i = 0; tids && nframes; i++, tids >>= 1) { 1660 struct ath_atx_tid *tid; 1661 1662 if (!(tids & 1)) 1663 continue; 1664 1665 tid = ATH_AN_2_TID(an, i); 1666 1667 ath_txq_lock(sc, tid->txq); 1668 while (nframes > 0) { 1669 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q); 1670 if (!bf) 1671 break; 1672 1673 __skb_unlink(bf->bf_mpdu, tid_q); 1674 list_add_tail(&bf->list, &bf_q); 1675 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1676 if (bf_isampdu(bf)) { 1677 ath_tx_addto_baw(sc, tid, bf); 1678 bf->bf_state.bf_type &= ~BUF_AGGR; 1679 } 1680 if (bf_tail) 1681 bf_tail->bf_next = bf; 1682 1683 bf_tail = bf; 1684 nframes--; 1685 sent++; 1686 TX_STAT_INC(txq->axq_qnum, a_queued_hw); 1687 1688 if (an->sta && !ath_tid_has_buffered(tid)) 1689 ieee80211_sta_set_buffered(an->sta, i, false); 1690 } 1691 ath_txq_unlock_complete(sc, tid->txq); 1692 } 1693 1694 if (list_empty(&bf_q)) 1695 return; 1696 1697 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1698 info->flags |= IEEE80211_TX_STATUS_EOSP; 1699 1700 bf = list_first_entry(&bf_q, struct ath_buf, list); 1701 ath_txq_lock(sc, txq); 1702 ath_tx_fill_desc(sc, bf, txq, 0); 1703 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1704 ath_txq_unlock(sc, txq); 1705 } 1706 1707 /********************/ 1708 /* Queue Management */ 1709 /********************/ 1710 1711 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1712 { 1713 struct ath_hw *ah = sc->sc_ah; 1714 struct ath9k_tx_queue_info qi; 1715 static const int subtype_txq_to_hwq[] = { 1716 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1717 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1718 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1719 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1720 }; 1721 int axq_qnum, i; 1722 1723 memset(&qi, 0, sizeof(qi)); 1724 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1725 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1726 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1727 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1728 qi.tqi_physCompBuf = 0; 1729 1730 /* 1731 * Enable interrupts only for EOL and DESC conditions. 1732 * We mark tx descriptors to receive a DESC interrupt 1733 * when a tx queue gets deep; otherwise waiting for the 1734 * EOL to reap descriptors. Note that this is done to 1735 * reduce interrupt load and this only defers reaping 1736 * descriptors, never transmitting frames. Aside from 1737 * reducing interrupts this also permits more concurrency. 1738 * The only potential downside is if the tx queue backs 1739 * up in which case the top half of the kernel may backup 1740 * due to a lack of tx descriptors. 1741 * 1742 * The UAPSD queue is an exception, since we take a desc- 1743 * based intr on the EOSP frames. 1744 */ 1745 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1746 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1747 } else { 1748 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1749 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1750 else 1751 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1752 TXQ_FLAG_TXDESCINT_ENABLE; 1753 } 1754 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1755 if (axq_qnum == -1) { 1756 /* 1757 * NB: don't print a message, this happens 1758 * normally on parts with too few tx queues 1759 */ 1760 return NULL; 1761 } 1762 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1763 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1764 1765 txq->axq_qnum = axq_qnum; 1766 txq->mac80211_qnum = -1; 1767 txq->axq_link = NULL; 1768 __skb_queue_head_init(&txq->complete_q); 1769 INIT_LIST_HEAD(&txq->axq_q); 1770 spin_lock_init(&txq->axq_lock); 1771 txq->axq_depth = 0; 1772 txq->axq_ampdu_depth = 0; 1773 txq->axq_tx_inprogress = false; 1774 sc->tx.txqsetup |= 1<<axq_qnum; 1775 1776 txq->txq_headidx = txq->txq_tailidx = 0; 1777 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1778 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1779 } 1780 return &sc->tx.txq[axq_qnum]; 1781 } 1782 1783 int ath_txq_update(struct ath_softc *sc, int qnum, 1784 struct ath9k_tx_queue_info *qinfo) 1785 { 1786 struct ath_hw *ah = sc->sc_ah; 1787 int error = 0; 1788 struct ath9k_tx_queue_info qi; 1789 1790 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1791 1792 ath9k_hw_get_txq_props(ah, qnum, &qi); 1793 qi.tqi_aifs = qinfo->tqi_aifs; 1794 qi.tqi_cwmin = qinfo->tqi_cwmin; 1795 qi.tqi_cwmax = qinfo->tqi_cwmax; 1796 qi.tqi_burstTime = qinfo->tqi_burstTime; 1797 qi.tqi_readyTime = qinfo->tqi_readyTime; 1798 1799 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1800 ath_err(ath9k_hw_common(sc->sc_ah), 1801 "Unable to update hardware queue %u!\n", qnum); 1802 error = -EIO; 1803 } else { 1804 ath9k_hw_resettxqueue(ah, qnum); 1805 } 1806 1807 return error; 1808 } 1809 1810 int ath_cabq_update(struct ath_softc *sc) 1811 { 1812 struct ath9k_tx_queue_info qi; 1813 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1814 int qnum = sc->beacon.cabq->axq_qnum; 1815 1816 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1817 1818 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1819 ATH_CABQ_READY_TIME) / 100; 1820 ath_txq_update(sc, qnum, &qi); 1821 1822 return 0; 1823 } 1824 1825 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1826 struct list_head *list) 1827 { 1828 struct ath_buf *bf, *lastbf; 1829 struct list_head bf_head; 1830 struct ath_tx_status ts; 1831 1832 memset(&ts, 0, sizeof(ts)); 1833 ts.ts_status = ATH9K_TX_FLUSH; 1834 INIT_LIST_HEAD(&bf_head); 1835 1836 while (!list_empty(list)) { 1837 bf = list_first_entry(list, struct ath_buf, list); 1838 1839 if (bf->bf_state.stale) { 1840 list_del(&bf->list); 1841 1842 ath_tx_return_buffer(sc, bf); 1843 continue; 1844 } 1845 1846 lastbf = bf->bf_lastbf; 1847 list_cut_position(&bf_head, list, &lastbf->list); 1848 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1849 } 1850 } 1851 1852 /* 1853 * Drain a given TX queue (could be Beacon or Data) 1854 * 1855 * This assumes output has been stopped and 1856 * we do not need to block ath_tx_tasklet. 1857 */ 1858 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1859 { 1860 rcu_read_lock(); 1861 ath_txq_lock(sc, txq); 1862 1863 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1864 int idx = txq->txq_tailidx; 1865 1866 while (!list_empty(&txq->txq_fifo[idx])) { 1867 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1868 1869 INCR(idx, ATH_TXFIFO_DEPTH); 1870 } 1871 txq->txq_tailidx = idx; 1872 } 1873 1874 txq->axq_link = NULL; 1875 txq->axq_tx_inprogress = false; 1876 ath_drain_txq_list(sc, txq, &txq->axq_q); 1877 1878 ath_txq_unlock_complete(sc, txq); 1879 rcu_read_unlock(); 1880 } 1881 1882 bool ath_drain_all_txq(struct ath_softc *sc) 1883 { 1884 struct ath_hw *ah = sc->sc_ah; 1885 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1886 struct ath_txq *txq; 1887 int i; 1888 u32 npend = 0; 1889 1890 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1891 return true; 1892 1893 ath9k_hw_abort_tx_dma(ah); 1894 1895 /* Check if any queue remains active */ 1896 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1897 if (!ATH_TXQ_SETUP(sc, i)) 1898 continue; 1899 1900 if (!sc->tx.txq[i].axq_depth) 1901 continue; 1902 1903 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1904 npend |= BIT(i); 1905 } 1906 1907 if (npend) { 1908 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1909 ath_dbg(common, RESET, 1910 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1911 } 1912 1913 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1914 if (!ATH_TXQ_SETUP(sc, i)) 1915 continue; 1916 1917 /* 1918 * The caller will resume queues with ieee80211_wake_queues. 1919 * Mark the queue as not stopped to prevent ath_tx_complete 1920 * from waking the queue too early. 1921 */ 1922 txq = &sc->tx.txq[i]; 1923 txq->stopped = false; 1924 ath_draintxq(sc, txq); 1925 } 1926 1927 return !npend; 1928 } 1929 1930 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1931 { 1932 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1933 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1934 } 1935 1936 /* For each acq entry, for each tid, try to schedule packets 1937 * for transmit until ampdu_depth has reached min Q depth. 1938 */ 1939 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1940 { 1941 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1942 struct ath_atx_tid *tid, *last_tid; 1943 struct list_head *tid_list; 1944 bool sent = false; 1945 1946 if (txq->mac80211_qnum < 0) 1947 return; 1948 1949 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1950 return; 1951 1952 spin_lock_bh(&sc->chan_lock); 1953 tid_list = &sc->cur_chan->acq[txq->mac80211_qnum]; 1954 1955 if (list_empty(tid_list)) { 1956 spin_unlock_bh(&sc->chan_lock); 1957 return; 1958 } 1959 1960 rcu_read_lock(); 1961 1962 last_tid = list_entry(tid_list->prev, struct ath_atx_tid, list); 1963 while (!list_empty(tid_list)) { 1964 bool stop = false; 1965 1966 if (sc->cur_chan->stopped) 1967 break; 1968 1969 tid = list_first_entry(tid_list, struct ath_atx_tid, list); 1970 list_del_init(&tid->list); 1971 1972 if (ath_tx_sched_aggr(sc, txq, tid, &stop)) 1973 sent = true; 1974 1975 /* 1976 * add tid to round-robin queue if more frames 1977 * are pending for the tid 1978 */ 1979 if (ath_tid_has_buffered(tid)) 1980 ath_tx_queue_tid(sc, txq, tid); 1981 1982 if (stop) 1983 break; 1984 1985 if (tid == last_tid) { 1986 if (!sent) 1987 break; 1988 1989 sent = false; 1990 last_tid = list_entry(tid_list->prev, 1991 struct ath_atx_tid, list); 1992 } 1993 } 1994 1995 rcu_read_unlock(); 1996 spin_unlock_bh(&sc->chan_lock); 1997 } 1998 1999 void ath_txq_schedule_all(struct ath_softc *sc) 2000 { 2001 struct ath_txq *txq; 2002 int i; 2003 2004 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2005 txq = sc->tx.txq_map[i]; 2006 2007 spin_lock_bh(&txq->axq_lock); 2008 ath_txq_schedule(sc, txq); 2009 spin_unlock_bh(&txq->axq_lock); 2010 } 2011 } 2012 2013 /***********/ 2014 /* TX, DMA */ 2015 /***********/ 2016 2017 /* 2018 * Insert a chain of ath_buf (descriptors) on a txq and 2019 * assume the descriptors are already chained together by caller. 2020 */ 2021 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2022 struct list_head *head, bool internal) 2023 { 2024 struct ath_hw *ah = sc->sc_ah; 2025 struct ath_common *common = ath9k_hw_common(ah); 2026 struct ath_buf *bf, *bf_last; 2027 bool puttxbuf = false; 2028 bool edma; 2029 2030 /* 2031 * Insert the frame on the outbound list and 2032 * pass it on to the hardware. 2033 */ 2034 2035 if (list_empty(head)) 2036 return; 2037 2038 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2039 bf = list_first_entry(head, struct ath_buf, list); 2040 bf_last = list_entry(head->prev, struct ath_buf, list); 2041 2042 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2043 txq->axq_qnum, txq->axq_depth); 2044 2045 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2046 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2047 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2048 puttxbuf = true; 2049 } else { 2050 list_splice_tail_init(head, &txq->axq_q); 2051 2052 if (txq->axq_link) { 2053 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2054 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2055 txq->axq_qnum, txq->axq_link, 2056 ito64(bf->bf_daddr), bf->bf_desc); 2057 } else if (!edma) 2058 puttxbuf = true; 2059 2060 txq->axq_link = bf_last->bf_desc; 2061 } 2062 2063 if (puttxbuf) { 2064 TX_STAT_INC(txq->axq_qnum, puttxbuf); 2065 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2066 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2067 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2068 } 2069 2070 if (!edma || sc->tx99_state) { 2071 TX_STAT_INC(txq->axq_qnum, txstart); 2072 ath9k_hw_txstart(ah, txq->axq_qnum); 2073 } 2074 2075 if (!internal) { 2076 while (bf) { 2077 txq->axq_depth++; 2078 if (bf_is_ampdu_not_probing(bf)) 2079 txq->axq_ampdu_depth++; 2080 2081 bf_last = bf->bf_lastbf; 2082 bf = bf_last->bf_next; 2083 bf_last->bf_next = NULL; 2084 } 2085 } 2086 } 2087 2088 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2089 struct ath_atx_tid *tid, struct sk_buff *skb) 2090 { 2091 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2092 struct ath_frame_info *fi = get_frame_info(skb); 2093 struct list_head bf_head; 2094 struct ath_buf *bf = fi->bf; 2095 2096 INIT_LIST_HEAD(&bf_head); 2097 list_add_tail(&bf->list, &bf_head); 2098 bf->bf_state.bf_type = 0; 2099 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2100 bf->bf_state.bf_type = BUF_AMPDU; 2101 ath_tx_addto_baw(sc, tid, bf); 2102 } 2103 2104 bf->bf_next = NULL; 2105 bf->bf_lastbf = bf; 2106 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2107 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2108 TX_STAT_INC(txq->axq_qnum, queued); 2109 } 2110 2111 static void setup_frame_info(struct ieee80211_hw *hw, 2112 struct ieee80211_sta *sta, 2113 struct sk_buff *skb, 2114 int framelen) 2115 { 2116 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2117 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2118 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2119 const struct ieee80211_rate *rate; 2120 struct ath_frame_info *fi = get_frame_info(skb); 2121 struct ath_node *an = NULL; 2122 enum ath9k_key_type keytype; 2123 bool short_preamble = false; 2124 u8 txpower; 2125 2126 /* 2127 * We check if Short Preamble is needed for the CTS rate by 2128 * checking the BSS's global flag. 2129 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2130 */ 2131 if (tx_info->control.vif && 2132 tx_info->control.vif->bss_conf.use_short_preamble) 2133 short_preamble = true; 2134 2135 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2136 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2137 2138 if (sta) 2139 an = (struct ath_node *) sta->drv_priv; 2140 2141 if (tx_info->control.vif) { 2142 struct ieee80211_vif *vif = tx_info->control.vif; 2143 2144 txpower = 2 * vif->bss_conf.txpower; 2145 } else { 2146 struct ath_softc *sc = hw->priv; 2147 2148 txpower = sc->cur_chan->cur_txpower; 2149 } 2150 2151 memset(fi, 0, sizeof(*fi)); 2152 fi->txq = -1; 2153 if (hw_key) 2154 fi->keyix = hw_key->hw_key_idx; 2155 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2156 fi->keyix = an->ps_key; 2157 else 2158 fi->keyix = ATH9K_TXKEYIX_INVALID; 2159 fi->keytype = keytype; 2160 fi->framelen = framelen; 2161 fi->tx_power = txpower; 2162 2163 if (!rate) 2164 return; 2165 fi->rtscts_rate = rate->hw_value; 2166 if (short_preamble) 2167 fi->rtscts_rate |= rate->hw_value_short; 2168 } 2169 2170 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2171 { 2172 struct ath_hw *ah = sc->sc_ah; 2173 struct ath9k_channel *curchan = ah->curchan; 2174 2175 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2176 (chainmask == 0x7) && (rate < 0x90)) 2177 return 0x3; 2178 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2179 IS_CCK_RATE(rate)) 2180 return 0x2; 2181 else 2182 return chainmask; 2183 } 2184 2185 /* 2186 * Assign a descriptor (and sequence number if necessary, 2187 * and map buffer for DMA. Frees skb on error 2188 */ 2189 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2190 struct ath_txq *txq, 2191 struct ath_atx_tid *tid, 2192 struct sk_buff *skb) 2193 { 2194 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2195 struct ath_frame_info *fi = get_frame_info(skb); 2196 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2197 struct ath_buf *bf; 2198 int fragno; 2199 u16 seqno; 2200 2201 bf = ath_tx_get_buffer(sc); 2202 if (!bf) { 2203 ath_dbg(common, XMIT, "TX buffers are full\n"); 2204 return NULL; 2205 } 2206 2207 ATH_TXBUF_RESET(bf); 2208 2209 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2210 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2211 seqno = tid->seq_next; 2212 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2213 2214 if (fragno) 2215 hdr->seq_ctrl |= cpu_to_le16(fragno); 2216 2217 if (!ieee80211_has_morefrags(hdr->frame_control)) 2218 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2219 2220 bf->bf_state.seqno = seqno; 2221 } 2222 2223 bf->bf_mpdu = skb; 2224 2225 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2226 skb->len, DMA_TO_DEVICE); 2227 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2228 bf->bf_mpdu = NULL; 2229 bf->bf_buf_addr = 0; 2230 ath_err(ath9k_hw_common(sc->sc_ah), 2231 "dma_mapping_error() on TX\n"); 2232 ath_tx_return_buffer(sc, bf); 2233 return NULL; 2234 } 2235 2236 fi->bf = bf; 2237 2238 return bf; 2239 } 2240 2241 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2242 { 2243 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2244 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2245 struct ieee80211_vif *vif = info->control.vif; 2246 struct ath_vif *avp; 2247 2248 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2249 return; 2250 2251 if (!vif) 2252 return; 2253 2254 avp = (struct ath_vif *)vif->drv_priv; 2255 2256 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2257 avp->seq_no += 0x10; 2258 2259 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2260 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2261 } 2262 2263 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2264 struct ath_tx_control *txctl) 2265 { 2266 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2267 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2268 struct ieee80211_sta *sta = txctl->sta; 2269 struct ieee80211_vif *vif = info->control.vif; 2270 struct ath_vif *avp; 2271 struct ath_softc *sc = hw->priv; 2272 int frmlen = skb->len + FCS_LEN; 2273 int padpos, padsize; 2274 2275 /* NOTE: sta can be NULL according to net/mac80211.h */ 2276 if (sta) 2277 txctl->an = (struct ath_node *)sta->drv_priv; 2278 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2279 avp = (void *)vif->drv_priv; 2280 txctl->an = &avp->mcast_node; 2281 } 2282 2283 if (info->control.hw_key) 2284 frmlen += info->control.hw_key->icv_len; 2285 2286 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2287 2288 if ((vif && vif->type != NL80211_IFTYPE_AP && 2289 vif->type != NL80211_IFTYPE_AP_VLAN) || 2290 !ieee80211_is_data(hdr->frame_control)) 2291 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2292 2293 /* Add the padding after the header if this is not already done */ 2294 padpos = ieee80211_hdrlen(hdr->frame_control); 2295 padsize = padpos & 3; 2296 if (padsize && skb->len > padpos) { 2297 if (skb_headroom(skb) < padsize) 2298 return -ENOMEM; 2299 2300 skb_push(skb, padsize); 2301 memmove(skb->data, skb->data + padsize, padpos); 2302 } 2303 2304 setup_frame_info(hw, sta, skb, frmlen); 2305 return 0; 2306 } 2307 2308 2309 /* Upon failure caller should free skb */ 2310 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2311 struct ath_tx_control *txctl) 2312 { 2313 struct ieee80211_hdr *hdr; 2314 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2315 struct ieee80211_sta *sta = txctl->sta; 2316 struct ieee80211_vif *vif = info->control.vif; 2317 struct ath_frame_info *fi = get_frame_info(skb); 2318 struct ath_vif *avp = NULL; 2319 struct ath_softc *sc = hw->priv; 2320 struct ath_txq *txq = txctl->txq; 2321 struct ath_atx_tid *tid = NULL; 2322 struct ath_buf *bf; 2323 bool queue, skip_uapsd = false, ps_resp; 2324 int q, ret; 2325 2326 if (vif) 2327 avp = (void *)vif->drv_priv; 2328 2329 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) 2330 txctl->force_channel = true; 2331 2332 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2333 2334 ret = ath_tx_prepare(hw, skb, txctl); 2335 if (ret) 2336 return ret; 2337 2338 hdr = (struct ieee80211_hdr *) skb->data; 2339 /* 2340 * At this point, the vif, hw_key and sta pointers in the tx control 2341 * info are no longer valid (overwritten by the ath_frame_info data. 2342 */ 2343 2344 q = skb_get_queue_mapping(skb); 2345 2346 ath_txq_lock(sc, txq); 2347 if (txq == sc->tx.txq_map[q]) { 2348 fi->txq = q; 2349 if (++txq->pending_frames > sc->tx.txq_max_pending[q] && 2350 !txq->stopped) { 2351 if (ath9k_is_chanctx_enabled()) 2352 ieee80211_stop_queue(sc->hw, info->hw_queue); 2353 else 2354 ieee80211_stop_queue(sc->hw, q); 2355 txq->stopped = true; 2356 } 2357 } 2358 2359 queue = ieee80211_is_data_present(hdr->frame_control); 2360 2361 /* If chanctx, queue all null frames while NOA could be there */ 2362 if (ath9k_is_chanctx_enabled() && 2363 ieee80211_is_nullfunc(hdr->frame_control) && 2364 !txctl->force_channel) 2365 queue = true; 2366 2367 /* Force queueing of all frames that belong to a virtual interface on 2368 * a different channel context, to ensure that they are sent on the 2369 * correct channel. 2370 */ 2371 if (((avp && avp->chanctx != sc->cur_chan) || 2372 sc->cur_chan->stopped) && !txctl->force_channel) { 2373 if (!txctl->an) 2374 txctl->an = &avp->mcast_node; 2375 queue = true; 2376 skip_uapsd = true; 2377 } 2378 2379 if (txctl->an && queue) 2380 tid = ath_get_skb_tid(sc, txctl->an, skb); 2381 2382 if (!skip_uapsd && ps_resp) { 2383 ath_txq_unlock(sc, txq); 2384 txq = sc->tx.uapsdq; 2385 ath_txq_lock(sc, txq); 2386 } else if (txctl->an && queue) { 2387 WARN_ON(tid->txq != txctl->txq); 2388 2389 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 2390 tid->clear_ps_filter = true; 2391 2392 /* 2393 * Add this frame to software queue for scheduling later 2394 * for aggregation. 2395 */ 2396 TX_STAT_INC(txq->axq_qnum, a_queued_sw); 2397 __skb_queue_tail(&tid->buf_q, skb); 2398 if (!txctl->an->sleeping) 2399 ath_tx_queue_tid(sc, txq, tid); 2400 2401 ath_txq_schedule(sc, txq); 2402 goto out; 2403 } 2404 2405 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2406 if (!bf) { 2407 ath_txq_skb_done(sc, txq, skb); 2408 if (txctl->paprd) 2409 dev_kfree_skb_any(skb); 2410 else 2411 ieee80211_free_txskb(sc->hw, skb); 2412 goto out; 2413 } 2414 2415 bf->bf_state.bfs_paprd = txctl->paprd; 2416 2417 if (txctl->paprd) 2418 bf->bf_state.bfs_paprd_timestamp = jiffies; 2419 2420 ath_set_rates(vif, sta, bf); 2421 ath_tx_send_normal(sc, txq, tid, skb); 2422 2423 out: 2424 ath_txq_unlock(sc, txq); 2425 2426 return 0; 2427 } 2428 2429 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2430 struct sk_buff *skb) 2431 { 2432 struct ath_softc *sc = hw->priv; 2433 struct ath_tx_control txctl = { 2434 .txq = sc->beacon.cabq 2435 }; 2436 struct ath_tx_info info = {}; 2437 struct ieee80211_hdr *hdr; 2438 struct ath_buf *bf_tail = NULL; 2439 struct ath_buf *bf; 2440 LIST_HEAD(bf_q); 2441 int duration = 0; 2442 int max_duration; 2443 2444 max_duration = 2445 sc->cur_chan->beacon.beacon_interval * 1000 * 2446 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2447 2448 do { 2449 struct ath_frame_info *fi = get_frame_info(skb); 2450 2451 if (ath_tx_prepare(hw, skb, &txctl)) 2452 break; 2453 2454 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2455 if (!bf) 2456 break; 2457 2458 bf->bf_lastbf = bf; 2459 ath_set_rates(vif, NULL, bf); 2460 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2461 duration += info.rates[0].PktDuration; 2462 if (bf_tail) 2463 bf_tail->bf_next = bf; 2464 2465 list_add_tail(&bf->list, &bf_q); 2466 bf_tail = bf; 2467 skb = NULL; 2468 2469 if (duration > max_duration) 2470 break; 2471 2472 skb = ieee80211_get_buffered_bc(hw, vif); 2473 } while(skb); 2474 2475 if (skb) 2476 ieee80211_free_txskb(hw, skb); 2477 2478 if (list_empty(&bf_q)) 2479 return; 2480 2481 bf = list_first_entry(&bf_q, struct ath_buf, list); 2482 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 2483 2484 if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) { 2485 hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA); 2486 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 2487 sizeof(*hdr), DMA_TO_DEVICE); 2488 } 2489 2490 ath_txq_lock(sc, txctl.txq); 2491 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2492 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2493 TX_STAT_INC(txctl.txq->axq_qnum, queued); 2494 ath_txq_unlock(sc, txctl.txq); 2495 } 2496 2497 /*****************/ 2498 /* TX Completion */ 2499 /*****************/ 2500 2501 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2502 int tx_flags, struct ath_txq *txq, 2503 struct ieee80211_sta *sta) 2504 { 2505 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2506 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2507 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2508 int padpos, padsize; 2509 unsigned long flags; 2510 2511 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2512 2513 if (sc->sc_ah->caldata) 2514 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2515 2516 if (!(tx_flags & ATH_TX_ERROR)) { 2517 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2518 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2519 else 2520 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2521 } 2522 2523 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 2524 padpos = ieee80211_hdrlen(hdr->frame_control); 2525 padsize = padpos & 3; 2526 if (padsize && skb->len>padpos+padsize) { 2527 /* 2528 * Remove MAC header padding before giving the frame back to 2529 * mac80211. 2530 */ 2531 memmove(skb->data + padsize, skb->data, padpos); 2532 skb_pull(skb, padsize); 2533 } 2534 } 2535 2536 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2537 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2538 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2539 ath_dbg(common, PS, 2540 "Going back to sleep after having received TX status (0x%lx)\n", 2541 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2542 PS_WAIT_FOR_CAB | 2543 PS_WAIT_FOR_PSPOLL_DATA | 2544 PS_WAIT_FOR_TX_ACK)); 2545 } 2546 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2547 2548 ath_txq_skb_done(sc, txq, skb); 2549 tx_info->status.status_driver_data[0] = sta; 2550 __skb_queue_tail(&txq->complete_q, skb); 2551 } 2552 2553 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2554 struct ath_txq *txq, struct list_head *bf_q, 2555 struct ieee80211_sta *sta, 2556 struct ath_tx_status *ts, int txok) 2557 { 2558 struct sk_buff *skb = bf->bf_mpdu; 2559 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2560 unsigned long flags; 2561 int tx_flags = 0; 2562 2563 if (!txok) 2564 tx_flags |= ATH_TX_ERROR; 2565 2566 if (ts->ts_status & ATH9K_TXERR_FILT) 2567 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2568 2569 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2570 bf->bf_buf_addr = 0; 2571 if (sc->tx99_state) 2572 goto skip_tx_complete; 2573 2574 if (bf->bf_state.bfs_paprd) { 2575 if (time_after(jiffies, 2576 bf->bf_state.bfs_paprd_timestamp + 2577 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2578 dev_kfree_skb_any(skb); 2579 else 2580 complete(&sc->paprd_complete); 2581 } else { 2582 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2583 ath_tx_complete(sc, skb, tx_flags, txq, sta); 2584 } 2585 skip_tx_complete: 2586 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2587 * accidentally reference it later. 2588 */ 2589 bf->bf_mpdu = NULL; 2590 2591 /* 2592 * Return the list of ath_buf of this mpdu to free queue 2593 */ 2594 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2595 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2596 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2597 } 2598 2599 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2600 struct ath_tx_status *ts, int nframes, int nbad, 2601 int txok) 2602 { 2603 struct sk_buff *skb = bf->bf_mpdu; 2604 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2605 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2606 struct ieee80211_hw *hw = sc->hw; 2607 struct ath_hw *ah = sc->sc_ah; 2608 u8 i, tx_rateindex; 2609 2610 if (txok) 2611 tx_info->status.ack_signal = ts->ts_rssi; 2612 2613 tx_rateindex = ts->ts_rateindex; 2614 WARN_ON(tx_rateindex >= hw->max_rates); 2615 2616 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2617 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2618 2619 BUG_ON(nbad > nframes); 2620 } 2621 tx_info->status.ampdu_len = nframes; 2622 tx_info->status.ampdu_ack_len = nframes - nbad; 2623 2624 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2625 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2626 /* 2627 * If an underrun error is seen assume it as an excessive 2628 * retry only if max frame trigger level has been reached 2629 * (2 KB for single stream, and 4 KB for dual stream). 2630 * Adjust the long retry as if the frame was tried 2631 * hw->max_rate_tries times to affect how rate control updates 2632 * PER for the failed rate. 2633 * In case of congestion on the bus penalizing this type of 2634 * underruns should help hardware actually transmit new frames 2635 * successfully by eventually preferring slower rates. 2636 * This itself should also alleviate congestion on the bus. 2637 */ 2638 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2639 ATH9K_TX_DELIM_UNDERRUN)) && 2640 ieee80211_is_data(hdr->frame_control) && 2641 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2642 tx_info->status.rates[tx_rateindex].count = 2643 hw->max_rate_tries; 2644 } 2645 2646 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2647 tx_info->status.rates[i].count = 0; 2648 tx_info->status.rates[i].idx = -1; 2649 } 2650 2651 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2652 } 2653 2654 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2655 { 2656 struct ath_hw *ah = sc->sc_ah; 2657 struct ath_common *common = ath9k_hw_common(ah); 2658 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2659 struct list_head bf_head; 2660 struct ath_desc *ds; 2661 struct ath_tx_status ts; 2662 int status; 2663 2664 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2665 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2666 txq->axq_link); 2667 2668 ath_txq_lock(sc, txq); 2669 for (;;) { 2670 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2671 break; 2672 2673 if (list_empty(&txq->axq_q)) { 2674 txq->axq_link = NULL; 2675 ath_txq_schedule(sc, txq); 2676 break; 2677 } 2678 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2679 2680 /* 2681 * There is a race condition that a BH gets scheduled 2682 * after sw writes TxE and before hw re-load the last 2683 * descriptor to get the newly chained one. 2684 * Software must keep the last DONE descriptor as a 2685 * holding descriptor - software does so by marking 2686 * it with the STALE flag. 2687 */ 2688 bf_held = NULL; 2689 if (bf->bf_state.stale) { 2690 bf_held = bf; 2691 if (list_is_last(&bf_held->list, &txq->axq_q)) 2692 break; 2693 2694 bf = list_entry(bf_held->list.next, struct ath_buf, 2695 list); 2696 } 2697 2698 lastbf = bf->bf_lastbf; 2699 ds = lastbf->bf_desc; 2700 2701 memset(&ts, 0, sizeof(ts)); 2702 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2703 if (status == -EINPROGRESS) 2704 break; 2705 2706 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2707 2708 /* 2709 * Remove ath_buf's of the same transmit unit from txq, 2710 * however leave the last descriptor back as the holding 2711 * descriptor for hw. 2712 */ 2713 lastbf->bf_state.stale = true; 2714 INIT_LIST_HEAD(&bf_head); 2715 if (!list_is_singular(&lastbf->list)) 2716 list_cut_position(&bf_head, 2717 &txq->axq_q, lastbf->list.prev); 2718 2719 if (bf_held) { 2720 list_del(&bf_held->list); 2721 ath_tx_return_buffer(sc, bf_held); 2722 } 2723 2724 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2725 } 2726 ath_txq_unlock_complete(sc, txq); 2727 } 2728 2729 void ath_tx_tasklet(struct ath_softc *sc) 2730 { 2731 struct ath_hw *ah = sc->sc_ah; 2732 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2733 int i; 2734 2735 rcu_read_lock(); 2736 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2737 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2738 ath_tx_processq(sc, &sc->tx.txq[i]); 2739 } 2740 rcu_read_unlock(); 2741 } 2742 2743 void ath_tx_edma_tasklet(struct ath_softc *sc) 2744 { 2745 struct ath_tx_status ts; 2746 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2747 struct ath_hw *ah = sc->sc_ah; 2748 struct ath_txq *txq; 2749 struct ath_buf *bf, *lastbf; 2750 struct list_head bf_head; 2751 struct list_head *fifo_list; 2752 int status; 2753 2754 rcu_read_lock(); 2755 for (;;) { 2756 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2757 break; 2758 2759 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2760 if (status == -EINPROGRESS) 2761 break; 2762 if (status == -EIO) { 2763 ath_dbg(common, XMIT, "Error processing tx status\n"); 2764 break; 2765 } 2766 2767 /* Process beacon completions separately */ 2768 if (ts.qid == sc->beacon.beaconq) { 2769 sc->beacon.tx_processed = true; 2770 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2771 2772 if (ath9k_is_chanctx_enabled()) { 2773 ath_chanctx_event(sc, NULL, 2774 ATH_CHANCTX_EVENT_BEACON_SENT); 2775 } 2776 2777 ath9k_csa_update(sc); 2778 continue; 2779 } 2780 2781 txq = &sc->tx.txq[ts.qid]; 2782 2783 ath_txq_lock(sc, txq); 2784 2785 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2786 2787 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2788 if (list_empty(fifo_list)) { 2789 ath_txq_unlock(sc, txq); 2790 return; 2791 } 2792 2793 bf = list_first_entry(fifo_list, struct ath_buf, list); 2794 if (bf->bf_state.stale) { 2795 list_del(&bf->list); 2796 ath_tx_return_buffer(sc, bf); 2797 bf = list_first_entry(fifo_list, struct ath_buf, list); 2798 } 2799 2800 lastbf = bf->bf_lastbf; 2801 2802 INIT_LIST_HEAD(&bf_head); 2803 if (list_is_last(&lastbf->list, fifo_list)) { 2804 list_splice_tail_init(fifo_list, &bf_head); 2805 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2806 2807 if (!list_empty(&txq->axq_q)) { 2808 struct list_head bf_q; 2809 2810 INIT_LIST_HEAD(&bf_q); 2811 txq->axq_link = NULL; 2812 list_splice_tail_init(&txq->axq_q, &bf_q); 2813 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2814 } 2815 } else { 2816 lastbf->bf_state.stale = true; 2817 if (bf != lastbf) 2818 list_cut_position(&bf_head, fifo_list, 2819 lastbf->list.prev); 2820 } 2821 2822 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2823 ath_txq_unlock_complete(sc, txq); 2824 } 2825 rcu_read_unlock(); 2826 } 2827 2828 /*****************/ 2829 /* Init, Cleanup */ 2830 /*****************/ 2831 2832 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2833 { 2834 struct ath_descdma *dd = &sc->txsdma; 2835 u8 txs_len = sc->sc_ah->caps.txs_len; 2836 2837 dd->dd_desc_len = size * txs_len; 2838 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2839 &dd->dd_desc_paddr, GFP_KERNEL); 2840 if (!dd->dd_desc) 2841 return -ENOMEM; 2842 2843 return 0; 2844 } 2845 2846 static int ath_tx_edma_init(struct ath_softc *sc) 2847 { 2848 int err; 2849 2850 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2851 if (!err) 2852 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2853 sc->txsdma.dd_desc_paddr, 2854 ATH_TXSTATUS_RING_SIZE); 2855 2856 return err; 2857 } 2858 2859 int ath_tx_init(struct ath_softc *sc, int nbufs) 2860 { 2861 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2862 int error = 0; 2863 2864 spin_lock_init(&sc->tx.txbuflock); 2865 2866 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2867 "tx", nbufs, 1, 1); 2868 if (error != 0) { 2869 ath_err(common, 2870 "Failed to allocate tx descriptors: %d\n", error); 2871 return error; 2872 } 2873 2874 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2875 "beacon", ATH_BCBUF, 1, 1); 2876 if (error != 0) { 2877 ath_err(common, 2878 "Failed to allocate beacon descriptors: %d\n", error); 2879 return error; 2880 } 2881 2882 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2883 2884 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2885 error = ath_tx_edma_init(sc); 2886 2887 return error; 2888 } 2889 2890 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2891 { 2892 struct ath_atx_tid *tid; 2893 int tidno, acno; 2894 2895 for (tidno = 0, tid = &an->tid[tidno]; 2896 tidno < IEEE80211_NUM_TIDS; 2897 tidno++, tid++) { 2898 tid->an = an; 2899 tid->tidno = tidno; 2900 tid->seq_start = tid->seq_next = 0; 2901 tid->baw_size = WME_MAX_BA; 2902 tid->baw_head = tid->baw_tail = 0; 2903 tid->active = false; 2904 tid->clear_ps_filter = true; 2905 __skb_queue_head_init(&tid->buf_q); 2906 __skb_queue_head_init(&tid->retry_q); 2907 INIT_LIST_HEAD(&tid->list); 2908 acno = TID_TO_WME_AC(tidno); 2909 tid->txq = sc->tx.txq_map[acno]; 2910 } 2911 } 2912 2913 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2914 { 2915 struct ath_atx_tid *tid; 2916 struct ath_txq *txq; 2917 int tidno; 2918 2919 for (tidno = 0, tid = &an->tid[tidno]; 2920 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 2921 2922 txq = tid->txq; 2923 2924 ath_txq_lock(sc, txq); 2925 2926 if (!list_empty(&tid->list)) 2927 list_del_init(&tid->list); 2928 2929 ath_tid_drain(sc, txq, tid); 2930 tid->active = false; 2931 2932 ath_txq_unlock(sc, txq); 2933 } 2934 } 2935 2936 #ifdef CONFIG_ATH9K_TX99 2937 2938 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2939 struct ath_tx_control *txctl) 2940 { 2941 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2942 struct ath_frame_info *fi = get_frame_info(skb); 2943 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2944 struct ath_buf *bf; 2945 int padpos, padsize; 2946 2947 padpos = ieee80211_hdrlen(hdr->frame_control); 2948 padsize = padpos & 3; 2949 2950 if (padsize && skb->len > padpos) { 2951 if (skb_headroom(skb) < padsize) { 2952 ath_dbg(common, XMIT, 2953 "tx99 padding failed\n"); 2954 return -EINVAL; 2955 } 2956 2957 skb_push(skb, padsize); 2958 memmove(skb->data, skb->data + padsize, padpos); 2959 } 2960 2961 fi->keyix = ATH9K_TXKEYIX_INVALID; 2962 fi->framelen = skb->len + FCS_LEN; 2963 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2964 2965 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2966 if (!bf) { 2967 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2968 return -EINVAL; 2969 } 2970 2971 ath_set_rates(sc->tx99_vif, NULL, bf); 2972 2973 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2974 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2975 2976 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2977 2978 return 0; 2979 } 2980 2981 #endif /* CONFIG_ATH9K_TX99 */ 2982