xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/xmit.c (revision cce8e04c)
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20 
21 #define BITS_PER_BYTE           8
22 #define OFDM_PLCP_BITS          22
23 #define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF                   8
25 #define L_LTF                   8
26 #define L_SIG                   4
27 #define HT_SIG                  8
28 #define HT_STF                  4
29 #define HT_LTF(_ns)             (4 * (_ns))
30 #define SYMBOL_TIME(_ns)        ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)  /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t)         ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t)  (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 
37 
38 static u16 bits_per_symbol[][2] = {
39 	/* 20MHz 40MHz */
40 	{    26,   54 },     /*  0: BPSK */
41 	{    52,  108 },     /*  1: QPSK 1/2 */
42 	{    78,  162 },     /*  2: QPSK 3/4 */
43 	{   104,  216 },     /*  3: 16-QAM 1/2 */
44 	{   156,  324 },     /*  4: 16-QAM 3/4 */
45 	{   208,  432 },     /*  5: 64-QAM 2/3 */
46 	{   234,  486 },     /*  6: 64-QAM 3/4 */
47 	{   260,  540 },     /*  7: 64-QAM 5/6 */
48 };
49 
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 			       struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 			    int tx_flags, struct ath_txq *txq,
54 			    struct ieee80211_sta *sta);
55 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
56 				struct ath_txq *txq, struct list_head *bf_q,
57 				struct ieee80211_sta *sta,
58 				struct ath_tx_status *ts, int txok);
59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
60 			     struct list_head *head, bool internal);
61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 			     struct ath_tx_status *ts, int nframes, int nbad,
63 			     int txok);
64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 			      struct ath_buf *bf);
66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 					   struct ath_txq *txq,
68 					   struct ath_atx_tid *tid,
69 					   struct sk_buff *skb);
70 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
71 			  struct ath_tx_control *txctl);
72 
73 enum {
74 	MCS_HT20,
75 	MCS_HT20_SGI,
76 	MCS_HT40,
77 	MCS_HT40_SGI,
78 };
79 
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
83 
84 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
85 {
86 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
87 	struct ieee80211_sta *sta = info->status.status_driver_data[0];
88 
89 	if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS |
90 			   IEEE80211_TX_STATUS_EOSP)) {
91 		ieee80211_tx_status(hw, skb);
92 		return;
93 	}
94 
95 	if (sta)
96 		ieee80211_tx_status_noskb(hw, sta, info);
97 
98 	dev_kfree_skb(skb);
99 }
100 
101 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
102 	__releases(&txq->axq_lock)
103 {
104 	struct ieee80211_hw *hw = sc->hw;
105 	struct sk_buff_head q;
106 	struct sk_buff *skb;
107 
108 	__skb_queue_head_init(&q);
109 	skb_queue_splice_init(&txq->complete_q, &q);
110 	spin_unlock_bh(&txq->axq_lock);
111 
112 	while ((skb = __skb_dequeue(&q)))
113 		ath_tx_status(hw, skb);
114 }
115 
116 void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
117 {
118 	struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
119 	struct ath_chanctx *ctx = avp->chanctx;
120 	struct ath_acq *acq;
121 	struct list_head *tid_list;
122 	u8 acno = TID_TO_WME_AC(tid->tidno);
123 
124 	if (!ctx || !list_empty(&tid->list))
125 		return;
126 
127 
128 	acq = &ctx->acq[acno];
129 	if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) &&
130 	    tid->an->airtime_deficit[acno] > 0)
131 		tid_list = &acq->acq_new;
132 	else
133 		tid_list = &acq->acq_old;
134 
135 	list_add_tail(&tid->list, tid_list);
136 }
137 
138 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
139 {
140 	struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
141 	struct ath_chanctx *ctx = avp->chanctx;
142 	struct ath_acq *acq;
143 
144 	if (!ctx || !list_empty(&tid->list))
145 		return;
146 
147 	acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
148 	spin_lock_bh(&acq->lock);
149 	__ath_tx_queue_tid(sc, tid);
150 	spin_unlock_bh(&acq->lock);
151 }
152 
153 
154 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
155 {
156 	struct ath_softc *sc = hw->priv;
157 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
158 	struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
159 	struct ath_txq *txq = tid->txq;
160 
161 	ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
162 		queue->sta ? queue->sta->addr : queue->vif->addr,
163 		tid->tidno);
164 
165 	ath_txq_lock(sc, txq);
166 
167 	tid->has_queued = true;
168 	ath_tx_queue_tid(sc, tid);
169 	ath_txq_schedule(sc, txq);
170 
171 	ath_txq_unlock(sc, txq);
172 }
173 
174 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
175 {
176 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
177 	BUILD_BUG_ON(sizeof(struct ath_frame_info) >
178 		     sizeof(tx_info->rate_driver_data));
179 	return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
180 }
181 
182 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
183 {
184 	if (!tid->an->sta)
185 		return;
186 
187 	ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
188 			   seqno << IEEE80211_SEQ_SEQ_SHIFT);
189 }
190 
191 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
192 			  struct ath_buf *bf)
193 {
194 	ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
195 			       ARRAY_SIZE(bf->rates));
196 }
197 
198 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
199 			     struct sk_buff *skb)
200 {
201 	struct ath_frame_info *fi = get_frame_info(skb);
202 	int q = fi->txq;
203 
204 	if (q < 0)
205 		return;
206 
207 	txq = sc->tx.txq_map[q];
208 	if (WARN_ON(--txq->pending_frames < 0))
209 		txq->pending_frames = 0;
210 
211 }
212 
213 static struct ath_atx_tid *
214 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
215 {
216 	u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
217 	return ATH_AN_2_TID(an, tidno);
218 }
219 
220 static struct sk_buff *
221 ath_tid_pull(struct ath_atx_tid *tid)
222 {
223 	struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
224 	struct ath_softc *sc = tid->an->sc;
225 	struct ieee80211_hw *hw = sc->hw;
226 	struct ath_tx_control txctl = {
227 		.txq = tid->txq,
228 		.sta = tid->an->sta,
229 	};
230 	struct sk_buff *skb;
231 	struct ath_frame_info *fi;
232 	int q;
233 
234 	if (!tid->has_queued)
235 		return NULL;
236 
237 	skb = ieee80211_tx_dequeue(hw, txq);
238 	if (!skb) {
239 		tid->has_queued = false;
240 		return NULL;
241 	}
242 
243 	if (ath_tx_prepare(hw, skb, &txctl)) {
244 		ieee80211_free_txskb(hw, skb);
245 		return NULL;
246 	}
247 
248 	q = skb_get_queue_mapping(skb);
249 	if (tid->txq == sc->tx.txq_map[q]) {
250 		fi = get_frame_info(skb);
251 		fi->txq = q;
252 		++tid->txq->pending_frames;
253 	}
254 
255 	return skb;
256 }
257 
258 
259 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
260 {
261 	return !skb_queue_empty(&tid->retry_q) || tid->has_queued;
262 }
263 
264 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
265 {
266 	struct sk_buff *skb;
267 
268 	skb = __skb_dequeue(&tid->retry_q);
269 	if (!skb)
270 		skb = ath_tid_pull(tid);
271 
272 	return skb;
273 }
274 
275 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
276 {
277 	struct ath_txq *txq = tid->txq;
278 	struct sk_buff *skb;
279 	struct ath_buf *bf;
280 	struct list_head bf_head;
281 	struct ath_tx_status ts;
282 	struct ath_frame_info *fi;
283 	bool sendbar = false;
284 
285 	INIT_LIST_HEAD(&bf_head);
286 
287 	memset(&ts, 0, sizeof(ts));
288 
289 	while ((skb = __skb_dequeue(&tid->retry_q))) {
290 		fi = get_frame_info(skb);
291 		bf = fi->bf;
292 		if (!bf) {
293 			ath_txq_skb_done(sc, txq, skb);
294 			ieee80211_free_txskb(sc->hw, skb);
295 			continue;
296 		}
297 
298 		if (fi->baw_tracked) {
299 			ath_tx_update_baw(sc, tid, bf);
300 			sendbar = true;
301 		}
302 
303 		list_add_tail(&bf->list, &bf_head);
304 		ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
305 	}
306 
307 	if (sendbar) {
308 		ath_txq_unlock(sc, txq);
309 		ath_send_bar(tid, tid->seq_start);
310 		ath_txq_lock(sc, txq);
311 	}
312 }
313 
314 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
315 			      struct ath_buf *bf)
316 {
317 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
318 	u16 seqno = bf->bf_state.seqno;
319 	int index, cindex;
320 
321 	if (!fi->baw_tracked)
322 		return;
323 
324 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
325 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
326 
327 	__clear_bit(cindex, tid->tx_buf);
328 
329 	while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
330 		INCR(tid->seq_start, IEEE80211_SEQ_MAX);
331 		INCR(tid->baw_head, ATH_TID_MAX_BUFS);
332 		if (tid->bar_index >= 0)
333 			tid->bar_index--;
334 	}
335 }
336 
337 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
338 			     struct ath_buf *bf)
339 {
340 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
341 	u16 seqno = bf->bf_state.seqno;
342 	int index, cindex;
343 
344 	if (fi->baw_tracked)
345 		return;
346 
347 	index  = ATH_BA_INDEX(tid->seq_start, seqno);
348 	cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
349 	__set_bit(cindex, tid->tx_buf);
350 	fi->baw_tracked = 1;
351 
352 	if (index >= ((tid->baw_tail - tid->baw_head) &
353 		(ATH_TID_MAX_BUFS - 1))) {
354 		tid->baw_tail = cindex;
355 		INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
356 	}
357 }
358 
359 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
360 			  struct ath_atx_tid *tid)
361 
362 {
363 	struct sk_buff *skb;
364 	struct ath_buf *bf;
365 	struct list_head bf_head;
366 	struct ath_tx_status ts;
367 	struct ath_frame_info *fi;
368 
369 	memset(&ts, 0, sizeof(ts));
370 	INIT_LIST_HEAD(&bf_head);
371 
372 	while ((skb = ath_tid_dequeue(tid))) {
373 		fi = get_frame_info(skb);
374 		bf = fi->bf;
375 
376 		if (!bf) {
377 			ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
378 			continue;
379 		}
380 
381 		list_add_tail(&bf->list, &bf_head);
382 		ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
383 	}
384 }
385 
386 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
387 			     struct sk_buff *skb, int count)
388 {
389 	struct ath_frame_info *fi = get_frame_info(skb);
390 	struct ath_buf *bf = fi->bf;
391 	struct ieee80211_hdr *hdr;
392 	int prev = fi->retries;
393 
394 	TX_STAT_INC(sc, txq->axq_qnum, a_retries);
395 	fi->retries += count;
396 
397 	if (prev > 0)
398 		return;
399 
400 	hdr = (struct ieee80211_hdr *)skb->data;
401 	hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
402 	dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
403 		sizeof(*hdr), DMA_TO_DEVICE);
404 }
405 
406 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
407 {
408 	struct ath_buf *bf = NULL;
409 
410 	spin_lock_bh(&sc->tx.txbuflock);
411 
412 	if (unlikely(list_empty(&sc->tx.txbuf))) {
413 		spin_unlock_bh(&sc->tx.txbuflock);
414 		return NULL;
415 	}
416 
417 	bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
418 	list_del(&bf->list);
419 
420 	spin_unlock_bh(&sc->tx.txbuflock);
421 
422 	return bf;
423 }
424 
425 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
426 {
427 	spin_lock_bh(&sc->tx.txbuflock);
428 	list_add_tail(&bf->list, &sc->tx.txbuf);
429 	spin_unlock_bh(&sc->tx.txbuflock);
430 }
431 
432 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
433 {
434 	struct ath_buf *tbf;
435 
436 	tbf = ath_tx_get_buffer(sc);
437 	if (WARN_ON(!tbf))
438 		return NULL;
439 
440 	ATH_TXBUF_RESET(tbf);
441 
442 	tbf->bf_mpdu = bf->bf_mpdu;
443 	tbf->bf_buf_addr = bf->bf_buf_addr;
444 	memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
445 	tbf->bf_state = bf->bf_state;
446 	tbf->bf_state.stale = false;
447 
448 	return tbf;
449 }
450 
451 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
452 			        struct ath_tx_status *ts, int txok,
453 			        int *nframes, int *nbad)
454 {
455 	struct ath_frame_info *fi;
456 	u16 seq_st = 0;
457 	u32 ba[WME_BA_BMP_SIZE >> 5];
458 	int ba_index;
459 	int isaggr = 0;
460 
461 	*nbad = 0;
462 	*nframes = 0;
463 
464 	isaggr = bf_isaggr(bf);
465 	if (isaggr) {
466 		seq_st = ts->ts_seqnum;
467 		memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
468 	}
469 
470 	while (bf) {
471 		fi = get_frame_info(bf->bf_mpdu);
472 		ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
473 
474 		(*nframes)++;
475 		if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
476 			(*nbad)++;
477 
478 		bf = bf->bf_next;
479 	}
480 }
481 
482 
483 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
484 				 struct ath_buf *bf, struct list_head *bf_q,
485 				 struct ieee80211_sta *sta,
486 				 struct ath_atx_tid *tid,
487 				 struct ath_tx_status *ts, int txok)
488 {
489 	struct ath_node *an = NULL;
490 	struct sk_buff *skb;
491 	struct ieee80211_hdr *hdr;
492 	struct ieee80211_tx_info *tx_info;
493 	struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
494 	struct list_head bf_head;
495 	struct sk_buff_head bf_pending;
496 	u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
497 	u32 ba[WME_BA_BMP_SIZE >> 5];
498 	int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
499 	bool rc_update = true, isba;
500 	struct ieee80211_tx_rate rates[4];
501 	struct ath_frame_info *fi;
502 	int nframes;
503 	bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
504 	int i, retries;
505 	int bar_index = -1;
506 
507 	skb = bf->bf_mpdu;
508 	hdr = (struct ieee80211_hdr *)skb->data;
509 
510 	tx_info = IEEE80211_SKB_CB(skb);
511 
512 	memcpy(rates, bf->rates, sizeof(rates));
513 
514 	retries = ts->ts_longretry + 1;
515 	for (i = 0; i < ts->ts_rateindex; i++)
516 		retries += rates[i].count;
517 
518 	if (!sta) {
519 		INIT_LIST_HEAD(&bf_head);
520 		while (bf) {
521 			bf_next = bf->bf_next;
522 
523 			if (!bf->bf_state.stale || bf_next != NULL)
524 				list_move_tail(&bf->list, &bf_head);
525 
526 			ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
527 
528 			bf = bf_next;
529 		}
530 		return;
531 	}
532 
533 	an = (struct ath_node *)sta->drv_priv;
534 	seq_first = tid->seq_start;
535 	isba = ts->ts_flags & ATH9K_TX_BA;
536 
537 	/*
538 	 * The hardware occasionally sends a tx status for the wrong TID.
539 	 * In this case, the BA status cannot be considered valid and all
540 	 * subframes need to be retransmitted
541 	 *
542 	 * Only BlockAcks have a TID and therefore normal Acks cannot be
543 	 * checked
544 	 */
545 	if (isba && tid->tidno != ts->tid)
546 		txok = false;
547 
548 	isaggr = bf_isaggr(bf);
549 	memset(ba, 0, WME_BA_BMP_SIZE >> 3);
550 
551 	if (isaggr && txok) {
552 		if (ts->ts_flags & ATH9K_TX_BA) {
553 			seq_st = ts->ts_seqnum;
554 			memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
555 		} else {
556 			/*
557 			 * AR5416 can become deaf/mute when BA
558 			 * issue happens. Chip needs to be reset.
559 			 * But AP code may have sychronization issues
560 			 * when perform internal reset in this routine.
561 			 * Only enable reset in STA mode for now.
562 			 */
563 			if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
564 				needreset = 1;
565 		}
566 	}
567 
568 	__skb_queue_head_init(&bf_pending);
569 
570 	ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
571 	while (bf) {
572 		u16 seqno = bf->bf_state.seqno;
573 
574 		txfail = txpending = sendbar = 0;
575 		bf_next = bf->bf_next;
576 
577 		skb = bf->bf_mpdu;
578 		tx_info = IEEE80211_SKB_CB(skb);
579 		fi = get_frame_info(skb);
580 
581 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
582 		    !tid->active) {
583 			/*
584 			 * Outside of the current BlockAck window,
585 			 * maybe part of a previous session
586 			 */
587 			txfail = 1;
588 		} else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
589 			/* transmit completion, subframe is
590 			 * acked by block ack */
591 			acked_cnt++;
592 		} else if (!isaggr && txok) {
593 			/* transmit completion */
594 			acked_cnt++;
595 		} else if (flush) {
596 			txpending = 1;
597 		} else if (fi->retries < ATH_MAX_SW_RETRIES) {
598 			if (txok || !an->sleeping)
599 				ath_tx_set_retry(sc, txq, bf->bf_mpdu,
600 						 retries);
601 
602 			txpending = 1;
603 		} else {
604 			txfail = 1;
605 			txfail_cnt++;
606 			bar_index = max_t(int, bar_index,
607 				ATH_BA_INDEX(seq_first, seqno));
608 		}
609 
610 		/*
611 		 * Make sure the last desc is reclaimed if it
612 		 * not a holding desc.
613 		 */
614 		INIT_LIST_HEAD(&bf_head);
615 		if (bf_next != NULL || !bf_last->bf_state.stale)
616 			list_move_tail(&bf->list, &bf_head);
617 
618 		if (!txpending) {
619 			/*
620 			 * complete the acked-ones/xretried ones; update
621 			 * block-ack window
622 			 */
623 			ath_tx_update_baw(sc, tid, bf);
624 
625 			if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
626 				memcpy(tx_info->control.rates, rates, sizeof(rates));
627 				ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
628 				rc_update = false;
629 				if (bf == bf->bf_lastbf)
630 					ath_dynack_sample_tx_ts(sc->sc_ah,
631 								bf->bf_mpdu,
632 								ts, sta);
633 			}
634 
635 			ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
636 				!txfail);
637 		} else {
638 			if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
639 				tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
640 				ieee80211_sta_eosp(sta);
641 			}
642 			/* retry the un-acked ones */
643 			if (bf->bf_next == NULL && bf_last->bf_state.stale) {
644 				struct ath_buf *tbf;
645 
646 				tbf = ath_clone_txbuf(sc, bf_last);
647 				/*
648 				 * Update tx baw and complete the
649 				 * frame with failed status if we
650 				 * run out of tx buf.
651 				 */
652 				if (!tbf) {
653 					ath_tx_update_baw(sc, tid, bf);
654 
655 					ath_tx_complete_buf(sc, bf, txq,
656 							    &bf_head, NULL, ts,
657 							    0);
658 					bar_index = max_t(int, bar_index,
659 						ATH_BA_INDEX(seq_first, seqno));
660 					break;
661 				}
662 
663 				fi->bf = tbf;
664 			}
665 
666 			/*
667 			 * Put this buffer to the temporary pending
668 			 * queue to retain ordering
669 			 */
670 			__skb_queue_tail(&bf_pending, skb);
671 		}
672 
673 		bf = bf_next;
674 	}
675 
676 	/* prepend un-acked frames to the beginning of the pending frame queue */
677 	if (!skb_queue_empty(&bf_pending)) {
678 		if (an->sleeping)
679 			ieee80211_sta_set_buffered(sta, tid->tidno, true);
680 
681 		skb_queue_splice_tail(&bf_pending, &tid->retry_q);
682 		if (!an->sleeping) {
683 			ath_tx_queue_tid(sc, tid);
684 
685 			if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
686 				tid->clear_ps_filter = true;
687 		}
688 	}
689 
690 	if (bar_index >= 0) {
691 		u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
692 
693 		if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
694 			tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
695 
696 		ath_txq_unlock(sc, txq);
697 		ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
698 		ath_txq_lock(sc, txq);
699 	}
700 
701 	if (needreset)
702 		ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
703 }
704 
705 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
706 {
707     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
708     return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
709 }
710 
711 static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_node *an,
712 				 struct ath_atx_tid *tid, struct ath_buf *bf,
713 				 struct ath_tx_status *ts)
714 {
715 	struct ath_txq *txq = tid->txq;
716 	u32 airtime = 0;
717 	int i;
718 
719 	airtime += ts->duration * (ts->ts_longretry + 1);
720 	for(i = 0; i < ts->ts_rateindex; i++) {
721 		int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
722 		airtime += rate_dur * bf->rates[i].count;
723 	}
724 
725 	if (sc->airtime_flags & AIRTIME_USE_TX) {
726 		int q = txq->mac80211_qnum;
727 		struct ath_acq *acq = &sc->cur_chan->acq[q];
728 
729 		spin_lock_bh(&acq->lock);
730 		an->airtime_deficit[q] -= airtime;
731 		if (an->airtime_deficit[q] <= 0)
732 			__ath_tx_queue_tid(sc, tid);
733 		spin_unlock_bh(&acq->lock);
734 	}
735 	ath_debug_airtime(sc, an, 0, airtime);
736 }
737 
738 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
739 				  struct ath_tx_status *ts, struct ath_buf *bf,
740 				  struct list_head *bf_head)
741 {
742 	struct ieee80211_hw *hw = sc->hw;
743 	struct ieee80211_tx_info *info;
744 	struct ieee80211_sta *sta;
745 	struct ieee80211_hdr *hdr;
746 	struct ath_atx_tid *tid = NULL;
747 	bool txok, flush;
748 
749 	txok = !(ts->ts_status & ATH9K_TXERR_MASK);
750 	flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
751 	txq->axq_tx_inprogress = false;
752 
753 	txq->axq_depth--;
754 	if (bf_is_ampdu_not_probing(bf))
755 		txq->axq_ampdu_depth--;
756 
757 	ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
758 					     ts->ts_rateindex);
759 
760 	hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
761 	sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
762 	if (sta) {
763 		struct ath_node *an = (struct ath_node *)sta->drv_priv;
764 		tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
765 		ath_tx_count_airtime(sc, an, tid, bf, ts);
766 		if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
767 			tid->clear_ps_filter = true;
768 	}
769 
770 	if (!bf_isampdu(bf)) {
771 		if (!flush) {
772 			info = IEEE80211_SKB_CB(bf->bf_mpdu);
773 			memcpy(info->control.rates, bf->rates,
774 			       sizeof(info->control.rates));
775 			ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
776 			ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts,
777 						sta);
778 		}
779 		ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
780 	} else
781 		ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
782 
783 	if (!flush)
784 		ath_txq_schedule(sc, txq);
785 }
786 
787 static bool ath_lookup_legacy(struct ath_buf *bf)
788 {
789 	struct sk_buff *skb;
790 	struct ieee80211_tx_info *tx_info;
791 	struct ieee80211_tx_rate *rates;
792 	int i;
793 
794 	skb = bf->bf_mpdu;
795 	tx_info = IEEE80211_SKB_CB(skb);
796 	rates = tx_info->control.rates;
797 
798 	for (i = 0; i < 4; i++) {
799 		if (!rates[i].count || rates[i].idx < 0)
800 			break;
801 
802 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
803 			return true;
804 	}
805 
806 	return false;
807 }
808 
809 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
810 			   struct ath_atx_tid *tid)
811 {
812 	struct sk_buff *skb;
813 	struct ieee80211_tx_info *tx_info;
814 	struct ieee80211_tx_rate *rates;
815 	u32 max_4ms_framelen, frmlen;
816 	u16 aggr_limit, bt_aggr_limit, legacy = 0;
817 	int q = tid->txq->mac80211_qnum;
818 	int i;
819 
820 	skb = bf->bf_mpdu;
821 	tx_info = IEEE80211_SKB_CB(skb);
822 	rates = bf->rates;
823 
824 	/*
825 	 * Find the lowest frame length among the rate series that will have a
826 	 * 4ms (or TXOP limited) transmit duration.
827 	 */
828 	max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
829 
830 	for (i = 0; i < 4; i++) {
831 		int modeidx;
832 
833 		if (!rates[i].count)
834 			continue;
835 
836 		if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
837 			legacy = 1;
838 			break;
839 		}
840 
841 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
842 			modeidx = MCS_HT40;
843 		else
844 			modeidx = MCS_HT20;
845 
846 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
847 			modeidx++;
848 
849 		frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
850 		max_4ms_framelen = min(max_4ms_framelen, frmlen);
851 	}
852 
853 	/*
854 	 * limit aggregate size by the minimum rate if rate selected is
855 	 * not a probe rate, if rate selected is a probe rate then
856 	 * avoid aggregation of this packet.
857 	 */
858 	if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
859 		return 0;
860 
861 	aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
862 
863 	/*
864 	 * Override the default aggregation limit for BTCOEX.
865 	 */
866 	bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
867 	if (bt_aggr_limit)
868 		aggr_limit = bt_aggr_limit;
869 
870 	if (tid->an->maxampdu)
871 		aggr_limit = min(aggr_limit, tid->an->maxampdu);
872 
873 	return aggr_limit;
874 }
875 
876 /*
877  * Returns the number of delimiters to be added to
878  * meet the minimum required mpdudensity.
879  */
880 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
881 				  struct ath_buf *bf, u16 frmlen,
882 				  bool first_subfrm)
883 {
884 #define FIRST_DESC_NDELIMS 60
885 	u32 nsymbits, nsymbols;
886 	u16 minlen;
887 	u8 flags, rix;
888 	int width, streams, half_gi, ndelim, mindelim;
889 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
890 
891 	/* Select standard number of delimiters based on frame length alone */
892 	ndelim = ATH_AGGR_GET_NDELIM(frmlen);
893 
894 	/*
895 	 * If encryption enabled, hardware requires some more padding between
896 	 * subframes.
897 	 * TODO - this could be improved to be dependent on the rate.
898 	 *      The hardware can keep up at lower rates, but not higher rates
899 	 */
900 	if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
901 	    !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
902 		ndelim += ATH_AGGR_ENCRYPTDELIM;
903 
904 	/*
905 	 * Add delimiter when using RTS/CTS with aggregation
906 	 * and non enterprise AR9003 card
907 	 */
908 	if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
909 	    (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
910 		ndelim = max(ndelim, FIRST_DESC_NDELIMS);
911 
912 	/*
913 	 * Convert desired mpdu density from microeconds to bytes based
914 	 * on highest rate in rate series (i.e. first rate) to determine
915 	 * required minimum length for subframe. Take into account
916 	 * whether high rate is 20 or 40Mhz and half or full GI.
917 	 *
918 	 * If there is no mpdu density restriction, no further calculation
919 	 * is needed.
920 	 */
921 
922 	if (tid->an->mpdudensity == 0)
923 		return ndelim;
924 
925 	rix = bf->rates[0].idx;
926 	flags = bf->rates[0].flags;
927 	width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
928 	half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
929 
930 	if (half_gi)
931 		nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
932 	else
933 		nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
934 
935 	if (nsymbols == 0)
936 		nsymbols = 1;
937 
938 	streams = HT_RC_2_STREAMS(rix);
939 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
940 	minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
941 
942 	if (frmlen < minlen) {
943 		mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
944 		ndelim = max(mindelim, ndelim);
945 	}
946 
947 	return ndelim;
948 }
949 
950 static struct ath_buf *
951 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
952 			struct ath_atx_tid *tid)
953 {
954 	struct ieee80211_tx_info *tx_info;
955 	struct ath_frame_info *fi;
956 	struct sk_buff *skb, *first_skb = NULL;
957 	struct ath_buf *bf;
958 	u16 seqno;
959 
960 	while (1) {
961 		skb = ath_tid_dequeue(tid);
962 		if (!skb)
963 			break;
964 
965 		fi = get_frame_info(skb);
966 		bf = fi->bf;
967 		if (!fi->bf)
968 			bf = ath_tx_setup_buffer(sc, txq, tid, skb);
969 		else
970 			bf->bf_state.stale = false;
971 
972 		if (!bf) {
973 			ath_txq_skb_done(sc, txq, skb);
974 			ieee80211_free_txskb(sc->hw, skb);
975 			continue;
976 		}
977 
978 		bf->bf_next = NULL;
979 		bf->bf_lastbf = bf;
980 
981 		tx_info = IEEE80211_SKB_CB(skb);
982 		tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT |
983 				    IEEE80211_TX_STATUS_EOSP);
984 
985 		/*
986 		 * No aggregation session is running, but there may be frames
987 		 * from a previous session or a failed attempt in the queue.
988 		 * Send them out as normal data frames
989 		 */
990 		if (!tid->active)
991 			tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
992 
993 		if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
994 			bf->bf_state.bf_type = 0;
995 			return bf;
996 		}
997 
998 		bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
999 		seqno = bf->bf_state.seqno;
1000 
1001 		/* do not step over block-ack window */
1002 		if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
1003 			__skb_queue_tail(&tid->retry_q, skb);
1004 
1005 			/* If there are other skbs in the retry q, they are
1006 			 * probably within the BAW, so loop immediately to get
1007 			 * one of them. Otherwise the queue can get stuck. */
1008 			if (!skb_queue_is_first(&tid->retry_q, skb) &&
1009 			    !WARN_ON(skb == first_skb)) {
1010 				if(!first_skb) /* infinite loop prevention */
1011 					first_skb = skb;
1012 				continue;
1013 			}
1014 			break;
1015 		}
1016 
1017 		if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1018 			struct ath_tx_status ts = {};
1019 			struct list_head bf_head;
1020 
1021 			INIT_LIST_HEAD(&bf_head);
1022 			list_add(&bf->list, &bf_head);
1023 			ath_tx_update_baw(sc, tid, bf);
1024 			ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1025 			continue;
1026 		}
1027 
1028 		if (bf_isampdu(bf))
1029 			ath_tx_addto_baw(sc, tid, bf);
1030 
1031 		return bf;
1032 	}
1033 
1034 	return NULL;
1035 }
1036 
1037 static int
1038 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1039 		 struct ath_atx_tid *tid, struct list_head *bf_q,
1040 		 struct ath_buf *bf_first)
1041 {
1042 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1043 	struct ath_buf *bf = bf_first, *bf_prev = NULL;
1044 	int nframes = 0, ndelim;
1045 	u16 aggr_limit = 0, al = 0, bpad = 0,
1046 	    al_delta, h_baw = tid->baw_size / 2;
1047 	struct ieee80211_tx_info *tx_info;
1048 	struct ath_frame_info *fi;
1049 	struct sk_buff *skb;
1050 
1051 
1052 	bf = bf_first;
1053 	aggr_limit = ath_lookup_rate(sc, bf, tid);
1054 
1055 	while (bf)
1056 	{
1057 		skb = bf->bf_mpdu;
1058 		fi = get_frame_info(skb);
1059 
1060 		/* do not exceed aggregation limit */
1061 		al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1062 		if (nframes) {
1063 			if (aggr_limit < al + bpad + al_delta ||
1064 			    ath_lookup_legacy(bf) || nframes >= h_baw)
1065 				goto stop;
1066 
1067 			tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1068 			if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1069 			    !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1070 				goto stop;
1071 		}
1072 
1073 		/* add padding for previous frame to aggregation length */
1074 		al += bpad + al_delta;
1075 
1076 		/*
1077 		 * Get the delimiters needed to meet the MPDU
1078 		 * density for this node.
1079 		 */
1080 		ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1081 						!nframes);
1082 		bpad = PADBYTES(al_delta) + (ndelim << 2);
1083 
1084 		nframes++;
1085 		bf->bf_next = NULL;
1086 
1087 		/* link buffers of this frame to the aggregate */
1088 		bf->bf_state.ndelim = ndelim;
1089 
1090 		list_add_tail(&bf->list, bf_q);
1091 		if (bf_prev)
1092 			bf_prev->bf_next = bf;
1093 
1094 		bf_prev = bf;
1095 
1096 		bf = ath_tx_get_tid_subframe(sc, txq, tid);
1097 	}
1098 	goto finish;
1099 stop:
1100 	__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1101 finish:
1102 	bf = bf_first;
1103 	bf->bf_lastbf = bf_prev;
1104 
1105 	if (bf == bf_prev) {
1106 		al = get_frame_info(bf->bf_mpdu)->framelen;
1107 		bf->bf_state.bf_type = BUF_AMPDU;
1108 	} else {
1109 		TX_STAT_INC(sc, txq->axq_qnum, a_aggr);
1110 	}
1111 
1112 	return al;
1113 #undef PADBYTES
1114 }
1115 
1116 /*
1117  * rix - rate index
1118  * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1119  * width  - 0 for 20 MHz, 1 for 40 MHz
1120  * half_gi - to use 4us v/s 3.6 us for symbol time
1121  */
1122 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1123 		     int width, int half_gi, bool shortPreamble)
1124 {
1125 	u32 nbits, nsymbits, duration, nsymbols;
1126 	int streams;
1127 
1128 	/* find number of symbols: PLCP + data */
1129 	streams = HT_RC_2_STREAMS(rix);
1130 	nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1131 	nsymbits = bits_per_symbol[rix % 8][width] * streams;
1132 	nsymbols = (nbits + nsymbits - 1) / nsymbits;
1133 
1134 	if (!half_gi)
1135 		duration = SYMBOL_TIME(nsymbols);
1136 	else
1137 		duration = SYMBOL_TIME_HALFGI(nsymbols);
1138 
1139 	/* addup duration for legacy/ht training and signal fields */
1140 	duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1141 
1142 	return duration;
1143 }
1144 
1145 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1146 {
1147 	int streams = HT_RC_2_STREAMS(mcs);
1148 	int symbols, bits;
1149 	int bytes = 0;
1150 
1151 	usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1152 	symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1153 	bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1154 	bits -= OFDM_PLCP_BITS;
1155 	bytes = bits / 8;
1156 	if (bytes > 65532)
1157 		bytes = 65532;
1158 
1159 	return bytes;
1160 }
1161 
1162 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1163 {
1164 	u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1165 	int mcs;
1166 
1167 	/* 4ms is the default (and maximum) duration */
1168 	if (!txop || txop > 4096)
1169 		txop = 4096;
1170 
1171 	cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1172 	cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1173 	cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1174 	cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1175 	for (mcs = 0; mcs < 32; mcs++) {
1176 		cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1177 		cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1178 		cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1179 		cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1180 	}
1181 }
1182 
1183 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1184 			       u8 rateidx, bool is_40, bool is_cck)
1185 {
1186 	u8 max_power;
1187 	struct sk_buff *skb;
1188 	struct ath_frame_info *fi;
1189 	struct ieee80211_tx_info *info;
1190 	struct ath_hw *ah = sc->sc_ah;
1191 
1192 	if (sc->tx99_state || !ah->tpc_enabled)
1193 		return MAX_RATE_POWER;
1194 
1195 	skb = bf->bf_mpdu;
1196 	fi = get_frame_info(skb);
1197 	info = IEEE80211_SKB_CB(skb);
1198 
1199 	if (!AR_SREV_9300_20_OR_LATER(ah)) {
1200 		int txpower = fi->tx_power;
1201 
1202 		if (is_40) {
1203 			u8 power_ht40delta;
1204 			struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1205 			u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1206 
1207 			if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1208 				bool is_2ghz;
1209 				struct modal_eep_header *pmodal;
1210 
1211 				is_2ghz = info->band == NL80211_BAND_2GHZ;
1212 				pmodal = &eep->modalHeader[is_2ghz];
1213 				power_ht40delta = pmodal->ht40PowerIncForPdadc;
1214 			} else {
1215 				power_ht40delta = 2;
1216 			}
1217 			txpower += power_ht40delta;
1218 		}
1219 
1220 		if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1221 		    AR_SREV_9271(ah)) {
1222 			txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1223 		} else if (AR_SREV_9280_20_OR_LATER(ah)) {
1224 			s8 power_offset;
1225 
1226 			power_offset = ah->eep_ops->get_eeprom(ah,
1227 							EEP_PWR_TABLE_OFFSET);
1228 			txpower -= 2 * power_offset;
1229 		}
1230 
1231 		if (OLC_FOR_AR9280_20_LATER && is_cck)
1232 			txpower -= 2;
1233 
1234 		txpower = max(txpower, 0);
1235 		max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1236 
1237 		/* XXX: clamp minimum TX power at 1 for AR9160 since if
1238 		 * max_power is set to 0, frames are transmitted at max
1239 		 * TX power
1240 		 */
1241 		if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1242 			max_power = 1;
1243 	} else if (!bf->bf_state.bfs_paprd) {
1244 		if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1245 			max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1246 					  fi->tx_power);
1247 		else
1248 			max_power = min_t(u8, ah->tx_power[rateidx],
1249 					  fi->tx_power);
1250 	} else {
1251 		max_power = ah->paprd_training_power;
1252 	}
1253 
1254 	return max_power;
1255 }
1256 
1257 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1258 			     struct ath_tx_info *info, int len, bool rts)
1259 {
1260 	struct ath_hw *ah = sc->sc_ah;
1261 	struct ath_common *common = ath9k_hw_common(ah);
1262 	struct sk_buff *skb;
1263 	struct ieee80211_tx_info *tx_info;
1264 	struct ieee80211_tx_rate *rates;
1265 	const struct ieee80211_rate *rate;
1266 	struct ieee80211_hdr *hdr;
1267 	struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1268 	u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1269 	int i;
1270 	u8 rix = 0;
1271 
1272 	skb = bf->bf_mpdu;
1273 	tx_info = IEEE80211_SKB_CB(skb);
1274 	rates = bf->rates;
1275 	hdr = (struct ieee80211_hdr *)skb->data;
1276 
1277 	/* set dur_update_en for l-sig computation except for PS-Poll frames */
1278 	info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1279 	info->rtscts_rate = fi->rtscts_rate;
1280 
1281 	for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1282 		bool is_40, is_sgi, is_sp, is_cck;
1283 		int phy;
1284 
1285 		if (!rates[i].count || (rates[i].idx < 0))
1286 			continue;
1287 
1288 		rix = rates[i].idx;
1289 		info->rates[i].Tries = rates[i].count;
1290 
1291 		/*
1292 		 * Handle RTS threshold for unaggregated HT frames.
1293 		 */
1294 		if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1295 		    (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1296 		    unlikely(rts_thresh != (u32) -1)) {
1297 			if (!rts_thresh || (len > rts_thresh))
1298 				rts = true;
1299 		}
1300 
1301 		if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1302 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1303 			info->flags |= ATH9K_TXDESC_RTSENA;
1304 		} else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1305 			info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1306 			info->flags |= ATH9K_TXDESC_CTSENA;
1307 		}
1308 
1309 		if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1310 			info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1311 		if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1312 			info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1313 
1314 		is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1315 		is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1316 		is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1317 
1318 		if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1319 			/* MCS rates */
1320 			info->rates[i].Rate = rix | 0x80;
1321 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1322 					ah->txchainmask, info->rates[i].Rate);
1323 			info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1324 				 is_40, is_sgi, is_sp);
1325 			if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1326 				info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1327 
1328 			info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1329 								is_40, false);
1330 			continue;
1331 		}
1332 
1333 		/* legacy rates */
1334 		rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1335 		if ((tx_info->band == NL80211_BAND_2GHZ) &&
1336 		    !(rate->flags & IEEE80211_RATE_ERP_G))
1337 			phy = WLAN_RC_PHY_CCK;
1338 		else
1339 			phy = WLAN_RC_PHY_OFDM;
1340 
1341 		info->rates[i].Rate = rate->hw_value;
1342 		if (rate->hw_value_short) {
1343 			if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1344 				info->rates[i].Rate |= rate->hw_value_short;
1345 		} else {
1346 			is_sp = false;
1347 		}
1348 
1349 		if (bf->bf_state.bfs_paprd)
1350 			info->rates[i].ChSel = ah->txchainmask;
1351 		else
1352 			info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1353 					ah->txchainmask, info->rates[i].Rate);
1354 
1355 		info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1356 			phy, rate->bitrate * 100, len, rix, is_sp);
1357 
1358 		is_cck = IS_CCK_RATE(info->rates[i].Rate);
1359 		info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1360 							is_cck);
1361 	}
1362 
1363 	/* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1364 	if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1365 		info->flags &= ~ATH9K_TXDESC_RTSENA;
1366 
1367 	/* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1368 	if (info->flags & ATH9K_TXDESC_RTSENA)
1369 		info->flags &= ~ATH9K_TXDESC_CTSENA;
1370 }
1371 
1372 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1373 {
1374 	struct ieee80211_hdr *hdr;
1375 	enum ath9k_pkt_type htype;
1376 	__le16 fc;
1377 
1378 	hdr = (struct ieee80211_hdr *)skb->data;
1379 	fc = hdr->frame_control;
1380 
1381 	if (ieee80211_is_beacon(fc))
1382 		htype = ATH9K_PKT_TYPE_BEACON;
1383 	else if (ieee80211_is_probe_resp(fc))
1384 		htype = ATH9K_PKT_TYPE_PROBE_RESP;
1385 	else if (ieee80211_is_atim(fc))
1386 		htype = ATH9K_PKT_TYPE_ATIM;
1387 	else if (ieee80211_is_pspoll(fc))
1388 		htype = ATH9K_PKT_TYPE_PSPOLL;
1389 	else
1390 		htype = ATH9K_PKT_TYPE_NORMAL;
1391 
1392 	return htype;
1393 }
1394 
1395 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1396 			     struct ath_txq *txq, int len)
1397 {
1398 	struct ath_hw *ah = sc->sc_ah;
1399 	struct ath_buf *bf_first = NULL;
1400 	struct ath_tx_info info;
1401 	u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1402 	bool rts = false;
1403 
1404 	memset(&info, 0, sizeof(info));
1405 	info.is_first = true;
1406 	info.is_last = true;
1407 	info.qcu = txq->axq_qnum;
1408 
1409 	while (bf) {
1410 		struct sk_buff *skb = bf->bf_mpdu;
1411 		struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1412 		struct ath_frame_info *fi = get_frame_info(skb);
1413 		bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1414 
1415 		info.type = get_hw_packet_type(skb);
1416 		if (bf->bf_next)
1417 			info.link = bf->bf_next->bf_daddr;
1418 		else
1419 			info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1420 
1421 		if (!bf_first) {
1422 			bf_first = bf;
1423 
1424 			if (!sc->tx99_state)
1425 				info.flags = ATH9K_TXDESC_INTREQ;
1426 			if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1427 			    txq == sc->tx.uapsdq)
1428 				info.flags |= ATH9K_TXDESC_CLRDMASK;
1429 
1430 			if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1431 				info.flags |= ATH9K_TXDESC_NOACK;
1432 			if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1433 				info.flags |= ATH9K_TXDESC_LDPC;
1434 
1435 			if (bf->bf_state.bfs_paprd)
1436 				info.flags |= (u32) bf->bf_state.bfs_paprd <<
1437 					      ATH9K_TXDESC_PAPRD_S;
1438 
1439 			/*
1440 			 * mac80211 doesn't handle RTS threshold for HT because
1441 			 * the decision has to be taken based on AMPDU length
1442 			 * and aggregation is done entirely inside ath9k.
1443 			 * Set the RTS/CTS flag for the first subframe based
1444 			 * on the threshold.
1445 			 */
1446 			if (aggr && (bf == bf_first) &&
1447 			    unlikely(rts_thresh != (u32) -1)) {
1448 				/*
1449 				 * "len" is the size of the entire AMPDU.
1450 				 */
1451 				if (!rts_thresh || (len > rts_thresh))
1452 					rts = true;
1453 			}
1454 
1455 			if (!aggr)
1456 				len = fi->framelen;
1457 
1458 			ath_buf_set_rate(sc, bf, &info, len, rts);
1459 		}
1460 
1461 		info.buf_addr[0] = bf->bf_buf_addr;
1462 		info.buf_len[0] = skb->len;
1463 		info.pkt_len = fi->framelen;
1464 		info.keyix = fi->keyix;
1465 		info.keytype = fi->keytype;
1466 
1467 		if (aggr) {
1468 			if (bf == bf_first)
1469 				info.aggr = AGGR_BUF_FIRST;
1470 			else if (bf == bf_first->bf_lastbf)
1471 				info.aggr = AGGR_BUF_LAST;
1472 			else
1473 				info.aggr = AGGR_BUF_MIDDLE;
1474 
1475 			info.ndelim = bf->bf_state.ndelim;
1476 			info.aggr_len = len;
1477 		}
1478 
1479 		if (bf == bf_first->bf_lastbf)
1480 			bf_first = NULL;
1481 
1482 		ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1483 		bf = bf->bf_next;
1484 	}
1485 }
1486 
1487 static void
1488 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1489 		  struct ath_atx_tid *tid, struct list_head *bf_q,
1490 		  struct ath_buf *bf_first)
1491 {
1492 	struct ath_buf *bf = bf_first, *bf_prev = NULL;
1493 	int nframes = 0;
1494 
1495 	do {
1496 		struct ieee80211_tx_info *tx_info;
1497 
1498 		nframes++;
1499 		list_add_tail(&bf->list, bf_q);
1500 		if (bf_prev)
1501 			bf_prev->bf_next = bf;
1502 		bf_prev = bf;
1503 
1504 		if (nframes >= 2)
1505 			break;
1506 
1507 		bf = ath_tx_get_tid_subframe(sc, txq, tid);
1508 		if (!bf)
1509 			break;
1510 
1511 		tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1512 		if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1513 			__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1514 			break;
1515 		}
1516 
1517 		ath_set_rates(tid->an->vif, tid->an->sta, bf);
1518 	} while (1);
1519 }
1520 
1521 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1522 			      struct ath_atx_tid *tid)
1523 {
1524 	struct ath_buf *bf;
1525 	struct ieee80211_tx_info *tx_info;
1526 	struct list_head bf_q;
1527 	int aggr_len = 0;
1528 	bool aggr;
1529 
1530 	if (!ath_tid_has_buffered(tid))
1531 		return false;
1532 
1533 	INIT_LIST_HEAD(&bf_q);
1534 
1535 	bf = ath_tx_get_tid_subframe(sc, txq, tid);
1536 	if (!bf)
1537 		return false;
1538 
1539 	tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1540 	aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1541 	if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1542 	    (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1543 		__skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1544 		return false;
1545 	}
1546 
1547 	ath_set_rates(tid->an->vif, tid->an->sta, bf);
1548 	if (aggr)
1549 		aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1550 	else
1551 		ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1552 
1553 	if (list_empty(&bf_q))
1554 		return false;
1555 
1556 	if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1557 		tid->clear_ps_filter = false;
1558 		tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1559 	}
1560 
1561 	ath_tx_fill_desc(sc, bf, txq, aggr_len);
1562 	ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1563 	return true;
1564 }
1565 
1566 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1567 		      u16 tid, u16 *ssn)
1568 {
1569 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1570 	struct ath_atx_tid *txtid;
1571 	struct ath_txq *txq;
1572 	struct ath_node *an;
1573 	u8 density;
1574 
1575 	ath_dbg(common, XMIT, "%s called\n", __func__);
1576 
1577 	an = (struct ath_node *)sta->drv_priv;
1578 	txtid = ATH_AN_2_TID(an, tid);
1579 	txq = txtid->txq;
1580 
1581 	ath_txq_lock(sc, txq);
1582 
1583 	/* update ampdu factor/density, they may have changed. This may happen
1584 	 * in HT IBSS when a beacon with HT-info is received after the station
1585 	 * has already been added.
1586 	 */
1587 	if (sta->ht_cap.ht_supported) {
1588 		an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1589 				      sta->ht_cap.ampdu_factor)) - 1;
1590 		density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1591 		an->mpdudensity = density;
1592 	}
1593 
1594 	txtid->active = true;
1595 	*ssn = txtid->seq_start = txtid->seq_next;
1596 	txtid->bar_index = -1;
1597 
1598 	memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1599 	txtid->baw_head = txtid->baw_tail = 0;
1600 
1601 	ath_txq_unlock_complete(sc, txq);
1602 
1603 	return 0;
1604 }
1605 
1606 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1607 {
1608 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1609 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1610 	struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1611 	struct ath_txq *txq = txtid->txq;
1612 
1613 	ath_dbg(common, XMIT, "%s called\n", __func__);
1614 
1615 	ath_txq_lock(sc, txq);
1616 	txtid->active = false;
1617 	ath_tx_flush_tid(sc, txtid);
1618 	ath_txq_unlock_complete(sc, txq);
1619 }
1620 
1621 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1622 		       struct ath_node *an)
1623 {
1624 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1625 	struct ath_atx_tid *tid;
1626 	struct ath_txq *txq;
1627 	int tidno;
1628 
1629 	ath_dbg(common, XMIT, "%s called\n", __func__);
1630 
1631 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1632 		tid = ath_node_to_tid(an, tidno);
1633 		txq = tid->txq;
1634 
1635 		ath_txq_lock(sc, txq);
1636 
1637 		if (list_empty(&tid->list)) {
1638 			ath_txq_unlock(sc, txq);
1639 			continue;
1640 		}
1641 
1642 		if (!skb_queue_empty(&tid->retry_q))
1643 			ieee80211_sta_set_buffered(sta, tid->tidno, true);
1644 
1645 		list_del_init(&tid->list);
1646 
1647 		ath_txq_unlock(sc, txq);
1648 	}
1649 }
1650 
1651 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1652 {
1653 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1654 	struct ath_atx_tid *tid;
1655 	struct ath_txq *txq;
1656 	int tidno;
1657 
1658 	ath_dbg(common, XMIT, "%s called\n", __func__);
1659 
1660 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1661 		tid = ath_node_to_tid(an, tidno);
1662 		txq = tid->txq;
1663 
1664 		ath_txq_lock(sc, txq);
1665 		tid->clear_ps_filter = true;
1666 		if (ath_tid_has_buffered(tid)) {
1667 			ath_tx_queue_tid(sc, tid);
1668 			ath_txq_schedule(sc, txq);
1669 		}
1670 		ath_txq_unlock_complete(sc, txq);
1671 	}
1672 }
1673 
1674 
1675 static void
1676 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val)
1677 {
1678 	struct ieee80211_hdr *hdr;
1679 	u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1680 	u16 mask_val = mask * val;
1681 
1682 	hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
1683 	if ((hdr->frame_control & mask) != mask_val) {
1684 		hdr->frame_control = (hdr->frame_control & ~mask) | mask_val;
1685 		dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
1686 			sizeof(*hdr), DMA_TO_DEVICE);
1687 	}
1688 }
1689 
1690 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1691 				   struct ieee80211_sta *sta,
1692 				   u16 tids, int nframes,
1693 				   enum ieee80211_frame_release_type reason,
1694 				   bool more_data)
1695 {
1696 	struct ath_softc *sc = hw->priv;
1697 	struct ath_node *an = (struct ath_node *)sta->drv_priv;
1698 	struct ath_txq *txq = sc->tx.uapsdq;
1699 	struct ieee80211_tx_info *info;
1700 	struct list_head bf_q;
1701 	struct ath_buf *bf_tail = NULL, *bf;
1702 	int sent = 0;
1703 	int i;
1704 
1705 	INIT_LIST_HEAD(&bf_q);
1706 	for (i = 0; tids && nframes; i++, tids >>= 1) {
1707 		struct ath_atx_tid *tid;
1708 
1709 		if (!(tids & 1))
1710 			continue;
1711 
1712 		tid = ATH_AN_2_TID(an, i);
1713 
1714 		ath_txq_lock(sc, tid->txq);
1715 		while (nframes > 0) {
1716 			bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid);
1717 			if (!bf)
1718 				break;
1719 
1720 			ath9k_set_moredata(sc, bf, true);
1721 			list_add_tail(&bf->list, &bf_q);
1722 			ath_set_rates(tid->an->vif, tid->an->sta, bf);
1723 			if (bf_isampdu(bf))
1724 				bf->bf_state.bf_type &= ~BUF_AGGR;
1725 			if (bf_tail)
1726 				bf_tail->bf_next = bf;
1727 
1728 			bf_tail = bf;
1729 			nframes--;
1730 			sent++;
1731 			TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw);
1732 
1733 			if (an->sta && skb_queue_empty(&tid->retry_q))
1734 				ieee80211_sta_set_buffered(an->sta, i, false);
1735 		}
1736 		ath_txq_unlock_complete(sc, tid->txq);
1737 	}
1738 
1739 	if (list_empty(&bf_q))
1740 		return;
1741 
1742 	if (!more_data)
1743 		ath9k_set_moredata(sc, bf_tail, false);
1744 
1745 	info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1746 	info->flags |= IEEE80211_TX_STATUS_EOSP;
1747 
1748 	bf = list_first_entry(&bf_q, struct ath_buf, list);
1749 	ath_txq_lock(sc, txq);
1750 	ath_tx_fill_desc(sc, bf, txq, 0);
1751 	ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1752 	ath_txq_unlock(sc, txq);
1753 }
1754 
1755 /********************/
1756 /* Queue Management */
1757 /********************/
1758 
1759 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1760 {
1761 	struct ath_hw *ah = sc->sc_ah;
1762 	struct ath9k_tx_queue_info qi;
1763 	static const int subtype_txq_to_hwq[] = {
1764 		[IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1765 		[IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1766 		[IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1767 		[IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1768 	};
1769 	int axq_qnum, i;
1770 
1771 	memset(&qi, 0, sizeof(qi));
1772 	qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1773 	qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1774 	qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1775 	qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1776 	qi.tqi_physCompBuf = 0;
1777 
1778 	/*
1779 	 * Enable interrupts only for EOL and DESC conditions.
1780 	 * We mark tx descriptors to receive a DESC interrupt
1781 	 * when a tx queue gets deep; otherwise waiting for the
1782 	 * EOL to reap descriptors.  Note that this is done to
1783 	 * reduce interrupt load and this only defers reaping
1784 	 * descriptors, never transmitting frames.  Aside from
1785 	 * reducing interrupts this also permits more concurrency.
1786 	 * The only potential downside is if the tx queue backs
1787 	 * up in which case the top half of the kernel may backup
1788 	 * due to a lack of tx descriptors.
1789 	 *
1790 	 * The UAPSD queue is an exception, since we take a desc-
1791 	 * based intr on the EOSP frames.
1792 	 */
1793 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1794 		qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1795 	} else {
1796 		if (qtype == ATH9K_TX_QUEUE_UAPSD)
1797 			qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1798 		else
1799 			qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1800 					TXQ_FLAG_TXDESCINT_ENABLE;
1801 	}
1802 	axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1803 	if (axq_qnum == -1) {
1804 		/*
1805 		 * NB: don't print a message, this happens
1806 		 * normally on parts with too few tx queues
1807 		 */
1808 		return NULL;
1809 	}
1810 	if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1811 		struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1812 
1813 		txq->axq_qnum = axq_qnum;
1814 		txq->mac80211_qnum = -1;
1815 		txq->axq_link = NULL;
1816 		__skb_queue_head_init(&txq->complete_q);
1817 		INIT_LIST_HEAD(&txq->axq_q);
1818 		spin_lock_init(&txq->axq_lock);
1819 		txq->axq_depth = 0;
1820 		txq->axq_ampdu_depth = 0;
1821 		txq->axq_tx_inprogress = false;
1822 		sc->tx.txqsetup |= 1<<axq_qnum;
1823 
1824 		txq->txq_headidx = txq->txq_tailidx = 0;
1825 		for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1826 			INIT_LIST_HEAD(&txq->txq_fifo[i]);
1827 	}
1828 	return &sc->tx.txq[axq_qnum];
1829 }
1830 
1831 int ath_txq_update(struct ath_softc *sc, int qnum,
1832 		   struct ath9k_tx_queue_info *qinfo)
1833 {
1834 	struct ath_hw *ah = sc->sc_ah;
1835 	int error = 0;
1836 	struct ath9k_tx_queue_info qi;
1837 
1838 	BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1839 
1840 	ath9k_hw_get_txq_props(ah, qnum, &qi);
1841 	qi.tqi_aifs = qinfo->tqi_aifs;
1842 	qi.tqi_cwmin = qinfo->tqi_cwmin;
1843 	qi.tqi_cwmax = qinfo->tqi_cwmax;
1844 	qi.tqi_burstTime = qinfo->tqi_burstTime;
1845 	qi.tqi_readyTime = qinfo->tqi_readyTime;
1846 
1847 	if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1848 		ath_err(ath9k_hw_common(sc->sc_ah),
1849 			"Unable to update hardware queue %u!\n", qnum);
1850 		error = -EIO;
1851 	} else {
1852 		ath9k_hw_resettxqueue(ah, qnum);
1853 	}
1854 
1855 	return error;
1856 }
1857 
1858 int ath_cabq_update(struct ath_softc *sc)
1859 {
1860 	struct ath9k_tx_queue_info qi;
1861 	struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1862 	int qnum = sc->beacon.cabq->axq_qnum;
1863 
1864 	ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1865 
1866 	qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1867 			    ATH_CABQ_READY_TIME) / 100;
1868 	ath_txq_update(sc, qnum, &qi);
1869 
1870 	return 0;
1871 }
1872 
1873 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1874 			       struct list_head *list)
1875 {
1876 	struct ath_buf *bf, *lastbf;
1877 	struct list_head bf_head;
1878 	struct ath_tx_status ts;
1879 
1880 	memset(&ts, 0, sizeof(ts));
1881 	ts.ts_status = ATH9K_TX_FLUSH;
1882 	INIT_LIST_HEAD(&bf_head);
1883 
1884 	while (!list_empty(list)) {
1885 		bf = list_first_entry(list, struct ath_buf, list);
1886 
1887 		if (bf->bf_state.stale) {
1888 			list_del(&bf->list);
1889 
1890 			ath_tx_return_buffer(sc, bf);
1891 			continue;
1892 		}
1893 
1894 		lastbf = bf->bf_lastbf;
1895 		list_cut_position(&bf_head, list, &lastbf->list);
1896 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1897 	}
1898 }
1899 
1900 /*
1901  * Drain a given TX queue (could be Beacon or Data)
1902  *
1903  * This assumes output has been stopped and
1904  * we do not need to block ath_tx_tasklet.
1905  */
1906 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1907 {
1908 	rcu_read_lock();
1909 	ath_txq_lock(sc, txq);
1910 
1911 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1912 		int idx = txq->txq_tailidx;
1913 
1914 		while (!list_empty(&txq->txq_fifo[idx])) {
1915 			ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1916 
1917 			INCR(idx, ATH_TXFIFO_DEPTH);
1918 		}
1919 		txq->txq_tailidx = idx;
1920 	}
1921 
1922 	txq->axq_link = NULL;
1923 	txq->axq_tx_inprogress = false;
1924 	ath_drain_txq_list(sc, txq, &txq->axq_q);
1925 
1926 	ath_txq_unlock_complete(sc, txq);
1927 	rcu_read_unlock();
1928 }
1929 
1930 bool ath_drain_all_txq(struct ath_softc *sc)
1931 {
1932 	struct ath_hw *ah = sc->sc_ah;
1933 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1934 	struct ath_txq *txq;
1935 	int i;
1936 	u32 npend = 0;
1937 
1938 	if (test_bit(ATH_OP_INVALID, &common->op_flags))
1939 		return true;
1940 
1941 	ath9k_hw_abort_tx_dma(ah);
1942 
1943 	/* Check if any queue remains active */
1944 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1945 		if (!ATH_TXQ_SETUP(sc, i))
1946 			continue;
1947 
1948 		if (!sc->tx.txq[i].axq_depth)
1949 			continue;
1950 
1951 		if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1952 			npend |= BIT(i);
1953 	}
1954 
1955 	if (npend) {
1956 		RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1957 		ath_dbg(common, RESET,
1958 			"Failed to stop TX DMA, queues=0x%03x!\n", npend);
1959 	}
1960 
1961 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1962 		if (!ATH_TXQ_SETUP(sc, i))
1963 			continue;
1964 
1965 		txq = &sc->tx.txq[i];
1966 		ath_draintxq(sc, txq);
1967 	}
1968 
1969 	return !npend;
1970 }
1971 
1972 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1973 {
1974 	ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1975 	sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1976 }
1977 
1978 /* For each acq entry, for each tid, try to schedule packets
1979  * for transmit until ampdu_depth has reached min Q depth.
1980  */
1981 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1982 {
1983 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1984 	struct ath_atx_tid *tid;
1985 	struct list_head *tid_list;
1986 	struct ath_acq *acq;
1987 	bool active = AIRTIME_ACTIVE(sc->airtime_flags);
1988 
1989 	if (txq->mac80211_qnum < 0)
1990 		return;
1991 
1992 	if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1993 		return;
1994 
1995 	spin_lock_bh(&sc->chan_lock);
1996 	rcu_read_lock();
1997 	acq = &sc->cur_chan->acq[txq->mac80211_qnum];
1998 
1999 	if (sc->cur_chan->stopped)
2000 		goto out;
2001 
2002 begin:
2003 	tid_list = &acq->acq_new;
2004 	if (list_empty(tid_list)) {
2005 		tid_list = &acq->acq_old;
2006 		if (list_empty(tid_list))
2007 			goto out;
2008 	}
2009 	tid = list_first_entry(tid_list, struct ath_atx_tid, list);
2010 
2011 	if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) {
2012 		spin_lock_bh(&acq->lock);
2013 		tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM;
2014 		list_move_tail(&tid->list, &acq->acq_old);
2015 		spin_unlock_bh(&acq->lock);
2016 		goto begin;
2017 	}
2018 
2019 	if (!ath_tid_has_buffered(tid)) {
2020 		spin_lock_bh(&acq->lock);
2021 		if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old))
2022 			list_move_tail(&tid->list, &acq->acq_old);
2023 		else {
2024 			list_del_init(&tid->list);
2025 		}
2026 		spin_unlock_bh(&acq->lock);
2027 		goto begin;
2028 	}
2029 
2030 
2031 	/*
2032 	 * If we succeed in scheduling something, immediately restart to make
2033 	 * sure we keep the HW busy.
2034 	 */
2035 	if(ath_tx_sched_aggr(sc, txq, tid)) {
2036 		if (!active) {
2037 			spin_lock_bh(&acq->lock);
2038 			list_move_tail(&tid->list, &acq->acq_old);
2039 			spin_unlock_bh(&acq->lock);
2040 		}
2041 		goto begin;
2042 	}
2043 
2044 out:
2045 	rcu_read_unlock();
2046 	spin_unlock_bh(&sc->chan_lock);
2047 }
2048 
2049 void ath_txq_schedule_all(struct ath_softc *sc)
2050 {
2051 	struct ath_txq *txq;
2052 	int i;
2053 
2054 	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2055 		txq = sc->tx.txq_map[i];
2056 
2057 		spin_lock_bh(&txq->axq_lock);
2058 		ath_txq_schedule(sc, txq);
2059 		spin_unlock_bh(&txq->axq_lock);
2060 	}
2061 }
2062 
2063 /***********/
2064 /* TX, DMA */
2065 /***********/
2066 
2067 /*
2068  * Insert a chain of ath_buf (descriptors) on a txq and
2069  * assume the descriptors are already chained together by caller.
2070  */
2071 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2072 			     struct list_head *head, bool internal)
2073 {
2074 	struct ath_hw *ah = sc->sc_ah;
2075 	struct ath_common *common = ath9k_hw_common(ah);
2076 	struct ath_buf *bf, *bf_last;
2077 	bool puttxbuf = false;
2078 	bool edma;
2079 
2080 	/*
2081 	 * Insert the frame on the outbound list and
2082 	 * pass it on to the hardware.
2083 	 */
2084 
2085 	if (list_empty(head))
2086 		return;
2087 
2088 	edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2089 	bf = list_first_entry(head, struct ath_buf, list);
2090 	bf_last = list_entry(head->prev, struct ath_buf, list);
2091 
2092 	ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2093 		txq->axq_qnum, txq->axq_depth);
2094 
2095 	if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2096 		list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2097 		INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2098 		puttxbuf = true;
2099 	} else {
2100 		list_splice_tail_init(head, &txq->axq_q);
2101 
2102 		if (txq->axq_link) {
2103 			ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2104 			ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2105 				txq->axq_qnum, txq->axq_link,
2106 				ito64(bf->bf_daddr), bf->bf_desc);
2107 		} else if (!edma)
2108 			puttxbuf = true;
2109 
2110 		txq->axq_link = bf_last->bf_desc;
2111 	}
2112 
2113 	if (puttxbuf) {
2114 		TX_STAT_INC(sc, txq->axq_qnum, puttxbuf);
2115 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2116 		ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2117 			txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2118 	}
2119 
2120 	if (!edma || sc->tx99_state) {
2121 		TX_STAT_INC(sc, txq->axq_qnum, txstart);
2122 		ath9k_hw_txstart(ah, txq->axq_qnum);
2123 	}
2124 
2125 	if (!internal) {
2126 		while (bf) {
2127 			txq->axq_depth++;
2128 			if (bf_is_ampdu_not_probing(bf))
2129 				txq->axq_ampdu_depth++;
2130 
2131 			bf_last = bf->bf_lastbf;
2132 			bf = bf_last->bf_next;
2133 			bf_last->bf_next = NULL;
2134 		}
2135 	}
2136 }
2137 
2138 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2139 			       struct ath_atx_tid *tid, struct sk_buff *skb)
2140 {
2141 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2142 	struct ath_frame_info *fi = get_frame_info(skb);
2143 	struct list_head bf_head;
2144 	struct ath_buf *bf = fi->bf;
2145 
2146 	INIT_LIST_HEAD(&bf_head);
2147 	list_add_tail(&bf->list, &bf_head);
2148 	bf->bf_state.bf_type = 0;
2149 	if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2150 		bf->bf_state.bf_type = BUF_AMPDU;
2151 		ath_tx_addto_baw(sc, tid, bf);
2152 	}
2153 
2154 	bf->bf_next = NULL;
2155 	bf->bf_lastbf = bf;
2156 	ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2157 	ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2158 	TX_STAT_INC(sc, txq->axq_qnum, queued);
2159 }
2160 
2161 static void setup_frame_info(struct ieee80211_hw *hw,
2162 			     struct ieee80211_sta *sta,
2163 			     struct sk_buff *skb,
2164 			     int framelen)
2165 {
2166 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2167 	struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2168 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2169 	const struct ieee80211_rate *rate;
2170 	struct ath_frame_info *fi = get_frame_info(skb);
2171 	struct ath_node *an = NULL;
2172 	enum ath9k_key_type keytype;
2173 	bool short_preamble = false;
2174 	u8 txpower;
2175 
2176 	/*
2177 	 * We check if Short Preamble is needed for the CTS rate by
2178 	 * checking the BSS's global flag.
2179 	 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2180 	 */
2181 	if (tx_info->control.vif &&
2182 	    tx_info->control.vif->bss_conf.use_short_preamble)
2183 		short_preamble = true;
2184 
2185 	rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2186 	keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2187 
2188 	if (sta)
2189 		an = (struct ath_node *) sta->drv_priv;
2190 
2191 	if (tx_info->control.vif) {
2192 		struct ieee80211_vif *vif = tx_info->control.vif;
2193 
2194 		txpower = 2 * vif->bss_conf.txpower;
2195 	} else {
2196 		struct ath_softc *sc = hw->priv;
2197 
2198 		txpower = sc->cur_chan->cur_txpower;
2199 	}
2200 
2201 	memset(fi, 0, sizeof(*fi));
2202 	fi->txq = -1;
2203 	if (hw_key)
2204 		fi->keyix = hw_key->hw_key_idx;
2205 	else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2206 		fi->keyix = an->ps_key;
2207 	else
2208 		fi->keyix = ATH9K_TXKEYIX_INVALID;
2209 	fi->keytype = keytype;
2210 	fi->framelen = framelen;
2211 	fi->tx_power = txpower;
2212 
2213 	if (!rate)
2214 		return;
2215 	fi->rtscts_rate = rate->hw_value;
2216 	if (short_preamble)
2217 		fi->rtscts_rate |= rate->hw_value_short;
2218 }
2219 
2220 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2221 {
2222 	struct ath_hw *ah = sc->sc_ah;
2223 	struct ath9k_channel *curchan = ah->curchan;
2224 
2225 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2226 	    (chainmask == 0x7) && (rate < 0x90))
2227 		return 0x3;
2228 	else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2229 		 IS_CCK_RATE(rate))
2230 		return 0x2;
2231 	else
2232 		return chainmask;
2233 }
2234 
2235 /*
2236  * Assign a descriptor (and sequence number if necessary,
2237  * and map buffer for DMA. Frees skb on error
2238  */
2239 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2240 					   struct ath_txq *txq,
2241 					   struct ath_atx_tid *tid,
2242 					   struct sk_buff *skb)
2243 {
2244 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2245 	struct ath_frame_info *fi = get_frame_info(skb);
2246 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2247 	struct ath_buf *bf;
2248 	int fragno;
2249 	u16 seqno;
2250 
2251 	bf = ath_tx_get_buffer(sc);
2252 	if (!bf) {
2253 		ath_dbg(common, XMIT, "TX buffers are full\n");
2254 		return NULL;
2255 	}
2256 
2257 	ATH_TXBUF_RESET(bf);
2258 
2259 	if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2260 		fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2261 		seqno = tid->seq_next;
2262 		hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2263 
2264 		if (fragno)
2265 			hdr->seq_ctrl |= cpu_to_le16(fragno);
2266 
2267 		if (!ieee80211_has_morefrags(hdr->frame_control))
2268 			INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2269 
2270 		bf->bf_state.seqno = seqno;
2271 	}
2272 
2273 	bf->bf_mpdu = skb;
2274 
2275 	bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2276 					 skb->len, DMA_TO_DEVICE);
2277 	if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2278 		bf->bf_mpdu = NULL;
2279 		bf->bf_buf_addr = 0;
2280 		ath_err(ath9k_hw_common(sc->sc_ah),
2281 			"dma_mapping_error() on TX\n");
2282 		ath_tx_return_buffer(sc, bf);
2283 		return NULL;
2284 	}
2285 
2286 	fi->bf = bf;
2287 
2288 	return bf;
2289 }
2290 
2291 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2292 {
2293 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2294 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2295 	struct ieee80211_vif *vif = info->control.vif;
2296 	struct ath_vif *avp;
2297 
2298 	if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2299 		return;
2300 
2301 	if (!vif)
2302 		return;
2303 
2304 	avp = (struct ath_vif *)vif->drv_priv;
2305 
2306 	if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2307 		avp->seq_no += 0x10;
2308 
2309 	hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2310 	hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2311 }
2312 
2313 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2314 			  struct ath_tx_control *txctl)
2315 {
2316 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2317 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2318 	struct ieee80211_sta *sta = txctl->sta;
2319 	struct ieee80211_vif *vif = info->control.vif;
2320 	struct ath_vif *avp;
2321 	struct ath_softc *sc = hw->priv;
2322 	int frmlen = skb->len + FCS_LEN;
2323 	int padpos, padsize;
2324 
2325 	/* NOTE:  sta can be NULL according to net/mac80211.h */
2326 	if (sta)
2327 		txctl->an = (struct ath_node *)sta->drv_priv;
2328 	else if (vif && ieee80211_is_data(hdr->frame_control)) {
2329 		avp = (void *)vif->drv_priv;
2330 		txctl->an = &avp->mcast_node;
2331 	}
2332 
2333 	if (info->control.hw_key)
2334 		frmlen += info->control.hw_key->icv_len;
2335 
2336 	ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2337 
2338 	if ((vif && vif->type != NL80211_IFTYPE_AP &&
2339 	            vif->type != NL80211_IFTYPE_AP_VLAN) ||
2340 	    !ieee80211_is_data(hdr->frame_control))
2341 		info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2342 
2343 	/* Add the padding after the header if this is not already done */
2344 	padpos = ieee80211_hdrlen(hdr->frame_control);
2345 	padsize = padpos & 3;
2346 	if (padsize && skb->len > padpos) {
2347 		if (skb_headroom(skb) < padsize)
2348 			return -ENOMEM;
2349 
2350 		skb_push(skb, padsize);
2351 		memmove(skb->data, skb->data + padsize, padpos);
2352 	}
2353 
2354 	setup_frame_info(hw, sta, skb, frmlen);
2355 	return 0;
2356 }
2357 
2358 
2359 /* Upon failure caller should free skb */
2360 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2361 		 struct ath_tx_control *txctl)
2362 {
2363 	struct ieee80211_hdr *hdr;
2364 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2365 	struct ieee80211_sta *sta = txctl->sta;
2366 	struct ieee80211_vif *vif = info->control.vif;
2367 	struct ath_frame_info *fi = get_frame_info(skb);
2368 	struct ath_vif *avp = NULL;
2369 	struct ath_softc *sc = hw->priv;
2370 	struct ath_txq *txq = txctl->txq;
2371 	struct ath_atx_tid *tid = NULL;
2372 	struct ath_node *an = NULL;
2373 	struct ath_buf *bf;
2374 	bool ps_resp;
2375 	int q, ret;
2376 
2377 	if (vif)
2378 		avp = (void *)vif->drv_priv;
2379 
2380 	ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2381 
2382 	ret = ath_tx_prepare(hw, skb, txctl);
2383 	if (ret)
2384 	    return ret;
2385 
2386 	hdr = (struct ieee80211_hdr *) skb->data;
2387 	/*
2388 	 * At this point, the vif, hw_key and sta pointers in the tx control
2389 	 * info are no longer valid (overwritten by the ath_frame_info data.
2390 	 */
2391 
2392 	q = skb_get_queue_mapping(skb);
2393 
2394 	if (ps_resp)
2395 		txq = sc->tx.uapsdq;
2396 
2397 	if (txctl->sta) {
2398 		an = (struct ath_node *) sta->drv_priv;
2399 		tid = ath_get_skb_tid(sc, an, skb);
2400 	}
2401 
2402 	ath_txq_lock(sc, txq);
2403 	if (txq == sc->tx.txq_map[q]) {
2404 		fi->txq = q;
2405 		++txq->pending_frames;
2406 	}
2407 
2408 	bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2409 	if (!bf) {
2410 		ath_txq_skb_done(sc, txq, skb);
2411 		if (txctl->paprd)
2412 			dev_kfree_skb_any(skb);
2413 		else
2414 			ieee80211_free_txskb(sc->hw, skb);
2415 		goto out;
2416 	}
2417 
2418 	bf->bf_state.bfs_paprd = txctl->paprd;
2419 
2420 	if (txctl->paprd)
2421 		bf->bf_state.bfs_paprd_timestamp = jiffies;
2422 
2423 	ath_set_rates(vif, sta, bf);
2424 	ath_tx_send_normal(sc, txq, tid, skb);
2425 
2426 out:
2427 	ath_txq_unlock(sc, txq);
2428 
2429 	return 0;
2430 }
2431 
2432 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2433 		 struct sk_buff *skb)
2434 {
2435 	struct ath_softc *sc = hw->priv;
2436 	struct ath_tx_control txctl = {
2437 		.txq = sc->beacon.cabq
2438 	};
2439 	struct ath_tx_info info = {};
2440 	struct ath_buf *bf_tail = NULL;
2441 	struct ath_buf *bf;
2442 	LIST_HEAD(bf_q);
2443 	int duration = 0;
2444 	int max_duration;
2445 
2446 	max_duration =
2447 		sc->cur_chan->beacon.beacon_interval * 1000 *
2448 		sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2449 
2450 	do {
2451 		struct ath_frame_info *fi = get_frame_info(skb);
2452 
2453 		if (ath_tx_prepare(hw, skb, &txctl))
2454 			break;
2455 
2456 		bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2457 		if (!bf)
2458 			break;
2459 
2460 		bf->bf_lastbf = bf;
2461 		ath_set_rates(vif, NULL, bf);
2462 		ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2463 		duration += info.rates[0].PktDuration;
2464 		if (bf_tail)
2465 			bf_tail->bf_next = bf;
2466 
2467 		list_add_tail(&bf->list, &bf_q);
2468 		bf_tail = bf;
2469 		skb = NULL;
2470 
2471 		if (duration > max_duration)
2472 			break;
2473 
2474 		skb = ieee80211_get_buffered_bc(hw, vif);
2475 	} while(skb);
2476 
2477 	if (skb)
2478 		ieee80211_free_txskb(hw, skb);
2479 
2480 	if (list_empty(&bf_q))
2481 		return;
2482 
2483 	bf = list_last_entry(&bf_q, struct ath_buf, list);
2484 	ath9k_set_moredata(sc, bf, false);
2485 
2486 	bf = list_first_entry(&bf_q, struct ath_buf, list);
2487 	ath_txq_lock(sc, txctl.txq);
2488 	ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2489 	ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2490 	TX_STAT_INC(sc, txctl.txq->axq_qnum, queued);
2491 	ath_txq_unlock(sc, txctl.txq);
2492 }
2493 
2494 /*****************/
2495 /* TX Completion */
2496 /*****************/
2497 
2498 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2499 			    int tx_flags, struct ath_txq *txq,
2500 			    struct ieee80211_sta *sta)
2501 {
2502 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2503 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2504 	struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2505 	int padpos, padsize;
2506 	unsigned long flags;
2507 
2508 	ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2509 
2510 	if (sc->sc_ah->caldata)
2511 		set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2512 
2513 	if (!(tx_flags & ATH_TX_ERROR)) {
2514 		if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2515 			tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2516 		else
2517 			tx_info->flags |= IEEE80211_TX_STAT_ACK;
2518 	}
2519 
2520 	if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2521 		padpos = ieee80211_hdrlen(hdr->frame_control);
2522 		padsize = padpos & 3;
2523 		if (padsize && skb->len>padpos+padsize) {
2524 			/*
2525 			 * Remove MAC header padding before giving the frame back to
2526 			 * mac80211.
2527 			 */
2528 			memmove(skb->data + padsize, skb->data, padpos);
2529 			skb_pull(skb, padsize);
2530 		}
2531 	}
2532 
2533 	spin_lock_irqsave(&sc->sc_pm_lock, flags);
2534 	if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2535 		sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2536 		ath_dbg(common, PS,
2537 			"Going back to sleep after having received TX status (0x%lx)\n",
2538 			sc->ps_flags & (PS_WAIT_FOR_BEACON |
2539 					PS_WAIT_FOR_CAB |
2540 					PS_WAIT_FOR_PSPOLL_DATA |
2541 					PS_WAIT_FOR_TX_ACK));
2542 	}
2543 	spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2544 
2545 	ath_txq_skb_done(sc, txq, skb);
2546 	tx_info->status.status_driver_data[0] = sta;
2547 	__skb_queue_tail(&txq->complete_q, skb);
2548 }
2549 
2550 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2551 				struct ath_txq *txq, struct list_head *bf_q,
2552 				struct ieee80211_sta *sta,
2553 				struct ath_tx_status *ts, int txok)
2554 {
2555 	struct sk_buff *skb = bf->bf_mpdu;
2556 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2557 	unsigned long flags;
2558 	int tx_flags = 0;
2559 
2560 	if (!txok)
2561 		tx_flags |= ATH_TX_ERROR;
2562 
2563 	if (ts->ts_status & ATH9K_TXERR_FILT)
2564 		tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2565 
2566 	dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2567 	bf->bf_buf_addr = 0;
2568 	if (sc->tx99_state)
2569 		goto skip_tx_complete;
2570 
2571 	if (bf->bf_state.bfs_paprd) {
2572 		if (time_after(jiffies,
2573 				bf->bf_state.bfs_paprd_timestamp +
2574 				msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2575 			dev_kfree_skb_any(skb);
2576 		else
2577 			complete(&sc->paprd_complete);
2578 	} else {
2579 		ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2580 		ath_tx_complete(sc, skb, tx_flags, txq, sta);
2581 	}
2582 skip_tx_complete:
2583 	/* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2584 	 * accidentally reference it later.
2585 	 */
2586 	bf->bf_mpdu = NULL;
2587 
2588 	/*
2589 	 * Return the list of ath_buf of this mpdu to free queue
2590 	 */
2591 	spin_lock_irqsave(&sc->tx.txbuflock, flags);
2592 	list_splice_tail_init(bf_q, &sc->tx.txbuf);
2593 	spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2594 }
2595 
2596 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2597 			     struct ath_tx_status *ts, int nframes, int nbad,
2598 			     int txok)
2599 {
2600 	struct sk_buff *skb = bf->bf_mpdu;
2601 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2602 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2603 	struct ieee80211_hw *hw = sc->hw;
2604 	struct ath_hw *ah = sc->sc_ah;
2605 	u8 i, tx_rateindex;
2606 
2607 	if (txok)
2608 		tx_info->status.ack_signal = ts->ts_rssi;
2609 
2610 	tx_rateindex = ts->ts_rateindex;
2611 	WARN_ON(tx_rateindex >= hw->max_rates);
2612 
2613 	if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2614 		tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2615 
2616 		BUG_ON(nbad > nframes);
2617 	}
2618 	tx_info->status.ampdu_len = nframes;
2619 	tx_info->status.ampdu_ack_len = nframes - nbad;
2620 
2621 	if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2622 	    (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2623 		/*
2624 		 * If an underrun error is seen assume it as an excessive
2625 		 * retry only if max frame trigger level has been reached
2626 		 * (2 KB for single stream, and 4 KB for dual stream).
2627 		 * Adjust the long retry as if the frame was tried
2628 		 * hw->max_rate_tries times to affect how rate control updates
2629 		 * PER for the failed rate.
2630 		 * In case of congestion on the bus penalizing this type of
2631 		 * underruns should help hardware actually transmit new frames
2632 		 * successfully by eventually preferring slower rates.
2633 		 * This itself should also alleviate congestion on the bus.
2634 		 */
2635 		if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2636 		                             ATH9K_TX_DELIM_UNDERRUN)) &&
2637 		    ieee80211_is_data(hdr->frame_control) &&
2638 		    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2639 			tx_info->status.rates[tx_rateindex].count =
2640 				hw->max_rate_tries;
2641 	}
2642 
2643 	for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2644 		tx_info->status.rates[i].count = 0;
2645 		tx_info->status.rates[i].idx = -1;
2646 	}
2647 
2648 	tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2649 }
2650 
2651 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2652 {
2653 	struct ath_hw *ah = sc->sc_ah;
2654 	struct ath_common *common = ath9k_hw_common(ah);
2655 	struct ath_buf *bf, *lastbf, *bf_held = NULL;
2656 	struct list_head bf_head;
2657 	struct ath_desc *ds;
2658 	struct ath_tx_status ts;
2659 	int status;
2660 
2661 	ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2662 		txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2663 		txq->axq_link);
2664 
2665 	ath_txq_lock(sc, txq);
2666 	for (;;) {
2667 		if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2668 			break;
2669 
2670 		if (list_empty(&txq->axq_q)) {
2671 			txq->axq_link = NULL;
2672 			ath_txq_schedule(sc, txq);
2673 			break;
2674 		}
2675 		bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2676 
2677 		/*
2678 		 * There is a race condition that a BH gets scheduled
2679 		 * after sw writes TxE and before hw re-load the last
2680 		 * descriptor to get the newly chained one.
2681 		 * Software must keep the last DONE descriptor as a
2682 		 * holding descriptor - software does so by marking
2683 		 * it with the STALE flag.
2684 		 */
2685 		bf_held = NULL;
2686 		if (bf->bf_state.stale) {
2687 			bf_held = bf;
2688 			if (list_is_last(&bf_held->list, &txq->axq_q))
2689 				break;
2690 
2691 			bf = list_entry(bf_held->list.next, struct ath_buf,
2692 					list);
2693 		}
2694 
2695 		lastbf = bf->bf_lastbf;
2696 		ds = lastbf->bf_desc;
2697 
2698 		memset(&ts, 0, sizeof(ts));
2699 		status = ath9k_hw_txprocdesc(ah, ds, &ts);
2700 		if (status == -EINPROGRESS)
2701 			break;
2702 
2703 		TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2704 
2705 		/*
2706 		 * Remove ath_buf's of the same transmit unit from txq,
2707 		 * however leave the last descriptor back as the holding
2708 		 * descriptor for hw.
2709 		 */
2710 		lastbf->bf_state.stale = true;
2711 		INIT_LIST_HEAD(&bf_head);
2712 		if (!list_is_singular(&lastbf->list))
2713 			list_cut_position(&bf_head,
2714 				&txq->axq_q, lastbf->list.prev);
2715 
2716 		if (bf_held) {
2717 			list_del(&bf_held->list);
2718 			ath_tx_return_buffer(sc, bf_held);
2719 		}
2720 
2721 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2722 	}
2723 	ath_txq_unlock_complete(sc, txq);
2724 }
2725 
2726 void ath_tx_tasklet(struct ath_softc *sc)
2727 {
2728 	struct ath_hw *ah = sc->sc_ah;
2729 	u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2730 	int i;
2731 
2732 	rcu_read_lock();
2733 	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2734 		if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2735 			ath_tx_processq(sc, &sc->tx.txq[i]);
2736 	}
2737 	rcu_read_unlock();
2738 }
2739 
2740 void ath_tx_edma_tasklet(struct ath_softc *sc)
2741 {
2742 	struct ath_tx_status ts;
2743 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2744 	struct ath_hw *ah = sc->sc_ah;
2745 	struct ath_txq *txq;
2746 	struct ath_buf *bf, *lastbf;
2747 	struct list_head bf_head;
2748 	struct list_head *fifo_list;
2749 	int status;
2750 
2751 	rcu_read_lock();
2752 	for (;;) {
2753 		if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2754 			break;
2755 
2756 		status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2757 		if (status == -EINPROGRESS)
2758 			break;
2759 		if (status == -EIO) {
2760 			ath_dbg(common, XMIT, "Error processing tx status\n");
2761 			break;
2762 		}
2763 
2764 		/* Process beacon completions separately */
2765 		if (ts.qid == sc->beacon.beaconq) {
2766 			sc->beacon.tx_processed = true;
2767 			sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2768 
2769 			if (ath9k_is_chanctx_enabled()) {
2770 				ath_chanctx_event(sc, NULL,
2771 						  ATH_CHANCTX_EVENT_BEACON_SENT);
2772 			}
2773 
2774 			ath9k_csa_update(sc);
2775 			continue;
2776 		}
2777 
2778 		txq = &sc->tx.txq[ts.qid];
2779 
2780 		ath_txq_lock(sc, txq);
2781 
2782 		TX_STAT_INC(sc, txq->axq_qnum, txprocdesc);
2783 
2784 		fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2785 		if (list_empty(fifo_list)) {
2786 			ath_txq_unlock(sc, txq);
2787 			break;
2788 		}
2789 
2790 		bf = list_first_entry(fifo_list, struct ath_buf, list);
2791 		if (bf->bf_state.stale) {
2792 			list_del(&bf->list);
2793 			ath_tx_return_buffer(sc, bf);
2794 			bf = list_first_entry(fifo_list, struct ath_buf, list);
2795 		}
2796 
2797 		lastbf = bf->bf_lastbf;
2798 
2799 		INIT_LIST_HEAD(&bf_head);
2800 		if (list_is_last(&lastbf->list, fifo_list)) {
2801 			list_splice_tail_init(fifo_list, &bf_head);
2802 			INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2803 
2804 			if (!list_empty(&txq->axq_q)) {
2805 				struct list_head bf_q;
2806 
2807 				INIT_LIST_HEAD(&bf_q);
2808 				txq->axq_link = NULL;
2809 				list_splice_tail_init(&txq->axq_q, &bf_q);
2810 				ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2811 			}
2812 		} else {
2813 			lastbf->bf_state.stale = true;
2814 			if (bf != lastbf)
2815 				list_cut_position(&bf_head, fifo_list,
2816 						  lastbf->list.prev);
2817 		}
2818 
2819 		ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2820 		ath_txq_unlock_complete(sc, txq);
2821 	}
2822 	rcu_read_unlock();
2823 }
2824 
2825 /*****************/
2826 /* Init, Cleanup */
2827 /*****************/
2828 
2829 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2830 {
2831 	struct ath_descdma *dd = &sc->txsdma;
2832 	u8 txs_len = sc->sc_ah->caps.txs_len;
2833 
2834 	dd->dd_desc_len = size * txs_len;
2835 	dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2836 					  &dd->dd_desc_paddr, GFP_KERNEL);
2837 	if (!dd->dd_desc)
2838 		return -ENOMEM;
2839 
2840 	return 0;
2841 }
2842 
2843 static int ath_tx_edma_init(struct ath_softc *sc)
2844 {
2845 	int err;
2846 
2847 	err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2848 	if (!err)
2849 		ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2850 					  sc->txsdma.dd_desc_paddr,
2851 					  ATH_TXSTATUS_RING_SIZE);
2852 
2853 	return err;
2854 }
2855 
2856 int ath_tx_init(struct ath_softc *sc, int nbufs)
2857 {
2858 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2859 	int error = 0;
2860 
2861 	spin_lock_init(&sc->tx.txbuflock);
2862 
2863 	error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2864 				  "tx", nbufs, 1, 1);
2865 	if (error != 0) {
2866 		ath_err(common,
2867 			"Failed to allocate tx descriptors: %d\n", error);
2868 		return error;
2869 	}
2870 
2871 	error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2872 				  "beacon", ATH_BCBUF, 1, 1);
2873 	if (error != 0) {
2874 		ath_err(common,
2875 			"Failed to allocate beacon descriptors: %d\n", error);
2876 		return error;
2877 	}
2878 
2879 	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2880 		error = ath_tx_edma_init(sc);
2881 
2882 	return error;
2883 }
2884 
2885 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2886 {
2887 	struct ath_atx_tid *tid;
2888 	int tidno, acno;
2889 
2890 	for (acno = 0; acno < IEEE80211_NUM_ACS; acno++)
2891 		an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM;
2892 
2893 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2894 		tid = ath_node_to_tid(an, tidno);
2895 		tid->an        = an;
2896 		tid->tidno     = tidno;
2897 		tid->seq_start = tid->seq_next = 0;
2898 		tid->baw_size  = WME_MAX_BA;
2899 		tid->baw_head  = tid->baw_tail = 0;
2900 		tid->active	   = false;
2901 		tid->clear_ps_filter = true;
2902 		tid->has_queued  = false;
2903 		__skb_queue_head_init(&tid->retry_q);
2904 		INIT_LIST_HEAD(&tid->list);
2905 		acno = TID_TO_WME_AC(tidno);
2906 		tid->txq = sc->tx.txq_map[acno];
2907 
2908 		if (!an->sta)
2909 			break; /* just one multicast ath_atx_tid */
2910 	}
2911 }
2912 
2913 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2914 {
2915 	struct ath_atx_tid *tid;
2916 	struct ath_txq *txq;
2917 	int tidno;
2918 
2919 	rcu_read_lock();
2920 
2921 	for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2922 		tid = ath_node_to_tid(an, tidno);
2923 		txq = tid->txq;
2924 
2925 		ath_txq_lock(sc, txq);
2926 
2927 		if (!list_empty(&tid->list))
2928 			list_del_init(&tid->list);
2929 
2930 		ath_tid_drain(sc, txq, tid);
2931 		tid->active = false;
2932 
2933 		ath_txq_unlock(sc, txq);
2934 
2935 		if (!an->sta)
2936 			break; /* just one multicast ath_atx_tid */
2937 	}
2938 
2939 	rcu_read_unlock();
2940 }
2941 
2942 #ifdef CONFIG_ATH9K_TX99
2943 
2944 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2945 		    struct ath_tx_control *txctl)
2946 {
2947 	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2948 	struct ath_frame_info *fi = get_frame_info(skb);
2949 	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2950 	struct ath_buf *bf;
2951 	int padpos, padsize;
2952 
2953 	padpos = ieee80211_hdrlen(hdr->frame_control);
2954 	padsize = padpos & 3;
2955 
2956 	if (padsize && skb->len > padpos) {
2957 		if (skb_headroom(skb) < padsize) {
2958 			ath_dbg(common, XMIT,
2959 				"tx99 padding failed\n");
2960 			return -EINVAL;
2961 		}
2962 
2963 		skb_push(skb, padsize);
2964 		memmove(skb->data, skb->data + padsize, padpos);
2965 	}
2966 
2967 	fi->keyix = ATH9K_TXKEYIX_INVALID;
2968 	fi->framelen = skb->len + FCS_LEN;
2969 	fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2970 
2971 	bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2972 	if (!bf) {
2973 		ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2974 		return -EINVAL;
2975 	}
2976 
2977 	ath_set_rates(sc->tx99_vif, NULL, bf);
2978 
2979 	ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2980 	ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2981 
2982 	ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2983 
2984 	return 0;
2985 }
2986 
2987 #endif /* CONFIG_ATH9K_TX99 */
2988