1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38 static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48 }; 49 50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq); 54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 55 struct ath_txq *txq, struct list_head *bf_q, 56 struct ath_tx_status *ts, int txok); 57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 58 struct list_head *head, bool internal); 59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 60 struct ath_tx_status *ts, int nframes, int nbad, 61 int txok); 62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 63 int seqno); 64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 65 struct ath_txq *txq, 66 struct ath_atx_tid *tid, 67 struct sk_buff *skb); 68 69 enum { 70 MCS_HT20, 71 MCS_HT20_SGI, 72 MCS_HT40, 73 MCS_HT40_SGI, 74 }; 75 76 /*********************/ 77 /* Aggregation logic */ 78 /*********************/ 79 80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 81 __acquires(&txq->axq_lock) 82 { 83 spin_lock_bh(&txq->axq_lock); 84 } 85 86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 87 __releases(&txq->axq_lock) 88 { 89 spin_unlock_bh(&txq->axq_lock); 90 } 91 92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 93 __releases(&txq->axq_lock) 94 { 95 struct sk_buff_head q; 96 struct sk_buff *skb; 97 98 __skb_queue_head_init(&q); 99 skb_queue_splice_init(&txq->complete_q, &q); 100 spin_unlock_bh(&txq->axq_lock); 101 102 while ((skb = __skb_dequeue(&q))) 103 ieee80211_tx_status(sc->hw, skb); 104 } 105 106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq, 107 struct ath_atx_tid *tid) 108 { 109 struct ath_atx_ac *ac = tid->ac; 110 struct list_head *list; 111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv; 112 struct ath_chanctx *ctx = avp->chanctx; 113 114 if (!ctx) 115 return; 116 117 if (tid->sched) 118 return; 119 120 tid->sched = true; 121 list_add_tail(&tid->list, &ac->tid_q); 122 123 if (ac->sched) 124 return; 125 126 ac->sched = true; 127 128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)]; 129 list_add_tail(&ac->list, list); 130 } 131 132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 133 { 134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 135 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 136 sizeof(tx_info->rate_driver_data)); 137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 138 } 139 140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 141 { 142 if (!tid->an->sta) 143 return; 144 145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 146 seqno << IEEE80211_SEQ_SEQ_SHIFT); 147 } 148 149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 150 struct ath_buf *bf) 151 { 152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 153 ARRAY_SIZE(bf->rates)); 154 } 155 156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 157 struct sk_buff *skb) 158 { 159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 160 struct ath_frame_info *fi = get_frame_info(skb); 161 int q = fi->txq; 162 163 if (q < 0) 164 return; 165 166 txq = sc->tx.txq_map[q]; 167 if (WARN_ON(--txq->pending_frames < 0)) 168 txq->pending_frames = 0; 169 170 if (txq->stopped && 171 txq->pending_frames < sc->tx.txq_max_pending[q]) { 172 if (ath9k_is_chanctx_enabled()) 173 ieee80211_wake_queue(sc->hw, info->hw_queue); 174 else 175 ieee80211_wake_queue(sc->hw, q); 176 txq->stopped = false; 177 } 178 } 179 180 static struct ath_atx_tid * 181 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 182 { 183 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 184 return ATH_AN_2_TID(an, tidno); 185 } 186 187 static bool ath_tid_has_buffered(struct ath_atx_tid *tid) 188 { 189 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q); 190 } 191 192 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid) 193 { 194 struct sk_buff *skb; 195 196 skb = __skb_dequeue(&tid->retry_q); 197 if (!skb) 198 skb = __skb_dequeue(&tid->buf_q); 199 200 return skb; 201 } 202 203 /* 204 * ath_tx_tid_change_state: 205 * - clears a-mpdu flag of previous session 206 * - force sequence number allocation to fix next BlockAck Window 207 */ 208 static void 209 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid) 210 { 211 struct ath_txq *txq = tid->ac->txq; 212 struct ieee80211_tx_info *tx_info; 213 struct sk_buff *skb, *tskb; 214 struct ath_buf *bf; 215 struct ath_frame_info *fi; 216 217 skb_queue_walk_safe(&tid->buf_q, skb, tskb) { 218 fi = get_frame_info(skb); 219 bf = fi->bf; 220 221 tx_info = IEEE80211_SKB_CB(skb); 222 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 223 224 if (bf) 225 continue; 226 227 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 228 if (!bf) { 229 __skb_unlink(skb, &tid->buf_q); 230 ath_txq_skb_done(sc, txq, skb); 231 ieee80211_free_txskb(sc->hw, skb); 232 continue; 233 } 234 } 235 236 } 237 238 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 239 { 240 struct ath_txq *txq = tid->ac->txq; 241 struct sk_buff *skb; 242 struct ath_buf *bf; 243 struct list_head bf_head; 244 struct ath_tx_status ts; 245 struct ath_frame_info *fi; 246 bool sendbar = false; 247 248 INIT_LIST_HEAD(&bf_head); 249 250 memset(&ts, 0, sizeof(ts)); 251 252 while ((skb = __skb_dequeue(&tid->retry_q))) { 253 fi = get_frame_info(skb); 254 bf = fi->bf; 255 if (!bf) { 256 ath_txq_skb_done(sc, txq, skb); 257 ieee80211_free_txskb(sc->hw, skb); 258 continue; 259 } 260 261 if (fi->baw_tracked) { 262 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 263 sendbar = true; 264 } 265 266 list_add_tail(&bf->list, &bf_head); 267 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 268 } 269 270 if (sendbar) { 271 ath_txq_unlock(sc, txq); 272 ath_send_bar(tid, tid->seq_start); 273 ath_txq_lock(sc, txq); 274 } 275 } 276 277 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 278 int seqno) 279 { 280 int index, cindex; 281 282 index = ATH_BA_INDEX(tid->seq_start, seqno); 283 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 284 285 __clear_bit(cindex, tid->tx_buf); 286 287 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 288 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 289 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 290 if (tid->bar_index >= 0) 291 tid->bar_index--; 292 } 293 } 294 295 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 296 struct ath_buf *bf) 297 { 298 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 299 u16 seqno = bf->bf_state.seqno; 300 int index, cindex; 301 302 index = ATH_BA_INDEX(tid->seq_start, seqno); 303 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 304 __set_bit(cindex, tid->tx_buf); 305 fi->baw_tracked = 1; 306 307 if (index >= ((tid->baw_tail - tid->baw_head) & 308 (ATH_TID_MAX_BUFS - 1))) { 309 tid->baw_tail = cindex; 310 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 311 } 312 } 313 314 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 315 struct ath_atx_tid *tid) 316 317 { 318 struct sk_buff *skb; 319 struct ath_buf *bf; 320 struct list_head bf_head; 321 struct ath_tx_status ts; 322 struct ath_frame_info *fi; 323 324 memset(&ts, 0, sizeof(ts)); 325 INIT_LIST_HEAD(&bf_head); 326 327 while ((skb = ath_tid_dequeue(tid))) { 328 fi = get_frame_info(skb); 329 bf = fi->bf; 330 331 if (!bf) { 332 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); 333 continue; 334 } 335 336 list_add_tail(&bf->list, &bf_head); 337 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 338 } 339 } 340 341 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 342 struct sk_buff *skb, int count) 343 { 344 struct ath_frame_info *fi = get_frame_info(skb); 345 struct ath_buf *bf = fi->bf; 346 struct ieee80211_hdr *hdr; 347 int prev = fi->retries; 348 349 TX_STAT_INC(txq->axq_qnum, a_retries); 350 fi->retries += count; 351 352 if (prev > 0) 353 return; 354 355 hdr = (struct ieee80211_hdr *)skb->data; 356 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 357 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 358 sizeof(*hdr), DMA_TO_DEVICE); 359 } 360 361 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 362 { 363 struct ath_buf *bf = NULL; 364 365 spin_lock_bh(&sc->tx.txbuflock); 366 367 if (unlikely(list_empty(&sc->tx.txbuf))) { 368 spin_unlock_bh(&sc->tx.txbuflock); 369 return NULL; 370 } 371 372 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 373 list_del(&bf->list); 374 375 spin_unlock_bh(&sc->tx.txbuflock); 376 377 return bf; 378 } 379 380 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 381 { 382 spin_lock_bh(&sc->tx.txbuflock); 383 list_add_tail(&bf->list, &sc->tx.txbuf); 384 spin_unlock_bh(&sc->tx.txbuflock); 385 } 386 387 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 388 { 389 struct ath_buf *tbf; 390 391 tbf = ath_tx_get_buffer(sc); 392 if (WARN_ON(!tbf)) 393 return NULL; 394 395 ATH_TXBUF_RESET(tbf); 396 397 tbf->bf_mpdu = bf->bf_mpdu; 398 tbf->bf_buf_addr = bf->bf_buf_addr; 399 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 400 tbf->bf_state = bf->bf_state; 401 tbf->bf_state.stale = false; 402 403 return tbf; 404 } 405 406 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 407 struct ath_tx_status *ts, int txok, 408 int *nframes, int *nbad) 409 { 410 struct ath_frame_info *fi; 411 u16 seq_st = 0; 412 u32 ba[WME_BA_BMP_SIZE >> 5]; 413 int ba_index; 414 int isaggr = 0; 415 416 *nbad = 0; 417 *nframes = 0; 418 419 isaggr = bf_isaggr(bf); 420 if (isaggr) { 421 seq_st = ts->ts_seqnum; 422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 423 } 424 425 while (bf) { 426 fi = get_frame_info(bf->bf_mpdu); 427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 428 429 (*nframes)++; 430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 431 (*nbad)++; 432 433 bf = bf->bf_next; 434 } 435 } 436 437 438 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 439 struct ath_buf *bf, struct list_head *bf_q, 440 struct ath_tx_status *ts, int txok) 441 { 442 struct ath_node *an = NULL; 443 struct sk_buff *skb; 444 struct ieee80211_sta *sta; 445 struct ieee80211_hw *hw = sc->hw; 446 struct ieee80211_hdr *hdr; 447 struct ieee80211_tx_info *tx_info; 448 struct ath_atx_tid *tid = NULL; 449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 450 struct list_head bf_head; 451 struct sk_buff_head bf_pending; 452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 453 u32 ba[WME_BA_BMP_SIZE >> 5]; 454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 455 bool rc_update = true, isba; 456 struct ieee80211_tx_rate rates[4]; 457 struct ath_frame_info *fi; 458 int nframes; 459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 460 int i, retries; 461 int bar_index = -1; 462 463 skb = bf->bf_mpdu; 464 hdr = (struct ieee80211_hdr *)skb->data; 465 466 tx_info = IEEE80211_SKB_CB(skb); 467 468 memcpy(rates, bf->rates, sizeof(rates)); 469 470 retries = ts->ts_longretry + 1; 471 for (i = 0; i < ts->ts_rateindex; i++) 472 retries += rates[i].count; 473 474 rcu_read_lock(); 475 476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 477 if (!sta) { 478 rcu_read_unlock(); 479 480 INIT_LIST_HEAD(&bf_head); 481 while (bf) { 482 bf_next = bf->bf_next; 483 484 if (!bf->bf_state.stale || bf_next != NULL) 485 list_move_tail(&bf->list, &bf_head); 486 487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); 488 489 bf = bf_next; 490 } 491 return; 492 } 493 494 an = (struct ath_node *)sta->drv_priv; 495 tid = ath_get_skb_tid(sc, an, skb); 496 seq_first = tid->seq_start; 497 isba = ts->ts_flags & ATH9K_TX_BA; 498 499 /* 500 * The hardware occasionally sends a tx status for the wrong TID. 501 * In this case, the BA status cannot be considered valid and all 502 * subframes need to be retransmitted 503 * 504 * Only BlockAcks have a TID and therefore normal Acks cannot be 505 * checked 506 */ 507 if (isba && tid->tidno != ts->tid) 508 txok = false; 509 510 isaggr = bf_isaggr(bf); 511 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 512 513 if (isaggr && txok) { 514 if (ts->ts_flags & ATH9K_TX_BA) { 515 seq_st = ts->ts_seqnum; 516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 517 } else { 518 /* 519 * AR5416 can become deaf/mute when BA 520 * issue happens. Chip needs to be reset. 521 * But AP code may have sychronization issues 522 * when perform internal reset in this routine. 523 * Only enable reset in STA mode for now. 524 */ 525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 526 needreset = 1; 527 } 528 } 529 530 __skb_queue_head_init(&bf_pending); 531 532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 533 while (bf) { 534 u16 seqno = bf->bf_state.seqno; 535 536 txfail = txpending = sendbar = 0; 537 bf_next = bf->bf_next; 538 539 skb = bf->bf_mpdu; 540 tx_info = IEEE80211_SKB_CB(skb); 541 fi = get_frame_info(skb); 542 543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 544 !tid->active) { 545 /* 546 * Outside of the current BlockAck window, 547 * maybe part of a previous session 548 */ 549 txfail = 1; 550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 551 /* transmit completion, subframe is 552 * acked by block ack */ 553 acked_cnt++; 554 } else if (!isaggr && txok) { 555 /* transmit completion */ 556 acked_cnt++; 557 } else if (flush) { 558 txpending = 1; 559 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 560 if (txok || !an->sleeping) 561 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 562 retries); 563 564 txpending = 1; 565 } else { 566 txfail = 1; 567 txfail_cnt++; 568 bar_index = max_t(int, bar_index, 569 ATH_BA_INDEX(seq_first, seqno)); 570 } 571 572 /* 573 * Make sure the last desc is reclaimed if it 574 * not a holding desc. 575 */ 576 INIT_LIST_HEAD(&bf_head); 577 if (bf_next != NULL || !bf_last->bf_state.stale) 578 list_move_tail(&bf->list, &bf_head); 579 580 if (!txpending) { 581 /* 582 * complete the acked-ones/xretried ones; update 583 * block-ack window 584 */ 585 ath_tx_update_baw(sc, tid, seqno); 586 587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 588 memcpy(tx_info->control.rates, rates, sizeof(rates)); 589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 590 rc_update = false; 591 if (bf == bf->bf_lastbf) 592 ath_dynack_sample_tx_ts(sc->sc_ah, 593 bf->bf_mpdu, 594 ts); 595 } 596 597 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 598 !txfail); 599 } else { 600 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 601 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 602 ieee80211_sta_eosp(sta); 603 } 604 /* retry the un-acked ones */ 605 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 606 struct ath_buf *tbf; 607 608 tbf = ath_clone_txbuf(sc, bf_last); 609 /* 610 * Update tx baw and complete the 611 * frame with failed status if we 612 * run out of tx buf. 613 */ 614 if (!tbf) { 615 ath_tx_update_baw(sc, tid, seqno); 616 617 ath_tx_complete_buf(sc, bf, txq, 618 &bf_head, ts, 0); 619 bar_index = max_t(int, bar_index, 620 ATH_BA_INDEX(seq_first, seqno)); 621 break; 622 } 623 624 fi->bf = tbf; 625 } 626 627 /* 628 * Put this buffer to the temporary pending 629 * queue to retain ordering 630 */ 631 __skb_queue_tail(&bf_pending, skb); 632 } 633 634 bf = bf_next; 635 } 636 637 /* prepend un-acked frames to the beginning of the pending frame queue */ 638 if (!skb_queue_empty(&bf_pending)) { 639 if (an->sleeping) 640 ieee80211_sta_set_buffered(sta, tid->tidno, true); 641 642 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 643 if (!an->sleeping) { 644 ath_tx_queue_tid(sc, txq, tid); 645 646 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 647 tid->ac->clear_ps_filter = true; 648 } 649 } 650 651 if (bar_index >= 0) { 652 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 653 654 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 655 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 656 657 ath_txq_unlock(sc, txq); 658 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 659 ath_txq_lock(sc, txq); 660 } 661 662 rcu_read_unlock(); 663 664 if (needreset) 665 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 666 } 667 668 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 669 { 670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 671 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 672 } 673 674 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 675 struct ath_tx_status *ts, struct ath_buf *bf, 676 struct list_head *bf_head) 677 { 678 struct ieee80211_tx_info *info; 679 bool txok, flush; 680 681 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 682 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 683 txq->axq_tx_inprogress = false; 684 685 txq->axq_depth--; 686 if (bf_is_ampdu_not_probing(bf)) 687 txq->axq_ampdu_depth--; 688 689 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 690 ts->ts_rateindex); 691 if (!bf_isampdu(bf)) { 692 if (!flush) { 693 info = IEEE80211_SKB_CB(bf->bf_mpdu); 694 memcpy(info->control.rates, bf->rates, 695 sizeof(info->control.rates)); 696 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 697 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts); 698 } 699 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); 700 } else 701 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok); 702 703 if (!flush) 704 ath_txq_schedule(sc, txq); 705 } 706 707 static bool ath_lookup_legacy(struct ath_buf *bf) 708 { 709 struct sk_buff *skb; 710 struct ieee80211_tx_info *tx_info; 711 struct ieee80211_tx_rate *rates; 712 int i; 713 714 skb = bf->bf_mpdu; 715 tx_info = IEEE80211_SKB_CB(skb); 716 rates = tx_info->control.rates; 717 718 for (i = 0; i < 4; i++) { 719 if (!rates[i].count || rates[i].idx < 0) 720 break; 721 722 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 723 return true; 724 } 725 726 return false; 727 } 728 729 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 730 struct ath_atx_tid *tid) 731 { 732 struct sk_buff *skb; 733 struct ieee80211_tx_info *tx_info; 734 struct ieee80211_tx_rate *rates; 735 u32 max_4ms_framelen, frmlen; 736 u16 aggr_limit, bt_aggr_limit, legacy = 0; 737 int q = tid->ac->txq->mac80211_qnum; 738 int i; 739 740 skb = bf->bf_mpdu; 741 tx_info = IEEE80211_SKB_CB(skb); 742 rates = bf->rates; 743 744 /* 745 * Find the lowest frame length among the rate series that will have a 746 * 4ms (or TXOP limited) transmit duration. 747 */ 748 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 749 750 for (i = 0; i < 4; i++) { 751 int modeidx; 752 753 if (!rates[i].count) 754 continue; 755 756 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 757 legacy = 1; 758 break; 759 } 760 761 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 762 modeidx = MCS_HT40; 763 else 764 modeidx = MCS_HT20; 765 766 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 767 modeidx++; 768 769 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 770 max_4ms_framelen = min(max_4ms_framelen, frmlen); 771 } 772 773 /* 774 * limit aggregate size by the minimum rate if rate selected is 775 * not a probe rate, if rate selected is a probe rate then 776 * avoid aggregation of this packet. 777 */ 778 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 779 return 0; 780 781 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 782 783 /* 784 * Override the default aggregation limit for BTCOEX. 785 */ 786 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 787 if (bt_aggr_limit) 788 aggr_limit = bt_aggr_limit; 789 790 if (tid->an->maxampdu) 791 aggr_limit = min(aggr_limit, tid->an->maxampdu); 792 793 return aggr_limit; 794 } 795 796 /* 797 * Returns the number of delimiters to be added to 798 * meet the minimum required mpdudensity. 799 */ 800 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 801 struct ath_buf *bf, u16 frmlen, 802 bool first_subfrm) 803 { 804 #define FIRST_DESC_NDELIMS 60 805 u32 nsymbits, nsymbols; 806 u16 minlen; 807 u8 flags, rix; 808 int width, streams, half_gi, ndelim, mindelim; 809 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 810 811 /* Select standard number of delimiters based on frame length alone */ 812 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 813 814 /* 815 * If encryption enabled, hardware requires some more padding between 816 * subframes. 817 * TODO - this could be improved to be dependent on the rate. 818 * The hardware can keep up at lower rates, but not higher rates 819 */ 820 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 821 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 822 ndelim += ATH_AGGR_ENCRYPTDELIM; 823 824 /* 825 * Add delimiter when using RTS/CTS with aggregation 826 * and non enterprise AR9003 card 827 */ 828 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 829 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 830 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 831 832 /* 833 * Convert desired mpdu density from microeconds to bytes based 834 * on highest rate in rate series (i.e. first rate) to determine 835 * required minimum length for subframe. Take into account 836 * whether high rate is 20 or 40Mhz and half or full GI. 837 * 838 * If there is no mpdu density restriction, no further calculation 839 * is needed. 840 */ 841 842 if (tid->an->mpdudensity == 0) 843 return ndelim; 844 845 rix = bf->rates[0].idx; 846 flags = bf->rates[0].flags; 847 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 848 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 849 850 if (half_gi) 851 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 852 else 853 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 854 855 if (nsymbols == 0) 856 nsymbols = 1; 857 858 streams = HT_RC_2_STREAMS(rix); 859 nsymbits = bits_per_symbol[rix % 8][width] * streams; 860 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 861 862 if (frmlen < minlen) { 863 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 864 ndelim = max(mindelim, ndelim); 865 } 866 867 return ndelim; 868 } 869 870 static struct ath_buf * 871 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 872 struct ath_atx_tid *tid, struct sk_buff_head **q) 873 { 874 struct ieee80211_tx_info *tx_info; 875 struct ath_frame_info *fi; 876 struct sk_buff *skb; 877 struct ath_buf *bf; 878 u16 seqno; 879 880 while (1) { 881 *q = &tid->retry_q; 882 if (skb_queue_empty(*q)) 883 *q = &tid->buf_q; 884 885 skb = skb_peek(*q); 886 if (!skb) 887 break; 888 889 fi = get_frame_info(skb); 890 bf = fi->bf; 891 if (!fi->bf) 892 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 893 else 894 bf->bf_state.stale = false; 895 896 if (!bf) { 897 __skb_unlink(skb, *q); 898 ath_txq_skb_done(sc, txq, skb); 899 ieee80211_free_txskb(sc->hw, skb); 900 continue; 901 } 902 903 bf->bf_next = NULL; 904 bf->bf_lastbf = bf; 905 906 tx_info = IEEE80211_SKB_CB(skb); 907 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 908 909 /* 910 * No aggregation session is running, but there may be frames 911 * from a previous session or a failed attempt in the queue. 912 * Send them out as normal data frames 913 */ 914 if (!tid->active) 915 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 916 917 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 918 bf->bf_state.bf_type = 0; 919 return bf; 920 } 921 922 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 923 seqno = bf->bf_state.seqno; 924 925 /* do not step over block-ack window */ 926 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) 927 break; 928 929 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 930 struct ath_tx_status ts = {}; 931 struct list_head bf_head; 932 933 INIT_LIST_HEAD(&bf_head); 934 list_add(&bf->list, &bf_head); 935 __skb_unlink(skb, *q); 936 ath_tx_update_baw(sc, tid, seqno); 937 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 938 continue; 939 } 940 941 return bf; 942 } 943 944 return NULL; 945 } 946 947 static bool 948 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 949 struct ath_atx_tid *tid, struct list_head *bf_q, 950 struct ath_buf *bf_first, struct sk_buff_head *tid_q, 951 int *aggr_len) 952 { 953 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 954 struct ath_buf *bf = bf_first, *bf_prev = NULL; 955 int nframes = 0, ndelim; 956 u16 aggr_limit = 0, al = 0, bpad = 0, 957 al_delta, h_baw = tid->baw_size / 2; 958 struct ieee80211_tx_info *tx_info; 959 struct ath_frame_info *fi; 960 struct sk_buff *skb; 961 bool closed = false; 962 963 bf = bf_first; 964 aggr_limit = ath_lookup_rate(sc, bf, tid); 965 966 do { 967 skb = bf->bf_mpdu; 968 fi = get_frame_info(skb); 969 970 /* do not exceed aggregation limit */ 971 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 972 if (nframes) { 973 if (aggr_limit < al + bpad + al_delta || 974 ath_lookup_legacy(bf) || nframes >= h_baw) 975 break; 976 977 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 978 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 979 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 980 break; 981 } 982 983 /* add padding for previous frame to aggregation length */ 984 al += bpad + al_delta; 985 986 /* 987 * Get the delimiters needed to meet the MPDU 988 * density for this node. 989 */ 990 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 991 !nframes); 992 bpad = PADBYTES(al_delta) + (ndelim << 2); 993 994 nframes++; 995 bf->bf_next = NULL; 996 997 /* link buffers of this frame to the aggregate */ 998 if (!fi->baw_tracked) 999 ath_tx_addto_baw(sc, tid, bf); 1000 bf->bf_state.ndelim = ndelim; 1001 1002 __skb_unlink(skb, tid_q); 1003 list_add_tail(&bf->list, bf_q); 1004 if (bf_prev) 1005 bf_prev->bf_next = bf; 1006 1007 bf_prev = bf; 1008 1009 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1010 if (!bf) { 1011 closed = true; 1012 break; 1013 } 1014 } while (ath_tid_has_buffered(tid)); 1015 1016 bf = bf_first; 1017 bf->bf_lastbf = bf_prev; 1018 1019 if (bf == bf_prev) { 1020 al = get_frame_info(bf->bf_mpdu)->framelen; 1021 bf->bf_state.bf_type = BUF_AMPDU; 1022 } else { 1023 TX_STAT_INC(txq->axq_qnum, a_aggr); 1024 } 1025 1026 *aggr_len = al; 1027 1028 return closed; 1029 #undef PADBYTES 1030 } 1031 1032 /* 1033 * rix - rate index 1034 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1035 * width - 0 for 20 MHz, 1 for 40 MHz 1036 * half_gi - to use 4us v/s 3.6 us for symbol time 1037 */ 1038 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1039 int width, int half_gi, bool shortPreamble) 1040 { 1041 u32 nbits, nsymbits, duration, nsymbols; 1042 int streams; 1043 1044 /* find number of symbols: PLCP + data */ 1045 streams = HT_RC_2_STREAMS(rix); 1046 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1047 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1048 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1049 1050 if (!half_gi) 1051 duration = SYMBOL_TIME(nsymbols); 1052 else 1053 duration = SYMBOL_TIME_HALFGI(nsymbols); 1054 1055 /* addup duration for legacy/ht training and signal fields */ 1056 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1057 1058 return duration; 1059 } 1060 1061 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1062 { 1063 int streams = HT_RC_2_STREAMS(mcs); 1064 int symbols, bits; 1065 int bytes = 0; 1066 1067 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1068 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1069 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1070 bits -= OFDM_PLCP_BITS; 1071 bytes = bits / 8; 1072 if (bytes > 65532) 1073 bytes = 65532; 1074 1075 return bytes; 1076 } 1077 1078 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1079 { 1080 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1081 int mcs; 1082 1083 /* 4ms is the default (and maximum) duration */ 1084 if (!txop || txop > 4096) 1085 txop = 4096; 1086 1087 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1088 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1089 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1090 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1091 for (mcs = 0; mcs < 32; mcs++) { 1092 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1093 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1094 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1095 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1096 } 1097 } 1098 1099 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1100 u8 rateidx, bool is_40, bool is_cck) 1101 { 1102 u8 max_power; 1103 struct sk_buff *skb; 1104 struct ath_frame_info *fi; 1105 struct ieee80211_tx_info *info; 1106 struct ath_hw *ah = sc->sc_ah; 1107 1108 if (sc->tx99_state || !ah->tpc_enabled) 1109 return MAX_RATE_POWER; 1110 1111 skb = bf->bf_mpdu; 1112 fi = get_frame_info(skb); 1113 info = IEEE80211_SKB_CB(skb); 1114 1115 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1116 int txpower = fi->tx_power; 1117 1118 if (is_40) { 1119 u8 power_ht40delta; 1120 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1121 1122 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) { 1123 bool is_2ghz; 1124 struct modal_eep_header *pmodal; 1125 1126 is_2ghz = info->band == IEEE80211_BAND_2GHZ; 1127 pmodal = &eep->modalHeader[is_2ghz]; 1128 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1129 } else { 1130 power_ht40delta = 2; 1131 } 1132 txpower += power_ht40delta; 1133 } 1134 1135 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1136 AR_SREV_9271(ah)) { 1137 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1138 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1139 s8 power_offset; 1140 1141 power_offset = ah->eep_ops->get_eeprom(ah, 1142 EEP_PWR_TABLE_OFFSET); 1143 txpower -= 2 * power_offset; 1144 } 1145 1146 if (OLC_FOR_AR9280_20_LATER && is_cck) 1147 txpower -= 2; 1148 1149 txpower = max(txpower, 0); 1150 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1151 1152 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1153 * max_power is set to 0, frames are transmitted at max 1154 * TX power 1155 */ 1156 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1157 max_power = 1; 1158 } else if (!bf->bf_state.bfs_paprd) { 1159 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC)) 1160 max_power = min(ah->tx_power_stbc[rateidx], 1161 fi->tx_power); 1162 else 1163 max_power = min(ah->tx_power[rateidx], fi->tx_power); 1164 } else { 1165 max_power = ah->paprd_training_power; 1166 } 1167 1168 return max_power; 1169 } 1170 1171 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1172 struct ath_tx_info *info, int len, bool rts) 1173 { 1174 struct ath_hw *ah = sc->sc_ah; 1175 struct ath_common *common = ath9k_hw_common(ah); 1176 struct sk_buff *skb; 1177 struct ieee80211_tx_info *tx_info; 1178 struct ieee80211_tx_rate *rates; 1179 const struct ieee80211_rate *rate; 1180 struct ieee80211_hdr *hdr; 1181 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1182 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1183 int i; 1184 u8 rix = 0; 1185 1186 skb = bf->bf_mpdu; 1187 tx_info = IEEE80211_SKB_CB(skb); 1188 rates = bf->rates; 1189 hdr = (struct ieee80211_hdr *)skb->data; 1190 1191 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1192 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1193 info->rtscts_rate = fi->rtscts_rate; 1194 1195 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1196 bool is_40, is_sgi, is_sp, is_cck; 1197 int phy; 1198 1199 if (!rates[i].count || (rates[i].idx < 0)) 1200 continue; 1201 1202 rix = rates[i].idx; 1203 info->rates[i].Tries = rates[i].count; 1204 1205 /* 1206 * Handle RTS threshold for unaggregated HT frames. 1207 */ 1208 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1209 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1210 unlikely(rts_thresh != (u32) -1)) { 1211 if (!rts_thresh || (len > rts_thresh)) 1212 rts = true; 1213 } 1214 1215 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1216 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1217 info->flags |= ATH9K_TXDESC_RTSENA; 1218 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1219 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1220 info->flags |= ATH9K_TXDESC_CTSENA; 1221 } 1222 1223 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1224 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1225 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1226 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1227 1228 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1229 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1230 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1231 1232 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1233 /* MCS rates */ 1234 info->rates[i].Rate = rix | 0x80; 1235 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1236 ah->txchainmask, info->rates[i].Rate); 1237 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1238 is_40, is_sgi, is_sp); 1239 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1240 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1241 1242 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1243 is_40, false); 1244 continue; 1245 } 1246 1247 /* legacy rates */ 1248 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1249 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1250 !(rate->flags & IEEE80211_RATE_ERP_G)) 1251 phy = WLAN_RC_PHY_CCK; 1252 else 1253 phy = WLAN_RC_PHY_OFDM; 1254 1255 info->rates[i].Rate = rate->hw_value; 1256 if (rate->hw_value_short) { 1257 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1258 info->rates[i].Rate |= rate->hw_value_short; 1259 } else { 1260 is_sp = false; 1261 } 1262 1263 if (bf->bf_state.bfs_paprd) 1264 info->rates[i].ChSel = ah->txchainmask; 1265 else 1266 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1267 ah->txchainmask, info->rates[i].Rate); 1268 1269 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1270 phy, rate->bitrate * 100, len, rix, is_sp); 1271 1272 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1273 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1274 is_cck); 1275 } 1276 1277 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1278 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1279 info->flags &= ~ATH9K_TXDESC_RTSENA; 1280 1281 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1282 if (info->flags & ATH9K_TXDESC_RTSENA) 1283 info->flags &= ~ATH9K_TXDESC_CTSENA; 1284 } 1285 1286 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1287 { 1288 struct ieee80211_hdr *hdr; 1289 enum ath9k_pkt_type htype; 1290 __le16 fc; 1291 1292 hdr = (struct ieee80211_hdr *)skb->data; 1293 fc = hdr->frame_control; 1294 1295 if (ieee80211_is_beacon(fc)) 1296 htype = ATH9K_PKT_TYPE_BEACON; 1297 else if (ieee80211_is_probe_resp(fc)) 1298 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1299 else if (ieee80211_is_atim(fc)) 1300 htype = ATH9K_PKT_TYPE_ATIM; 1301 else if (ieee80211_is_pspoll(fc)) 1302 htype = ATH9K_PKT_TYPE_PSPOLL; 1303 else 1304 htype = ATH9K_PKT_TYPE_NORMAL; 1305 1306 return htype; 1307 } 1308 1309 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1310 struct ath_txq *txq, int len) 1311 { 1312 struct ath_hw *ah = sc->sc_ah; 1313 struct ath_buf *bf_first = NULL; 1314 struct ath_tx_info info; 1315 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1316 bool rts = false; 1317 1318 memset(&info, 0, sizeof(info)); 1319 info.is_first = true; 1320 info.is_last = true; 1321 info.qcu = txq->axq_qnum; 1322 1323 while (bf) { 1324 struct sk_buff *skb = bf->bf_mpdu; 1325 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1326 struct ath_frame_info *fi = get_frame_info(skb); 1327 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1328 1329 info.type = get_hw_packet_type(skb); 1330 if (bf->bf_next) 1331 info.link = bf->bf_next->bf_daddr; 1332 else 1333 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1334 1335 if (!bf_first) { 1336 bf_first = bf; 1337 1338 if (!sc->tx99_state) 1339 info.flags = ATH9K_TXDESC_INTREQ; 1340 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1341 txq == sc->tx.uapsdq) 1342 info.flags |= ATH9K_TXDESC_CLRDMASK; 1343 1344 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1345 info.flags |= ATH9K_TXDESC_NOACK; 1346 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1347 info.flags |= ATH9K_TXDESC_LDPC; 1348 1349 if (bf->bf_state.bfs_paprd) 1350 info.flags |= (u32) bf->bf_state.bfs_paprd << 1351 ATH9K_TXDESC_PAPRD_S; 1352 1353 /* 1354 * mac80211 doesn't handle RTS threshold for HT because 1355 * the decision has to be taken based on AMPDU length 1356 * and aggregation is done entirely inside ath9k. 1357 * Set the RTS/CTS flag for the first subframe based 1358 * on the threshold. 1359 */ 1360 if (aggr && (bf == bf_first) && 1361 unlikely(rts_thresh != (u32) -1)) { 1362 /* 1363 * "len" is the size of the entire AMPDU. 1364 */ 1365 if (!rts_thresh || (len > rts_thresh)) 1366 rts = true; 1367 } 1368 1369 if (!aggr) 1370 len = fi->framelen; 1371 1372 ath_buf_set_rate(sc, bf, &info, len, rts); 1373 } 1374 1375 info.buf_addr[0] = bf->bf_buf_addr; 1376 info.buf_len[0] = skb->len; 1377 info.pkt_len = fi->framelen; 1378 info.keyix = fi->keyix; 1379 info.keytype = fi->keytype; 1380 1381 if (aggr) { 1382 if (bf == bf_first) 1383 info.aggr = AGGR_BUF_FIRST; 1384 else if (bf == bf_first->bf_lastbf) 1385 info.aggr = AGGR_BUF_LAST; 1386 else 1387 info.aggr = AGGR_BUF_MIDDLE; 1388 1389 info.ndelim = bf->bf_state.ndelim; 1390 info.aggr_len = len; 1391 } 1392 1393 if (bf == bf_first->bf_lastbf) 1394 bf_first = NULL; 1395 1396 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1397 bf = bf->bf_next; 1398 } 1399 } 1400 1401 static void 1402 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1403 struct ath_atx_tid *tid, struct list_head *bf_q, 1404 struct ath_buf *bf_first, struct sk_buff_head *tid_q) 1405 { 1406 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1407 struct sk_buff *skb; 1408 int nframes = 0; 1409 1410 do { 1411 struct ieee80211_tx_info *tx_info; 1412 skb = bf->bf_mpdu; 1413 1414 nframes++; 1415 __skb_unlink(skb, tid_q); 1416 list_add_tail(&bf->list, bf_q); 1417 if (bf_prev) 1418 bf_prev->bf_next = bf; 1419 bf_prev = bf; 1420 1421 if (nframes >= 2) 1422 break; 1423 1424 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1425 if (!bf) 1426 break; 1427 1428 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1429 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) 1430 break; 1431 1432 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1433 } while (1); 1434 } 1435 1436 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1437 struct ath_atx_tid *tid, bool *stop) 1438 { 1439 struct ath_buf *bf; 1440 struct ieee80211_tx_info *tx_info; 1441 struct sk_buff_head *tid_q; 1442 struct list_head bf_q; 1443 int aggr_len = 0; 1444 bool aggr, last = true; 1445 1446 if (!ath_tid_has_buffered(tid)) 1447 return false; 1448 1449 INIT_LIST_HEAD(&bf_q); 1450 1451 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q); 1452 if (!bf) 1453 return false; 1454 1455 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1456 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1457 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1458 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1459 *stop = true; 1460 return false; 1461 } 1462 1463 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1464 if (aggr) 1465 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf, 1466 tid_q, &aggr_len); 1467 else 1468 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q); 1469 1470 if (list_empty(&bf_q)) 1471 return false; 1472 1473 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) { 1474 tid->ac->clear_ps_filter = false; 1475 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1476 } 1477 1478 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1479 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1480 return true; 1481 } 1482 1483 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1484 u16 tid, u16 *ssn) 1485 { 1486 struct ath_atx_tid *txtid; 1487 struct ath_txq *txq; 1488 struct ath_node *an; 1489 u8 density; 1490 1491 an = (struct ath_node *)sta->drv_priv; 1492 txtid = ATH_AN_2_TID(an, tid); 1493 txq = txtid->ac->txq; 1494 1495 ath_txq_lock(sc, txq); 1496 1497 /* update ampdu factor/density, they may have changed. This may happen 1498 * in HT IBSS when a beacon with HT-info is received after the station 1499 * has already been added. 1500 */ 1501 if (sta->ht_cap.ht_supported) { 1502 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1503 sta->ht_cap.ampdu_factor)) - 1; 1504 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1505 an->mpdudensity = density; 1506 } 1507 1508 /* force sequence number allocation for pending frames */ 1509 ath_tx_tid_change_state(sc, txtid); 1510 1511 txtid->active = true; 1512 *ssn = txtid->seq_start = txtid->seq_next; 1513 txtid->bar_index = -1; 1514 1515 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1516 txtid->baw_head = txtid->baw_tail = 0; 1517 1518 ath_txq_unlock_complete(sc, txq); 1519 1520 return 0; 1521 } 1522 1523 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1524 { 1525 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1526 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1527 struct ath_txq *txq = txtid->ac->txq; 1528 1529 ath_txq_lock(sc, txq); 1530 txtid->active = false; 1531 ath_tx_flush_tid(sc, txtid); 1532 ath_tx_tid_change_state(sc, txtid); 1533 ath_txq_unlock_complete(sc, txq); 1534 } 1535 1536 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1537 struct ath_node *an) 1538 { 1539 struct ath_atx_tid *tid; 1540 struct ath_atx_ac *ac; 1541 struct ath_txq *txq; 1542 bool buffered; 1543 int tidno; 1544 1545 for (tidno = 0, tid = &an->tid[tidno]; 1546 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1547 1548 ac = tid->ac; 1549 txq = ac->txq; 1550 1551 ath_txq_lock(sc, txq); 1552 1553 if (!tid->sched) { 1554 ath_txq_unlock(sc, txq); 1555 continue; 1556 } 1557 1558 buffered = ath_tid_has_buffered(tid); 1559 1560 tid->sched = false; 1561 list_del(&tid->list); 1562 1563 if (ac->sched) { 1564 ac->sched = false; 1565 list_del(&ac->list); 1566 } 1567 1568 ath_txq_unlock(sc, txq); 1569 1570 ieee80211_sta_set_buffered(sta, tidno, buffered); 1571 } 1572 } 1573 1574 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1575 { 1576 struct ath_atx_tid *tid; 1577 struct ath_atx_ac *ac; 1578 struct ath_txq *txq; 1579 int tidno; 1580 1581 for (tidno = 0, tid = &an->tid[tidno]; 1582 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 1583 1584 ac = tid->ac; 1585 txq = ac->txq; 1586 1587 ath_txq_lock(sc, txq); 1588 ac->clear_ps_filter = true; 1589 1590 if (ath_tid_has_buffered(tid)) { 1591 ath_tx_queue_tid(sc, txq, tid); 1592 ath_txq_schedule(sc, txq); 1593 } 1594 1595 ath_txq_unlock_complete(sc, txq); 1596 } 1597 } 1598 1599 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, 1600 u16 tidno) 1601 { 1602 struct ath_atx_tid *tid; 1603 struct ath_node *an; 1604 struct ath_txq *txq; 1605 1606 an = (struct ath_node *)sta->drv_priv; 1607 tid = ATH_AN_2_TID(an, tidno); 1608 txq = tid->ac->txq; 1609 1610 ath_txq_lock(sc, txq); 1611 1612 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1613 1614 if (ath_tid_has_buffered(tid)) { 1615 ath_tx_queue_tid(sc, txq, tid); 1616 ath_txq_schedule(sc, txq); 1617 } 1618 1619 ath_txq_unlock_complete(sc, txq); 1620 } 1621 1622 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1623 struct ieee80211_sta *sta, 1624 u16 tids, int nframes, 1625 enum ieee80211_frame_release_type reason, 1626 bool more_data) 1627 { 1628 struct ath_softc *sc = hw->priv; 1629 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1630 struct ath_txq *txq = sc->tx.uapsdq; 1631 struct ieee80211_tx_info *info; 1632 struct list_head bf_q; 1633 struct ath_buf *bf_tail = NULL, *bf; 1634 struct sk_buff_head *tid_q; 1635 int sent = 0; 1636 int i; 1637 1638 INIT_LIST_HEAD(&bf_q); 1639 for (i = 0; tids && nframes; i++, tids >>= 1) { 1640 struct ath_atx_tid *tid; 1641 1642 if (!(tids & 1)) 1643 continue; 1644 1645 tid = ATH_AN_2_TID(an, i); 1646 1647 ath_txq_lock(sc, tid->ac->txq); 1648 while (nframes > 0) { 1649 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q); 1650 if (!bf) 1651 break; 1652 1653 __skb_unlink(bf->bf_mpdu, tid_q); 1654 list_add_tail(&bf->list, &bf_q); 1655 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1656 if (bf_isampdu(bf)) { 1657 ath_tx_addto_baw(sc, tid, bf); 1658 bf->bf_state.bf_type &= ~BUF_AGGR; 1659 } 1660 if (bf_tail) 1661 bf_tail->bf_next = bf; 1662 1663 bf_tail = bf; 1664 nframes--; 1665 sent++; 1666 TX_STAT_INC(txq->axq_qnum, a_queued_hw); 1667 1668 if (an->sta && !ath_tid_has_buffered(tid)) 1669 ieee80211_sta_set_buffered(an->sta, i, false); 1670 } 1671 ath_txq_unlock_complete(sc, tid->ac->txq); 1672 } 1673 1674 if (list_empty(&bf_q)) 1675 return; 1676 1677 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1678 info->flags |= IEEE80211_TX_STATUS_EOSP; 1679 1680 bf = list_first_entry(&bf_q, struct ath_buf, list); 1681 ath_txq_lock(sc, txq); 1682 ath_tx_fill_desc(sc, bf, txq, 0); 1683 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1684 ath_txq_unlock(sc, txq); 1685 } 1686 1687 /********************/ 1688 /* Queue Management */ 1689 /********************/ 1690 1691 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1692 { 1693 struct ath_hw *ah = sc->sc_ah; 1694 struct ath9k_tx_queue_info qi; 1695 static const int subtype_txq_to_hwq[] = { 1696 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1697 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1698 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1699 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1700 }; 1701 int axq_qnum, i; 1702 1703 memset(&qi, 0, sizeof(qi)); 1704 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1705 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1706 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1707 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1708 qi.tqi_physCompBuf = 0; 1709 1710 /* 1711 * Enable interrupts only for EOL and DESC conditions. 1712 * We mark tx descriptors to receive a DESC interrupt 1713 * when a tx queue gets deep; otherwise waiting for the 1714 * EOL to reap descriptors. Note that this is done to 1715 * reduce interrupt load and this only defers reaping 1716 * descriptors, never transmitting frames. Aside from 1717 * reducing interrupts this also permits more concurrency. 1718 * The only potential downside is if the tx queue backs 1719 * up in which case the top half of the kernel may backup 1720 * due to a lack of tx descriptors. 1721 * 1722 * The UAPSD queue is an exception, since we take a desc- 1723 * based intr on the EOSP frames. 1724 */ 1725 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1726 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1727 } else { 1728 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1729 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1730 else 1731 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1732 TXQ_FLAG_TXDESCINT_ENABLE; 1733 } 1734 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1735 if (axq_qnum == -1) { 1736 /* 1737 * NB: don't print a message, this happens 1738 * normally on parts with too few tx queues 1739 */ 1740 return NULL; 1741 } 1742 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1743 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1744 1745 txq->axq_qnum = axq_qnum; 1746 txq->mac80211_qnum = -1; 1747 txq->axq_link = NULL; 1748 __skb_queue_head_init(&txq->complete_q); 1749 INIT_LIST_HEAD(&txq->axq_q); 1750 spin_lock_init(&txq->axq_lock); 1751 txq->axq_depth = 0; 1752 txq->axq_ampdu_depth = 0; 1753 txq->axq_tx_inprogress = false; 1754 sc->tx.txqsetup |= 1<<axq_qnum; 1755 1756 txq->txq_headidx = txq->txq_tailidx = 0; 1757 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1758 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1759 } 1760 return &sc->tx.txq[axq_qnum]; 1761 } 1762 1763 int ath_txq_update(struct ath_softc *sc, int qnum, 1764 struct ath9k_tx_queue_info *qinfo) 1765 { 1766 struct ath_hw *ah = sc->sc_ah; 1767 int error = 0; 1768 struct ath9k_tx_queue_info qi; 1769 1770 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1771 1772 ath9k_hw_get_txq_props(ah, qnum, &qi); 1773 qi.tqi_aifs = qinfo->tqi_aifs; 1774 qi.tqi_cwmin = qinfo->tqi_cwmin; 1775 qi.tqi_cwmax = qinfo->tqi_cwmax; 1776 qi.tqi_burstTime = qinfo->tqi_burstTime; 1777 qi.tqi_readyTime = qinfo->tqi_readyTime; 1778 1779 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1780 ath_err(ath9k_hw_common(sc->sc_ah), 1781 "Unable to update hardware queue %u!\n", qnum); 1782 error = -EIO; 1783 } else { 1784 ath9k_hw_resettxqueue(ah, qnum); 1785 } 1786 1787 return error; 1788 } 1789 1790 int ath_cabq_update(struct ath_softc *sc) 1791 { 1792 struct ath9k_tx_queue_info qi; 1793 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1794 int qnum = sc->beacon.cabq->axq_qnum; 1795 1796 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1797 1798 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1799 ATH_CABQ_READY_TIME) / 100; 1800 ath_txq_update(sc, qnum, &qi); 1801 1802 return 0; 1803 } 1804 1805 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1806 struct list_head *list) 1807 { 1808 struct ath_buf *bf, *lastbf; 1809 struct list_head bf_head; 1810 struct ath_tx_status ts; 1811 1812 memset(&ts, 0, sizeof(ts)); 1813 ts.ts_status = ATH9K_TX_FLUSH; 1814 INIT_LIST_HEAD(&bf_head); 1815 1816 while (!list_empty(list)) { 1817 bf = list_first_entry(list, struct ath_buf, list); 1818 1819 if (bf->bf_state.stale) { 1820 list_del(&bf->list); 1821 1822 ath_tx_return_buffer(sc, bf); 1823 continue; 1824 } 1825 1826 lastbf = bf->bf_lastbf; 1827 list_cut_position(&bf_head, list, &lastbf->list); 1828 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1829 } 1830 } 1831 1832 /* 1833 * Drain a given TX queue (could be Beacon or Data) 1834 * 1835 * This assumes output has been stopped and 1836 * we do not need to block ath_tx_tasklet. 1837 */ 1838 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1839 { 1840 ath_txq_lock(sc, txq); 1841 1842 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1843 int idx = txq->txq_tailidx; 1844 1845 while (!list_empty(&txq->txq_fifo[idx])) { 1846 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1847 1848 INCR(idx, ATH_TXFIFO_DEPTH); 1849 } 1850 txq->txq_tailidx = idx; 1851 } 1852 1853 txq->axq_link = NULL; 1854 txq->axq_tx_inprogress = false; 1855 ath_drain_txq_list(sc, txq, &txq->axq_q); 1856 1857 ath_txq_unlock_complete(sc, txq); 1858 } 1859 1860 bool ath_drain_all_txq(struct ath_softc *sc) 1861 { 1862 struct ath_hw *ah = sc->sc_ah; 1863 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1864 struct ath_txq *txq; 1865 int i; 1866 u32 npend = 0; 1867 1868 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1869 return true; 1870 1871 ath9k_hw_abort_tx_dma(ah); 1872 1873 /* Check if any queue remains active */ 1874 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1875 if (!ATH_TXQ_SETUP(sc, i)) 1876 continue; 1877 1878 if (!sc->tx.txq[i].axq_depth) 1879 continue; 1880 1881 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1882 npend |= BIT(i); 1883 } 1884 1885 if (npend) 1886 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1887 1888 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1889 if (!ATH_TXQ_SETUP(sc, i)) 1890 continue; 1891 1892 /* 1893 * The caller will resume queues with ieee80211_wake_queues. 1894 * Mark the queue as not stopped to prevent ath_tx_complete 1895 * from waking the queue too early. 1896 */ 1897 txq = &sc->tx.txq[i]; 1898 txq->stopped = false; 1899 ath_draintxq(sc, txq); 1900 } 1901 1902 return !npend; 1903 } 1904 1905 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1906 { 1907 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1908 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1909 } 1910 1911 /* For each acq entry, for each tid, try to schedule packets 1912 * for transmit until ampdu_depth has reached min Q depth. 1913 */ 1914 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1915 { 1916 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1917 struct ath_atx_ac *ac, *last_ac; 1918 struct ath_atx_tid *tid, *last_tid; 1919 struct list_head *ac_list; 1920 bool sent = false; 1921 1922 if (txq->mac80211_qnum < 0) 1923 return; 1924 1925 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1926 return; 1927 1928 spin_lock_bh(&sc->chan_lock); 1929 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum]; 1930 1931 if (list_empty(ac_list)) { 1932 spin_unlock_bh(&sc->chan_lock); 1933 return; 1934 } 1935 1936 rcu_read_lock(); 1937 1938 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list); 1939 while (!list_empty(ac_list)) { 1940 bool stop = false; 1941 1942 if (sc->cur_chan->stopped) 1943 break; 1944 1945 ac = list_first_entry(ac_list, struct ath_atx_ac, list); 1946 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); 1947 list_del(&ac->list); 1948 ac->sched = false; 1949 1950 while (!list_empty(&ac->tid_q)) { 1951 1952 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, 1953 list); 1954 list_del(&tid->list); 1955 tid->sched = false; 1956 1957 if (ath_tx_sched_aggr(sc, txq, tid, &stop)) 1958 sent = true; 1959 1960 /* 1961 * add tid to round-robin queue if more frames 1962 * are pending for the tid 1963 */ 1964 if (ath_tid_has_buffered(tid)) 1965 ath_tx_queue_tid(sc, txq, tid); 1966 1967 if (stop || tid == last_tid) 1968 break; 1969 } 1970 1971 if (!list_empty(&ac->tid_q) && !ac->sched) { 1972 ac->sched = true; 1973 list_add_tail(&ac->list, ac_list); 1974 } 1975 1976 if (stop) 1977 break; 1978 1979 if (ac == last_ac) { 1980 if (!sent) 1981 break; 1982 1983 sent = false; 1984 last_ac = list_entry(ac_list->prev, 1985 struct ath_atx_ac, list); 1986 } 1987 } 1988 1989 rcu_read_unlock(); 1990 spin_unlock_bh(&sc->chan_lock); 1991 } 1992 1993 void ath_txq_schedule_all(struct ath_softc *sc) 1994 { 1995 struct ath_txq *txq; 1996 int i; 1997 1998 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 1999 txq = sc->tx.txq_map[i]; 2000 2001 spin_lock_bh(&txq->axq_lock); 2002 ath_txq_schedule(sc, txq); 2003 spin_unlock_bh(&txq->axq_lock); 2004 } 2005 } 2006 2007 /***********/ 2008 /* TX, DMA */ 2009 /***********/ 2010 2011 /* 2012 * Insert a chain of ath_buf (descriptors) on a txq and 2013 * assume the descriptors are already chained together by caller. 2014 */ 2015 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2016 struct list_head *head, bool internal) 2017 { 2018 struct ath_hw *ah = sc->sc_ah; 2019 struct ath_common *common = ath9k_hw_common(ah); 2020 struct ath_buf *bf, *bf_last; 2021 bool puttxbuf = false; 2022 bool edma; 2023 2024 /* 2025 * Insert the frame on the outbound list and 2026 * pass it on to the hardware. 2027 */ 2028 2029 if (list_empty(head)) 2030 return; 2031 2032 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2033 bf = list_first_entry(head, struct ath_buf, list); 2034 bf_last = list_entry(head->prev, struct ath_buf, list); 2035 2036 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2037 txq->axq_qnum, txq->axq_depth); 2038 2039 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2040 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2041 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2042 puttxbuf = true; 2043 } else { 2044 list_splice_tail_init(head, &txq->axq_q); 2045 2046 if (txq->axq_link) { 2047 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2048 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2049 txq->axq_qnum, txq->axq_link, 2050 ito64(bf->bf_daddr), bf->bf_desc); 2051 } else if (!edma) 2052 puttxbuf = true; 2053 2054 txq->axq_link = bf_last->bf_desc; 2055 } 2056 2057 if (puttxbuf) { 2058 TX_STAT_INC(txq->axq_qnum, puttxbuf); 2059 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2060 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2061 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2062 } 2063 2064 if (!edma || sc->tx99_state) { 2065 TX_STAT_INC(txq->axq_qnum, txstart); 2066 ath9k_hw_txstart(ah, txq->axq_qnum); 2067 } 2068 2069 if (!internal) { 2070 while (bf) { 2071 txq->axq_depth++; 2072 if (bf_is_ampdu_not_probing(bf)) 2073 txq->axq_ampdu_depth++; 2074 2075 bf_last = bf->bf_lastbf; 2076 bf = bf_last->bf_next; 2077 bf_last->bf_next = NULL; 2078 } 2079 } 2080 } 2081 2082 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2083 struct ath_atx_tid *tid, struct sk_buff *skb) 2084 { 2085 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2086 struct ath_frame_info *fi = get_frame_info(skb); 2087 struct list_head bf_head; 2088 struct ath_buf *bf = fi->bf; 2089 2090 INIT_LIST_HEAD(&bf_head); 2091 list_add_tail(&bf->list, &bf_head); 2092 bf->bf_state.bf_type = 0; 2093 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2094 bf->bf_state.bf_type = BUF_AMPDU; 2095 ath_tx_addto_baw(sc, tid, bf); 2096 } 2097 2098 bf->bf_next = NULL; 2099 bf->bf_lastbf = bf; 2100 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2101 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2102 TX_STAT_INC(txq->axq_qnum, queued); 2103 } 2104 2105 static void setup_frame_info(struct ieee80211_hw *hw, 2106 struct ieee80211_sta *sta, 2107 struct sk_buff *skb, 2108 int framelen) 2109 { 2110 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2111 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2112 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2113 const struct ieee80211_rate *rate; 2114 struct ath_frame_info *fi = get_frame_info(skb); 2115 struct ath_node *an = NULL; 2116 enum ath9k_key_type keytype; 2117 bool short_preamble = false; 2118 2119 /* 2120 * We check if Short Preamble is needed for the CTS rate by 2121 * checking the BSS's global flag. 2122 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2123 */ 2124 if (tx_info->control.vif && 2125 tx_info->control.vif->bss_conf.use_short_preamble) 2126 short_preamble = true; 2127 2128 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2129 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2130 2131 if (sta) 2132 an = (struct ath_node *) sta->drv_priv; 2133 2134 memset(fi, 0, sizeof(*fi)); 2135 fi->txq = -1; 2136 if (hw_key) 2137 fi->keyix = hw_key->hw_key_idx; 2138 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2139 fi->keyix = an->ps_key; 2140 else 2141 fi->keyix = ATH9K_TXKEYIX_INVALID; 2142 fi->keytype = keytype; 2143 fi->framelen = framelen; 2144 fi->tx_power = MAX_RATE_POWER; 2145 2146 if (!rate) 2147 return; 2148 fi->rtscts_rate = rate->hw_value; 2149 if (short_preamble) 2150 fi->rtscts_rate |= rate->hw_value_short; 2151 } 2152 2153 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2154 { 2155 struct ath_hw *ah = sc->sc_ah; 2156 struct ath9k_channel *curchan = ah->curchan; 2157 2158 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2159 (chainmask == 0x7) && (rate < 0x90)) 2160 return 0x3; 2161 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2162 IS_CCK_RATE(rate)) 2163 return 0x2; 2164 else 2165 return chainmask; 2166 } 2167 2168 /* 2169 * Assign a descriptor (and sequence number if necessary, 2170 * and map buffer for DMA. Frees skb on error 2171 */ 2172 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2173 struct ath_txq *txq, 2174 struct ath_atx_tid *tid, 2175 struct sk_buff *skb) 2176 { 2177 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2178 struct ath_frame_info *fi = get_frame_info(skb); 2179 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2180 struct ath_buf *bf; 2181 int fragno; 2182 u16 seqno; 2183 2184 bf = ath_tx_get_buffer(sc); 2185 if (!bf) { 2186 ath_dbg(common, XMIT, "TX buffers are full\n"); 2187 return NULL; 2188 } 2189 2190 ATH_TXBUF_RESET(bf); 2191 2192 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2193 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2194 seqno = tid->seq_next; 2195 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2196 2197 if (fragno) 2198 hdr->seq_ctrl |= cpu_to_le16(fragno); 2199 2200 if (!ieee80211_has_morefrags(hdr->frame_control)) 2201 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2202 2203 bf->bf_state.seqno = seqno; 2204 } 2205 2206 bf->bf_mpdu = skb; 2207 2208 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2209 skb->len, DMA_TO_DEVICE); 2210 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2211 bf->bf_mpdu = NULL; 2212 bf->bf_buf_addr = 0; 2213 ath_err(ath9k_hw_common(sc->sc_ah), 2214 "dma_mapping_error() on TX\n"); 2215 ath_tx_return_buffer(sc, bf); 2216 return NULL; 2217 } 2218 2219 fi->bf = bf; 2220 2221 return bf; 2222 } 2223 2224 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2225 { 2226 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2227 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2228 struct ieee80211_vif *vif = info->control.vif; 2229 struct ath_vif *avp; 2230 2231 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2232 return; 2233 2234 if (!vif) 2235 return; 2236 2237 avp = (struct ath_vif *)vif->drv_priv; 2238 2239 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2240 avp->seq_no += 0x10; 2241 2242 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2243 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2244 } 2245 2246 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2247 struct ath_tx_control *txctl) 2248 { 2249 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2250 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2251 struct ieee80211_sta *sta = txctl->sta; 2252 struct ieee80211_vif *vif = info->control.vif; 2253 struct ath_vif *avp; 2254 struct ath_softc *sc = hw->priv; 2255 int frmlen = skb->len + FCS_LEN; 2256 int padpos, padsize; 2257 2258 /* NOTE: sta can be NULL according to net/mac80211.h */ 2259 if (sta) 2260 txctl->an = (struct ath_node *)sta->drv_priv; 2261 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2262 avp = (void *)vif->drv_priv; 2263 txctl->an = &avp->mcast_node; 2264 } 2265 2266 if (info->control.hw_key) 2267 frmlen += info->control.hw_key->icv_len; 2268 2269 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2270 2271 if ((vif && vif->type != NL80211_IFTYPE_AP && 2272 vif->type != NL80211_IFTYPE_AP_VLAN) || 2273 !ieee80211_is_data(hdr->frame_control)) 2274 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2275 2276 /* Add the padding after the header if this is not already done */ 2277 padpos = ieee80211_hdrlen(hdr->frame_control); 2278 padsize = padpos & 3; 2279 if (padsize && skb->len > padpos) { 2280 if (skb_headroom(skb) < padsize) 2281 return -ENOMEM; 2282 2283 skb_push(skb, padsize); 2284 memmove(skb->data, skb->data + padsize, padpos); 2285 } 2286 2287 setup_frame_info(hw, sta, skb, frmlen); 2288 return 0; 2289 } 2290 2291 2292 /* Upon failure caller should free skb */ 2293 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2294 struct ath_tx_control *txctl) 2295 { 2296 struct ieee80211_hdr *hdr; 2297 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2298 struct ieee80211_sta *sta = txctl->sta; 2299 struct ieee80211_vif *vif = info->control.vif; 2300 struct ath_frame_info *fi = get_frame_info(skb); 2301 struct ath_vif *avp = NULL; 2302 struct ath_softc *sc = hw->priv; 2303 struct ath_txq *txq = txctl->txq; 2304 struct ath_atx_tid *tid = NULL; 2305 struct ath_buf *bf; 2306 bool queue, skip_uapsd = false, ps_resp; 2307 int q, ret; 2308 2309 if (vif) 2310 avp = (void *)vif->drv_priv; 2311 2312 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) 2313 txctl->force_channel = true; 2314 2315 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2316 2317 ret = ath_tx_prepare(hw, skb, txctl); 2318 if (ret) 2319 return ret; 2320 2321 hdr = (struct ieee80211_hdr *) skb->data; 2322 /* 2323 * At this point, the vif, hw_key and sta pointers in the tx control 2324 * info are no longer valid (overwritten by the ath_frame_info data. 2325 */ 2326 2327 q = skb_get_queue_mapping(skb); 2328 2329 ath_txq_lock(sc, txq); 2330 if (txq == sc->tx.txq_map[q]) { 2331 fi->txq = q; 2332 if (++txq->pending_frames > sc->tx.txq_max_pending[q] && 2333 !txq->stopped) { 2334 if (ath9k_is_chanctx_enabled()) 2335 ieee80211_stop_queue(sc->hw, info->hw_queue); 2336 else 2337 ieee80211_stop_queue(sc->hw, q); 2338 txq->stopped = true; 2339 } 2340 } 2341 2342 queue = ieee80211_is_data_present(hdr->frame_control); 2343 2344 /* Force queueing of all frames that belong to a virtual interface on 2345 * a different channel context, to ensure that they are sent on the 2346 * correct channel. 2347 */ 2348 if (((avp && avp->chanctx != sc->cur_chan) || 2349 sc->cur_chan->stopped) && !txctl->force_channel) { 2350 if (!txctl->an) 2351 txctl->an = &avp->mcast_node; 2352 queue = true; 2353 skip_uapsd = true; 2354 } 2355 2356 if (txctl->an && queue) 2357 tid = ath_get_skb_tid(sc, txctl->an, skb); 2358 2359 if (!skip_uapsd && ps_resp) { 2360 ath_txq_unlock(sc, txq); 2361 txq = sc->tx.uapsdq; 2362 ath_txq_lock(sc, txq); 2363 } else if (txctl->an && queue) { 2364 WARN_ON(tid->ac->txq != txctl->txq); 2365 2366 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 2367 tid->ac->clear_ps_filter = true; 2368 2369 /* 2370 * Add this frame to software queue for scheduling later 2371 * for aggregation. 2372 */ 2373 TX_STAT_INC(txq->axq_qnum, a_queued_sw); 2374 __skb_queue_tail(&tid->buf_q, skb); 2375 if (!txctl->an->sleeping) 2376 ath_tx_queue_tid(sc, txq, tid); 2377 2378 ath_txq_schedule(sc, txq); 2379 goto out; 2380 } 2381 2382 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2383 if (!bf) { 2384 ath_txq_skb_done(sc, txq, skb); 2385 if (txctl->paprd) 2386 dev_kfree_skb_any(skb); 2387 else 2388 ieee80211_free_txskb(sc->hw, skb); 2389 goto out; 2390 } 2391 2392 bf->bf_state.bfs_paprd = txctl->paprd; 2393 2394 if (txctl->paprd) 2395 bf->bf_state.bfs_paprd_timestamp = jiffies; 2396 2397 ath_set_rates(vif, sta, bf); 2398 ath_tx_send_normal(sc, txq, tid, skb); 2399 2400 out: 2401 ath_txq_unlock(sc, txq); 2402 2403 return 0; 2404 } 2405 2406 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2407 struct sk_buff *skb) 2408 { 2409 struct ath_softc *sc = hw->priv; 2410 struct ath_tx_control txctl = { 2411 .txq = sc->beacon.cabq 2412 }; 2413 struct ath_tx_info info = {}; 2414 struct ieee80211_hdr *hdr; 2415 struct ath_buf *bf_tail = NULL; 2416 struct ath_buf *bf; 2417 LIST_HEAD(bf_q); 2418 int duration = 0; 2419 int max_duration; 2420 2421 max_duration = 2422 sc->cur_chan->beacon.beacon_interval * 1000 * 2423 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2424 2425 do { 2426 struct ath_frame_info *fi = get_frame_info(skb); 2427 2428 if (ath_tx_prepare(hw, skb, &txctl)) 2429 break; 2430 2431 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2432 if (!bf) 2433 break; 2434 2435 bf->bf_lastbf = bf; 2436 ath_set_rates(vif, NULL, bf); 2437 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2438 duration += info.rates[0].PktDuration; 2439 if (bf_tail) 2440 bf_tail->bf_next = bf; 2441 2442 list_add_tail(&bf->list, &bf_q); 2443 bf_tail = bf; 2444 skb = NULL; 2445 2446 if (duration > max_duration) 2447 break; 2448 2449 skb = ieee80211_get_buffered_bc(hw, vif); 2450 } while(skb); 2451 2452 if (skb) 2453 ieee80211_free_txskb(hw, skb); 2454 2455 if (list_empty(&bf_q)) 2456 return; 2457 2458 bf = list_first_entry(&bf_q, struct ath_buf, list); 2459 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 2460 2461 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) { 2462 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA; 2463 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 2464 sizeof(*hdr), DMA_TO_DEVICE); 2465 } 2466 2467 ath_txq_lock(sc, txctl.txq); 2468 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2469 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2470 TX_STAT_INC(txctl.txq->axq_qnum, queued); 2471 ath_txq_unlock(sc, txctl.txq); 2472 } 2473 2474 /*****************/ 2475 /* TX Completion */ 2476 /*****************/ 2477 2478 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2479 int tx_flags, struct ath_txq *txq) 2480 { 2481 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2482 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2483 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2484 int padpos, padsize; 2485 unsigned long flags; 2486 2487 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2488 2489 if (sc->sc_ah->caldata) 2490 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2491 2492 if (!(tx_flags & ATH_TX_ERROR)) { 2493 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2494 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2495 else 2496 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2497 } 2498 2499 padpos = ieee80211_hdrlen(hdr->frame_control); 2500 padsize = padpos & 3; 2501 if (padsize && skb->len>padpos+padsize) { 2502 /* 2503 * Remove MAC header padding before giving the frame back to 2504 * mac80211. 2505 */ 2506 memmove(skb->data + padsize, skb->data, padpos); 2507 skb_pull(skb, padsize); 2508 } 2509 2510 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2511 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2512 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2513 ath_dbg(common, PS, 2514 "Going back to sleep after having received TX status (0x%lx)\n", 2515 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2516 PS_WAIT_FOR_CAB | 2517 PS_WAIT_FOR_PSPOLL_DATA | 2518 PS_WAIT_FOR_TX_ACK)); 2519 } 2520 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2521 2522 __skb_queue_tail(&txq->complete_q, skb); 2523 ath_txq_skb_done(sc, txq, skb); 2524 } 2525 2526 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2527 struct ath_txq *txq, struct list_head *bf_q, 2528 struct ath_tx_status *ts, int txok) 2529 { 2530 struct sk_buff *skb = bf->bf_mpdu; 2531 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2532 unsigned long flags; 2533 int tx_flags = 0; 2534 2535 if (!txok) 2536 tx_flags |= ATH_TX_ERROR; 2537 2538 if (ts->ts_status & ATH9K_TXERR_FILT) 2539 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2540 2541 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2542 bf->bf_buf_addr = 0; 2543 if (sc->tx99_state) 2544 goto skip_tx_complete; 2545 2546 if (bf->bf_state.bfs_paprd) { 2547 if (time_after(jiffies, 2548 bf->bf_state.bfs_paprd_timestamp + 2549 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2550 dev_kfree_skb_any(skb); 2551 else 2552 complete(&sc->paprd_complete); 2553 } else { 2554 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2555 ath_tx_complete(sc, skb, tx_flags, txq); 2556 } 2557 skip_tx_complete: 2558 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2559 * accidentally reference it later. 2560 */ 2561 bf->bf_mpdu = NULL; 2562 2563 /* 2564 * Return the list of ath_buf of this mpdu to free queue 2565 */ 2566 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2567 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2568 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2569 } 2570 2571 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2572 struct ath_tx_status *ts, int nframes, int nbad, 2573 int txok) 2574 { 2575 struct sk_buff *skb = bf->bf_mpdu; 2576 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2577 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2578 struct ieee80211_hw *hw = sc->hw; 2579 struct ath_hw *ah = sc->sc_ah; 2580 u8 i, tx_rateindex; 2581 2582 if (txok) 2583 tx_info->status.ack_signal = ts->ts_rssi; 2584 2585 tx_rateindex = ts->ts_rateindex; 2586 WARN_ON(tx_rateindex >= hw->max_rates); 2587 2588 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2589 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2590 2591 BUG_ON(nbad > nframes); 2592 } 2593 tx_info->status.ampdu_len = nframes; 2594 tx_info->status.ampdu_ack_len = nframes - nbad; 2595 2596 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2597 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2598 /* 2599 * If an underrun error is seen assume it as an excessive 2600 * retry only if max frame trigger level has been reached 2601 * (2 KB for single stream, and 4 KB for dual stream). 2602 * Adjust the long retry as if the frame was tried 2603 * hw->max_rate_tries times to affect how rate control updates 2604 * PER for the failed rate. 2605 * In case of congestion on the bus penalizing this type of 2606 * underruns should help hardware actually transmit new frames 2607 * successfully by eventually preferring slower rates. 2608 * This itself should also alleviate congestion on the bus. 2609 */ 2610 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2611 ATH9K_TX_DELIM_UNDERRUN)) && 2612 ieee80211_is_data(hdr->frame_control) && 2613 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2614 tx_info->status.rates[tx_rateindex].count = 2615 hw->max_rate_tries; 2616 } 2617 2618 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2619 tx_info->status.rates[i].count = 0; 2620 tx_info->status.rates[i].idx = -1; 2621 } 2622 2623 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2624 } 2625 2626 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2627 { 2628 struct ath_hw *ah = sc->sc_ah; 2629 struct ath_common *common = ath9k_hw_common(ah); 2630 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2631 struct list_head bf_head; 2632 struct ath_desc *ds; 2633 struct ath_tx_status ts; 2634 int status; 2635 2636 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2637 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2638 txq->axq_link); 2639 2640 ath_txq_lock(sc, txq); 2641 for (;;) { 2642 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2643 break; 2644 2645 if (list_empty(&txq->axq_q)) { 2646 txq->axq_link = NULL; 2647 ath_txq_schedule(sc, txq); 2648 break; 2649 } 2650 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2651 2652 /* 2653 * There is a race condition that a BH gets scheduled 2654 * after sw writes TxE and before hw re-load the last 2655 * descriptor to get the newly chained one. 2656 * Software must keep the last DONE descriptor as a 2657 * holding descriptor - software does so by marking 2658 * it with the STALE flag. 2659 */ 2660 bf_held = NULL; 2661 if (bf->bf_state.stale) { 2662 bf_held = bf; 2663 if (list_is_last(&bf_held->list, &txq->axq_q)) 2664 break; 2665 2666 bf = list_entry(bf_held->list.next, struct ath_buf, 2667 list); 2668 } 2669 2670 lastbf = bf->bf_lastbf; 2671 ds = lastbf->bf_desc; 2672 2673 memset(&ts, 0, sizeof(ts)); 2674 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2675 if (status == -EINPROGRESS) 2676 break; 2677 2678 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2679 2680 /* 2681 * Remove ath_buf's of the same transmit unit from txq, 2682 * however leave the last descriptor back as the holding 2683 * descriptor for hw. 2684 */ 2685 lastbf->bf_state.stale = true; 2686 INIT_LIST_HEAD(&bf_head); 2687 if (!list_is_singular(&lastbf->list)) 2688 list_cut_position(&bf_head, 2689 &txq->axq_q, lastbf->list.prev); 2690 2691 if (bf_held) { 2692 list_del(&bf_held->list); 2693 ath_tx_return_buffer(sc, bf_held); 2694 } 2695 2696 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2697 } 2698 ath_txq_unlock_complete(sc, txq); 2699 } 2700 2701 void ath_tx_tasklet(struct ath_softc *sc) 2702 { 2703 struct ath_hw *ah = sc->sc_ah; 2704 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2705 int i; 2706 2707 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2708 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2709 ath_tx_processq(sc, &sc->tx.txq[i]); 2710 } 2711 } 2712 2713 void ath_tx_edma_tasklet(struct ath_softc *sc) 2714 { 2715 struct ath_tx_status ts; 2716 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2717 struct ath_hw *ah = sc->sc_ah; 2718 struct ath_txq *txq; 2719 struct ath_buf *bf, *lastbf; 2720 struct list_head bf_head; 2721 struct list_head *fifo_list; 2722 int status; 2723 2724 for (;;) { 2725 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2726 break; 2727 2728 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2729 if (status == -EINPROGRESS) 2730 break; 2731 if (status == -EIO) { 2732 ath_dbg(common, XMIT, "Error processing tx status\n"); 2733 break; 2734 } 2735 2736 /* Process beacon completions separately */ 2737 if (ts.qid == sc->beacon.beaconq) { 2738 sc->beacon.tx_processed = true; 2739 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2740 2741 if (ath9k_is_chanctx_enabled()) { 2742 ath_chanctx_event(sc, NULL, 2743 ATH_CHANCTX_EVENT_BEACON_SENT); 2744 } 2745 2746 ath9k_csa_update(sc); 2747 continue; 2748 } 2749 2750 txq = &sc->tx.txq[ts.qid]; 2751 2752 ath_txq_lock(sc, txq); 2753 2754 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2755 2756 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2757 if (list_empty(fifo_list)) { 2758 ath_txq_unlock(sc, txq); 2759 return; 2760 } 2761 2762 bf = list_first_entry(fifo_list, struct ath_buf, list); 2763 if (bf->bf_state.stale) { 2764 list_del(&bf->list); 2765 ath_tx_return_buffer(sc, bf); 2766 bf = list_first_entry(fifo_list, struct ath_buf, list); 2767 } 2768 2769 lastbf = bf->bf_lastbf; 2770 2771 INIT_LIST_HEAD(&bf_head); 2772 if (list_is_last(&lastbf->list, fifo_list)) { 2773 list_splice_tail_init(fifo_list, &bf_head); 2774 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2775 2776 if (!list_empty(&txq->axq_q)) { 2777 struct list_head bf_q; 2778 2779 INIT_LIST_HEAD(&bf_q); 2780 txq->axq_link = NULL; 2781 list_splice_tail_init(&txq->axq_q, &bf_q); 2782 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2783 } 2784 } else { 2785 lastbf->bf_state.stale = true; 2786 if (bf != lastbf) 2787 list_cut_position(&bf_head, fifo_list, 2788 lastbf->list.prev); 2789 } 2790 2791 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2792 ath_txq_unlock_complete(sc, txq); 2793 } 2794 } 2795 2796 /*****************/ 2797 /* Init, Cleanup */ 2798 /*****************/ 2799 2800 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2801 { 2802 struct ath_descdma *dd = &sc->txsdma; 2803 u8 txs_len = sc->sc_ah->caps.txs_len; 2804 2805 dd->dd_desc_len = size * txs_len; 2806 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2807 &dd->dd_desc_paddr, GFP_KERNEL); 2808 if (!dd->dd_desc) 2809 return -ENOMEM; 2810 2811 return 0; 2812 } 2813 2814 static int ath_tx_edma_init(struct ath_softc *sc) 2815 { 2816 int err; 2817 2818 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2819 if (!err) 2820 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2821 sc->txsdma.dd_desc_paddr, 2822 ATH_TXSTATUS_RING_SIZE); 2823 2824 return err; 2825 } 2826 2827 int ath_tx_init(struct ath_softc *sc, int nbufs) 2828 { 2829 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2830 int error = 0; 2831 2832 spin_lock_init(&sc->tx.txbuflock); 2833 2834 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2835 "tx", nbufs, 1, 1); 2836 if (error != 0) { 2837 ath_err(common, 2838 "Failed to allocate tx descriptors: %d\n", error); 2839 return error; 2840 } 2841 2842 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2843 "beacon", ATH_BCBUF, 1, 1); 2844 if (error != 0) { 2845 ath_err(common, 2846 "Failed to allocate beacon descriptors: %d\n", error); 2847 return error; 2848 } 2849 2850 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2851 2852 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2853 error = ath_tx_edma_init(sc); 2854 2855 return error; 2856 } 2857 2858 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2859 { 2860 struct ath_atx_tid *tid; 2861 struct ath_atx_ac *ac; 2862 int tidno, acno; 2863 2864 for (tidno = 0, tid = &an->tid[tidno]; 2865 tidno < IEEE80211_NUM_TIDS; 2866 tidno++, tid++) { 2867 tid->an = an; 2868 tid->tidno = tidno; 2869 tid->seq_start = tid->seq_next = 0; 2870 tid->baw_size = WME_MAX_BA; 2871 tid->baw_head = tid->baw_tail = 0; 2872 tid->sched = false; 2873 tid->active = false; 2874 __skb_queue_head_init(&tid->buf_q); 2875 __skb_queue_head_init(&tid->retry_q); 2876 acno = TID_TO_WME_AC(tidno); 2877 tid->ac = &an->ac[acno]; 2878 } 2879 2880 for (acno = 0, ac = &an->ac[acno]; 2881 acno < IEEE80211_NUM_ACS; acno++, ac++) { 2882 ac->sched = false; 2883 ac->clear_ps_filter = true; 2884 ac->txq = sc->tx.txq_map[acno]; 2885 INIT_LIST_HEAD(&ac->tid_q); 2886 } 2887 } 2888 2889 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2890 { 2891 struct ath_atx_ac *ac; 2892 struct ath_atx_tid *tid; 2893 struct ath_txq *txq; 2894 int tidno; 2895 2896 for (tidno = 0, tid = &an->tid[tidno]; 2897 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) { 2898 2899 ac = tid->ac; 2900 txq = ac->txq; 2901 2902 ath_txq_lock(sc, txq); 2903 2904 if (tid->sched) { 2905 list_del(&tid->list); 2906 tid->sched = false; 2907 } 2908 2909 if (ac->sched) { 2910 list_del(&ac->list); 2911 tid->ac->sched = false; 2912 } 2913 2914 ath_tid_drain(sc, txq, tid); 2915 tid->active = false; 2916 2917 ath_txq_unlock(sc, txq); 2918 } 2919 } 2920 2921 #ifdef CONFIG_ATH9K_TX99 2922 2923 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2924 struct ath_tx_control *txctl) 2925 { 2926 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2927 struct ath_frame_info *fi = get_frame_info(skb); 2928 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2929 struct ath_buf *bf; 2930 int padpos, padsize; 2931 2932 padpos = ieee80211_hdrlen(hdr->frame_control); 2933 padsize = padpos & 3; 2934 2935 if (padsize && skb->len > padpos) { 2936 if (skb_headroom(skb) < padsize) { 2937 ath_dbg(common, XMIT, 2938 "tx99 padding failed\n"); 2939 return -EINVAL; 2940 } 2941 2942 skb_push(skb, padsize); 2943 memmove(skb->data, skb->data + padsize, padpos); 2944 } 2945 2946 fi->keyix = ATH9K_TXKEYIX_INVALID; 2947 fi->framelen = skb->len + FCS_LEN; 2948 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2949 2950 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2951 if (!bf) { 2952 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2953 return -EINVAL; 2954 } 2955 2956 ath_set_rates(sc->tx99_vif, NULL, bf); 2957 2958 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2959 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2960 2961 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2962 2963 return 0; 2964 } 2965 2966 #endif /* CONFIG_ATH9K_TX99 */ 2967