1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 /* Shifts in ar5008_phy.c and ar9003_phy.c are equal for all revisions */ 38 #define ATH9K_PWRTBL_11NA_OFDM_SHIFT 0 39 #define ATH9K_PWRTBL_11NG_OFDM_SHIFT 4 40 #define ATH9K_PWRTBL_11NA_HT_SHIFT 8 41 #define ATH9K_PWRTBL_11NG_HT_SHIFT 12 42 43 44 static u16 bits_per_symbol[][2] = { 45 /* 20MHz 40MHz */ 46 { 26, 54 }, /* 0: BPSK */ 47 { 52, 108 }, /* 1: QPSK 1/2 */ 48 { 78, 162 }, /* 2: QPSK 3/4 */ 49 { 104, 216 }, /* 3: 16-QAM 1/2 */ 50 { 156, 324 }, /* 4: 16-QAM 3/4 */ 51 { 208, 432 }, /* 5: 64-QAM 2/3 */ 52 { 234, 486 }, /* 6: 64-QAM 3/4 */ 53 { 260, 540 }, /* 7: 64-QAM 5/6 */ 54 }; 55 56 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 57 struct ath_atx_tid *tid, struct sk_buff *skb); 58 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 59 int tx_flags, struct ath_txq *txq, 60 struct ieee80211_sta *sta); 61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_txq *txq, struct list_head *bf_q, 63 struct ieee80211_sta *sta, 64 struct ath_tx_status *ts, int txok); 65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 66 struct list_head *head, bool internal); 67 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 68 struct ath_tx_status *ts, int nframes, int nbad, 69 int txok); 70 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 71 struct ath_buf *bf); 72 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 73 struct ath_txq *txq, 74 struct ath_atx_tid *tid, 75 struct sk_buff *skb); 76 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 77 struct ath_tx_control *txctl); 78 79 enum { 80 MCS_HT20, 81 MCS_HT20_SGI, 82 MCS_HT40, 83 MCS_HT40_SGI, 84 }; 85 86 /*********************/ 87 /* Aggregation logic */ 88 /*********************/ 89 90 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 91 { 92 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 93 struct ieee80211_sta *sta = info->status.status_driver_data[0]; 94 95 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | 96 IEEE80211_TX_STATUS_EOSP)) { 97 ieee80211_tx_status(hw, skb); 98 return; 99 } 100 101 if (sta) 102 ieee80211_tx_status_noskb(hw, sta, info); 103 104 dev_kfree_skb(skb); 105 } 106 107 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 108 __releases(&txq->axq_lock) 109 { 110 struct ieee80211_hw *hw = sc->hw; 111 struct sk_buff_head q; 112 struct sk_buff *skb; 113 114 __skb_queue_head_init(&q); 115 skb_queue_splice_init(&txq->complete_q, &q); 116 spin_unlock_bh(&txq->axq_lock); 117 118 while ((skb = __skb_dequeue(&q))) 119 ath_tx_status(hw, skb); 120 } 121 122 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 123 { 124 struct ieee80211_txq *queue = 125 container_of((void *)tid, struct ieee80211_txq, drv_priv); 126 127 ieee80211_schedule_txq(sc->hw, queue); 128 } 129 130 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue) 131 { 132 struct ath_softc *sc = hw->priv; 133 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 134 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv; 135 struct ath_txq *txq = tid->txq; 136 137 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n", 138 queue->sta ? queue->sta->addr : queue->vif->addr, 139 tid->tidno); 140 141 ath_txq_lock(sc, txq); 142 ath_txq_schedule(sc, txq); 143 ath_txq_unlock(sc, txq); 144 } 145 146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 147 { 148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 149 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 150 sizeof(tx_info->status.status_driver_data)); 151 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0]; 152 } 153 154 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 155 { 156 if (!tid->an->sta) 157 return; 158 159 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 160 seqno << IEEE80211_SEQ_SEQ_SHIFT); 161 } 162 163 static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf, 164 struct ieee80211_tx_info *tx_info) 165 { 166 struct ieee80211_sta_rates *ratetbl; 167 u8 i; 168 169 if (!sta) 170 return false; 171 172 ratetbl = rcu_dereference(sta->rates); 173 if (!ratetbl) 174 return false; 175 176 if (tx_info->control.rates[0].idx < 0 || 177 tx_info->control.rates[0].count == 0) 178 { 179 i = 0; 180 } else { 181 bf->rates[0] = tx_info->control.rates[0]; 182 i = 1; 183 } 184 185 for ( ; i < IEEE80211_TX_MAX_RATES; i++) { 186 bf->rates[i].idx = ratetbl->rate[i].idx; 187 bf->rates[i].flags = ratetbl->rate[i].flags; 188 if (tx_info->control.use_rts) 189 bf->rates[i].count = ratetbl->rate[i].count_rts; 190 else if (tx_info->control.use_cts_prot) 191 bf->rates[i].count = ratetbl->rate[i].count_cts; 192 else 193 bf->rates[i].count = ratetbl->rate[i].count; 194 } 195 196 return true; 197 } 198 199 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 200 struct ath_buf *bf) 201 { 202 struct ieee80211_tx_info *tx_info; 203 204 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 205 206 if (!ath_merge_ratetbl(sta, bf, tx_info)) 207 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 208 ARRAY_SIZE(bf->rates)); 209 } 210 211 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq, 212 struct sk_buff *skb) 213 { 214 struct ath_frame_info *fi = get_frame_info(skb); 215 int q = fi->txq; 216 217 if (q < 0) 218 return; 219 220 txq = sc->tx.txq_map[q]; 221 if (WARN_ON(--txq->pending_frames < 0)) 222 txq->pending_frames = 0; 223 224 } 225 226 static struct ath_atx_tid * 227 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb) 228 { 229 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 230 return ATH_AN_2_TID(an, tidno); 231 } 232 233 static int 234 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf) 235 { 236 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv); 237 struct ath_softc *sc = tid->an->sc; 238 struct ieee80211_hw *hw = sc->hw; 239 struct ath_tx_control txctl = { 240 .txq = tid->txq, 241 .sta = tid->an->sta, 242 }; 243 struct sk_buff *skb; 244 struct ath_frame_info *fi; 245 int q, ret; 246 247 skb = ieee80211_tx_dequeue(hw, txq); 248 if (!skb) 249 return -ENOENT; 250 251 ret = ath_tx_prepare(hw, skb, &txctl); 252 if (ret) { 253 ieee80211_free_txskb(hw, skb); 254 return ret; 255 } 256 257 q = skb_get_queue_mapping(skb); 258 if (tid->txq == sc->tx.txq_map[q]) { 259 fi = get_frame_info(skb); 260 fi->txq = q; 261 ++tid->txq->pending_frames; 262 } 263 264 *skbuf = skb; 265 return 0; 266 } 267 268 static int ath_tid_dequeue(struct ath_atx_tid *tid, 269 struct sk_buff **skb) 270 { 271 int ret = 0; 272 *skb = __skb_dequeue(&tid->retry_q); 273 if (!*skb) 274 ret = ath_tid_pull(tid, skb); 275 276 return ret; 277 } 278 279 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 280 { 281 struct ath_txq *txq = tid->txq; 282 struct sk_buff *skb; 283 struct ath_buf *bf; 284 struct list_head bf_head; 285 struct ath_tx_status ts; 286 struct ath_frame_info *fi; 287 bool sendbar = false; 288 289 INIT_LIST_HEAD(&bf_head); 290 291 memset(&ts, 0, sizeof(ts)); 292 293 while ((skb = __skb_dequeue(&tid->retry_q))) { 294 fi = get_frame_info(skb); 295 bf = fi->bf; 296 if (!bf) { 297 ath_txq_skb_done(sc, txq, skb); 298 ieee80211_free_txskb(sc->hw, skb); 299 continue; 300 } 301 302 if (fi->baw_tracked) { 303 ath_tx_update_baw(sc, tid, bf); 304 sendbar = true; 305 } 306 307 list_add_tail(&bf->list, &bf_head); 308 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 309 } 310 311 if (sendbar) { 312 ath_txq_unlock(sc, txq); 313 ath_send_bar(tid, tid->seq_start); 314 ath_txq_lock(sc, txq); 315 } 316 } 317 318 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 319 struct ath_buf *bf) 320 { 321 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 322 u16 seqno = bf->bf_state.seqno; 323 int index, cindex; 324 325 if (!fi->baw_tracked) 326 return; 327 328 index = ATH_BA_INDEX(tid->seq_start, seqno); 329 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 330 331 __clear_bit(cindex, tid->tx_buf); 332 333 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 334 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 335 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 336 if (tid->bar_index >= 0) 337 tid->bar_index--; 338 } 339 } 340 341 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 342 struct ath_buf *bf) 343 { 344 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 345 u16 seqno = bf->bf_state.seqno; 346 int index, cindex; 347 348 if (fi->baw_tracked) 349 return; 350 351 index = ATH_BA_INDEX(tid->seq_start, seqno); 352 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 353 __set_bit(cindex, tid->tx_buf); 354 fi->baw_tracked = 1; 355 356 if (index >= ((tid->baw_tail - tid->baw_head) & 357 (ATH_TID_MAX_BUFS - 1))) { 358 tid->baw_tail = cindex; 359 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 360 } 361 } 362 363 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 364 struct ath_atx_tid *tid) 365 366 { 367 struct sk_buff *skb; 368 struct ath_buf *bf; 369 struct list_head bf_head; 370 struct ath_tx_status ts; 371 struct ath_frame_info *fi; 372 int ret; 373 374 memset(&ts, 0, sizeof(ts)); 375 INIT_LIST_HEAD(&bf_head); 376 377 while ((ret = ath_tid_dequeue(tid, &skb)) == 0) { 378 fi = get_frame_info(skb); 379 bf = fi->bf; 380 381 if (!bf) { 382 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); 383 continue; 384 } 385 386 list_add_tail(&bf->list, &bf_head); 387 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 388 } 389 } 390 391 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 392 struct sk_buff *skb, int count) 393 { 394 struct ath_frame_info *fi = get_frame_info(skb); 395 struct ath_buf *bf = fi->bf; 396 struct ieee80211_hdr *hdr; 397 int prev = fi->retries; 398 399 TX_STAT_INC(sc, txq->axq_qnum, a_retries); 400 fi->retries += count; 401 402 if (prev > 0) 403 return; 404 405 hdr = (struct ieee80211_hdr *)skb->data; 406 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 407 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 408 sizeof(*hdr), DMA_TO_DEVICE); 409 } 410 411 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 412 { 413 struct ath_buf *bf = NULL; 414 415 spin_lock_bh(&sc->tx.txbuflock); 416 417 if (unlikely(list_empty(&sc->tx.txbuf))) { 418 spin_unlock_bh(&sc->tx.txbuflock); 419 return NULL; 420 } 421 422 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 423 list_del(&bf->list); 424 425 spin_unlock_bh(&sc->tx.txbuflock); 426 427 return bf; 428 } 429 430 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 431 { 432 spin_lock_bh(&sc->tx.txbuflock); 433 list_add_tail(&bf->list, &sc->tx.txbuf); 434 spin_unlock_bh(&sc->tx.txbuflock); 435 } 436 437 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 438 { 439 struct ath_buf *tbf; 440 441 tbf = ath_tx_get_buffer(sc); 442 if (WARN_ON(!tbf)) 443 return NULL; 444 445 ATH_TXBUF_RESET(tbf); 446 447 tbf->bf_mpdu = bf->bf_mpdu; 448 tbf->bf_buf_addr = bf->bf_buf_addr; 449 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 450 tbf->bf_state = bf->bf_state; 451 tbf->bf_state.stale = false; 452 453 return tbf; 454 } 455 456 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 457 struct ath_tx_status *ts, int txok, 458 int *nframes, int *nbad) 459 { 460 u16 seq_st = 0; 461 u32 ba[WME_BA_BMP_SIZE >> 5]; 462 int ba_index; 463 int isaggr = 0; 464 465 *nbad = 0; 466 *nframes = 0; 467 468 isaggr = bf_isaggr(bf); 469 if (isaggr) { 470 seq_st = ts->ts_seqnum; 471 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 472 } 473 474 while (bf) { 475 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 476 477 (*nframes)++; 478 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 479 (*nbad)++; 480 481 bf = bf->bf_next; 482 } 483 } 484 485 486 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 487 struct ath_buf *bf, struct list_head *bf_q, 488 struct ieee80211_sta *sta, 489 struct ath_atx_tid *tid, 490 struct ath_tx_status *ts, int txok) 491 { 492 struct ath_node *an = NULL; 493 struct sk_buff *skb; 494 struct ieee80211_tx_info *tx_info; 495 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 496 struct list_head bf_head; 497 struct sk_buff_head bf_pending; 498 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 499 u32 ba[WME_BA_BMP_SIZE >> 5]; 500 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 501 bool rc_update = true, isba; 502 struct ieee80211_tx_rate rates[4]; 503 struct ath_frame_info *fi; 504 int nframes; 505 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 506 int i, retries; 507 int bar_index = -1; 508 509 skb = bf->bf_mpdu; 510 tx_info = IEEE80211_SKB_CB(skb); 511 512 memcpy(rates, bf->rates, sizeof(rates)); 513 514 retries = ts->ts_longretry + 1; 515 for (i = 0; i < ts->ts_rateindex; i++) 516 retries += rates[i].count; 517 518 if (!sta) { 519 INIT_LIST_HEAD(&bf_head); 520 while (bf) { 521 bf_next = bf->bf_next; 522 523 if (!bf->bf_state.stale || bf_next != NULL) 524 list_move_tail(&bf->list, &bf_head); 525 526 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); 527 528 bf = bf_next; 529 } 530 return; 531 } 532 533 an = (struct ath_node *)sta->drv_priv; 534 seq_first = tid->seq_start; 535 isba = ts->ts_flags & ATH9K_TX_BA; 536 537 /* 538 * The hardware occasionally sends a tx status for the wrong TID. 539 * In this case, the BA status cannot be considered valid and all 540 * subframes need to be retransmitted 541 * 542 * Only BlockAcks have a TID and therefore normal Acks cannot be 543 * checked 544 */ 545 if (isba && tid->tidno != ts->tid) 546 txok = false; 547 548 isaggr = bf_isaggr(bf); 549 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 550 551 if (isaggr && txok) { 552 if (ts->ts_flags & ATH9K_TX_BA) { 553 seq_st = ts->ts_seqnum; 554 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 555 } else { 556 /* 557 * AR5416 can become deaf/mute when BA 558 * issue happens. Chip needs to be reset. 559 * But AP code may have sychronization issues 560 * when perform internal reset in this routine. 561 * Only enable reset in STA mode for now. 562 */ 563 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 564 needreset = 1; 565 } 566 } 567 568 __skb_queue_head_init(&bf_pending); 569 570 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 571 while (bf) { 572 u16 seqno = bf->bf_state.seqno; 573 574 txfail = txpending = sendbar = 0; 575 bf_next = bf->bf_next; 576 577 skb = bf->bf_mpdu; 578 tx_info = IEEE80211_SKB_CB(skb); 579 fi = get_frame_info(skb); 580 581 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 582 !tid->active) { 583 /* 584 * Outside of the current BlockAck window, 585 * maybe part of a previous session 586 */ 587 txfail = 1; 588 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 589 /* transmit completion, subframe is 590 * acked by block ack */ 591 acked_cnt++; 592 } else if (!isaggr && txok) { 593 /* transmit completion */ 594 acked_cnt++; 595 } else if (flush) { 596 txpending = 1; 597 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 598 if (txok || !an->sleeping) 599 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 600 retries); 601 602 txpending = 1; 603 } else { 604 txfail = 1; 605 txfail_cnt++; 606 bar_index = max_t(int, bar_index, 607 ATH_BA_INDEX(seq_first, seqno)); 608 } 609 610 /* 611 * Make sure the last desc is reclaimed if it 612 * not a holding desc. 613 */ 614 INIT_LIST_HEAD(&bf_head); 615 if (bf_next != NULL || !bf_last->bf_state.stale) 616 list_move_tail(&bf->list, &bf_head); 617 618 if (!txpending) { 619 /* 620 * complete the acked-ones/xretried ones; update 621 * block-ack window 622 */ 623 ath_tx_update_baw(sc, tid, bf); 624 625 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 626 memcpy(tx_info->control.rates, rates, sizeof(rates)); 627 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 628 rc_update = false; 629 if (bf == bf->bf_lastbf) 630 ath_dynack_sample_tx_ts(sc->sc_ah, 631 bf->bf_mpdu, 632 ts, sta); 633 } 634 635 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, 636 !txfail); 637 } else { 638 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 639 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 640 ieee80211_sta_eosp(sta); 641 } 642 /* retry the un-acked ones */ 643 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 644 struct ath_buf *tbf; 645 646 tbf = ath_clone_txbuf(sc, bf_last); 647 /* 648 * Update tx baw and complete the 649 * frame with failed status if we 650 * run out of tx buf. 651 */ 652 if (!tbf) { 653 ath_tx_update_baw(sc, tid, bf); 654 655 ath_tx_complete_buf(sc, bf, txq, 656 &bf_head, NULL, ts, 657 0); 658 bar_index = max_t(int, bar_index, 659 ATH_BA_INDEX(seq_first, seqno)); 660 break; 661 } 662 663 fi->bf = tbf; 664 } 665 666 /* 667 * Put this buffer to the temporary pending 668 * queue to retain ordering 669 */ 670 __skb_queue_tail(&bf_pending, skb); 671 } 672 673 bf = bf_next; 674 } 675 676 /* prepend un-acked frames to the beginning of the pending frame queue */ 677 if (!skb_queue_empty(&bf_pending)) { 678 if (an->sleeping) 679 ieee80211_sta_set_buffered(sta, tid->tidno, true); 680 681 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 682 if (!an->sleeping) { 683 ath_tx_queue_tid(sc, tid); 684 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 685 tid->clear_ps_filter = true; 686 } 687 } 688 689 if (bar_index >= 0) { 690 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 691 692 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 693 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 694 695 ath_txq_unlock(sc, txq); 696 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 697 ath_txq_lock(sc, txq); 698 } 699 700 if (needreset) 701 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 702 } 703 704 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 705 { 706 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 707 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 708 } 709 710 static void ath_tx_count_airtime(struct ath_softc *sc, 711 struct ieee80211_sta *sta, 712 struct ath_buf *bf, 713 struct ath_tx_status *ts, 714 u8 tid) 715 { 716 u32 airtime = 0; 717 int i; 718 719 airtime += ts->duration * (ts->ts_longretry + 1); 720 for(i = 0; i < ts->ts_rateindex; i++) { 721 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i); 722 airtime += rate_dur * bf->rates[i].count; 723 } 724 725 ieee80211_sta_register_airtime(sta, tid, airtime, 0); 726 } 727 728 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 729 struct ath_tx_status *ts, struct ath_buf *bf, 730 struct list_head *bf_head) 731 { 732 struct ieee80211_hw *hw = sc->hw; 733 struct ieee80211_tx_info *info; 734 struct ieee80211_sta *sta; 735 struct ieee80211_hdr *hdr; 736 struct ath_atx_tid *tid = NULL; 737 bool txok, flush; 738 739 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 740 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 741 txq->axq_tx_inprogress = false; 742 743 txq->axq_depth--; 744 if (bf_is_ampdu_not_probing(bf)) 745 txq->axq_ampdu_depth--; 746 747 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 748 ts->ts_rateindex); 749 750 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 751 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 752 if (sta) { 753 struct ath_node *an = (struct ath_node *)sta->drv_priv; 754 tid = ath_get_skb_tid(sc, an, bf->bf_mpdu); 755 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno); 756 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 757 tid->clear_ps_filter = true; 758 } 759 760 if (!bf_isampdu(bf)) { 761 if (!flush) { 762 info = IEEE80211_SKB_CB(bf->bf_mpdu); 763 memcpy(info->control.rates, bf->rates, 764 sizeof(info->control.rates)); 765 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 766 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts, 767 sta); 768 } 769 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); 770 } else 771 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); 772 773 if (!flush) 774 ath_txq_schedule(sc, txq); 775 } 776 777 static bool ath_lookup_legacy(struct ath_buf *bf) 778 { 779 struct sk_buff *skb; 780 struct ieee80211_tx_info *tx_info; 781 struct ieee80211_tx_rate *rates; 782 int i; 783 784 skb = bf->bf_mpdu; 785 tx_info = IEEE80211_SKB_CB(skb); 786 rates = tx_info->control.rates; 787 788 for (i = 0; i < 4; i++) { 789 if (!rates[i].count || rates[i].idx < 0) 790 break; 791 792 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 793 return true; 794 } 795 796 return false; 797 } 798 799 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 800 struct ath_atx_tid *tid) 801 { 802 struct sk_buff *skb; 803 struct ieee80211_tx_info *tx_info; 804 struct ieee80211_tx_rate *rates; 805 u32 max_4ms_framelen, frmlen; 806 u16 aggr_limit, bt_aggr_limit, legacy = 0; 807 int q = tid->txq->mac80211_qnum; 808 int i; 809 810 skb = bf->bf_mpdu; 811 tx_info = IEEE80211_SKB_CB(skb); 812 rates = bf->rates; 813 814 /* 815 * Find the lowest frame length among the rate series that will have a 816 * 4ms (or TXOP limited) transmit duration. 817 */ 818 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 819 820 for (i = 0; i < 4; i++) { 821 int modeidx; 822 823 if (!rates[i].count) 824 continue; 825 826 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 827 legacy = 1; 828 break; 829 } 830 831 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 832 modeidx = MCS_HT40; 833 else 834 modeidx = MCS_HT20; 835 836 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 837 modeidx++; 838 839 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 840 max_4ms_framelen = min(max_4ms_framelen, frmlen); 841 } 842 843 /* 844 * limit aggregate size by the minimum rate if rate selected is 845 * not a probe rate, if rate selected is a probe rate then 846 * avoid aggregation of this packet. 847 */ 848 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 849 return 0; 850 851 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 852 853 /* 854 * Override the default aggregation limit for BTCOEX. 855 */ 856 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 857 if (bt_aggr_limit) 858 aggr_limit = bt_aggr_limit; 859 860 if (tid->an->maxampdu) 861 aggr_limit = min(aggr_limit, tid->an->maxampdu); 862 863 return aggr_limit; 864 } 865 866 /* 867 * Returns the number of delimiters to be added to 868 * meet the minimum required mpdudensity. 869 */ 870 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 871 struct ath_buf *bf, u16 frmlen, 872 bool first_subfrm) 873 { 874 #define FIRST_DESC_NDELIMS 60 875 u32 nsymbits, nsymbols; 876 u16 minlen; 877 u8 flags, rix; 878 int width, streams, half_gi, ndelim, mindelim; 879 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 880 881 /* Select standard number of delimiters based on frame length alone */ 882 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 883 884 /* 885 * If encryption enabled, hardware requires some more padding between 886 * subframes. 887 * TODO - this could be improved to be dependent on the rate. 888 * The hardware can keep up at lower rates, but not higher rates 889 */ 890 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 891 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 892 ndelim += ATH_AGGR_ENCRYPTDELIM; 893 894 /* 895 * Add delimiter when using RTS/CTS with aggregation 896 * and non enterprise AR9003 card 897 */ 898 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 899 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 900 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 901 902 /* 903 * Convert desired mpdu density from microeconds to bytes based 904 * on highest rate in rate series (i.e. first rate) to determine 905 * required minimum length for subframe. Take into account 906 * whether high rate is 20 or 40Mhz and half or full GI. 907 * 908 * If there is no mpdu density restriction, no further calculation 909 * is needed. 910 */ 911 912 if (tid->an->mpdudensity == 0) 913 return ndelim; 914 915 rix = bf->rates[0].idx; 916 flags = bf->rates[0].flags; 917 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 918 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 919 920 if (half_gi) 921 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 922 else 923 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 924 925 if (nsymbols == 0) 926 nsymbols = 1; 927 928 streams = HT_RC_2_STREAMS(rix); 929 nsymbits = bits_per_symbol[rix % 8][width] * streams; 930 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 931 932 if (frmlen < minlen) { 933 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 934 ndelim = max(mindelim, ndelim); 935 } 936 937 return ndelim; 938 } 939 940 static int 941 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 942 struct ath_atx_tid *tid, struct ath_buf **buf) 943 { 944 struct ieee80211_tx_info *tx_info; 945 struct ath_frame_info *fi; 946 struct ath_buf *bf; 947 struct sk_buff *skb, *first_skb = NULL; 948 u16 seqno; 949 int ret; 950 951 while (1) { 952 ret = ath_tid_dequeue(tid, &skb); 953 if (ret < 0) 954 return ret; 955 956 fi = get_frame_info(skb); 957 bf = fi->bf; 958 if (!fi->bf) 959 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 960 else 961 bf->bf_state.stale = false; 962 963 if (!bf) { 964 ath_txq_skb_done(sc, txq, skb); 965 ieee80211_free_txskb(sc->hw, skb); 966 continue; 967 } 968 969 bf->bf_next = NULL; 970 bf->bf_lastbf = bf; 971 972 tx_info = IEEE80211_SKB_CB(skb); 973 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT | 974 IEEE80211_TX_STATUS_EOSP); 975 976 /* 977 * No aggregation session is running, but there may be frames 978 * from a previous session or a failed attempt in the queue. 979 * Send them out as normal data frames 980 */ 981 if (!tid->active) 982 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 983 984 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 985 bf->bf_state.bf_type = 0; 986 break; 987 } 988 989 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 990 seqno = bf->bf_state.seqno; 991 992 /* do not step over block-ack window */ 993 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 994 __skb_queue_tail(&tid->retry_q, skb); 995 996 /* If there are other skbs in the retry q, they are 997 * probably within the BAW, so loop immediately to get 998 * one of them. Otherwise the queue can get stuck. */ 999 if (!skb_queue_is_first(&tid->retry_q, skb) && 1000 !WARN_ON(skb == first_skb)) { 1001 if(!first_skb) /* infinite loop prevention */ 1002 first_skb = skb; 1003 continue; 1004 } 1005 return -EINPROGRESS; 1006 } 1007 1008 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 1009 struct ath_tx_status ts = {}; 1010 struct list_head bf_head; 1011 1012 INIT_LIST_HEAD(&bf_head); 1013 list_add(&bf->list, &bf_head); 1014 ath_tx_update_baw(sc, tid, bf); 1015 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 1016 continue; 1017 } 1018 1019 if (bf_isampdu(bf)) 1020 ath_tx_addto_baw(sc, tid, bf); 1021 1022 break; 1023 } 1024 1025 *buf = bf; 1026 return 0; 1027 } 1028 1029 static int 1030 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 1031 struct ath_atx_tid *tid, struct list_head *bf_q, 1032 struct ath_buf *bf_first) 1033 { 1034 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 1035 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1036 int nframes = 0, ndelim, ret; 1037 u16 aggr_limit = 0, al = 0, bpad = 0, 1038 al_delta, h_baw = tid->baw_size / 2; 1039 struct ieee80211_tx_info *tx_info; 1040 struct ath_frame_info *fi; 1041 struct sk_buff *skb; 1042 1043 1044 bf = bf_first; 1045 aggr_limit = ath_lookup_rate(sc, bf, tid); 1046 1047 while (bf) 1048 { 1049 skb = bf->bf_mpdu; 1050 fi = get_frame_info(skb); 1051 1052 /* do not exceed aggregation limit */ 1053 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 1054 if (nframes) { 1055 if (aggr_limit < al + bpad + al_delta || 1056 ath_lookup_legacy(bf) || nframes >= h_baw) 1057 goto stop; 1058 1059 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1060 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 1061 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 1062 goto stop; 1063 } 1064 1065 /* add padding for previous frame to aggregation length */ 1066 al += bpad + al_delta; 1067 1068 /* 1069 * Get the delimiters needed to meet the MPDU 1070 * density for this node. 1071 */ 1072 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 1073 !nframes); 1074 bpad = PADBYTES(al_delta) + (ndelim << 2); 1075 1076 nframes++; 1077 bf->bf_next = NULL; 1078 1079 /* link buffers of this frame to the aggregate */ 1080 bf->bf_state.ndelim = ndelim; 1081 1082 list_add_tail(&bf->list, bf_q); 1083 if (bf_prev) 1084 bf_prev->bf_next = bf; 1085 1086 bf_prev = bf; 1087 1088 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1089 if (ret < 0) 1090 break; 1091 } 1092 goto finish; 1093 stop: 1094 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1095 finish: 1096 bf = bf_first; 1097 bf->bf_lastbf = bf_prev; 1098 1099 if (bf == bf_prev) { 1100 al = get_frame_info(bf->bf_mpdu)->framelen; 1101 bf->bf_state.bf_type = BUF_AMPDU; 1102 } else { 1103 TX_STAT_INC(sc, txq->axq_qnum, a_aggr); 1104 } 1105 1106 return al; 1107 #undef PADBYTES 1108 } 1109 1110 /* 1111 * rix - rate index 1112 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1113 * width - 0 for 20 MHz, 1 for 40 MHz 1114 * half_gi - to use 4us v/s 3.6 us for symbol time 1115 */ 1116 u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 1117 int width, int half_gi, bool shortPreamble) 1118 { 1119 u32 nbits, nsymbits, duration, nsymbols; 1120 int streams; 1121 1122 /* find number of symbols: PLCP + data */ 1123 streams = HT_RC_2_STREAMS(rix); 1124 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1125 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1126 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1127 1128 if (!half_gi) 1129 duration = SYMBOL_TIME(nsymbols); 1130 else 1131 duration = SYMBOL_TIME_HALFGI(nsymbols); 1132 1133 /* addup duration for legacy/ht training and signal fields */ 1134 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1135 1136 return duration; 1137 } 1138 1139 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1140 { 1141 int streams = HT_RC_2_STREAMS(mcs); 1142 int symbols, bits; 1143 int bytes = 0; 1144 1145 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1146 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1147 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1148 bits -= OFDM_PLCP_BITS; 1149 bytes = bits / 8; 1150 if (bytes > 65532) 1151 bytes = 65532; 1152 1153 return bytes; 1154 } 1155 1156 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1157 { 1158 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1159 int mcs; 1160 1161 /* 4ms is the default (and maximum) duration */ 1162 if (!txop || txop > 4096) 1163 txop = 4096; 1164 1165 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1166 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1167 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1168 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1169 for (mcs = 0; mcs < 32; mcs++) { 1170 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1171 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1172 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1173 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1174 } 1175 } 1176 1177 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1178 u8 rateidx, bool is_40, bool is_cck, bool is_mcs) 1179 { 1180 u8 max_power; 1181 struct sk_buff *skb; 1182 struct ath_frame_info *fi; 1183 struct ieee80211_tx_info *info; 1184 struct ath_hw *ah = sc->sc_ah; 1185 bool is_2ghz, is_5ghz, use_stbc; 1186 1187 if (sc->tx99_state || !ah->tpc_enabled) 1188 return MAX_RATE_POWER; 1189 1190 skb = bf->bf_mpdu; 1191 fi = get_frame_info(skb); 1192 info = IEEE80211_SKB_CB(skb); 1193 1194 is_2ghz = info->band == NL80211_BAND_2GHZ; 1195 is_5ghz = info->band == NL80211_BAND_5GHZ; 1196 use_stbc = is_mcs && rateidx < 8 && (info->flags & 1197 IEEE80211_TX_CTL_STBC); 1198 1199 if (is_mcs) 1200 rateidx += is_5ghz ? ATH9K_PWRTBL_11NA_HT_SHIFT 1201 : ATH9K_PWRTBL_11NG_HT_SHIFT; 1202 else if (is_2ghz && !is_cck) 1203 rateidx += ATH9K_PWRTBL_11NG_OFDM_SHIFT; 1204 else 1205 rateidx += ATH9K_PWRTBL_11NA_OFDM_SHIFT; 1206 1207 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1208 int txpower = fi->tx_power; 1209 1210 if (is_40) { 1211 u8 power_ht40delta; 1212 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1213 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah); 1214 1215 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) { 1216 struct modal_eep_header *pmodal; 1217 1218 pmodal = &eep->modalHeader[is_2ghz]; 1219 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1220 } else { 1221 power_ht40delta = 2; 1222 } 1223 txpower += power_ht40delta; 1224 } 1225 1226 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1227 AR_SREV_9271(ah)) { 1228 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1229 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1230 s8 power_offset; 1231 1232 power_offset = ah->eep_ops->get_eeprom(ah, 1233 EEP_PWR_TABLE_OFFSET); 1234 txpower -= 2 * power_offset; 1235 } 1236 1237 if (OLC_FOR_AR9280_20_LATER(ah) && is_cck) 1238 txpower -= 2; 1239 1240 txpower = max(txpower, 0); 1241 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1242 1243 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1244 * max_power is set to 0, frames are transmitted at max 1245 * TX power 1246 */ 1247 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1248 max_power = 1; 1249 } else if (!bf->bf_state.bfs_paprd) { 1250 if (use_stbc) 1251 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1252 fi->tx_power); 1253 else 1254 max_power = min_t(u8, ah->tx_power[rateidx], 1255 fi->tx_power); 1256 } else { 1257 max_power = ah->paprd_training_power; 1258 } 1259 1260 return max_power; 1261 } 1262 1263 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1264 struct ath_tx_info *info, int len, bool rts) 1265 { 1266 struct ath_hw *ah = sc->sc_ah; 1267 struct ath_common *common = ath9k_hw_common(ah); 1268 struct sk_buff *skb; 1269 struct ieee80211_tx_info *tx_info; 1270 struct ieee80211_tx_rate *rates; 1271 const struct ieee80211_rate *rate; 1272 struct ieee80211_hdr *hdr; 1273 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1274 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1275 int i; 1276 u8 rix = 0; 1277 1278 skb = bf->bf_mpdu; 1279 tx_info = IEEE80211_SKB_CB(skb); 1280 rates = bf->rates; 1281 hdr = (struct ieee80211_hdr *)skb->data; 1282 1283 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1284 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1285 info->rtscts_rate = fi->rtscts_rate; 1286 1287 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1288 bool is_40, is_sgi, is_sp, is_cck; 1289 int phy; 1290 1291 if (!rates[i].count || (rates[i].idx < 0)) 1292 break; 1293 1294 rix = rates[i].idx; 1295 info->rates[i].Tries = rates[i].count; 1296 1297 /* 1298 * Handle RTS threshold for unaggregated HT frames. 1299 */ 1300 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1301 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1302 unlikely(rts_thresh != (u32) -1)) { 1303 if (!rts_thresh || (len > rts_thresh)) 1304 rts = true; 1305 } 1306 1307 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1308 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1309 info->flags |= ATH9K_TXDESC_RTSENA; 1310 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1311 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1312 info->flags |= ATH9K_TXDESC_CTSENA; 1313 } 1314 1315 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1316 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1317 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1318 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1319 1320 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1321 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1322 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1323 1324 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1325 /* MCS rates */ 1326 info->rates[i].Rate = rix | 0x80; 1327 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1328 ah->txchainmask, info->rates[i].Rate); 1329 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 1330 is_40, is_sgi, is_sp); 1331 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1332 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1333 if (rix >= 8 && fi->dyn_smps) { 1334 info->rates[i].RateFlags |= 1335 ATH9K_RATESERIES_RTS_CTS; 1336 info->flags |= ATH9K_TXDESC_CTSENA; 1337 } 1338 1339 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1340 is_40, false, true); 1341 continue; 1342 } 1343 1344 /* legacy rates */ 1345 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1346 if ((tx_info->band == NL80211_BAND_2GHZ) && 1347 !(rate->flags & IEEE80211_RATE_ERP_G)) 1348 phy = WLAN_RC_PHY_CCK; 1349 else 1350 phy = WLAN_RC_PHY_OFDM; 1351 1352 info->rates[i].Rate = rate->hw_value; 1353 if (rate->hw_value_short) { 1354 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1355 info->rates[i].Rate |= rate->hw_value_short; 1356 } else { 1357 is_sp = false; 1358 } 1359 1360 if (bf->bf_state.bfs_paprd) 1361 info->rates[i].ChSel = ah->txchainmask; 1362 else 1363 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1364 ah->txchainmask, info->rates[i].Rate); 1365 1366 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1367 phy, rate->bitrate * 100, len, rix, is_sp); 1368 1369 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1370 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1371 is_cck, false); 1372 } 1373 1374 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1375 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1376 info->flags &= ~ATH9K_TXDESC_RTSENA; 1377 1378 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1379 if (info->flags & ATH9K_TXDESC_RTSENA) 1380 info->flags &= ~ATH9K_TXDESC_CTSENA; 1381 } 1382 1383 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1384 { 1385 struct ieee80211_hdr *hdr; 1386 enum ath9k_pkt_type htype; 1387 __le16 fc; 1388 1389 hdr = (struct ieee80211_hdr *)skb->data; 1390 fc = hdr->frame_control; 1391 1392 if (ieee80211_is_beacon(fc)) 1393 htype = ATH9K_PKT_TYPE_BEACON; 1394 else if (ieee80211_is_probe_resp(fc)) 1395 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1396 else if (ieee80211_is_atim(fc)) 1397 htype = ATH9K_PKT_TYPE_ATIM; 1398 else if (ieee80211_is_pspoll(fc)) 1399 htype = ATH9K_PKT_TYPE_PSPOLL; 1400 else 1401 htype = ATH9K_PKT_TYPE_NORMAL; 1402 1403 return htype; 1404 } 1405 1406 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1407 struct ath_txq *txq, int len) 1408 { 1409 struct ath_hw *ah = sc->sc_ah; 1410 struct ath_buf *bf_first = NULL; 1411 struct ath_tx_info info; 1412 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1413 bool rts = false; 1414 1415 memset(&info, 0, sizeof(info)); 1416 info.is_first = true; 1417 info.is_last = true; 1418 info.qcu = txq->axq_qnum; 1419 1420 while (bf) { 1421 struct sk_buff *skb = bf->bf_mpdu; 1422 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1423 struct ath_frame_info *fi = get_frame_info(skb); 1424 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1425 1426 info.type = get_hw_packet_type(skb); 1427 if (bf->bf_next) 1428 info.link = bf->bf_next->bf_daddr; 1429 else 1430 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1431 1432 if (!bf_first) { 1433 bf_first = bf; 1434 1435 if (!sc->tx99_state) 1436 info.flags = ATH9K_TXDESC_INTREQ; 1437 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1438 txq == sc->tx.uapsdq) 1439 info.flags |= ATH9K_TXDESC_CLRDMASK; 1440 1441 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1442 info.flags |= ATH9K_TXDESC_NOACK; 1443 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1444 info.flags |= ATH9K_TXDESC_LDPC; 1445 1446 if (bf->bf_state.bfs_paprd) 1447 info.flags |= (u32) bf->bf_state.bfs_paprd << 1448 ATH9K_TXDESC_PAPRD_S; 1449 1450 /* 1451 * mac80211 doesn't handle RTS threshold for HT because 1452 * the decision has to be taken based on AMPDU length 1453 * and aggregation is done entirely inside ath9k. 1454 * Set the RTS/CTS flag for the first subframe based 1455 * on the threshold. 1456 */ 1457 if (aggr && (bf == bf_first) && 1458 unlikely(rts_thresh != (u32) -1)) { 1459 /* 1460 * "len" is the size of the entire AMPDU. 1461 */ 1462 if (!rts_thresh || (len > rts_thresh)) 1463 rts = true; 1464 } 1465 1466 if (!aggr) 1467 len = fi->framelen; 1468 1469 ath_buf_set_rate(sc, bf, &info, len, rts); 1470 } 1471 1472 info.buf_addr[0] = bf->bf_buf_addr; 1473 info.buf_len[0] = skb->len; 1474 info.pkt_len = fi->framelen; 1475 info.keyix = fi->keyix; 1476 info.keytype = fi->keytype; 1477 1478 if (aggr) { 1479 if (bf == bf_first) 1480 info.aggr = AGGR_BUF_FIRST; 1481 else if (bf == bf_first->bf_lastbf) 1482 info.aggr = AGGR_BUF_LAST; 1483 else 1484 info.aggr = AGGR_BUF_MIDDLE; 1485 1486 info.ndelim = bf->bf_state.ndelim; 1487 info.aggr_len = len; 1488 } 1489 1490 if (bf == bf_first->bf_lastbf) 1491 bf_first = NULL; 1492 1493 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1494 bf = bf->bf_next; 1495 } 1496 } 1497 1498 static void 1499 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1500 struct ath_atx_tid *tid, struct list_head *bf_q, 1501 struct ath_buf *bf_first) 1502 { 1503 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1504 int nframes = 0, ret; 1505 1506 do { 1507 struct ieee80211_tx_info *tx_info; 1508 1509 nframes++; 1510 list_add_tail(&bf->list, bf_q); 1511 if (bf_prev) 1512 bf_prev->bf_next = bf; 1513 bf_prev = bf; 1514 1515 if (nframes >= 2) 1516 break; 1517 1518 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1519 if (ret < 0) 1520 break; 1521 1522 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1523 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1524 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1525 break; 1526 } 1527 1528 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1529 } while (1); 1530 } 1531 1532 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1533 struct ath_atx_tid *tid) 1534 { 1535 struct ath_buf *bf = NULL; 1536 struct ieee80211_tx_info *tx_info; 1537 struct list_head bf_q; 1538 int aggr_len = 0, ret; 1539 bool aggr; 1540 1541 INIT_LIST_HEAD(&bf_q); 1542 1543 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1544 if (ret < 0) 1545 return ret; 1546 1547 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1548 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1549 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1550 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1551 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1552 return -EBUSY; 1553 } 1554 1555 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1556 if (aggr) 1557 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf); 1558 else 1559 ath_tx_form_burst(sc, txq, tid, &bf_q, bf); 1560 1561 if (list_empty(&bf_q)) 1562 return -EAGAIN; 1563 1564 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1565 tid->clear_ps_filter = false; 1566 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1567 } 1568 1569 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1570 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1571 return 0; 1572 } 1573 1574 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1575 u16 tid, u16 *ssn) 1576 { 1577 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1578 struct ath_atx_tid *txtid; 1579 struct ath_txq *txq; 1580 struct ath_node *an; 1581 u8 density; 1582 1583 ath_dbg(common, XMIT, "%s called\n", __func__); 1584 1585 an = (struct ath_node *)sta->drv_priv; 1586 txtid = ATH_AN_2_TID(an, tid); 1587 txq = txtid->txq; 1588 1589 ath_txq_lock(sc, txq); 1590 1591 /* update ampdu factor/density, they may have changed. This may happen 1592 * in HT IBSS when a beacon with HT-info is received after the station 1593 * has already been added. 1594 */ 1595 if (sta->deflink.ht_cap.ht_supported) { 1596 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1597 sta->deflink.ht_cap.ampdu_factor)) - 1; 1598 density = ath9k_parse_mpdudensity(sta->deflink.ht_cap.ampdu_density); 1599 an->mpdudensity = density; 1600 } 1601 1602 txtid->active = true; 1603 *ssn = txtid->seq_start = txtid->seq_next; 1604 txtid->bar_index = -1; 1605 1606 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1607 txtid->baw_head = txtid->baw_tail = 0; 1608 1609 ath_txq_unlock_complete(sc, txq); 1610 1611 return 0; 1612 } 1613 1614 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1615 { 1616 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1617 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1618 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1619 struct ath_txq *txq = txtid->txq; 1620 1621 ath_dbg(common, XMIT, "%s called\n", __func__); 1622 1623 ath_txq_lock(sc, txq); 1624 txtid->active = false; 1625 ath_tx_flush_tid(sc, txtid); 1626 ath_txq_unlock_complete(sc, txq); 1627 } 1628 1629 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1630 struct ath_node *an) 1631 { 1632 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1633 struct ath_atx_tid *tid; 1634 int tidno; 1635 1636 ath_dbg(common, XMIT, "%s called\n", __func__); 1637 1638 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1639 tid = ath_node_to_tid(an, tidno); 1640 1641 if (!skb_queue_empty(&tid->retry_q)) 1642 ieee80211_sta_set_buffered(sta, tid->tidno, true); 1643 1644 } 1645 } 1646 1647 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1648 { 1649 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1650 struct ath_atx_tid *tid; 1651 struct ath_txq *txq; 1652 int tidno; 1653 1654 ath_dbg(common, XMIT, "%s called\n", __func__); 1655 1656 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1657 tid = ath_node_to_tid(an, tidno); 1658 txq = tid->txq; 1659 1660 ath_txq_lock(sc, txq); 1661 tid->clear_ps_filter = true; 1662 if (!skb_queue_empty(&tid->retry_q)) { 1663 ath_tx_queue_tid(sc, tid); 1664 ath_txq_schedule(sc, txq); 1665 } 1666 ath_txq_unlock_complete(sc, txq); 1667 1668 } 1669 } 1670 1671 1672 static void 1673 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val) 1674 { 1675 struct ieee80211_hdr *hdr; 1676 u16 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA); 1677 u16 mask_val = mask * val; 1678 1679 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 1680 if ((hdr->frame_control & mask) != mask_val) { 1681 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val; 1682 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 1683 sizeof(*hdr), DMA_TO_DEVICE); 1684 } 1685 } 1686 1687 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1688 struct ieee80211_sta *sta, 1689 u16 tids, int nframes, 1690 enum ieee80211_frame_release_type reason, 1691 bool more_data) 1692 { 1693 struct ath_softc *sc = hw->priv; 1694 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1695 struct ath_txq *txq = sc->tx.uapsdq; 1696 struct ieee80211_tx_info *info; 1697 struct list_head bf_q; 1698 struct ath_buf *bf_tail = NULL, *bf = NULL; 1699 int i, ret; 1700 1701 INIT_LIST_HEAD(&bf_q); 1702 for (i = 0; tids && nframes; i++, tids >>= 1) { 1703 struct ath_atx_tid *tid; 1704 1705 if (!(tids & 1)) 1706 continue; 1707 1708 tid = ATH_AN_2_TID(an, i); 1709 1710 ath_txq_lock(sc, tid->txq); 1711 while (nframes > 0) { 1712 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, 1713 tid, &bf); 1714 if (ret < 0) 1715 break; 1716 1717 ath9k_set_moredata(sc, bf, true); 1718 list_add_tail(&bf->list, &bf_q); 1719 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1720 if (bf_isampdu(bf)) 1721 bf->bf_state.bf_type &= ~BUF_AGGR; 1722 if (bf_tail) 1723 bf_tail->bf_next = bf; 1724 1725 bf_tail = bf; 1726 nframes--; 1727 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw); 1728 1729 if (an->sta && skb_queue_empty(&tid->retry_q)) 1730 ieee80211_sta_set_buffered(an->sta, i, false); 1731 } 1732 ath_txq_unlock_complete(sc, tid->txq); 1733 } 1734 1735 if (list_empty(&bf_q)) 1736 return; 1737 1738 if (!more_data) 1739 ath9k_set_moredata(sc, bf_tail, false); 1740 1741 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1742 info->flags |= IEEE80211_TX_STATUS_EOSP; 1743 1744 bf = list_first_entry(&bf_q, struct ath_buf, list); 1745 ath_txq_lock(sc, txq); 1746 ath_tx_fill_desc(sc, bf, txq, 0); 1747 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1748 ath_txq_unlock(sc, txq); 1749 } 1750 1751 /********************/ 1752 /* Queue Management */ 1753 /********************/ 1754 1755 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1756 { 1757 struct ath_hw *ah = sc->sc_ah; 1758 struct ath9k_tx_queue_info qi; 1759 static const int subtype_txq_to_hwq[] = { 1760 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1761 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1762 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1763 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1764 }; 1765 int axq_qnum, i; 1766 1767 memset(&qi, 0, sizeof(qi)); 1768 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1769 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1770 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1771 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1772 qi.tqi_physCompBuf = 0; 1773 1774 /* 1775 * Enable interrupts only for EOL and DESC conditions. 1776 * We mark tx descriptors to receive a DESC interrupt 1777 * when a tx queue gets deep; otherwise waiting for the 1778 * EOL to reap descriptors. Note that this is done to 1779 * reduce interrupt load and this only defers reaping 1780 * descriptors, never transmitting frames. Aside from 1781 * reducing interrupts this also permits more concurrency. 1782 * The only potential downside is if the tx queue backs 1783 * up in which case the top half of the kernel may backup 1784 * due to a lack of tx descriptors. 1785 * 1786 * The UAPSD queue is an exception, since we take a desc- 1787 * based intr on the EOSP frames. 1788 */ 1789 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1790 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1791 } else { 1792 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1793 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1794 else 1795 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1796 TXQ_FLAG_TXDESCINT_ENABLE; 1797 } 1798 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1799 if (axq_qnum == -1) { 1800 /* 1801 * NB: don't print a message, this happens 1802 * normally on parts with too few tx queues 1803 */ 1804 return NULL; 1805 } 1806 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1807 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1808 1809 txq->axq_qnum = axq_qnum; 1810 txq->mac80211_qnum = -1; 1811 txq->axq_link = NULL; 1812 __skb_queue_head_init(&txq->complete_q); 1813 INIT_LIST_HEAD(&txq->axq_q); 1814 spin_lock_init(&txq->axq_lock); 1815 txq->axq_depth = 0; 1816 txq->axq_ampdu_depth = 0; 1817 txq->axq_tx_inprogress = false; 1818 sc->tx.txqsetup |= 1<<axq_qnum; 1819 1820 txq->txq_headidx = txq->txq_tailidx = 0; 1821 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1822 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1823 } 1824 return &sc->tx.txq[axq_qnum]; 1825 } 1826 1827 int ath_txq_update(struct ath_softc *sc, int qnum, 1828 struct ath9k_tx_queue_info *qinfo) 1829 { 1830 struct ath_hw *ah = sc->sc_ah; 1831 int error = 0; 1832 struct ath9k_tx_queue_info qi; 1833 1834 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1835 1836 ath9k_hw_get_txq_props(ah, qnum, &qi); 1837 qi.tqi_aifs = qinfo->tqi_aifs; 1838 qi.tqi_cwmin = qinfo->tqi_cwmin; 1839 qi.tqi_cwmax = qinfo->tqi_cwmax; 1840 qi.tqi_burstTime = qinfo->tqi_burstTime; 1841 qi.tqi_readyTime = qinfo->tqi_readyTime; 1842 1843 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1844 ath_err(ath9k_hw_common(sc->sc_ah), 1845 "Unable to update hardware queue %u!\n", qnum); 1846 error = -EIO; 1847 } else { 1848 ath9k_hw_resettxqueue(ah, qnum); 1849 } 1850 1851 return error; 1852 } 1853 1854 int ath_cabq_update(struct ath_softc *sc) 1855 { 1856 struct ath9k_tx_queue_info qi; 1857 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1858 int qnum = sc->beacon.cabq->axq_qnum; 1859 1860 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1861 1862 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1863 ATH_CABQ_READY_TIME) / 100; 1864 ath_txq_update(sc, qnum, &qi); 1865 1866 return 0; 1867 } 1868 1869 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1870 struct list_head *list) 1871 { 1872 struct ath_buf *bf, *lastbf; 1873 struct list_head bf_head; 1874 struct ath_tx_status ts; 1875 1876 memset(&ts, 0, sizeof(ts)); 1877 ts.ts_status = ATH9K_TX_FLUSH; 1878 INIT_LIST_HEAD(&bf_head); 1879 1880 while (!list_empty(list)) { 1881 bf = list_first_entry(list, struct ath_buf, list); 1882 1883 if (bf->bf_state.stale) { 1884 list_del(&bf->list); 1885 1886 ath_tx_return_buffer(sc, bf); 1887 continue; 1888 } 1889 1890 lastbf = bf->bf_lastbf; 1891 list_cut_position(&bf_head, list, &lastbf->list); 1892 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1893 } 1894 } 1895 1896 /* 1897 * Drain a given TX queue (could be Beacon or Data) 1898 * 1899 * This assumes output has been stopped and 1900 * we do not need to block ath_tx_tasklet. 1901 */ 1902 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1903 { 1904 rcu_read_lock(); 1905 ath_txq_lock(sc, txq); 1906 1907 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1908 int idx = txq->txq_tailidx; 1909 1910 while (!list_empty(&txq->txq_fifo[idx])) { 1911 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1912 1913 INCR(idx, ATH_TXFIFO_DEPTH); 1914 } 1915 txq->txq_tailidx = idx; 1916 } 1917 1918 txq->axq_link = NULL; 1919 txq->axq_tx_inprogress = false; 1920 ath_drain_txq_list(sc, txq, &txq->axq_q); 1921 1922 ath_txq_unlock_complete(sc, txq); 1923 rcu_read_unlock(); 1924 } 1925 1926 bool ath_drain_all_txq(struct ath_softc *sc) 1927 { 1928 struct ath_hw *ah = sc->sc_ah; 1929 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1930 struct ath_txq *txq; 1931 int i; 1932 u32 npend = 0; 1933 1934 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1935 return true; 1936 1937 ath9k_hw_abort_tx_dma(ah); 1938 1939 /* Check if any queue remains active */ 1940 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1941 if (!ATH_TXQ_SETUP(sc, i)) 1942 continue; 1943 1944 if (!sc->tx.txq[i].axq_depth) 1945 continue; 1946 1947 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1948 npend |= BIT(i); 1949 } 1950 1951 if (npend) { 1952 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1953 ath_dbg(common, RESET, 1954 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1955 } 1956 1957 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1958 if (!ATH_TXQ_SETUP(sc, i)) 1959 continue; 1960 1961 txq = &sc->tx.txq[i]; 1962 ath_draintxq(sc, txq); 1963 } 1964 1965 return !npend; 1966 } 1967 1968 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1969 { 1970 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1971 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1972 } 1973 1974 /* For each acq entry, for each tid, try to schedule packets 1975 * for transmit until ampdu_depth has reached min Q depth. 1976 */ 1977 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1978 { 1979 struct ieee80211_hw *hw = sc->hw; 1980 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1981 struct ieee80211_txq *queue; 1982 struct ath_atx_tid *tid; 1983 int ret; 1984 1985 if (txq->mac80211_qnum < 0) 1986 return; 1987 1988 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1989 return; 1990 1991 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum); 1992 spin_lock_bh(&sc->chan_lock); 1993 rcu_read_lock(); 1994 1995 if (sc->cur_chan->stopped) 1996 goto out; 1997 1998 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) { 1999 bool force; 2000 2001 tid = (struct ath_atx_tid *)queue->drv_priv; 2002 2003 ret = ath_tx_sched_aggr(sc, txq, tid); 2004 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret); 2005 2006 force = !skb_queue_empty(&tid->retry_q); 2007 ieee80211_return_txq(hw, queue, force); 2008 } 2009 2010 out: 2011 rcu_read_unlock(); 2012 spin_unlock_bh(&sc->chan_lock); 2013 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum); 2014 } 2015 2016 void ath_txq_schedule_all(struct ath_softc *sc) 2017 { 2018 struct ath_txq *txq; 2019 int i; 2020 2021 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2022 txq = sc->tx.txq_map[i]; 2023 2024 spin_lock_bh(&txq->axq_lock); 2025 ath_txq_schedule(sc, txq); 2026 spin_unlock_bh(&txq->axq_lock); 2027 } 2028 } 2029 2030 /***********/ 2031 /* TX, DMA */ 2032 /***********/ 2033 2034 /* 2035 * Insert a chain of ath_buf (descriptors) on a txq and 2036 * assume the descriptors are already chained together by caller. 2037 */ 2038 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2039 struct list_head *head, bool internal) 2040 { 2041 struct ath_hw *ah = sc->sc_ah; 2042 struct ath_common *common = ath9k_hw_common(ah); 2043 struct ath_buf *bf, *bf_last; 2044 bool puttxbuf = false; 2045 bool edma; 2046 2047 /* 2048 * Insert the frame on the outbound list and 2049 * pass it on to the hardware. 2050 */ 2051 2052 if (list_empty(head)) 2053 return; 2054 2055 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2056 bf = list_first_entry(head, struct ath_buf, list); 2057 bf_last = list_entry(head->prev, struct ath_buf, list); 2058 2059 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2060 txq->axq_qnum, txq->axq_depth); 2061 2062 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2063 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2064 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2065 puttxbuf = true; 2066 } else { 2067 list_splice_tail_init(head, &txq->axq_q); 2068 2069 if (txq->axq_link) { 2070 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2071 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2072 txq->axq_qnum, txq->axq_link, 2073 ito64(bf->bf_daddr), bf->bf_desc); 2074 } else if (!edma) 2075 puttxbuf = true; 2076 2077 txq->axq_link = bf_last->bf_desc; 2078 } 2079 2080 if (puttxbuf) { 2081 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf); 2082 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2083 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2084 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2085 } 2086 2087 if (!edma || sc->tx99_state) { 2088 TX_STAT_INC(sc, txq->axq_qnum, txstart); 2089 ath9k_hw_txstart(ah, txq->axq_qnum); 2090 } 2091 2092 if (!internal) { 2093 while (bf) { 2094 txq->axq_depth++; 2095 if (bf_is_ampdu_not_probing(bf)) 2096 txq->axq_ampdu_depth++; 2097 2098 bf_last = bf->bf_lastbf; 2099 bf = bf_last->bf_next; 2100 bf_last->bf_next = NULL; 2101 } 2102 } 2103 } 2104 2105 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2106 struct ath_atx_tid *tid, struct sk_buff *skb) 2107 { 2108 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2109 struct ath_frame_info *fi = get_frame_info(skb); 2110 struct list_head bf_head; 2111 struct ath_buf *bf = fi->bf; 2112 2113 INIT_LIST_HEAD(&bf_head); 2114 list_add_tail(&bf->list, &bf_head); 2115 bf->bf_state.bf_type = 0; 2116 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2117 bf->bf_state.bf_type = BUF_AMPDU; 2118 ath_tx_addto_baw(sc, tid, bf); 2119 } 2120 2121 bf->bf_next = NULL; 2122 bf->bf_lastbf = bf; 2123 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2124 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2125 TX_STAT_INC(sc, txq->axq_qnum, queued); 2126 } 2127 2128 static void setup_frame_info(struct ieee80211_hw *hw, 2129 struct ieee80211_sta *sta, 2130 struct sk_buff *skb, 2131 int framelen) 2132 { 2133 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2134 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2135 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2136 const struct ieee80211_rate *rate; 2137 struct ath_frame_info *fi = get_frame_info(skb); 2138 struct ath_node *an = NULL; 2139 enum ath9k_key_type keytype; 2140 bool short_preamble = false; 2141 u8 txpower; 2142 2143 /* 2144 * We check if Short Preamble is needed for the CTS rate by 2145 * checking the BSS's global flag. 2146 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2147 */ 2148 if (tx_info->control.vif && 2149 tx_info->control.vif->bss_conf.use_short_preamble) 2150 short_preamble = true; 2151 2152 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2153 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2154 2155 if (sta) 2156 an = (struct ath_node *) sta->drv_priv; 2157 2158 if (tx_info->control.vif) { 2159 struct ieee80211_vif *vif = tx_info->control.vif; 2160 if (vif->bss_conf.txpower == INT_MIN) 2161 goto nonvifpower; 2162 txpower = 2 * vif->bss_conf.txpower; 2163 } else { 2164 struct ath_softc *sc; 2165 nonvifpower: 2166 sc = hw->priv; 2167 2168 txpower = sc->cur_chan->cur_txpower; 2169 } 2170 2171 memset(fi, 0, sizeof(*fi)); 2172 fi->txq = -1; 2173 if (hw_key) 2174 fi->keyix = hw_key->hw_key_idx; 2175 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2176 fi->keyix = an->ps_key; 2177 else 2178 fi->keyix = ATH9K_TXKEYIX_INVALID; 2179 fi->dyn_smps = sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC; 2180 fi->keytype = keytype; 2181 fi->framelen = framelen; 2182 fi->tx_power = txpower; 2183 2184 if (!rate) 2185 return; 2186 fi->rtscts_rate = rate->hw_value; 2187 if (short_preamble) 2188 fi->rtscts_rate |= rate->hw_value_short; 2189 } 2190 2191 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2192 { 2193 struct ath_hw *ah = sc->sc_ah; 2194 struct ath9k_channel *curchan = ah->curchan; 2195 2196 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2197 (chainmask == 0x7) && (rate < 0x90)) 2198 return 0x3; 2199 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2200 IS_CCK_RATE(rate)) 2201 return 0x2; 2202 else 2203 return chainmask; 2204 } 2205 2206 /* 2207 * Assign a descriptor (and sequence number if necessary, 2208 * and map buffer for DMA. Frees skb on error 2209 */ 2210 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2211 struct ath_txq *txq, 2212 struct ath_atx_tid *tid, 2213 struct sk_buff *skb) 2214 { 2215 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2216 struct ath_frame_info *fi = get_frame_info(skb); 2217 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2218 struct ath_buf *bf; 2219 int fragno; 2220 u16 seqno; 2221 2222 bf = ath_tx_get_buffer(sc); 2223 if (!bf) { 2224 ath_dbg(common, XMIT, "TX buffers are full\n"); 2225 return NULL; 2226 } 2227 2228 ATH_TXBUF_RESET(bf); 2229 2230 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2231 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2232 seqno = tid->seq_next; 2233 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2234 2235 if (fragno) 2236 hdr->seq_ctrl |= cpu_to_le16(fragno); 2237 2238 if (!ieee80211_has_morefrags(hdr->frame_control)) 2239 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2240 2241 bf->bf_state.seqno = seqno; 2242 } 2243 2244 bf->bf_mpdu = skb; 2245 2246 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2247 skb->len, DMA_TO_DEVICE); 2248 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2249 bf->bf_mpdu = NULL; 2250 bf->bf_buf_addr = 0; 2251 ath_err(ath9k_hw_common(sc->sc_ah), 2252 "dma_mapping_error() on TX\n"); 2253 ath_tx_return_buffer(sc, bf); 2254 return NULL; 2255 } 2256 2257 fi->bf = bf; 2258 2259 return bf; 2260 } 2261 2262 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2263 { 2264 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2265 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2266 struct ieee80211_vif *vif = info->control.vif; 2267 struct ath_vif *avp; 2268 2269 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2270 return; 2271 2272 if (!vif) 2273 return; 2274 2275 avp = (struct ath_vif *)vif->drv_priv; 2276 2277 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2278 avp->seq_no += 0x10; 2279 2280 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2281 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2282 } 2283 2284 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2285 struct ath_tx_control *txctl) 2286 { 2287 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2288 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2289 struct ieee80211_sta *sta = txctl->sta; 2290 struct ieee80211_vif *vif = info->control.vif; 2291 struct ath_vif *avp; 2292 struct ath_softc *sc = hw->priv; 2293 int frmlen = skb->len + FCS_LEN; 2294 int padpos, padsize; 2295 2296 /* NOTE: sta can be NULL according to net/mac80211.h */ 2297 if (sta) 2298 txctl->an = (struct ath_node *)sta->drv_priv; 2299 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2300 avp = (void *)vif->drv_priv; 2301 txctl->an = &avp->mcast_node; 2302 } 2303 2304 if (info->control.hw_key) 2305 frmlen += info->control.hw_key->icv_len; 2306 2307 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2308 2309 if ((vif && vif->type != NL80211_IFTYPE_AP && 2310 vif->type != NL80211_IFTYPE_AP_VLAN) || 2311 !ieee80211_is_data(hdr->frame_control)) 2312 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2313 2314 /* Add the padding after the header if this is not already done */ 2315 padpos = ieee80211_hdrlen(hdr->frame_control); 2316 padsize = padpos & 3; 2317 if (padsize && skb->len > padpos) { 2318 if (skb_headroom(skb) < padsize) 2319 return -ENOMEM; 2320 2321 skb_push(skb, padsize); 2322 memmove(skb->data, skb->data + padsize, padpos); 2323 } 2324 2325 setup_frame_info(hw, sta, skb, frmlen); 2326 return 0; 2327 } 2328 2329 2330 /* Upon failure caller should free skb */ 2331 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2332 struct ath_tx_control *txctl) 2333 { 2334 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2335 struct ieee80211_sta *sta = txctl->sta; 2336 struct ieee80211_vif *vif = info->control.vif; 2337 struct ath_frame_info *fi = get_frame_info(skb); 2338 struct ath_softc *sc = hw->priv; 2339 struct ath_txq *txq = txctl->txq; 2340 struct ath_atx_tid *tid = NULL; 2341 struct ath_node *an = NULL; 2342 struct ath_buf *bf; 2343 bool ps_resp; 2344 int q, ret; 2345 2346 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2347 2348 ret = ath_tx_prepare(hw, skb, txctl); 2349 if (ret) 2350 return ret; 2351 2352 /* 2353 * At this point, the vif, hw_key and sta pointers in the tx control 2354 * info are no longer valid (overwritten by the ath_frame_info data. 2355 */ 2356 2357 q = skb_get_queue_mapping(skb); 2358 2359 if (ps_resp) 2360 txq = sc->tx.uapsdq; 2361 2362 if (txctl->sta) { 2363 an = (struct ath_node *) sta->drv_priv; 2364 tid = ath_get_skb_tid(sc, an, skb); 2365 } 2366 2367 ath_txq_lock(sc, txq); 2368 if (txq == sc->tx.txq_map[q]) { 2369 fi->txq = q; 2370 ++txq->pending_frames; 2371 } 2372 2373 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2374 if (!bf) { 2375 ath_txq_skb_done(sc, txq, skb); 2376 if (txctl->paprd) 2377 dev_kfree_skb_any(skb); 2378 else 2379 ieee80211_free_txskb(sc->hw, skb); 2380 goto out; 2381 } 2382 2383 bf->bf_state.bfs_paprd = txctl->paprd; 2384 2385 if (txctl->paprd) 2386 bf->bf_state.bfs_paprd_timestamp = jiffies; 2387 2388 ath_set_rates(vif, sta, bf); 2389 ath_tx_send_normal(sc, txq, tid, skb); 2390 2391 out: 2392 ath_txq_unlock(sc, txq); 2393 2394 return 0; 2395 } 2396 2397 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2398 struct sk_buff *skb) 2399 { 2400 struct ath_softc *sc = hw->priv; 2401 struct ath_tx_control txctl = { 2402 .txq = sc->beacon.cabq 2403 }; 2404 struct ath_tx_info info = {}; 2405 struct ath_buf *bf_tail = NULL; 2406 struct ath_buf *bf; 2407 LIST_HEAD(bf_q); 2408 int duration = 0; 2409 int max_duration; 2410 2411 max_duration = 2412 sc->cur_chan->beacon.beacon_interval * 1000 * 2413 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2414 2415 do { 2416 struct ath_frame_info *fi = get_frame_info(skb); 2417 2418 if (ath_tx_prepare(hw, skb, &txctl)) 2419 break; 2420 2421 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2422 if (!bf) 2423 break; 2424 2425 bf->bf_lastbf = bf; 2426 ath_set_rates(vif, NULL, bf); 2427 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2428 duration += info.rates[0].PktDuration; 2429 if (bf_tail) 2430 bf_tail->bf_next = bf; 2431 2432 list_add_tail(&bf->list, &bf_q); 2433 bf_tail = bf; 2434 skb = NULL; 2435 2436 if (duration > max_duration) 2437 break; 2438 2439 skb = ieee80211_get_buffered_bc(hw, vif); 2440 } while(skb); 2441 2442 if (skb) 2443 ieee80211_free_txskb(hw, skb); 2444 2445 if (list_empty(&bf_q)) 2446 return; 2447 2448 bf = list_last_entry(&bf_q, struct ath_buf, list); 2449 ath9k_set_moredata(sc, bf, false); 2450 2451 bf = list_first_entry(&bf_q, struct ath_buf, list); 2452 ath_txq_lock(sc, txctl.txq); 2453 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2454 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2455 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued); 2456 ath_txq_unlock(sc, txctl.txq); 2457 } 2458 2459 /*****************/ 2460 /* TX Completion */ 2461 /*****************/ 2462 2463 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2464 int tx_flags, struct ath_txq *txq, 2465 struct ieee80211_sta *sta) 2466 { 2467 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2468 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2469 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2470 int padpos, padsize; 2471 unsigned long flags; 2472 2473 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2474 2475 if (sc->sc_ah->caldata) 2476 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2477 2478 if (!(tx_flags & ATH_TX_ERROR)) { 2479 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2480 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2481 else 2482 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2483 } 2484 2485 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 2486 padpos = ieee80211_hdrlen(hdr->frame_control); 2487 padsize = padpos & 3; 2488 if (padsize && skb->len>padpos+padsize) { 2489 /* 2490 * Remove MAC header padding before giving the frame back to 2491 * mac80211. 2492 */ 2493 memmove(skb->data + padsize, skb->data, padpos); 2494 skb_pull(skb, padsize); 2495 } 2496 } 2497 2498 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2499 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2500 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2501 ath_dbg(common, PS, 2502 "Going back to sleep after having received TX status (0x%lx)\n", 2503 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2504 PS_WAIT_FOR_CAB | 2505 PS_WAIT_FOR_PSPOLL_DATA | 2506 PS_WAIT_FOR_TX_ACK)); 2507 } 2508 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2509 2510 ath_txq_skb_done(sc, txq, skb); 2511 tx_info->status.status_driver_data[0] = sta; 2512 __skb_queue_tail(&txq->complete_q, skb); 2513 } 2514 2515 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2516 struct ath_txq *txq, struct list_head *bf_q, 2517 struct ieee80211_sta *sta, 2518 struct ath_tx_status *ts, int txok) 2519 { 2520 struct sk_buff *skb = bf->bf_mpdu; 2521 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2522 unsigned long flags; 2523 int tx_flags = 0; 2524 2525 if (!txok) 2526 tx_flags |= ATH_TX_ERROR; 2527 2528 if (ts->ts_status & ATH9K_TXERR_FILT) 2529 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2530 2531 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2532 bf->bf_buf_addr = 0; 2533 if (sc->tx99_state) 2534 goto skip_tx_complete; 2535 2536 if (bf->bf_state.bfs_paprd) { 2537 if (time_after(jiffies, 2538 bf->bf_state.bfs_paprd_timestamp + 2539 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2540 dev_kfree_skb_any(skb); 2541 else 2542 complete(&sc->paprd_complete); 2543 } else { 2544 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2545 ath_tx_complete(sc, skb, tx_flags, txq, sta); 2546 } 2547 skip_tx_complete: 2548 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2549 * accidentally reference it later. 2550 */ 2551 bf->bf_mpdu = NULL; 2552 2553 /* 2554 * Return the list of ath_buf of this mpdu to free queue 2555 */ 2556 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2557 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2558 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2559 } 2560 2561 static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info) 2562 { 2563 void *ptr = &tx_info->status; 2564 2565 memset(ptr + sizeof(tx_info->status.rates), 0, 2566 sizeof(tx_info->status) - 2567 sizeof(tx_info->status.rates) - 2568 sizeof(tx_info->status.status_driver_data)); 2569 } 2570 2571 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2572 struct ath_tx_status *ts, int nframes, int nbad, 2573 int txok) 2574 { 2575 struct sk_buff *skb = bf->bf_mpdu; 2576 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2577 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2578 struct ieee80211_hw *hw = sc->hw; 2579 struct ath_hw *ah = sc->sc_ah; 2580 u8 i, tx_rateindex; 2581 2582 ath_clear_tx_status(tx_info); 2583 2584 if (txok) 2585 tx_info->status.ack_signal = ts->ts_rssi; 2586 2587 tx_rateindex = ts->ts_rateindex; 2588 WARN_ON(tx_rateindex >= hw->max_rates); 2589 2590 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2591 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2592 2593 BUG_ON(nbad > nframes); 2594 } 2595 tx_info->status.ampdu_len = nframes; 2596 tx_info->status.ampdu_ack_len = nframes - nbad; 2597 2598 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2599 2600 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2601 tx_info->status.rates[i].count = 0; 2602 tx_info->status.rates[i].idx = -1; 2603 } 2604 2605 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2606 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2607 /* 2608 * If an underrun error is seen assume it as an excessive 2609 * retry only if max frame trigger level has been reached 2610 * (2 KB for single stream, and 4 KB for dual stream). 2611 * Adjust the long retry as if the frame was tried 2612 * hw->max_rate_tries times to affect how rate control updates 2613 * PER for the failed rate. 2614 * In case of congestion on the bus penalizing this type of 2615 * underruns should help hardware actually transmit new frames 2616 * successfully by eventually preferring slower rates. 2617 * This itself should also alleviate congestion on the bus. 2618 */ 2619 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2620 ATH9K_TX_DELIM_UNDERRUN)) && 2621 ieee80211_is_data(hdr->frame_control) && 2622 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2623 tx_info->status.rates[tx_rateindex].count = 2624 hw->max_rate_tries; 2625 } 2626 } 2627 2628 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2629 { 2630 struct ath_hw *ah = sc->sc_ah; 2631 struct ath_common *common = ath9k_hw_common(ah); 2632 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2633 struct list_head bf_head; 2634 struct ath_desc *ds; 2635 struct ath_tx_status ts; 2636 int status; 2637 2638 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2639 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2640 txq->axq_link); 2641 2642 ath_txq_lock(sc, txq); 2643 for (;;) { 2644 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2645 break; 2646 2647 if (list_empty(&txq->axq_q)) { 2648 txq->axq_link = NULL; 2649 ath_txq_schedule(sc, txq); 2650 break; 2651 } 2652 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2653 2654 /* 2655 * There is a race condition that a BH gets scheduled 2656 * after sw writes TxE and before hw re-load the last 2657 * descriptor to get the newly chained one. 2658 * Software must keep the last DONE descriptor as a 2659 * holding descriptor - software does so by marking 2660 * it with the STALE flag. 2661 */ 2662 bf_held = NULL; 2663 if (bf->bf_state.stale) { 2664 bf_held = bf; 2665 if (list_is_last(&bf_held->list, &txq->axq_q)) 2666 break; 2667 2668 bf = list_entry(bf_held->list.next, struct ath_buf, 2669 list); 2670 } 2671 2672 lastbf = bf->bf_lastbf; 2673 ds = lastbf->bf_desc; 2674 2675 memset(&ts, 0, sizeof(ts)); 2676 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2677 if (status == -EINPROGRESS) 2678 break; 2679 2680 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2681 2682 /* 2683 * Remove ath_buf's of the same transmit unit from txq, 2684 * however leave the last descriptor back as the holding 2685 * descriptor for hw. 2686 */ 2687 lastbf->bf_state.stale = true; 2688 INIT_LIST_HEAD(&bf_head); 2689 if (!list_is_singular(&lastbf->list)) 2690 list_cut_position(&bf_head, 2691 &txq->axq_q, lastbf->list.prev); 2692 2693 if (bf_held) { 2694 list_del(&bf_held->list); 2695 ath_tx_return_buffer(sc, bf_held); 2696 } 2697 2698 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2699 } 2700 ath_txq_unlock_complete(sc, txq); 2701 } 2702 2703 void ath_tx_tasklet(struct ath_softc *sc) 2704 { 2705 struct ath_hw *ah = sc->sc_ah; 2706 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2707 int i; 2708 2709 rcu_read_lock(); 2710 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2711 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2712 ath_tx_processq(sc, &sc->tx.txq[i]); 2713 } 2714 rcu_read_unlock(); 2715 } 2716 2717 void ath_tx_edma_tasklet(struct ath_softc *sc) 2718 { 2719 struct ath_tx_status ts; 2720 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2721 struct ath_hw *ah = sc->sc_ah; 2722 struct ath_txq *txq; 2723 struct ath_buf *bf, *lastbf; 2724 struct list_head bf_head; 2725 struct list_head *fifo_list; 2726 int status; 2727 2728 rcu_read_lock(); 2729 for (;;) { 2730 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2731 break; 2732 2733 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2734 if (status == -EINPROGRESS) 2735 break; 2736 if (status == -EIO) { 2737 ath_dbg(common, XMIT, "Error processing tx status\n"); 2738 break; 2739 } 2740 2741 /* Process beacon completions separately */ 2742 if (ts.qid == sc->beacon.beaconq) { 2743 sc->beacon.tx_processed = true; 2744 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2745 2746 if (ath9k_is_chanctx_enabled()) { 2747 ath_chanctx_event(sc, NULL, 2748 ATH_CHANCTX_EVENT_BEACON_SENT); 2749 } 2750 2751 ath9k_csa_update(sc); 2752 continue; 2753 } 2754 2755 txq = &sc->tx.txq[ts.qid]; 2756 2757 ath_txq_lock(sc, txq); 2758 2759 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2760 2761 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2762 if (list_empty(fifo_list)) { 2763 ath_txq_unlock(sc, txq); 2764 break; 2765 } 2766 2767 bf = list_first_entry(fifo_list, struct ath_buf, list); 2768 if (bf->bf_state.stale) { 2769 list_del(&bf->list); 2770 ath_tx_return_buffer(sc, bf); 2771 bf = list_first_entry(fifo_list, struct ath_buf, list); 2772 } 2773 2774 lastbf = bf->bf_lastbf; 2775 2776 INIT_LIST_HEAD(&bf_head); 2777 if (list_is_last(&lastbf->list, fifo_list)) { 2778 list_splice_tail_init(fifo_list, &bf_head); 2779 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2780 2781 if (!list_empty(&txq->axq_q)) { 2782 struct list_head bf_q; 2783 2784 INIT_LIST_HEAD(&bf_q); 2785 txq->axq_link = NULL; 2786 list_splice_tail_init(&txq->axq_q, &bf_q); 2787 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2788 } 2789 } else { 2790 lastbf->bf_state.stale = true; 2791 if (bf != lastbf) 2792 list_cut_position(&bf_head, fifo_list, 2793 lastbf->list.prev); 2794 } 2795 2796 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2797 ath_txq_unlock_complete(sc, txq); 2798 } 2799 rcu_read_unlock(); 2800 } 2801 2802 /*****************/ 2803 /* Init, Cleanup */ 2804 /*****************/ 2805 2806 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2807 { 2808 struct ath_descdma *dd = &sc->txsdma; 2809 u8 txs_len = sc->sc_ah->caps.txs_len; 2810 2811 dd->dd_desc_len = size * txs_len; 2812 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2813 &dd->dd_desc_paddr, GFP_KERNEL); 2814 if (!dd->dd_desc) 2815 return -ENOMEM; 2816 2817 return 0; 2818 } 2819 2820 static int ath_tx_edma_init(struct ath_softc *sc) 2821 { 2822 int err; 2823 2824 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2825 if (!err) 2826 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2827 sc->txsdma.dd_desc_paddr, 2828 ATH_TXSTATUS_RING_SIZE); 2829 2830 return err; 2831 } 2832 2833 int ath_tx_init(struct ath_softc *sc, int nbufs) 2834 { 2835 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2836 int error = 0; 2837 2838 spin_lock_init(&sc->tx.txbuflock); 2839 2840 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2841 "tx", nbufs, 1, 1); 2842 if (error != 0) { 2843 ath_err(common, 2844 "Failed to allocate tx descriptors: %d\n", error); 2845 return error; 2846 } 2847 2848 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2849 "beacon", ATH_BCBUF, 1, 1); 2850 if (error != 0) { 2851 ath_err(common, 2852 "Failed to allocate beacon descriptors: %d\n", error); 2853 return error; 2854 } 2855 2856 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2857 error = ath_tx_edma_init(sc); 2858 2859 return error; 2860 } 2861 2862 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2863 { 2864 struct ath_atx_tid *tid; 2865 int tidno, acno; 2866 2867 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2868 tid = ath_node_to_tid(an, tidno); 2869 tid->an = an; 2870 tid->tidno = tidno; 2871 tid->seq_start = tid->seq_next = 0; 2872 tid->baw_size = WME_MAX_BA; 2873 tid->baw_head = tid->baw_tail = 0; 2874 tid->active = false; 2875 tid->clear_ps_filter = true; 2876 __skb_queue_head_init(&tid->retry_q); 2877 INIT_LIST_HEAD(&tid->list); 2878 acno = TID_TO_WME_AC(tidno); 2879 tid->txq = sc->tx.txq_map[acno]; 2880 2881 if (!an->sta) 2882 break; /* just one multicast ath_atx_tid */ 2883 } 2884 } 2885 2886 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2887 { 2888 struct ath_atx_tid *tid; 2889 struct ath_txq *txq; 2890 int tidno; 2891 2892 rcu_read_lock(); 2893 2894 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2895 tid = ath_node_to_tid(an, tidno); 2896 txq = tid->txq; 2897 2898 ath_txq_lock(sc, txq); 2899 2900 if (!list_empty(&tid->list)) 2901 list_del_init(&tid->list); 2902 2903 ath_tid_drain(sc, txq, tid); 2904 tid->active = false; 2905 2906 ath_txq_unlock(sc, txq); 2907 2908 if (!an->sta) 2909 break; /* just one multicast ath_atx_tid */ 2910 } 2911 2912 rcu_read_unlock(); 2913 } 2914 2915 #ifdef CONFIG_ATH9K_TX99 2916 2917 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2918 struct ath_tx_control *txctl) 2919 { 2920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2921 struct ath_frame_info *fi = get_frame_info(skb); 2922 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2923 struct ath_buf *bf; 2924 int padpos, padsize; 2925 2926 padpos = ieee80211_hdrlen(hdr->frame_control); 2927 padsize = padpos & 3; 2928 2929 if (padsize && skb->len > padpos) { 2930 if (skb_headroom(skb) < padsize) { 2931 ath_dbg(common, XMIT, 2932 "tx99 padding failed\n"); 2933 return -EINVAL; 2934 } 2935 2936 skb_push(skb, padsize); 2937 memmove(skb->data, skb->data + padsize, padpos); 2938 } 2939 2940 fi->keyix = ATH9K_TXKEYIX_INVALID; 2941 fi->framelen = skb->len + FCS_LEN; 2942 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2943 2944 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2945 if (!bf) { 2946 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2947 return -EINVAL; 2948 } 2949 2950 ath_set_rates(sc->tx99_vif, NULL, bf); 2951 2952 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2953 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2954 2955 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2956 2957 return 0; 2958 } 2959 2960 #endif /* CONFIG_ATH9K_TX99 */ 2961