1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef REG_H 18 #define REG_H 19 20 #include "../reg.h" 21 22 #define AR_CR 0x0008 23 #define AR_CR_RXE 0x00000004 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 26 27 #define AR_RXDP 0x000C 28 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 34 #define AR_CFG_SWRG 0x00000010 35 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 36 #define AR_CFG_PHOK 0x00000100 37 #define AR_CFG_CLK_GATE_DIS 0x00000400 38 #define AR_CFG_EEBS 0x00000200 39 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 40 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 41 42 #define AR_MIRT 0x0020 43 #define AR_MIRT_VAL 0x0000ffff 44 #define AR_MIRT_VAL_S 16 45 46 #define AR_IER 0x0024 47 #define AR_IER_ENABLE 0x00000001 48 #define AR_IER_DISABLE 0x00000000 49 50 #define AR_TIMT 0x0028 51 #define AR_TIMT_LAST 0x0000ffff 52 #define AR_TIMT_LAST_S 0 53 #define AR_TIMT_FIRST 0xffff0000 54 #define AR_TIMT_FIRST_S 16 55 56 #define AR_RIMT 0x002C 57 #define AR_RIMT_LAST 0x0000ffff 58 #define AR_RIMT_LAST_S 0 59 #define AR_RIMT_FIRST 0xffff0000 60 #define AR_RIMT_FIRST_S 16 61 62 #define AR_DMASIZE_4B 0x00000000 63 #define AR_DMASIZE_8B 0x00000001 64 #define AR_DMASIZE_16B 0x00000002 65 #define AR_DMASIZE_32B 0x00000003 66 #define AR_DMASIZE_64B 0x00000004 67 #define AR_DMASIZE_128B 0x00000005 68 #define AR_DMASIZE_256B 0x00000006 69 #define AR_DMASIZE_512B 0x00000007 70 71 #define AR_TXCFG 0x0030 72 #define AR_TXCFG_DMASZ_MASK 0x00000007 73 #define AR_TXCFG_DMASZ_4B 0 74 #define AR_TXCFG_DMASZ_8B 1 75 #define AR_TXCFG_DMASZ_16B 2 76 #define AR_TXCFG_DMASZ_32B 3 77 #define AR_TXCFG_DMASZ_64B 4 78 #define AR_TXCFG_DMASZ_128B 5 79 #define AR_TXCFG_DMASZ_256B 6 80 #define AR_TXCFG_DMASZ_512B 7 81 #define AR_FTRIG 0x000003F0 82 #define AR_FTRIG_S 4 83 #define AR_FTRIG_IMMED 0x00000000 84 #define AR_FTRIG_64B 0x00000010 85 #define AR_FTRIG_128B 0x00000020 86 #define AR_FTRIG_192B 0x00000030 87 #define AR_FTRIG_256B 0x00000040 88 #define AR_FTRIG_512B 0x00000080 89 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 90 91 #define AR_RXCFG 0x0034 92 #define AR_RXCFG_CHIRP 0x00000008 93 #define AR_RXCFG_ZLFDMA 0x00000010 94 #define AR_RXCFG_DMASZ_MASK 0x00000007 95 #define AR_RXCFG_DMASZ_4B 0 96 #define AR_RXCFG_DMASZ_8B 1 97 #define AR_RXCFG_DMASZ_16B 2 98 #define AR_RXCFG_DMASZ_32B 3 99 #define AR_RXCFG_DMASZ_64B 4 100 #define AR_RXCFG_DMASZ_128B 5 101 #define AR_RXCFG_DMASZ_256B 6 102 #define AR_RXCFG_DMASZ_512B 7 103 104 #define AR_MIBC 0x0040 105 #define AR_MIBC_COW 0x00000001 106 #define AR_MIBC_FMC 0x00000002 107 #define AR_MIBC_CMC 0x00000004 108 #define AR_MIBC_MCS 0x00000008 109 110 #define AR_TOPS 0x0044 111 #define AR_TOPS_MASK 0x0000FFFF 112 113 #define AR_RXNPTO 0x0048 114 #define AR_RXNPTO_MASK 0x000003FF 115 116 #define AR_TXNPTO 0x004C 117 #define AR_TXNPTO_MASK 0x000003FF 118 #define AR_TXNPTO_QCU_MASK 0x000FFC00 119 120 #define AR_RPGTO 0x0050 121 #define AR_RPGTO_MASK 0x000003FF 122 123 #define AR_RPCNT 0x0054 124 #define AR_RPCNT_MASK 0x0000001F 125 126 #define AR_MACMISC 0x0058 127 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 128 #define AR_MACMISC_DMA_OBS 0x000001E0 129 #define AR_MACMISC_DMA_OBS_S 5 130 #define AR_MACMISC_DMA_OBS_LINE_0 0 131 #define AR_MACMISC_DMA_OBS_LINE_1 1 132 #define AR_MACMISC_DMA_OBS_LINE_2 2 133 #define AR_MACMISC_DMA_OBS_LINE_3 3 134 #define AR_MACMISC_DMA_OBS_LINE_4 4 135 #define AR_MACMISC_DMA_OBS_LINE_5 5 136 #define AR_MACMISC_DMA_OBS_LINE_6 6 137 #define AR_MACMISC_DMA_OBS_LINE_7 7 138 #define AR_MACMISC_DMA_OBS_LINE_8 8 139 #define AR_MACMISC_MISC_OBS 0x00000E00 140 #define AR_MACMISC_MISC_OBS_S 9 141 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 142 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 143 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 144 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 145 #define AR_MACMISC_MISC_OBS_BUS_1 1 146 147 #define AR_GTXTO 0x0064 148 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 149 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 150 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 151 152 #define AR_GTTM 0x0068 153 #define AR_GTTM_USEC 0x00000001 154 #define AR_GTTM_IGNORE_IDLE 0x00000002 155 #define AR_GTTM_RESET_IDLE 0x00000004 156 #define AR_GTTM_CST_USEC 0x00000008 157 158 #define AR_CST 0x006C 159 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF 160 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 161 #define AR_CST_TIMEOUT_LIMIT_S 16 162 163 #define AR_ISR 0x0080 164 #define AR_ISR_RXOK 0x00000001 165 #define AR_ISR_RXDESC 0x00000002 166 #define AR_ISR_RXERR 0x00000004 167 #define AR_ISR_RXNOPKT 0x00000008 168 #define AR_ISR_RXEOL 0x00000010 169 #define AR_ISR_RXORN 0x00000020 170 #define AR_ISR_TXOK 0x00000040 171 #define AR_ISR_TXDESC 0x00000080 172 #define AR_ISR_TXERR 0x00000100 173 #define AR_ISR_TXNOPKT 0x00000200 174 #define AR_ISR_TXEOL 0x00000400 175 #define AR_ISR_TXURN 0x00000800 176 #define AR_ISR_MIB 0x00001000 177 #define AR_ISR_SWI 0x00002000 178 #define AR_ISR_RXPHY 0x00004000 179 #define AR_ISR_RXKCM 0x00008000 180 #define AR_ISR_SWBA 0x00010000 181 #define AR_ISR_BRSSI 0x00020000 182 #define AR_ISR_BMISS 0x00040000 183 #define AR_ISR_BNR 0x00100000 184 #define AR_ISR_RXCHIRP 0x00200000 185 #define AR_ISR_BCNMISC 0x00800000 186 #define AR_ISR_TIM 0x00800000 187 #define AR_ISR_QCBROVF 0x02000000 188 #define AR_ISR_QCBRURN 0x04000000 189 #define AR_ISR_QTRIG 0x08000000 190 #define AR_ISR_GENTMR 0x10000000 191 192 #define AR_ISR_TXMINTR 0x00080000 193 #define AR_ISR_RXMINTR 0x01000000 194 #define AR_ISR_TXINTM 0x40000000 195 #define AR_ISR_RXINTM 0x80000000 196 197 #define AR_ISR_S0 0x0084 198 #define AR_ISR_S0_QCU_TXOK 0x000003FF 199 #define AR_ISR_S0_QCU_TXOK_S 0 200 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 201 #define AR_ISR_S0_QCU_TXDESC_S 16 202 203 #define AR_ISR_S1 0x0088 204 #define AR_ISR_S1_QCU_TXERR 0x000003FF 205 #define AR_ISR_S1_QCU_TXERR_S 0 206 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 207 #define AR_ISR_S1_QCU_TXEOL_S 16 208 209 #define AR_ISR_S2 0x008c 210 #define AR_ISR_S2_QCU_TXURN 0x000003FF 211 #define AR_ISR_S2_CST 0x00400000 212 #define AR_ISR_S2_GTT 0x00800000 213 #define AR_ISR_S2_TIM 0x01000000 214 #define AR_ISR_S2_CABEND 0x02000000 215 #define AR_ISR_S2_DTIMSYNC 0x04000000 216 #define AR_ISR_S2_BCNTO 0x08000000 217 #define AR_ISR_S2_CABTO 0x10000000 218 #define AR_ISR_S2_DTIM 0x20000000 219 #define AR_ISR_S2_TSFOOR 0x40000000 220 #define AR_ISR_S2_TBTT_TIME 0x80000000 221 222 #define AR_ISR_S3 0x0090 223 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF 224 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 225 226 #define AR_ISR_S4 0x0094 227 #define AR_ISR_S4_QCU_QTRIG 0x000003FF 228 #define AR_ISR_S4_RESV0 0xFFFFFC00 229 230 #define AR_ISR_S5 0x0098 231 #define AR_ISR_S5_TIMER_TRIG 0x000000FF 232 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 233 #define AR_ISR_S5_TIM_TIMER 0x00000010 234 #define AR_ISR_S5_DTIM_TIMER 0x00000020 235 #define AR_ISR_S5_S 0x00d8 236 #define AR_IMR_S5 0x00b8 237 #define AR_IMR_S5_TIM_TIMER 0x00000010 238 #define AR_IMR_S5_DTIM_TIMER 0x00000020 239 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 240 #define AR_ISR_S5_GENTIMER_TRIG_S 0 241 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 242 #define AR_ISR_S5_GENTIMER_THRESH_S 16 243 #define AR_ISR_S5_S 0x00d8 244 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 245 #define AR_IMR_S5_GENTIMER_TRIG_S 0 246 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 247 #define AR_IMR_S5_GENTIMER_THRESH_S 16 248 249 #define AR_IMR 0x00a0 250 #define AR_IMR_RXOK 0x00000001 251 #define AR_IMR_RXDESC 0x00000002 252 #define AR_IMR_RXERR 0x00000004 253 #define AR_IMR_RXNOPKT 0x00000008 254 #define AR_IMR_RXEOL 0x00000010 255 #define AR_IMR_RXORN 0x00000020 256 #define AR_IMR_TXOK 0x00000040 257 #define AR_IMR_TXDESC 0x00000080 258 #define AR_IMR_TXERR 0x00000100 259 #define AR_IMR_TXNOPKT 0x00000200 260 #define AR_IMR_TXEOL 0x00000400 261 #define AR_IMR_TXURN 0x00000800 262 #define AR_IMR_MIB 0x00001000 263 #define AR_IMR_SWI 0x00002000 264 #define AR_IMR_RXPHY 0x00004000 265 #define AR_IMR_RXKCM 0x00008000 266 #define AR_IMR_SWBA 0x00010000 267 #define AR_IMR_BRSSI 0x00020000 268 #define AR_IMR_BMISS 0x00040000 269 #define AR_IMR_BNR 0x00100000 270 #define AR_IMR_RXCHIRP 0x00200000 271 #define AR_IMR_BCNMISC 0x00800000 272 #define AR_IMR_TIM 0x00800000 273 #define AR_IMR_QCBROVF 0x02000000 274 #define AR_IMR_QCBRURN 0x04000000 275 #define AR_IMR_QTRIG 0x08000000 276 #define AR_IMR_GENTMR 0x10000000 277 278 #define AR_IMR_TXMINTR 0x00080000 279 #define AR_IMR_RXMINTR 0x01000000 280 #define AR_IMR_TXINTM 0x40000000 281 #define AR_IMR_RXINTM 0x80000000 282 283 #define AR_IMR_S0 0x00a4 284 #define AR_IMR_S0_QCU_TXOK 0x000003FF 285 #define AR_IMR_S0_QCU_TXOK_S 0 286 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 287 #define AR_IMR_S0_QCU_TXDESC_S 16 288 289 #define AR_IMR_S1 0x00a8 290 #define AR_IMR_S1_QCU_TXERR 0x000003FF 291 #define AR_IMR_S1_QCU_TXERR_S 0 292 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 293 #define AR_IMR_S1_QCU_TXEOL_S 16 294 295 #define AR_IMR_S2 0x00ac 296 #define AR_IMR_S2_QCU_TXURN 0x000003FF 297 #define AR_IMR_S2_QCU_TXURN_S 0 298 #define AR_IMR_S2_CST 0x00400000 299 #define AR_IMR_S2_GTT 0x00800000 300 #define AR_IMR_S2_TIM 0x01000000 301 #define AR_IMR_S2_CABEND 0x02000000 302 #define AR_IMR_S2_DTIMSYNC 0x04000000 303 #define AR_IMR_S2_BCNTO 0x08000000 304 #define AR_IMR_S2_CABTO 0x10000000 305 #define AR_IMR_S2_DTIM 0x20000000 306 #define AR_IMR_S2_TSFOOR 0x40000000 307 308 #define AR_IMR_S3 0x00b0 309 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF 310 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 311 #define AR_IMR_S3_QCU_QCBRURN_S 16 312 313 #define AR_IMR_S4 0x00b4 314 #define AR_IMR_S4_QCU_QTRIG 0x000003FF 315 #define AR_IMR_S4_RESV0 0xFFFFFC00 316 317 #define AR_IMR_S5 0x00b8 318 #define AR_IMR_S5_TIMER_TRIG 0x000000FF 319 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 320 321 322 #define AR_ISR_RAC 0x00c0 323 #define AR_ISR_S0_S 0x00c4 324 #define AR_ISR_S0_QCU_TXOK 0x000003FF 325 #define AR_ISR_S0_QCU_TXOK_S 0 326 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 327 #define AR_ISR_S0_QCU_TXDESC_S 16 328 329 #define AR_ISR_S1_S 0x00c8 330 #define AR_ISR_S1_QCU_TXERR 0x000003FF 331 #define AR_ISR_S1_QCU_TXERR_S 0 332 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 333 #define AR_ISR_S1_QCU_TXEOL_S 16 334 335 #define AR_ISR_S2_S 0x00cc 336 #define AR_ISR_S3_S 0x00d0 337 #define AR_ISR_S4_S 0x00d4 338 #define AR_ISR_S5_S 0x00d8 339 #define AR_DMADBG_0 0x00e0 340 #define AR_DMADBG_1 0x00e4 341 #define AR_DMADBG_2 0x00e8 342 #define AR_DMADBG_3 0x00ec 343 #define AR_DMADBG_4 0x00f0 344 #define AR_DMADBG_5 0x00f4 345 #define AR_DMADBG_6 0x00f8 346 #define AR_DMADBG_7 0x00fc 347 348 #define AR_NUM_QCU 10 349 #define AR_QCU_0 0x0001 350 #define AR_QCU_1 0x0002 351 #define AR_QCU_2 0x0004 352 #define AR_QCU_3 0x0008 353 #define AR_QCU_4 0x0010 354 #define AR_QCU_5 0x0020 355 #define AR_QCU_6 0x0040 356 #define AR_QCU_7 0x0080 357 #define AR_QCU_8 0x0100 358 #define AR_QCU_9 0x0200 359 360 #define AR_Q0_TXDP 0x0800 361 #define AR_Q1_TXDP 0x0804 362 #define AR_Q2_TXDP 0x0808 363 #define AR_Q3_TXDP 0x080c 364 #define AR_Q4_TXDP 0x0810 365 #define AR_Q5_TXDP 0x0814 366 #define AR_Q6_TXDP 0x0818 367 #define AR_Q7_TXDP 0x081c 368 #define AR_Q8_TXDP 0x0820 369 #define AR_Q9_TXDP 0x0824 370 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 371 372 #define AR_Q_TXE 0x0840 373 #define AR_Q_TXE_M 0x000003FF 374 375 #define AR_Q_TXD 0x0880 376 #define AR_Q_TXD_M 0x000003FF 377 378 #define AR_Q0_CBRCFG 0x08c0 379 #define AR_Q1_CBRCFG 0x08c4 380 #define AR_Q2_CBRCFG 0x08c8 381 #define AR_Q3_CBRCFG 0x08cc 382 #define AR_Q4_CBRCFG 0x08d0 383 #define AR_Q5_CBRCFG 0x08d4 384 #define AR_Q6_CBRCFG 0x08d8 385 #define AR_Q7_CBRCFG 0x08dc 386 #define AR_Q8_CBRCFG 0x08e0 387 #define AR_Q9_CBRCFG 0x08e4 388 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 389 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF 390 #define AR_Q_CBRCFG_INTERVAL_S 0 391 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 392 #define AR_Q_CBRCFG_OVF_THRESH_S 24 393 394 #define AR_Q0_RDYTIMECFG 0x0900 395 #define AR_Q1_RDYTIMECFG 0x0904 396 #define AR_Q2_RDYTIMECFG 0x0908 397 #define AR_Q3_RDYTIMECFG 0x090c 398 #define AR_Q4_RDYTIMECFG 0x0910 399 #define AR_Q5_RDYTIMECFG 0x0914 400 #define AR_Q6_RDYTIMECFG 0x0918 401 #define AR_Q7_RDYTIMECFG 0x091c 402 #define AR_Q8_RDYTIMECFG 0x0920 403 #define AR_Q9_RDYTIMECFG 0x0924 404 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 405 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF 406 #define AR_Q_RDYTIMECFG_DURATION_S 0 407 #define AR_Q_RDYTIMECFG_EN 0x01000000 408 409 #define AR_Q_ONESHOTARM_SC 0x0940 410 #define AR_Q_ONESHOTARM_SC_M 0x000003FF 411 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 412 413 #define AR_Q_ONESHOTARM_CC 0x0980 414 #define AR_Q_ONESHOTARM_CC_M 0x000003FF 415 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 416 417 #define AR_Q0_MISC 0x09c0 418 #define AR_Q1_MISC 0x09c4 419 #define AR_Q2_MISC 0x09c8 420 #define AR_Q3_MISC 0x09cc 421 #define AR_Q4_MISC 0x09d0 422 #define AR_Q5_MISC 0x09d4 423 #define AR_Q6_MISC 0x09d8 424 #define AR_Q7_MISC 0x09dc 425 #define AR_Q8_MISC 0x09e0 426 #define AR_Q9_MISC 0x09e4 427 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 428 #define AR_Q_MISC_FSP 0x0000000F 429 #define AR_Q_MISC_FSP_ASAP 0 430 #define AR_Q_MISC_FSP_CBR 1 431 #define AR_Q_MISC_FSP_DBA_GATED 2 432 #define AR_Q_MISC_FSP_TIM_GATED 3 433 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 434 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 435 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 436 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 437 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 438 #define AR_Q_MISC_BEACON_USE 0x00000080 439 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 440 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 441 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 442 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 443 #define AR_Q_MISC_RESV0 0xFFFFF000 444 445 #define AR_Q0_STS 0x0a00 446 #define AR_Q1_STS 0x0a04 447 #define AR_Q2_STS 0x0a08 448 #define AR_Q3_STS 0x0a0c 449 #define AR_Q4_STS 0x0a10 450 #define AR_Q5_STS 0x0a14 451 #define AR_Q6_STS 0x0a18 452 #define AR_Q7_STS 0x0a1c 453 #define AR_Q8_STS 0x0a20 454 #define AR_Q9_STS 0x0a24 455 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 456 #define AR_Q_STS_PEND_FR_CNT 0x00000003 457 #define AR_Q_STS_RESV0 0x000000FC 458 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 459 #define AR_Q_STS_RESV1 0xFFFF0000 460 461 #define AR_Q_RDYTIMESHDN 0x0a40 462 #define AR_Q_RDYTIMESHDN_M 0x000003FF 463 464 465 #define AR_NUM_DCU 10 466 #define AR_DCU_0 0x0001 467 #define AR_DCU_1 0x0002 468 #define AR_DCU_2 0x0004 469 #define AR_DCU_3 0x0008 470 #define AR_DCU_4 0x0010 471 #define AR_DCU_5 0x0020 472 #define AR_DCU_6 0x0040 473 #define AR_DCU_7 0x0080 474 #define AR_DCU_8 0x0100 475 #define AR_DCU_9 0x0200 476 477 #define AR_D0_QCUMASK 0x1000 478 #define AR_D1_QCUMASK 0x1004 479 #define AR_D2_QCUMASK 0x1008 480 #define AR_D3_QCUMASK 0x100c 481 #define AR_D4_QCUMASK 0x1010 482 #define AR_D5_QCUMASK 0x1014 483 #define AR_D6_QCUMASK 0x1018 484 #define AR_D7_QCUMASK 0x101c 485 #define AR_D8_QCUMASK 0x1020 486 #define AR_D9_QCUMASK 0x1024 487 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 488 #define AR_D_QCUMASK 0x000003FF 489 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 490 491 #define AR_D_TXBLK_CMD 0x1038 492 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) 493 494 #define AR_D0_LCL_IFS 0x1040 495 #define AR_D1_LCL_IFS 0x1044 496 #define AR_D2_LCL_IFS 0x1048 497 #define AR_D3_LCL_IFS 0x104c 498 #define AR_D4_LCL_IFS 0x1050 499 #define AR_D5_LCL_IFS 0x1054 500 #define AR_D6_LCL_IFS 0x1058 501 #define AR_D7_LCL_IFS 0x105c 502 #define AR_D8_LCL_IFS 0x1060 503 #define AR_D9_LCL_IFS 0x1064 504 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 505 #define AR_D_LCL_IFS_CWMIN 0x000003FF 506 #define AR_D_LCL_IFS_CWMIN_S 0 507 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 508 #define AR_D_LCL_IFS_CWMAX_S 10 509 #define AR_D_LCL_IFS_AIFS 0x0FF00000 510 #define AR_D_LCL_IFS_AIFS_S 20 511 512 #define AR_D_LCL_IFS_RESV0 0xF0000000 513 514 #define AR_D0_RETRY_LIMIT 0x1080 515 #define AR_D1_RETRY_LIMIT 0x1084 516 #define AR_D2_RETRY_LIMIT 0x1088 517 #define AR_D3_RETRY_LIMIT 0x108c 518 #define AR_D4_RETRY_LIMIT 0x1090 519 #define AR_D5_RETRY_LIMIT 0x1094 520 #define AR_D6_RETRY_LIMIT 0x1098 521 #define AR_D7_RETRY_LIMIT 0x109c 522 #define AR_D8_RETRY_LIMIT 0x10a0 523 #define AR_D9_RETRY_LIMIT 0x10a4 524 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 525 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F 526 #define AR_D_RETRY_LIMIT_FR_SH_S 0 527 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 528 #define AR_D_RETRY_LIMIT_STA_SH_S 8 529 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 530 #define AR_D_RETRY_LIMIT_STA_LG_S 14 531 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 532 533 #define AR_D0_CHNTIME 0x10c0 534 #define AR_D1_CHNTIME 0x10c4 535 #define AR_D2_CHNTIME 0x10c8 536 #define AR_D3_CHNTIME 0x10cc 537 #define AR_D4_CHNTIME 0x10d0 538 #define AR_D5_CHNTIME 0x10d4 539 #define AR_D6_CHNTIME 0x10d8 540 #define AR_D7_CHNTIME 0x10dc 541 #define AR_D8_CHNTIME 0x10e0 542 #define AR_D9_CHNTIME 0x10e4 543 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 544 #define AR_D_CHNTIME_DUR 0x000FFFFF 545 #define AR_D_CHNTIME_DUR_S 0 546 #define AR_D_CHNTIME_EN 0x00100000 547 #define AR_D_CHNTIME_RESV0 0xFFE00000 548 549 #define AR_D0_MISC 0x1100 550 #define AR_D1_MISC 0x1104 551 #define AR_D2_MISC 0x1108 552 #define AR_D3_MISC 0x110c 553 #define AR_D4_MISC 0x1110 554 #define AR_D5_MISC 0x1114 555 #define AR_D6_MISC 0x1118 556 #define AR_D7_MISC 0x111c 557 #define AR_D8_MISC 0x1120 558 #define AR_D9_MISC 0x1124 559 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 560 #define AR_D_MISC_BKOFF_THRESH 0x0000003F 561 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 562 #define AR_D_MISC_CW_RESET_EN 0x00000080 563 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 564 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 565 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 566 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 567 #define AR_D_MISC_VIR_COL_HANDLING_S 14 568 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 569 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 570 #define AR_D_MISC_BEACON_USE 0x00010000 571 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 572 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 573 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 574 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 575 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 576 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 577 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 578 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 579 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 580 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 581 #define AR_D_MISC_RESV0 0xFF000000 582 583 #define AR_D_SEQNUM 0x1140 584 585 #define AR_D_GBL_IFS_SIFS 0x1030 586 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 587 #define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 588 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 589 590 #define AR_D_TXBLK_BASE 0x1038 591 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF 592 #define AR_D_TXBLK_WRITE_BITMASK_S 0 593 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 594 #define AR_D_TXBLK_WRITE_SLICE_S 16 595 #define AR_D_TXBLK_WRITE_DCU 0x00F00000 596 #define AR_D_TXBLK_WRITE_DCU_S 20 597 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 598 #define AR_D_TXBLK_WRITE_COMMAND_S 24 599 600 #define AR_D_GBL_IFS_SLOT 0x1070 601 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 602 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 603 #define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 604 605 #define AR_D_GBL_IFS_EIFS 0x10b0 606 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 607 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 608 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 609 610 #define AR_D_GBL_IFS_MISC 0x10f0 611 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 612 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 613 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 614 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 615 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 616 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 617 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 618 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 619 620 #define AR_D_FPCTL 0x1230 621 #define AR_D_FPCTL_DCU 0x0000000F 622 #define AR_D_FPCTL_DCU_S 0 623 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 624 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 625 #define AR_D_FPCTL_BURST_PREFETCH_S 5 626 627 #define AR_D_TXPSE 0x1270 628 #define AR_D_TXPSE_CTRL 0x000003FF 629 #define AR_D_TXPSE_RESV0 0x0000FC00 630 #define AR_D_TXPSE_STATUS 0x00010000 631 #define AR_D_TXPSE_RESV1 0xFFFE0000 632 633 #define AR_D_TXSLOTMASK 0x12f0 634 #define AR_D_TXSLOTMASK_NUM 0x0000000F 635 636 #define AR_CFG_LED 0x1f04 637 #define AR_CFG_SCLK_RATE_IND 0x00000003 638 #define AR_CFG_SCLK_RATE_IND_S 0 639 #define AR_CFG_SCLK_32MHZ 0x00000000 640 #define AR_CFG_SCLK_4MHZ 0x00000001 641 #define AR_CFG_SCLK_1MHZ 0x00000002 642 #define AR_CFG_SCLK_32KHZ 0x00000003 643 #define AR_CFG_LED_BLINK_SLOW 0x00000008 644 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 645 #define AR_CFG_LED_MODE_SEL 0x00000380 646 #define AR_CFG_LED_MODE_SEL_S 7 647 #define AR_CFG_LED_POWER 0x00000280 648 #define AR_CFG_LED_POWER_S 7 649 #define AR_CFG_LED_NETWORK 0x00000300 650 #define AR_CFG_LED_NETWORK_S 7 651 #define AR_CFG_LED_MODE_PROP 0x0 652 #define AR_CFG_LED_MODE_RPROP 0x1 653 #define AR_CFG_LED_MODE_SPLIT 0x2 654 #define AR_CFG_LED_MODE_RAND 0x3 655 #define AR_CFG_LED_MODE_POWER_OFF 0x4 656 #define AR_CFG_LED_MODE_POWER_ON 0x5 657 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 658 #define AR_CFG_LED_MODE_NETWORK_ON 0x6 659 #define AR_CFG_LED_ASSOC_CTL 0x00000c00 660 #define AR_CFG_LED_ASSOC_CTL_S 10 661 #define AR_CFG_LED_ASSOC_NONE 0x0 662 #define AR_CFG_LED_ASSOC_ACTIVE 0x1 663 #define AR_CFG_LED_ASSOC_PENDING 0x2 664 665 #define AR_CFG_LED_BLINK_SLOW 0x00000008 666 #define AR_CFG_LED_BLINK_SLOW_S 3 667 668 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 669 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 670 671 #define AR_MAC_SLEEP 0x1f00 672 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 673 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 674 675 #define AR_RC 0x4000 676 #define AR_RC_AHB 0x00000001 677 #define AR_RC_APB 0x00000002 678 #define AR_RC_HOSTIF 0x00000100 679 680 #define AR_WA 0x4004 681 #define AR_WA_D3_L1_DISABLE (1 << 14) 682 #define AR9285_WA_DEFAULT 0x004a05cb 683 #define AR9280_WA_DEFAULT 0x0040073b 684 #define AR_WA_DEFAULT 0x0000073f 685 686 687 #define AR_PM_STATE 0x4008 688 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 689 690 #define AR_HOST_TIMEOUT 0x4018 691 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 692 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 693 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 694 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 695 696 #define AR_EEPROM 0x401c 697 #define AR_EEPROM_ABSENT 0x00000100 698 #define AR_EEPROM_CORRUPT 0x00000200 699 #define AR_EEPROM_PROT_MASK 0x03FFFC00 700 #define AR_EEPROM_PROT_MASK_S 10 701 702 #define EEPROM_PROTECT_RP_0_31 0x0001 703 #define EEPROM_PROTECT_WP_0_31 0x0002 704 #define EEPROM_PROTECT_RP_32_63 0x0004 705 #define EEPROM_PROTECT_WP_32_63 0x0008 706 #define EEPROM_PROTECT_RP_64_127 0x0010 707 #define EEPROM_PROTECT_WP_64_127 0x0020 708 #define EEPROM_PROTECT_RP_128_191 0x0040 709 #define EEPROM_PROTECT_WP_128_191 0x0080 710 #define EEPROM_PROTECT_RP_192_255 0x0100 711 #define EEPROM_PROTECT_WP_192_255 0x0200 712 #define EEPROM_PROTECT_RP_256_511 0x0400 713 #define EEPROM_PROTECT_WP_256_511 0x0800 714 #define EEPROM_PROTECT_RP_512_1023 0x1000 715 #define EEPROM_PROTECT_WP_512_1023 0x2000 716 #define EEPROM_PROTECT_RP_1024_2047 0x4000 717 #define EEPROM_PROTECT_WP_1024_2047 0x8000 718 719 #define AR_SREV \ 720 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 721 722 #define AR_SREV_ID \ 723 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 724 #define AR_SREV_VERSION 0x000000F0 725 #define AR_SREV_VERSION_S 4 726 #define AR_SREV_REVISION 0x00000007 727 728 #define AR_SREV_ID2 0xFFFFFFFF 729 #define AR_SREV_VERSION2 0xFFFC0000 730 #define AR_SREV_VERSION2_S 18 731 #define AR_SREV_TYPE2 0x0003F000 732 #define AR_SREV_TYPE2_S 12 733 #define AR_SREV_TYPE2_CHAIN 0x00001000 734 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 735 #define AR_SREV_REVISION2 0x00000F00 736 #define AR_SREV_REVISION2_S 8 737 738 #define AR_SREV_VERSION_5416_PCI 0xD 739 #define AR_SREV_VERSION_5416_PCIE 0xC 740 #define AR_SREV_REVISION_5416_10 0 741 #define AR_SREV_REVISION_5416_20 1 742 #define AR_SREV_REVISION_5416_22 2 743 #define AR_SREV_VERSION_9100 0x14 744 #define AR_SREV_VERSION_9160 0x40 745 #define AR_SREV_REVISION_9160_10 0 746 #define AR_SREV_REVISION_9160_11 1 747 #define AR_SREV_VERSION_9280 0x80 748 #define AR_SREV_REVISION_9280_10 0 749 #define AR_SREV_REVISION_9280_20 1 750 #define AR_SREV_REVISION_9280_21 2 751 #define AR_SREV_VERSION_9285 0xC0 752 #define AR_SREV_REVISION_9285_10 0 753 #define AR_SREV_REVISION_9285_11 1 754 #define AR_SREV_REVISION_9285_12 2 755 #define AR_SREV_VERSION_9287 0x180 756 #define AR_SREV_REVISION_9287_10 0 757 #define AR_SREV_REVISION_9287_11 1 758 #define AR_SREV_REVISION_9287_12 2 759 #define AR_SREV_VERSION_9271 0x140 760 #define AR_SREV_REVISION_9271_10 0 761 #define AR_SREV_REVISION_9271_11 1 762 763 #define AR_SREV_5416(_ah) \ 764 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 765 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)) 766 #define AR_SREV_5416_20_OR_LATER(_ah) \ 767 (((AR_SREV_5416(_ah)) && \ 768 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \ 769 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 770 #define AR_SREV_5416_22_OR_LATER(_ah) \ 771 (((AR_SREV_5416(_ah)) && \ 772 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \ 773 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 774 775 #define AR_SREV_9100(ah) \ 776 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) 777 #define AR_SREV_9100_OR_LATER(_ah) \ 778 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 779 780 #define AR_SREV_9160(_ah) \ 781 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) 782 #define AR_SREV_9160_10_OR_LATER(_ah) \ 783 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) 784 #define AR_SREV_9160_11(_ah) \ 785 (AR_SREV_9160(_ah) && \ 786 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) 787 #define AR_SREV_9280(_ah) \ 788 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 789 #define AR_SREV_9280_10_OR_LATER(_ah) \ 790 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) 791 #define AR_SREV_9280_20(_ah) \ 792 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ 793 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)) 794 #define AR_SREV_9280_20_OR_LATER(_ah) \ 795 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \ 796 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ 797 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))) 798 799 #define AR_SREV_9285(_ah) \ 800 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) 801 #define AR_SREV_9285_10_OR_LATER(_ah) \ 802 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) 803 #define AR_SREV_9285_11(_ah) \ 804 (AR_SREV_9285(ah) && \ 805 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11)) 806 #define AR_SREV_9285_11_OR_LATER(_ah) \ 807 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ 808 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ 809 AR_SREV_REVISION_9285_11))) 810 #define AR_SREV_9285_12(_ah) \ 811 (AR_SREV_9285(ah) && \ 812 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12)) 813 #define AR_SREV_9285_12_OR_LATER(_ah) \ 814 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ 815 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ 816 AR_SREV_REVISION_9285_12))) 817 818 #define AR_SREV_9287(_ah) \ 819 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) 820 #define AR_SREV_9287_10_OR_LATER(_ah) \ 821 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) 822 #define AR_SREV_9287_10(_ah) \ 823 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 824 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10)) 825 #define AR_SREV_9287_11(_ah) \ 826 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 827 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) 828 #define AR_SREV_9287_11_OR_LATER(_ah) \ 829 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 830 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 831 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11))) 832 #define AR_SREV_9287_12(_ah) \ 833 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 834 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) 835 #define AR_SREV_9287_12_OR_LATER(_ah) \ 836 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 837 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 838 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12))) 839 #define AR_SREV_9271(_ah) \ 840 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271) 841 #define AR_SREV_9271_10(_ah) \ 842 (AR_SREV_9271(_ah) && \ 843 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10)) 844 #define AR_SREV_9271_11(_ah) \ 845 (AR_SREV_9271(_ah) && \ 846 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) 847 848 #define AR_RADIO_SREV_MAJOR 0xf0 849 #define AR_RAD5133_SREV_MAJOR 0xc0 850 #define AR_RAD2133_SREV_MAJOR 0xd0 851 #define AR_RAD5122_SREV_MAJOR 0xe0 852 #define AR_RAD2122_SREV_MAJOR 0xf0 853 854 #define AR_AHB_MODE 0x4024 855 #define AR_AHB_EXACT_WR_EN 0x00000000 856 #define AR_AHB_BUF_WR_EN 0x00000001 857 #define AR_AHB_EXACT_RD_EN 0x00000000 858 #define AR_AHB_CACHELINE_RD_EN 0x00000002 859 #define AR_AHB_PREFETCH_RD_EN 0x00000004 860 #define AR_AHB_PAGE_SIZE_1K 0x00000000 861 #define AR_AHB_PAGE_SIZE_2K 0x00000008 862 #define AR_AHB_PAGE_SIZE_4K 0x00000010 863 #define AR_AHB_CUSTOM_BURST_EN 0x000000C0 864 #define AR_AHB_CUSTOM_BURST_EN_S 6 865 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 866 867 #define AR_INTR_RTC_IRQ 0x00000001 868 #define AR_INTR_MAC_IRQ 0x00000002 869 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 870 #define AR_INTR_MAC_AWAKE 0x00020000 871 #define AR_INTR_MAC_ASLEEP 0x00040000 872 #define AR_INTR_SPURIOUS 0xFFFFFFFF 873 874 875 #define AR_INTR_SYNC_CAUSE_CLR 0x4028 876 877 #define AR_INTR_SYNC_CAUSE 0x4028 878 879 #define AR_INTR_SYNC_ENABLE 0x402c 880 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 881 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 882 883 enum { 884 AR_INTR_SYNC_RTC_IRQ = 0x00000001, 885 AR_INTR_SYNC_MAC_IRQ = 0x00000002, 886 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 887 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, 888 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 889 AR_INTR_SYNC_HOST1_FATAL = 0x00000020, 890 AR_INTR_SYNC_HOST1_PERR = 0x00000040, 891 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 892 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, 893 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 894 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 895 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 896 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 897 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 898 AR_INTR_SYNC_PM_ACCESS = 0x00004000, 899 AR_INTR_SYNC_MAC_AWAKE = 0x00008000, 900 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, 901 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 902 AR_INTR_SYNC_ALL = 0x0003FFFF, 903 904 905 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | 906 AR_INTR_SYNC_HOST1_PERR | 907 AR_INTR_SYNC_RADM_CPL_EP | 908 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | 909 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | 910 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | 911 AR_INTR_SYNC_RADM_CPL_TIMEOUT | 912 AR_INTR_SYNC_LOCAL_TIMEOUT | 913 AR_INTR_SYNC_MAC_SLEEP_ACCESS), 914 915 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 916 917 }; 918 919 #define AR_INTR_ASYNC_MASK 0x4030 920 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 921 #define AR_INTR_ASYNC_MASK_GPIO_S 18 922 923 #define AR_INTR_SYNC_MASK 0x4034 924 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 925 #define AR_INTR_SYNC_MASK_GPIO_S 18 926 927 #define AR_INTR_ASYNC_CAUSE_CLR 0x4038 928 #define AR_INTR_ASYNC_CAUSE 0x4038 929 930 #define AR_INTR_ASYNC_ENABLE 0x403c 931 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 932 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 933 934 #define AR_PCIE_SERDES 0x4040 935 #define AR_PCIE_SERDES2 0x4044 936 #define AR_PCIE_PM_CTRL 0x4014 937 #define AR_PCIE_PM_CTRL_ENA 0x00080000 938 939 #define AR_NUM_GPIO 14 940 #define AR928X_NUM_GPIO 10 941 #define AR9285_NUM_GPIO 12 942 #define AR9287_NUM_GPIO 11 943 944 #define AR_GPIO_IN_OUT 0x4048 945 #define AR_GPIO_IN_VAL 0x0FFFC000 946 #define AR_GPIO_IN_VAL_S 14 947 #define AR928X_GPIO_IN_VAL 0x000FFC00 948 #define AR928X_GPIO_IN_VAL_S 10 949 #define AR9285_GPIO_IN_VAL 0x00FFF000 950 #define AR9285_GPIO_IN_VAL_S 12 951 #define AR9287_GPIO_IN_VAL 0x003FF800 952 #define AR9287_GPIO_IN_VAL_S 11 953 954 #define AR_GPIO_OE_OUT 0x404c 955 #define AR_GPIO_OE_OUT_DRV 0x3 956 #define AR_GPIO_OE_OUT_DRV_NO 0x0 957 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 958 #define AR_GPIO_OE_OUT_DRV_HI 0x2 959 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 960 961 #define AR_GPIO_INTR_POL 0x4050 962 #define AR_GPIO_INTR_POL_VAL 0x00001FFF 963 #define AR_GPIO_INTR_POL_VAL_S 0 964 965 #define AR_GPIO_INPUT_EN_VAL 0x4054 966 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 967 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 968 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 969 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 970 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 971 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 972 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 973 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 974 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 975 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 976 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 977 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 978 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 979 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 980 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 981 #define AR_GPIO_JTAG_DISABLE 0x00020000 982 983 #define AR_GPIO_INPUT_MUX1 0x4058 984 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 985 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 986 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 987 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 988 989 #define AR_GPIO_INPUT_MUX2 0x405c 990 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 991 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 992 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 993 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 994 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 995 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 996 997 #define AR_GPIO_OUTPUT_MUX1 0x4060 998 #define AR_GPIO_OUTPUT_MUX2 0x4064 999 #define AR_GPIO_OUTPUT_MUX3 0x4068 1000 1001 #define AR_INPUT_STATE 0x406c 1002 1003 #define AR_EEPROM_STATUS_DATA 0x407c 1004 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1005 #define AR_EEPROM_STATUS_DATA_VAL_S 0 1006 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1007 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1008 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1009 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1010 1011 #define AR_OBS 0x4080 1012 1013 #define AR_GPIO_PDPU 0x4088 1014 1015 #define AR_PCIE_MSI 0x4094 1016 #define AR_PCIE_MSI_ENABLE 0x00000001 1017 1018 1019 #define AR_RTC_9160_PLL_DIV 0x000003ff 1020 #define AR_RTC_9160_PLL_DIV_S 0 1021 #define AR_RTC_9160_PLL_REFDIV 0x00003C00 1022 #define AR_RTC_9160_PLL_REFDIV_S 10 1023 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 1024 #define AR_RTC_9160_PLL_CLKSEL_S 14 1025 1026 #define AR_RTC_BASE 0x00020000 1027 #define AR_RTC_RC \ 1028 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000) 1029 #define AR_RTC_RC_M 0x00000003 1030 #define AR_RTC_RC_MAC_WARM 0x00000001 1031 #define AR_RTC_RC_MAC_COLD 0x00000002 1032 #define AR_RTC_RC_COLD_RESET 0x00000004 1033 #define AR_RTC_RC_WARM_RESET 0x00000008 1034 1035 #define AR_RTC_PLL_CONTROL \ 1036 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1037 1038 #define AR_RTC_PLL_DIV 0x0000001f 1039 #define AR_RTC_PLL_DIV_S 0 1040 #define AR_RTC_PLL_DIV2 0x00000020 1041 #define AR_RTC_PLL_REFDIV_5 0x000000c0 1042 #define AR_RTC_PLL_CLKSEL 0x00000300 1043 #define AR_RTC_PLL_CLKSEL_S 8 1044 1045 #define AR_RTC_RESET \ 1046 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1047 #define AR_RTC_RESET_EN (0x00000001) 1048 1049 #define AR_RTC_STATUS \ 1050 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) 1051 1052 #define AR_RTC_STATUS_M \ 1053 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) 1054 1055 #define AR_RTC_PM_STATUS_M 0x0000000f 1056 1057 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 1058 #define AR_RTC_STATUS_ON 0x00000002 1059 #define AR_RTC_STATUS_SLEEP 0x00000004 1060 #define AR_RTC_STATUS_WAKEUP 0x00000008 1061 1062 #define AR_RTC_SLEEP_CLK \ 1063 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 1064 #define AR_RTC_FORCE_DERIVED_CLK 0x2 1065 1066 #define AR_RTC_FORCE_WAKE \ 1067 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 1068 #define AR_RTC_FORCE_WAKE_EN 0x00000001 1069 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 1070 1071 1072 #define AR_RTC_INTR_CAUSE \ 1073 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) 1074 1075 #define AR_RTC_INTR_ENABLE \ 1076 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) 1077 1078 #define AR_RTC_INTR_MASK \ 1079 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) 1080 1081 /* RTC_DERIVED_* - only for AR9100 */ 1082 1083 #define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 1084 #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1085 #define AR_RTC_DERIVED_CLK_PERIOD_S 1 1086 1087 #define AR_SEQ_MASK 0x8060 1088 1089 #define AR_AN_RF2G1_CH0 0x7810 1090 #define AR_AN_RF2G1_CH0_OB 0x03800000 1091 #define AR_AN_RF2G1_CH0_OB_S 23 1092 #define AR_AN_RF2G1_CH0_DB 0x1C000000 1093 #define AR_AN_RF2G1_CH0_DB_S 26 1094 1095 #define AR_AN_RF5G1_CH0 0x7818 1096 #define AR_AN_RF5G1_CH0_OB5 0x00070000 1097 #define AR_AN_RF5G1_CH0_OB5_S 16 1098 #define AR_AN_RF5G1_CH0_DB5 0x00380000 1099 #define AR_AN_RF5G1_CH0_DB5_S 19 1100 1101 #define AR_AN_RF2G1_CH1 0x7834 1102 #define AR_AN_RF2G1_CH1_OB 0x03800000 1103 #define AR_AN_RF2G1_CH1_OB_S 23 1104 #define AR_AN_RF2G1_CH1_DB 0x1C000000 1105 #define AR_AN_RF2G1_CH1_DB_S 26 1106 1107 #define AR_AN_RF5G1_CH1 0x783C 1108 #define AR_AN_RF5G1_CH1_OB5 0x00070000 1109 #define AR_AN_RF5G1_CH1_OB5_S 16 1110 #define AR_AN_RF5G1_CH1_DB5 0x00380000 1111 #define AR_AN_RF5G1_CH1_DB5_S 19 1112 1113 #define AR_AN_TOP1 0x7890 1114 #define AR_AN_TOP1_DACIPMODE 0x00040000 1115 #define AR_AN_TOP1_DACIPMODE_S 18 1116 1117 #define AR_AN_TOP2 0x7894 1118 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1119 #define AR_AN_TOP2_XPABIAS_LVL_S 30 1120 #define AR_AN_TOP2_LOCALBIAS 0x00200000 1121 #define AR_AN_TOP2_LOCALBIAS_S 21 1122 #define AR_AN_TOP2_PWDCLKIND 0x00400000 1123 #define AR_AN_TOP2_PWDCLKIND_S 22 1124 1125 #define AR_AN_SYNTH9 0x7868 1126 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 1127 #define AR_AN_SYNTH9_REFDIVA_S 27 1128 1129 #define AR9285_AN_RF2G1 0x7820 1130 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 1131 #define AR9285_AN_RF2G1_ENPACAL_S 11 1132 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 1133 #define AR9285_AN_RF2G1_PDPADRV1_S 25 1134 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 1135 #define AR9285_AN_RF2G1_PDPADRV2_S 24 1136 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 1137 #define AR9285_AN_RF2G1_PDPAOUT_S 23 1138 1139 1140 #define AR9285_AN_RF2G2 0x7824 1141 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 1142 #define AR9285_AN_RF2G2_OFFCAL_S 12 1143 1144 #define AR9285_AN_RF2G3 0x7828 1145 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 1146 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 1147 #define AR9285_AN_RF2G3_OB_0 0x00E00000 1148 #define AR9285_AN_RF2G3_OB_0_S 21 1149 #define AR9285_AN_RF2G3_OB_1 0x001C0000 1150 #define AR9285_AN_RF2G3_OB_1_S 18 1151 #define AR9285_AN_RF2G3_OB_2 0x00038000 1152 #define AR9285_AN_RF2G3_OB_2_S 15 1153 #define AR9285_AN_RF2G3_OB_3 0x00007000 1154 #define AR9285_AN_RF2G3_OB_3_S 12 1155 #define AR9285_AN_RF2G3_OB_4 0x00000E00 1156 #define AR9285_AN_RF2G3_OB_4_S 9 1157 1158 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 1159 #define AR9285_AN_RF2G3_DB1_0_S 6 1160 #define AR9285_AN_RF2G3_DB1_1 0x00000038 1161 #define AR9285_AN_RF2G3_DB1_1_S 3 1162 #define AR9285_AN_RF2G3_DB1_2 0x00000007 1163 #define AR9285_AN_RF2G3_DB1_2_S 0 1164 #define AR9285_AN_RF2G4 0x782C 1165 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 1166 #define AR9285_AN_RF2G4_DB1_3_S 29 1167 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 1168 #define AR9285_AN_RF2G4_DB1_4_S 26 1169 1170 #define AR9285_AN_RF2G4_DB2_0 0x03800000 1171 #define AR9285_AN_RF2G4_DB2_0_S 23 1172 #define AR9285_AN_RF2G4_DB2_1 0x00700000 1173 #define AR9285_AN_RF2G4_DB2_1_S 20 1174 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 1175 #define AR9285_AN_RF2G4_DB2_2_S 17 1176 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 1177 #define AR9285_AN_RF2G4_DB2_3_S 14 1178 #define AR9285_AN_RF2G4_DB2_4 0x00003800 1179 #define AR9285_AN_RF2G4_DB2_4_S 11 1180 1181 /* AR9271 : 0x7828, 0x782c different setting from AR9285 */ 1182 #define AR9271_AN_RF2G3_OB_cck 0x001C0000 1183 #define AR9271_AN_RF2G3_OB_cck_S 18 1184 #define AR9271_AN_RF2G3_OB_psk 0x00038000 1185 #define AR9271_AN_RF2G3_OB_psk_S 15 1186 #define AR9271_AN_RF2G3_OB_qam 0x00007000 1187 #define AR9271_AN_RF2G3_OB_qam_S 12 1188 1189 #define AR9271_AN_RF2G3_DB_1 0x00E00000 1190 #define AR9271_AN_RF2G3_DB_1_S 21 1191 1192 #define AR9271_AN_RF2G3_CCOMP 0xFFF 1193 #define AR9271_AN_RF2G3_CCOMP_S 0 1194 1195 #define AR9271_AN_RF2G4_DB_2 0xE0000000 1196 #define AR9271_AN_RF2G4_DB_2_S 29 1197 1198 #define AR9285_AN_RF2G6 0x7834 1199 #define AR9285_AN_RF2G6_CCOMP 0x00007800 1200 #define AR9285_AN_RF2G6_CCOMP_S 11 1201 #define AR9285_AN_RF2G6_OFFS 0x03f00000 1202 #define AR9285_AN_RF2G6_OFFS_S 20 1203 1204 #define AR9271_AN_RF2G6_OFFS 0x07f00000 1205 #define AR9271_AN_RF2G6_OFFS_S 20 1206 1207 #define AR9285_AN_RF2G7 0x7838 1208 #define AR9285_AN_RF2G7_PWDDB 0x00000002 1209 #define AR9285_AN_RF2G7_PWDDB_S 1 1210 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 1211 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 1212 1213 #define AR9285_AN_RF2G8 0x783C 1214 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 1215 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 1216 1217 1218 #define AR9285_AN_RF2G9 0x7840 1219 #define AR9285_AN_RXTXBB1 0x7854 1220 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 1221 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 1222 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 1223 #define AR9285_AN_RXTXBB1_PDV2I_S 7 1224 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 1225 #define AR9285_AN_RXTXBB1_PDDACIF_S 8 1226 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 1227 #define AR9285_AN_RXTXBB1_SPARE9_S 0 1228 1229 #define AR9285_AN_TOP2 0x7868 1230 1231 #define AR9285_AN_TOP3 0x786c 1232 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1233 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1234 #define AR9285_AN_TOP3_PWDDAC 0x00800000 1235 #define AR9285_AN_TOP3_PWDDAC_S 23 1236 1237 #define AR9285_AN_TOP4 0x7870 1238 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 1239 1240 #define AR9287_AN_RF2G3_CH0 0x7808 1241 #define AR9287_AN_RF2G3_CH1 0x785c 1242 #define AR9287_AN_RF2G3_DB1 0xE0000000 1243 #define AR9287_AN_RF2G3_DB1_S 29 1244 #define AR9287_AN_RF2G3_DB2 0x1C000000 1245 #define AR9287_AN_RF2G3_DB2_S 26 1246 #define AR9287_AN_RF2G3_OB_CCK 0x03800000 1247 #define AR9287_AN_RF2G3_OB_CCK_S 23 1248 #define AR9287_AN_RF2G3_OB_PSK 0x00700000 1249 #define AR9287_AN_RF2G3_OB_PSK_S 20 1250 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000 1251 #define AR9287_AN_RF2G3_OB_QAM_S 17 1252 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000 1253 #define AR9287_AN_RF2G3_OB_PAL_OFF_S 14 1254 1255 #define AR9287_AN_TXPC0 0x7898 1256 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000 1257 #define AR9287_AN_TXPC0_TXPCMODE_S 14 1258 #define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0 1259 #define AR9287_AN_TXPC0_TXPCMODE_TEST 1 1260 #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2 1261 #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3 1262 1263 #define AR9287_AN_TOP2 0x78b4 1264 #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 1265 #define AR9287_AN_TOP2_XPABIAS_LVL_S 30 1266 1267 /* AR9271 specific stuff */ 1268 #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 1269 #define AR9271_RADIO_RF_RST 0x20 1270 #define AR9271_GATE_MAC_CTL 0x4000 1271 1272 #define AR_STA_ID0 0x8000 1273 #define AR_STA_ID1 0x8004 1274 #define AR_STA_ID1_SADH_MASK 0x0000FFFF 1275 #define AR_STA_ID1_STA_AP 0x00010000 1276 #define AR_STA_ID1_ADHOC 0x00020000 1277 #define AR_STA_ID1_PWR_SAV 0x00040000 1278 #define AR_STA_ID1_KSRCHDIS 0x00080000 1279 #define AR_STA_ID1_PCF 0x00100000 1280 #define AR_STA_ID1_USE_DEFANT 0x00200000 1281 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1282 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 1283 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 1284 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 1285 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1286 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1287 #define AR_STA_ID1_KSRCH_MODE 0x10000000 1288 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1289 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1290 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 1291 1292 #define AR_BSS_ID0 0x8008 1293 #define AR_BSS_ID1 0x800C 1294 #define AR_BSS_ID1_U16 0x0000FFFF 1295 #define AR_BSS_ID1_AID 0x07FF0000 1296 #define AR_BSS_ID1_AID_S 16 1297 1298 #define AR_BCN_RSSI_AVE 0x8010 1299 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF 1300 1301 #define AR_TIME_OUT 0x8014 1302 #define AR_TIME_OUT_ACK 0x00003FFF 1303 #define AR_TIME_OUT_ACK_S 0 1304 #define AR_TIME_OUT_CTS 0x3FFF0000 1305 #define AR_TIME_OUT_CTS_S 16 1306 #define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 1307 1308 #define AR_RSSI_THR 0x8018 1309 #define AR_RSSI_THR_MASK 0x000000FF 1310 #define AR_RSSI_THR_BM_THR 0x0000FF00 1311 #define AR_RSSI_THR_BM_THR_S 8 1312 #define AR_RSSI_BCN_WEIGHT 0x1F000000 1313 #define AR_RSSI_BCN_WEIGHT_S 24 1314 #define AR_RSSI_BCN_RSSI_RST 0x20000000 1315 1316 #define AR_USEC 0x801c 1317 #define AR_USEC_USEC 0x0000007F 1318 #define AR_USEC_TX_LAT 0x007FC000 1319 #define AR_USEC_TX_LAT_S 14 1320 #define AR_USEC_RX_LAT 0x1F800000 1321 #define AR_USEC_RX_LAT_S 23 1322 #define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1323 1324 #define AR_RESET_TSF 0x8020 1325 #define AR_RESET_TSF_ONCE 0x01000000 1326 1327 #define AR_MAX_CFP_DUR 0x8038 1328 #define AR_CFP_VAL 0x0000FFFF 1329 1330 #define AR_RX_FILTER 0x803C 1331 1332 #define AR_MCAST_FIL0 0x8040 1333 #define AR_MCAST_FIL1 0x8044 1334 1335 /* 1336 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. 1337 * 1338 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with 1339 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down 1340 * receive. The force RX abort bit will kill any frame which is currently being 1341 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) 1342 * will prevent any new frames from getting started. 1343 */ 1344 #define AR_DIAG_SW 0x8048 1345 #define AR_DIAG_CACHE_ACK 0x00000001 1346 #define AR_DIAG_ACK_DIS 0x00000002 1347 #define AR_DIAG_CTS_DIS 0x00000004 1348 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1349 #define AR_DIAG_DECRYPT_DIS 0x00000010 1350 #define AR_DIAG_RX_DIS 0x00000020 /* RX block */ 1351 #define AR_DIAG_LOOP_BACK 0x00000040 1352 #define AR_DIAG_CORR_FCS 0x00000080 1353 #define AR_DIAG_CHAN_INFO 0x00000100 1354 #define AR_DIAG_SCRAM_SEED 0x0001FE00 1355 #define AR_DIAG_SCRAM_SEED_S 8 1356 #define AR_DIAG_FRAME_NV0 0x00020000 1357 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 1358 #define AR_DIAG_OBS_PT_SEL1_S 18 1359 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ 1360 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1361 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1362 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1363 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1364 #define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ 1365 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1366 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1367 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1368 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1369 1370 #define AR_TSF_L32 0x804c 1371 #define AR_TSF_U32 0x8050 1372 1373 #define AR_TST_ADDAC 0x8054 1374 #define AR_DEF_ANTENNA 0x8058 1375 1376 #define AR_AES_MUTE_MASK0 0x805c 1377 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1378 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1379 #define AR_AES_MUTE_MASK0_QOS_S 16 1380 1381 #define AR_AES_MUTE_MASK1 0x8060 1382 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1383 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1384 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1385 1386 #define AR_GATED_CLKS 0x8064 1387 #define AR_GATED_CLKS_TX 0x00000002 1388 #define AR_GATED_CLKS_RX 0x00000004 1389 #define AR_GATED_CLKS_REG 0x00000008 1390 1391 #define AR_OBS_BUS_CTRL 0x8068 1392 #define AR_OBS_BUS_SEL_1 0x00040000 1393 #define AR_OBS_BUS_SEL_2 0x00080000 1394 #define AR_OBS_BUS_SEL_3 0x000C0000 1395 #define AR_OBS_BUS_SEL_4 0x08040000 1396 #define AR_OBS_BUS_SEL_5 0x08080000 1397 1398 #define AR_OBS_BUS_1 0x806c 1399 #define AR_OBS_BUS_1_PCU 0x00000001 1400 #define AR_OBS_BUS_1_RX_END 0x00000002 1401 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1402 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1403 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1404 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1405 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1406 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1407 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1408 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1409 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1410 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1411 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1412 #define AR_OBS_BUS_1_WEP_STATE_S 12 1413 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 1414 #define AR_OBS_BUS_1_RX_STATE_S 20 1415 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 1416 #define AR_OBS_BUS_1_TX_STATE_S 25 1417 1418 #define AR_LAST_TSTP 0x8080 1419 #define AR_NAV 0x8084 1420 #define AR_RTS_OK 0x8088 1421 #define AR_RTS_FAIL 0x808c 1422 #define AR_ACK_FAIL 0x8090 1423 #define AR_FCS_FAIL 0x8094 1424 #define AR_BEACON_CNT 0x8098 1425 1426 #define AR_SLEEP1 0x80d4 1427 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1428 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 1429 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1430 1431 #define AR_SLEEP2 0x80d8 1432 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1433 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1434 1435 #define AR_TPC 0x80e8 1436 #define AR_TPC_ACK 0x0000003f 1437 #define AR_TPC_ACK_S 0x00 1438 #define AR_TPC_CTS 0x00003f00 1439 #define AR_TPC_CTS_S 0x08 1440 #define AR_TPC_CHIRP 0x003f0000 1441 #define AR_TPC_CHIRP_S 0x16 1442 1443 #define AR_TFCNT 0x80ec 1444 #define AR_RFCNT 0x80f0 1445 #define AR_RCCNT 0x80f4 1446 #define AR_CCCNT 0x80f8 1447 1448 #define AR_QUIET1 0x80fc 1449 #define AR_QUIET1_NEXT_QUIET_S 0 1450 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1451 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1452 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1453 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1454 #define AR_QUIET2 0x8100 1455 #define AR_QUIET2_QUIET_PERIOD_S 0 1456 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1457 #define AR_QUIET2_QUIET_DUR_S 16 1458 #define AR_QUIET2_QUIET_DUR 0xffff0000 1459 1460 #define AR_TSF_PARM 0x8104 1461 #define AR_TSF_INCREMENT_M 0x000000ff 1462 #define AR_TSF_INCREMENT_S 0x00 1463 1464 #define AR_QOS_NO_ACK 0x8108 1465 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f 1466 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1467 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 1468 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1469 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 1470 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1471 1472 #define AR_PHY_ERR 0x810c 1473 1474 #define AR_PHY_ERR_DCHIRP 0x00000008 1475 #define AR_PHY_ERR_RADAR 0x00000020 1476 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1477 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1478 1479 #define AR_RXFIFO_CFG 0x8114 1480 1481 1482 #define AR_MIC_QOS_CONTROL 0x8118 1483 #define AR_MIC_QOS_SELECT 0x811c 1484 1485 #define AR_PCU_MISC 0x8120 1486 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1487 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1488 #define AR_PCU_TX_ADD_TSF 0x00000008 1489 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1490 #define AR_PCU_RX_ANT_UPDT 0x00000800 1491 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1492 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1493 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1494 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1495 #define AR_PCU_TBTT_PROTECT 0x00200000 1496 #define AR_PCU_CLEAR_VMF 0x01000000 1497 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1498 1499 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1500 #define AR_PCU_BT_ANT_PREVENT_RX_S 20 1501 1502 #define AR_FILT_OFDM 0x8124 1503 #define AR_FILT_OFDM_COUNT 0x00FFFFFF 1504 1505 #define AR_FILT_CCK 0x8128 1506 #define AR_FILT_CCK_COUNT 0x00FFFFFF 1507 1508 #define AR_PHY_ERR_1 0x812c 1509 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF 1510 #define AR_PHY_ERR_MASK_1 0x8130 1511 1512 #define AR_PHY_ERR_2 0x8134 1513 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF 1514 #define AR_PHY_ERR_MASK_2 0x8138 1515 1516 #define AR_PHY_COUNTMAX (3 << 22) 1517 #define AR_MIBCNT_INTRMASK (3 << 22) 1518 1519 #define AR_TSFOOR_THRESHOLD 0x813c 1520 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF 1521 1522 #define AR_PHY_ERR_EIFS_MASK 8144 1523 1524 #define AR_PHY_ERR_3 0x8168 1525 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1526 #define AR_PHY_ERR_MASK_3 0x816c 1527 1528 #define AR_BT_COEX_MODE 0x8170 1529 #define AR_BT_TIME_EXTEND 0x000000ff 1530 #define AR_BT_TIME_EXTEND_S 0 1531 #define AR_BT_TXSTATE_EXTEND 0x00000100 1532 #define AR_BT_TXSTATE_EXTEND_S 8 1533 #define AR_BT_TX_FRAME_EXTEND 0x00000200 1534 #define AR_BT_TX_FRAME_EXTEND_S 9 1535 #define AR_BT_MODE 0x00000c00 1536 #define AR_BT_MODE_S 10 1537 #define AR_BT_QUIET 0x00001000 1538 #define AR_BT_QUIET_S 12 1539 #define AR_BT_QCU_THRESH 0x0001e000 1540 #define AR_BT_QCU_THRESH_S 13 1541 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1542 #define AR_BT_RX_CLEAR_POLARITY_S 17 1543 #define AR_BT_PRIORITY_TIME 0x00fc0000 1544 #define AR_BT_PRIORITY_TIME_S 18 1545 #define AR_BT_FIRST_SLOT_TIME 0xff000000 1546 #define AR_BT_FIRST_SLOT_TIME_S 24 1547 1548 #define AR_BT_COEX_WEIGHT 0x8174 1549 #define AR_BT_COEX_WGHT 0xff55 1550 #define AR_STOMP_ALL_WLAN_WGHT 0xffcc 1551 #define AR_STOMP_LOW_WLAN_WGHT 0xaaa8 1552 #define AR_STOMP_NONE_WLAN_WGHT 0xaa00 1553 #define AR_BTCOEX_BT_WGHT 0x0000ffff 1554 #define AR_BTCOEX_BT_WGHT_S 0 1555 #define AR_BTCOEX_WL_WGHT 0xffff0000 1556 #define AR_BTCOEX_WL_WGHT_S 16 1557 1558 #define AR_BT_COEX_MODE2 0x817c 1559 #define AR_BT_BCN_MISS_THRESH 0x000000ff 1560 #define AR_BT_BCN_MISS_THRESH_S 0 1561 #define AR_BT_BCN_MISS_CNT 0x0000ff00 1562 #define AR_BT_BCN_MISS_CNT_S 8 1563 #define AR_BT_HOLD_RX_CLEAR 0x00010000 1564 #define AR_BT_HOLD_RX_CLEAR_S 16 1565 #define AR_BT_DISABLE_BT_ANT 0x00100000 1566 #define AR_BT_DISABLE_BT_ANT_S 20 1567 1568 #define AR_TXSIFS 0x81d0 1569 #define AR_TXSIFS_TIME 0x000000FF 1570 #define AR_TXSIFS_TX_LATENCY 0x00000F00 1571 #define AR_TXSIFS_TX_LATENCY_S 8 1572 #define AR_TXSIFS_ACK_SHIFT 0x00007000 1573 #define AR_TXSIFS_ACK_SHIFT_S 12 1574 1575 #define AR_TXOP_X 0x81ec 1576 #define AR_TXOP_X_VAL 0x000000FF 1577 1578 1579 #define AR_TXOP_0_3 0x81f0 1580 #define AR_TXOP_4_7 0x81f4 1581 #define AR_TXOP_8_11 0x81f8 1582 #define AR_TXOP_12_15 0x81fc 1583 1584 #define AR_NEXT_NDP2_TIMER 0x8180 1585 #define AR_FIRST_NDP_TIMER 7 1586 #define AR_NDP2_PERIOD 0x81a0 1587 #define AR_NDP2_TIMER_MODE 0x81c0 1588 #define AR_NEXT_TBTT_TIMER 0x8200 1589 #define AR_NEXT_DMA_BEACON_ALERT 0x8204 1590 #define AR_NEXT_SWBA 0x8208 1591 #define AR_NEXT_CFP 0x8208 1592 #define AR_NEXT_HCF 0x820C 1593 #define AR_NEXT_TIM 0x8210 1594 #define AR_NEXT_DTIM 0x8214 1595 #define AR_NEXT_QUIET_TIMER 0x8218 1596 #define AR_NEXT_NDP_TIMER 0x821C 1597 1598 #define AR_BEACON_PERIOD 0x8220 1599 #define AR_DMA_BEACON_PERIOD 0x8224 1600 #define AR_SWBA_PERIOD 0x8228 1601 #define AR_HCF_PERIOD 0x822C 1602 #define AR_TIM_PERIOD 0x8230 1603 #define AR_DTIM_PERIOD 0x8234 1604 #define AR_QUIET_PERIOD 0x8238 1605 #define AR_NDP_PERIOD 0x823C 1606 1607 #define AR_TIMER_MODE 0x8240 1608 #define AR_TBTT_TIMER_EN 0x00000001 1609 #define AR_DBA_TIMER_EN 0x00000002 1610 #define AR_SWBA_TIMER_EN 0x00000004 1611 #define AR_HCF_TIMER_EN 0x00000008 1612 #define AR_TIM_TIMER_EN 0x00000010 1613 #define AR_DTIM_TIMER_EN 0x00000020 1614 #define AR_QUIET_TIMER_EN 0x00000040 1615 #define AR_NDP_TIMER_EN 0x00000080 1616 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 1617 #define AR_TIMER_OVERFLOW_INDEX_S 8 1618 #define AR_TIMER_THRESH 0xFFFFF000 1619 #define AR_TIMER_THRESH_S 12 1620 1621 #define AR_SLP32_MODE 0x8244 1622 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF 1623 #define AR_SLP32_ENA 0x00100000 1624 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1625 1626 #define AR_SLP32_WAKE 0x8248 1627 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF 1628 1629 #define AR_SLP32_INC 0x824c 1630 #define AR_SLP32_TST_INC 0x000FFFFF 1631 1632 #define AR_SLP_CNT 0x8250 1633 #define AR_SLP_CYCLE_CNT 0x8254 1634 1635 #define AR_SLP_MIB_CTRL 0x8258 1636 #define AR_SLP_MIB_CLEAR 0x00000001 1637 #define AR_SLP_MIB_PENDING 0x00000002 1638 1639 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 1640 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1641 1642 1643 #define AR_2040_MODE 0x8318 1644 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1645 1646 1647 #define AR_EXTRCCNT 0x8328 1648 1649 #define AR_SELFGEN_MASK 0x832c 1650 1651 #define AR_PCU_TXBUF_CTRL 0x8340 1652 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 1653 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 1654 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 1655 1656 #define AR_PCU_MISC_MODE2 0x8344 1657 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1658 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1659 1660 #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 1661 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1662 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1663 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 1664 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1665 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 1666 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1667 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1668 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1669 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 1670 1671 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 1672 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1673 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1674 1675 1676 #define AR_AES_MUTE_MASK0 0x805c 1677 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1678 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1679 #define AR_AES_MUTE_MASK0_QOS_S 16 1680 1681 #define AR_AES_MUTE_MASK1 0x8060 1682 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1683 #define AR_AES_MUTE_MASK1_SEQ_S 0 1684 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1685 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1686 1687 #define AR_RATE_DURATION_0 0x8700 1688 #define AR_RATE_DURATION_31 0x87CC 1689 #define AR_RATE_DURATION_32 0x8780 1690 #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1691 1692 1693 #define AR_KEYTABLE_0 0x8800 1694 #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 1695 #define AR_KEY_CACHE_SIZE 128 1696 #define AR_RSVD_KEYTABLE_ENTRIES 4 1697 #define AR_KEY_TYPE 0x00000007 1698 #define AR_KEYTABLE_TYPE_40 0x00000000 1699 #define AR_KEYTABLE_TYPE_104 0x00000001 1700 #define AR_KEYTABLE_TYPE_128 0x00000003 1701 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 1702 #define AR_KEYTABLE_TYPE_AES 0x00000005 1703 #define AR_KEYTABLE_TYPE_CCM 0x00000006 1704 #define AR_KEYTABLE_TYPE_CLR 0x00000007 1705 #define AR_KEYTABLE_ANT 0x00000008 1706 #define AR_KEYTABLE_VALID 0x00008000 1707 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) 1708 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) 1709 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) 1710 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) 1711 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) 1712 #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) 1713 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1714 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1715 1716 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 1717 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 1718 1719 #endif 1720