1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef REG_H 18 #define REG_H 19 20 #include "../reg.h" 21 22 #define AR_CR 0x0008 23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004) 24 #define AR_CR_RXD 0x00000020 25 #define AR_CR_SWI 0x00000040 26 27 #define AR_RXDP 0x000C 28 29 #define AR_CFG 0x0014 30 #define AR_CFG_SWTD 0x00000001 31 #define AR_CFG_SWTB 0x00000002 32 #define AR_CFG_SWRD 0x00000004 33 #define AR_CFG_SWRB 0x00000008 34 #define AR_CFG_SWRG 0x00000010 35 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 36 #define AR_CFG_PHOK 0x00000100 37 #define AR_CFG_CLK_GATE_DIS 0x00000400 38 #define AR_CFG_EEBS 0x00000200 39 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 40 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 41 42 #define AR_RXBP_THRESH 0x0018 43 #define AR_RXBP_THRESH_HP 0x0000000f 44 #define AR_RXBP_THRESH_HP_S 0 45 #define AR_RXBP_THRESH_LP 0x00003f00 46 #define AR_RXBP_THRESH_LP_S 8 47 48 #define AR_MIRT 0x0020 49 #define AR_MIRT_VAL 0x0000ffff 50 #define AR_MIRT_VAL_S 16 51 52 #define AR_IER 0x0024 53 #define AR_IER_ENABLE 0x00000001 54 #define AR_IER_DISABLE 0x00000000 55 56 #define AR_TIMT 0x0028 57 #define AR_TIMT_LAST 0x0000ffff 58 #define AR_TIMT_LAST_S 0 59 #define AR_TIMT_FIRST 0xffff0000 60 #define AR_TIMT_FIRST_S 16 61 62 #define AR_RIMT 0x002C 63 #define AR_RIMT_LAST 0x0000ffff 64 #define AR_RIMT_LAST_S 0 65 #define AR_RIMT_FIRST 0xffff0000 66 #define AR_RIMT_FIRST_S 16 67 68 #define AR_DMASIZE_4B 0x00000000 69 #define AR_DMASIZE_8B 0x00000001 70 #define AR_DMASIZE_16B 0x00000002 71 #define AR_DMASIZE_32B 0x00000003 72 #define AR_DMASIZE_64B 0x00000004 73 #define AR_DMASIZE_128B 0x00000005 74 #define AR_DMASIZE_256B 0x00000006 75 #define AR_DMASIZE_512B 0x00000007 76 77 #define AR_TXCFG 0x0030 78 #define AR_TXCFG_DMASZ_MASK 0x00000007 79 #define AR_TXCFG_DMASZ_4B 0 80 #define AR_TXCFG_DMASZ_8B 1 81 #define AR_TXCFG_DMASZ_16B 2 82 #define AR_TXCFG_DMASZ_32B 3 83 #define AR_TXCFG_DMASZ_64B 4 84 #define AR_TXCFG_DMASZ_128B 5 85 #define AR_TXCFG_DMASZ_256B 6 86 #define AR_TXCFG_DMASZ_512B 7 87 #define AR_FTRIG 0x000003F0 88 #define AR_FTRIG_S 4 89 #define AR_FTRIG_IMMED 0x00000000 90 #define AR_FTRIG_64B 0x00000010 91 #define AR_FTRIG_128B 0x00000020 92 #define AR_FTRIG_192B 0x00000030 93 #define AR_FTRIG_256B 0x00000040 94 #define AR_FTRIG_512B 0x00000080 95 #define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 96 97 #define AR_RXCFG 0x0034 98 #define AR_RXCFG_CHIRP 0x00000008 99 #define AR_RXCFG_ZLFDMA 0x00000010 100 #define AR_RXCFG_DMASZ_MASK 0x00000007 101 #define AR_RXCFG_DMASZ_4B 0 102 #define AR_RXCFG_DMASZ_8B 1 103 #define AR_RXCFG_DMASZ_16B 2 104 #define AR_RXCFG_DMASZ_32B 3 105 #define AR_RXCFG_DMASZ_64B 4 106 #define AR_RXCFG_DMASZ_128B 5 107 #define AR_RXCFG_DMASZ_256B 6 108 #define AR_RXCFG_DMASZ_512B 7 109 110 #define AR_TOPS 0x0044 111 #define AR_TOPS_MASK 0x0000FFFF 112 113 #define AR_RXNPTO 0x0048 114 #define AR_RXNPTO_MASK 0x000003FF 115 116 #define AR_TXNPTO 0x004C 117 #define AR_TXNPTO_MASK 0x000003FF 118 #define AR_TXNPTO_QCU_MASK 0x000FFC00 119 120 #define AR_RPGTO 0x0050 121 #define AR_RPGTO_MASK 0x000003FF 122 123 #define AR_RPCNT 0x0054 124 #define AR_RPCNT_MASK 0x0000001F 125 126 #define AR_MACMISC 0x0058 127 #define AR_MACMISC_PCI_EXT_FORCE 0x00000010 128 #define AR_MACMISC_DMA_OBS 0x000001E0 129 #define AR_MACMISC_DMA_OBS_S 5 130 #define AR_MACMISC_DMA_OBS_LINE_0 0 131 #define AR_MACMISC_DMA_OBS_LINE_1 1 132 #define AR_MACMISC_DMA_OBS_LINE_2 2 133 #define AR_MACMISC_DMA_OBS_LINE_3 3 134 #define AR_MACMISC_DMA_OBS_LINE_4 4 135 #define AR_MACMISC_DMA_OBS_LINE_5 5 136 #define AR_MACMISC_DMA_OBS_LINE_6 6 137 #define AR_MACMISC_DMA_OBS_LINE_7 7 138 #define AR_MACMISC_DMA_OBS_LINE_8 8 139 #define AR_MACMISC_MISC_OBS 0x00000E00 140 #define AR_MACMISC_MISC_OBS_S 9 141 #define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 142 #define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 143 #define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 144 #define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 145 #define AR_MACMISC_MISC_OBS_BUS_1 1 146 147 #define AR_DATABUF_SIZE 0x0060 148 #define AR_DATABUF_SIZE_MASK 0x00000FFF 149 150 #define AR_GTXTO 0x0064 151 #define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 152 #define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 153 #define AR_GTXTO_TIMEOUT_LIMIT_S 16 154 155 #define AR_GTTM 0x0068 156 #define AR_GTTM_USEC 0x00000001 157 #define AR_GTTM_IGNORE_IDLE 0x00000002 158 #define AR_GTTM_RESET_IDLE 0x00000004 159 #define AR_GTTM_CST_USEC 0x00000008 160 161 #define AR_CST 0x006C 162 #define AR_CST_TIMEOUT_COUNTER 0x0000FFFF 163 #define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 164 #define AR_CST_TIMEOUT_LIMIT_S 16 165 166 #define AR_HP_RXDP 0x0074 167 #define AR_LP_RXDP 0x0078 168 169 #define AR_ISR 0x0080 170 #define AR_ISR_RXOK 0x00000001 171 #define AR_ISR_RXDESC 0x00000002 172 #define AR_ISR_HP_RXOK 0x00000001 173 #define AR_ISR_LP_RXOK 0x00000002 174 #define AR_ISR_RXERR 0x00000004 175 #define AR_ISR_RXNOPKT 0x00000008 176 #define AR_ISR_RXEOL 0x00000010 177 #define AR_ISR_RXORN 0x00000020 178 #define AR_ISR_TXOK 0x00000040 179 #define AR_ISR_TXDESC 0x00000080 180 #define AR_ISR_TXERR 0x00000100 181 #define AR_ISR_TXNOPKT 0x00000200 182 #define AR_ISR_TXEOL 0x00000400 183 #define AR_ISR_TXURN 0x00000800 184 #define AR_ISR_MIB 0x00001000 185 #define AR_ISR_SWI 0x00002000 186 #define AR_ISR_RXPHY 0x00004000 187 #define AR_ISR_RXKCM 0x00008000 188 #define AR_ISR_SWBA 0x00010000 189 #define AR_ISR_BRSSI 0x00020000 190 #define AR_ISR_BMISS 0x00040000 191 #define AR_ISR_BNR 0x00100000 192 #define AR_ISR_RXCHIRP 0x00200000 193 #define AR_ISR_BCNMISC 0x00800000 194 #define AR_ISR_TIM 0x00800000 195 #define AR_ISR_QCBROVF 0x02000000 196 #define AR_ISR_QCBRURN 0x04000000 197 #define AR_ISR_QTRIG 0x08000000 198 #define AR_ISR_GENTMR 0x10000000 199 200 #define AR_ISR_TXMINTR 0x00080000 201 #define AR_ISR_RXMINTR 0x01000000 202 #define AR_ISR_TXINTM 0x40000000 203 #define AR_ISR_RXINTM 0x80000000 204 205 #define AR_ISR_S0 0x0084 206 #define AR_ISR_S0_QCU_TXOK 0x000003FF 207 #define AR_ISR_S0_QCU_TXOK_S 0 208 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 209 #define AR_ISR_S0_QCU_TXDESC_S 16 210 211 #define AR_ISR_S1 0x0088 212 #define AR_ISR_S1_QCU_TXERR 0x000003FF 213 #define AR_ISR_S1_QCU_TXERR_S 0 214 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 215 #define AR_ISR_S1_QCU_TXEOL_S 16 216 217 #define AR_ISR_S2 0x008c 218 #define AR_ISR_S2_QCU_TXURN 0x000003FF 219 #define AR_ISR_S2_BB_WATCHDOG 0x00010000 220 #define AR_ISR_S2_CST 0x00400000 221 #define AR_ISR_S2_GTT 0x00800000 222 #define AR_ISR_S2_TIM 0x01000000 223 #define AR_ISR_S2_CABEND 0x02000000 224 #define AR_ISR_S2_DTIMSYNC 0x04000000 225 #define AR_ISR_S2_BCNTO 0x08000000 226 #define AR_ISR_S2_CABTO 0x10000000 227 #define AR_ISR_S2_DTIM 0x20000000 228 #define AR_ISR_S2_TSFOOR 0x40000000 229 #define AR_ISR_S2_TBTT_TIME 0x80000000 230 231 #define AR_ISR_S3 0x0090 232 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF 233 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 234 235 #define AR_ISR_S4 0x0094 236 #define AR_ISR_S4_QCU_QTRIG 0x000003FF 237 #define AR_ISR_S4_RESV0 0xFFFFFC00 238 239 #define AR_ISR_S5 0x0098 240 #define AR_ISR_S5_TIMER_TRIG 0x000000FF 241 #define AR_ISR_S5_TIMER_THRESH 0x0007FE00 242 #define AR_ISR_S5_TIM_TIMER 0x00000010 243 #define AR_ISR_S5_DTIM_TIMER 0x00000020 244 #define AR_IMR_S5 0x00b8 245 #define AR_IMR_S5_TIM_TIMER 0x00000010 246 #define AR_IMR_S5_DTIM_TIMER 0x00000020 247 #define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 248 #define AR_ISR_S5_GENTIMER_TRIG_S 0 249 #define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 250 #define AR_ISR_S5_GENTIMER_THRESH_S 16 251 #define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 252 #define AR_IMR_S5_GENTIMER_TRIG_S 0 253 #define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 254 #define AR_IMR_S5_GENTIMER_THRESH_S 16 255 256 #define AR_IMR 0x00a0 257 #define AR_IMR_RXOK 0x00000001 258 #define AR_IMR_RXDESC 0x00000002 259 #define AR_IMR_RXOK_HP 0x00000001 260 #define AR_IMR_RXOK_LP 0x00000002 261 #define AR_IMR_RXERR 0x00000004 262 #define AR_IMR_RXNOPKT 0x00000008 263 #define AR_IMR_RXEOL 0x00000010 264 #define AR_IMR_RXORN 0x00000020 265 #define AR_IMR_TXOK 0x00000040 266 #define AR_IMR_TXDESC 0x00000080 267 #define AR_IMR_TXERR 0x00000100 268 #define AR_IMR_TXNOPKT 0x00000200 269 #define AR_IMR_TXEOL 0x00000400 270 #define AR_IMR_TXURN 0x00000800 271 #define AR_IMR_MIB 0x00001000 272 #define AR_IMR_SWI 0x00002000 273 #define AR_IMR_RXPHY 0x00004000 274 #define AR_IMR_RXKCM 0x00008000 275 #define AR_IMR_SWBA 0x00010000 276 #define AR_IMR_BRSSI 0x00020000 277 #define AR_IMR_BMISS 0x00040000 278 #define AR_IMR_BNR 0x00100000 279 #define AR_IMR_RXCHIRP 0x00200000 280 #define AR_IMR_BCNMISC 0x00800000 281 #define AR_IMR_TIM 0x00800000 282 #define AR_IMR_QCBROVF 0x02000000 283 #define AR_IMR_QCBRURN 0x04000000 284 #define AR_IMR_QTRIG 0x08000000 285 #define AR_IMR_GENTMR 0x10000000 286 287 #define AR_IMR_TXMINTR 0x00080000 288 #define AR_IMR_RXMINTR 0x01000000 289 #define AR_IMR_TXINTM 0x40000000 290 #define AR_IMR_RXINTM 0x80000000 291 292 #define AR_IMR_S0 0x00a4 293 #define AR_IMR_S0_QCU_TXOK 0x000003FF 294 #define AR_IMR_S0_QCU_TXOK_S 0 295 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 296 #define AR_IMR_S0_QCU_TXDESC_S 16 297 298 #define AR_IMR_S1 0x00a8 299 #define AR_IMR_S1_QCU_TXERR 0x000003FF 300 #define AR_IMR_S1_QCU_TXERR_S 0 301 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 302 #define AR_IMR_S1_QCU_TXEOL_S 16 303 304 #define AR_IMR_S2 0x00ac 305 #define AR_IMR_S2_QCU_TXURN 0x000003FF 306 #define AR_IMR_S2_QCU_TXURN_S 0 307 #define AR_IMR_S2_BB_WATCHDOG 0x00010000 308 #define AR_IMR_S2_CST 0x00400000 309 #define AR_IMR_S2_GTT 0x00800000 310 #define AR_IMR_S2_TIM 0x01000000 311 #define AR_IMR_S2_CABEND 0x02000000 312 #define AR_IMR_S2_DTIMSYNC 0x04000000 313 #define AR_IMR_S2_BCNTO 0x08000000 314 #define AR_IMR_S2_CABTO 0x10000000 315 #define AR_IMR_S2_DTIM 0x20000000 316 #define AR_IMR_S2_TSFOOR 0x40000000 317 318 #define AR_IMR_S3 0x00b0 319 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF 320 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 321 #define AR_IMR_S3_QCU_QCBRURN_S 16 322 323 #define AR_IMR_S4 0x00b4 324 #define AR_IMR_S4_QCU_QTRIG 0x000003FF 325 #define AR_IMR_S4_RESV0 0xFFFFFC00 326 327 #define AR_IMR_S5 0x00b8 328 #define AR_IMR_S5_TIMER_TRIG 0x000000FF 329 #define AR_IMR_S5_TIMER_THRESH 0x0000FF00 330 331 332 #define AR_ISR_RAC 0x00c0 333 #define AR_ISR_S0_S 0x00c4 334 #define AR_ISR_S0_QCU_TXOK 0x000003FF 335 #define AR_ISR_S0_QCU_TXOK_S 0 336 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 337 #define AR_ISR_S0_QCU_TXDESC_S 16 338 339 #define AR_ISR_S1_S 0x00c8 340 #define AR_ISR_S1_QCU_TXERR 0x000003FF 341 #define AR_ISR_S1_QCU_TXERR_S 0 342 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 343 #define AR_ISR_S1_QCU_TXEOL_S 16 344 345 #define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc) 346 #define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0) 347 #define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4) 348 #define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8) 349 #define AR_DMADBG_0 0x00e0 350 #define AR_DMADBG_1 0x00e4 351 #define AR_DMADBG_2 0x00e8 352 #define AR_DMADBG_3 0x00ec 353 #define AR_DMADBG_4 0x00f0 354 #define AR_DMADBG_5 0x00f4 355 #define AR_DMADBG_6 0x00f8 356 #define AR_DMADBG_7 0x00fc 357 358 #define AR_NUM_QCU 10 359 #define AR_QCU_0 0x0001 360 #define AR_QCU_1 0x0002 361 #define AR_QCU_2 0x0004 362 #define AR_QCU_3 0x0008 363 #define AR_QCU_4 0x0010 364 #define AR_QCU_5 0x0020 365 #define AR_QCU_6 0x0040 366 #define AR_QCU_7 0x0080 367 #define AR_QCU_8 0x0100 368 #define AR_QCU_9 0x0200 369 370 #define AR_Q0_TXDP 0x0800 371 #define AR_Q1_TXDP 0x0804 372 #define AR_Q2_TXDP 0x0808 373 #define AR_Q3_TXDP 0x080c 374 #define AR_Q4_TXDP 0x0810 375 #define AR_Q5_TXDP 0x0814 376 #define AR_Q6_TXDP 0x0818 377 #define AR_Q7_TXDP 0x081c 378 #define AR_Q8_TXDP 0x0820 379 #define AR_Q9_TXDP 0x0824 380 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 381 382 #define AR_Q_STATUS_RING_START 0x830 383 #define AR_Q_STATUS_RING_END 0x834 384 385 #define AR_Q_TXE 0x0840 386 #define AR_Q_TXE_M 0x000003FF 387 388 #define AR_Q_TXD 0x0880 389 #define AR_Q_TXD_M 0x000003FF 390 391 #define AR_Q0_CBRCFG 0x08c0 392 #define AR_Q1_CBRCFG 0x08c4 393 #define AR_Q2_CBRCFG 0x08c8 394 #define AR_Q3_CBRCFG 0x08cc 395 #define AR_Q4_CBRCFG 0x08d0 396 #define AR_Q5_CBRCFG 0x08d4 397 #define AR_Q6_CBRCFG 0x08d8 398 #define AR_Q7_CBRCFG 0x08dc 399 #define AR_Q8_CBRCFG 0x08e0 400 #define AR_Q9_CBRCFG 0x08e4 401 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 402 #define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF 403 #define AR_Q_CBRCFG_INTERVAL_S 0 404 #define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 405 #define AR_Q_CBRCFG_OVF_THRESH_S 24 406 407 #define AR_Q0_RDYTIMECFG 0x0900 408 #define AR_Q1_RDYTIMECFG 0x0904 409 #define AR_Q2_RDYTIMECFG 0x0908 410 #define AR_Q3_RDYTIMECFG 0x090c 411 #define AR_Q4_RDYTIMECFG 0x0910 412 #define AR_Q5_RDYTIMECFG 0x0914 413 #define AR_Q6_RDYTIMECFG 0x0918 414 #define AR_Q7_RDYTIMECFG 0x091c 415 #define AR_Q8_RDYTIMECFG 0x0920 416 #define AR_Q9_RDYTIMECFG 0x0924 417 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 418 #define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF 419 #define AR_Q_RDYTIMECFG_DURATION_S 0 420 #define AR_Q_RDYTIMECFG_EN 0x01000000 421 422 #define AR_Q_ONESHOTARM_SC 0x0940 423 #define AR_Q_ONESHOTARM_SC_M 0x000003FF 424 #define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 425 426 #define AR_Q_ONESHOTARM_CC 0x0980 427 #define AR_Q_ONESHOTARM_CC_M 0x000003FF 428 #define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 429 430 #define AR_Q0_MISC 0x09c0 431 #define AR_Q1_MISC 0x09c4 432 #define AR_Q2_MISC 0x09c8 433 #define AR_Q3_MISC 0x09cc 434 #define AR_Q4_MISC 0x09d0 435 #define AR_Q5_MISC 0x09d4 436 #define AR_Q6_MISC 0x09d8 437 #define AR_Q7_MISC 0x09dc 438 #define AR_Q8_MISC 0x09e0 439 #define AR_Q9_MISC 0x09e4 440 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 441 #define AR_Q_MISC_FSP 0x0000000F 442 #define AR_Q_MISC_FSP_ASAP 0 443 #define AR_Q_MISC_FSP_CBR 1 444 #define AR_Q_MISC_FSP_DBA_GATED 2 445 #define AR_Q_MISC_FSP_TIM_GATED 3 446 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 447 #define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 448 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 449 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 450 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 451 #define AR_Q_MISC_BEACON_USE 0x00000080 452 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 453 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 454 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 455 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 456 #define AR_Q_MISC_RESV0 0xFFFFF000 457 458 #define AR_Q0_STS 0x0a00 459 #define AR_Q1_STS 0x0a04 460 #define AR_Q2_STS 0x0a08 461 #define AR_Q3_STS 0x0a0c 462 #define AR_Q4_STS 0x0a10 463 #define AR_Q5_STS 0x0a14 464 #define AR_Q6_STS 0x0a18 465 #define AR_Q7_STS 0x0a1c 466 #define AR_Q8_STS 0x0a20 467 #define AR_Q9_STS 0x0a24 468 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 469 #define AR_Q_STS_PEND_FR_CNT 0x00000003 470 #define AR_Q_STS_RESV0 0x000000FC 471 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 472 #define AR_Q_STS_RESV1 0xFFFF0000 473 474 #define AR_Q_RDYTIMESHDN 0x0a40 475 #define AR_Q_RDYTIMESHDN_M 0x000003FF 476 477 /* MAC Descriptor CRC check */ 478 #define AR_Q_DESC_CRCCHK 0xa44 479 /* Enable CRC check on the descriptor fetched from host */ 480 #define AR_Q_DESC_CRCCHK_EN 1 481 482 #define AR_NUM_DCU 10 483 #define AR_DCU_0 0x0001 484 #define AR_DCU_1 0x0002 485 #define AR_DCU_2 0x0004 486 #define AR_DCU_3 0x0008 487 #define AR_DCU_4 0x0010 488 #define AR_DCU_5 0x0020 489 #define AR_DCU_6 0x0040 490 #define AR_DCU_7 0x0080 491 #define AR_DCU_8 0x0100 492 #define AR_DCU_9 0x0200 493 494 #define AR_D0_QCUMASK 0x1000 495 #define AR_D1_QCUMASK 0x1004 496 #define AR_D2_QCUMASK 0x1008 497 #define AR_D3_QCUMASK 0x100c 498 #define AR_D4_QCUMASK 0x1010 499 #define AR_D5_QCUMASK 0x1014 500 #define AR_D6_QCUMASK 0x1018 501 #define AR_D7_QCUMASK 0x101c 502 #define AR_D8_QCUMASK 0x1020 503 #define AR_D9_QCUMASK 0x1024 504 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 505 #define AR_D_QCUMASK 0x000003FF 506 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 507 508 #define AR_D0_LCL_IFS 0x1040 509 #define AR_D1_LCL_IFS 0x1044 510 #define AR_D2_LCL_IFS 0x1048 511 #define AR_D3_LCL_IFS 0x104c 512 #define AR_D4_LCL_IFS 0x1050 513 #define AR_D5_LCL_IFS 0x1054 514 #define AR_D6_LCL_IFS 0x1058 515 #define AR_D7_LCL_IFS 0x105c 516 #define AR_D8_LCL_IFS 0x1060 517 #define AR_D9_LCL_IFS 0x1064 518 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 519 #define AR_D_LCL_IFS_CWMIN 0x000003FF 520 #define AR_D_LCL_IFS_CWMIN_S 0 521 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 522 #define AR_D_LCL_IFS_CWMAX_S 10 523 #define AR_D_LCL_IFS_AIFS 0x0FF00000 524 #define AR_D_LCL_IFS_AIFS_S 20 525 526 #define AR_D_LCL_IFS_RESV0 0xF0000000 527 528 #define AR_D0_RETRY_LIMIT 0x1080 529 #define AR_D1_RETRY_LIMIT 0x1084 530 #define AR_D2_RETRY_LIMIT 0x1088 531 #define AR_D3_RETRY_LIMIT 0x108c 532 #define AR_D4_RETRY_LIMIT 0x1090 533 #define AR_D5_RETRY_LIMIT 0x1094 534 #define AR_D6_RETRY_LIMIT 0x1098 535 #define AR_D7_RETRY_LIMIT 0x109c 536 #define AR_D8_RETRY_LIMIT 0x10a0 537 #define AR_D9_RETRY_LIMIT 0x10a4 538 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 539 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F 540 #define AR_D_RETRY_LIMIT_FR_SH_S 0 541 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 542 #define AR_D_RETRY_LIMIT_STA_SH_S 8 543 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 544 #define AR_D_RETRY_LIMIT_STA_LG_S 14 545 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 546 547 #define AR_D0_CHNTIME 0x10c0 548 #define AR_D1_CHNTIME 0x10c4 549 #define AR_D2_CHNTIME 0x10c8 550 #define AR_D3_CHNTIME 0x10cc 551 #define AR_D4_CHNTIME 0x10d0 552 #define AR_D5_CHNTIME 0x10d4 553 #define AR_D6_CHNTIME 0x10d8 554 #define AR_D7_CHNTIME 0x10dc 555 #define AR_D8_CHNTIME 0x10e0 556 #define AR_D9_CHNTIME 0x10e4 557 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 558 #define AR_D_CHNTIME_DUR 0x000FFFFF 559 #define AR_D_CHNTIME_DUR_S 0 560 #define AR_D_CHNTIME_EN 0x00100000 561 #define AR_D_CHNTIME_RESV0 0xFFE00000 562 563 #define AR_D0_MISC 0x1100 564 #define AR_D1_MISC 0x1104 565 #define AR_D2_MISC 0x1108 566 #define AR_D3_MISC 0x110c 567 #define AR_D4_MISC 0x1110 568 #define AR_D5_MISC 0x1114 569 #define AR_D6_MISC 0x1118 570 #define AR_D7_MISC 0x111c 571 #define AR_D8_MISC 0x1120 572 #define AR_D9_MISC 0x1124 573 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 574 #define AR_D_MISC_BKOFF_THRESH 0x0000003F 575 #define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 576 #define AR_D_MISC_CW_RESET_EN 0x00000080 577 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 578 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 579 #define AR_D_MISC_CW_BKOFF_EN 0x00001000 580 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 581 #define AR_D_MISC_VIR_COL_HANDLING_S 14 582 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 583 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 584 #define AR_D_MISC_BEACON_USE 0x00010000 585 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 586 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 587 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 588 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 589 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 590 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 591 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 592 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 593 #define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 594 #define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 595 #define AR_D_MISC_RESV0 0xFF000000 596 597 #define AR_D_SEQNUM 0x1140 598 599 #define AR_D_GBL_IFS_SIFS 0x1030 600 #define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 601 #define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 602 603 #define AR_D_TXBLK_BASE 0x1038 604 #define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF 605 #define AR_D_TXBLK_WRITE_BITMASK_S 0 606 #define AR_D_TXBLK_WRITE_SLICE 0x000F0000 607 #define AR_D_TXBLK_WRITE_SLICE_S 16 608 #define AR_D_TXBLK_WRITE_DCU 0x00F00000 609 #define AR_D_TXBLK_WRITE_DCU_S 20 610 #define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 611 #define AR_D_TXBLK_WRITE_COMMAND_S 24 612 613 #define AR_D_GBL_IFS_SLOT 0x1070 614 #define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 615 #define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 616 617 #define AR_D_GBL_IFS_EIFS 0x10b0 618 #define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 619 #define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 620 #define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363 621 622 #define AR_D_GBL_IFS_MISC 0x10f0 623 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 624 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 625 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 626 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 627 #define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 628 #define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 629 #define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 630 #define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 631 632 #define AR_D_FPCTL 0x1230 633 #define AR_D_FPCTL_DCU 0x0000000F 634 #define AR_D_FPCTL_DCU_S 0 635 #define AR_D_FPCTL_PREFETCH_EN 0x00000010 636 #define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 637 #define AR_D_FPCTL_BURST_PREFETCH_S 5 638 639 #define AR_D_TXPSE 0x1270 640 #define AR_D_TXPSE_CTRL 0x000003FF 641 #define AR_D_TXPSE_RESV0 0x0000FC00 642 #define AR_D_TXPSE_STATUS 0x00010000 643 #define AR_D_TXPSE_RESV1 0xFFFE0000 644 645 #define AR_D_TXSLOTMASK 0x12f0 646 #define AR_D_TXSLOTMASK_NUM 0x0000000F 647 648 #define AR_CFG_LED 0x1f04 649 #define AR_CFG_SCLK_RATE_IND 0x00000003 650 #define AR_CFG_SCLK_RATE_IND_S 0 651 #define AR_CFG_SCLK_32MHZ 0x00000000 652 #define AR_CFG_SCLK_4MHZ 0x00000001 653 #define AR_CFG_SCLK_1MHZ 0x00000002 654 #define AR_CFG_SCLK_32KHZ 0x00000003 655 #define AR_CFG_LED_BLINK_SLOW 0x00000008 656 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 657 #define AR_CFG_LED_MODE_SEL 0x00000380 658 #define AR_CFG_LED_MODE_SEL_S 7 659 #define AR_CFG_LED_POWER 0x00000280 660 #define AR_CFG_LED_POWER_S 7 661 #define AR_CFG_LED_NETWORK 0x00000300 662 #define AR_CFG_LED_NETWORK_S 7 663 #define AR_CFG_LED_MODE_PROP 0x0 664 #define AR_CFG_LED_MODE_RPROP 0x1 665 #define AR_CFG_LED_MODE_SPLIT 0x2 666 #define AR_CFG_LED_MODE_RAND 0x3 667 #define AR_CFG_LED_MODE_POWER_OFF 0x4 668 #define AR_CFG_LED_MODE_POWER_ON 0x5 669 #define AR_CFG_LED_MODE_NETWORK_OFF 0x4 670 #define AR_CFG_LED_MODE_NETWORK_ON 0x6 671 #define AR_CFG_LED_ASSOC_CTL 0x00000c00 672 #define AR_CFG_LED_ASSOC_CTL_S 10 673 #define AR_CFG_LED_ASSOC_NONE 0x0 674 #define AR_CFG_LED_ASSOC_ACTIVE 0x1 675 #define AR_CFG_LED_ASSOC_PENDING 0x2 676 677 #define AR_CFG_LED_BLINK_SLOW 0x00000008 678 #define AR_CFG_LED_BLINK_SLOW_S 3 679 680 #define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 681 #define AR_CFG_LED_BLINK_THRESH_SEL_S 4 682 683 #define AR_MAC_SLEEP 0x1f00 684 #define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 685 #define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 686 687 #define AR_RC 0x4000 688 #define AR_RC_AHB 0x00000001 689 #define AR_RC_APB 0x00000002 690 #define AR_RC_HOSTIF 0x00000100 691 692 #define AR_WA (AR_SREV_9340(ah) ? 0x40c4 : 0x4004) 693 #define AR_WA_BIT6 (1 << 6) 694 #define AR_WA_BIT7 (1 << 7) 695 #define AR_WA_BIT23 (1 << 23) 696 #define AR_WA_D3_L1_DISABLE (1 << 14) 697 #define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset 698 to POR (power-on-reset) */ 699 #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 700 #define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 701 #define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to 702 POR (bit 15) */ 703 #define AR_WA_ANALOG_SHIFT (1 << 20) 704 #define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 705 #define AR_WA_BIT22 (1 << 22) 706 #define AR9285_WA_DEFAULT 0x004a050b 707 #define AR9280_WA_DEFAULT 0x0040073b 708 #define AR_WA_DEFAULT 0x0000073f 709 710 711 #define AR_PM_STATE 0x4008 712 #define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 713 714 #define AR_HOST_TIMEOUT (AR_SREV_9340(ah) ? 0x4008 : 0x4018) 715 #define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 716 #define AR_HOST_TIMEOUT_APB_CNTR_S 0 717 #define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 718 #define AR_HOST_TIMEOUT_LCL_CNTR_S 16 719 720 #define AR_EEPROM 0x401c 721 #define AR_EEPROM_ABSENT 0x00000100 722 #define AR_EEPROM_CORRUPT 0x00000200 723 #define AR_EEPROM_PROT_MASK 0x03FFFC00 724 #define AR_EEPROM_PROT_MASK_S 10 725 726 #define EEPROM_PROTECT_RP_0_31 0x0001 727 #define EEPROM_PROTECT_WP_0_31 0x0002 728 #define EEPROM_PROTECT_RP_32_63 0x0004 729 #define EEPROM_PROTECT_WP_32_63 0x0008 730 #define EEPROM_PROTECT_RP_64_127 0x0010 731 #define EEPROM_PROTECT_WP_64_127 0x0020 732 #define EEPROM_PROTECT_RP_128_191 0x0040 733 #define EEPROM_PROTECT_WP_128_191 0x0080 734 #define EEPROM_PROTECT_RP_192_255 0x0100 735 #define EEPROM_PROTECT_WP_192_255 0x0200 736 #define EEPROM_PROTECT_RP_256_511 0x0400 737 #define EEPROM_PROTECT_WP_256_511 0x0800 738 #define EEPROM_PROTECT_RP_512_1023 0x1000 739 #define EEPROM_PROTECT_WP_512_1023 0x2000 740 #define EEPROM_PROTECT_RP_1024_2047 0x4000 741 #define EEPROM_PROTECT_WP_1024_2047 0x8000 742 743 #define AR_SREV \ 744 ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \ 745 ? 0x400c : 0x4020)) 746 747 #define AR_SREV_ID \ 748 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 749 #define AR_SREV_VERSION 0x000000F0 750 #define AR_SREV_VERSION_S 4 751 #define AR_SREV_REVISION 0x00000007 752 753 #define AR_SREV_ID2 0xFFFFFFFF 754 #define AR_SREV_VERSION2 0xFFFC0000 755 #define AR_SREV_VERSION2_S 18 756 #define AR_SREV_TYPE2 0x0003F000 757 #define AR_SREV_TYPE2_S 12 758 #define AR_SREV_TYPE2_CHAIN 0x00001000 759 #define AR_SREV_TYPE2_HOST_MODE 0x00002000 760 #define AR_SREV_REVISION2 0x00000F00 761 #define AR_SREV_REVISION2_S 8 762 763 #define AR_SREV_VERSION_5416_PCI 0xD 764 #define AR_SREV_VERSION_5416_PCIE 0xC 765 #define AR_SREV_REVISION_5416_10 0 766 #define AR_SREV_REVISION_5416_20 1 767 #define AR_SREV_REVISION_5416_22 2 768 #define AR_SREV_VERSION_9100 0x14 769 #define AR_SREV_VERSION_9160 0x40 770 #define AR_SREV_REVISION_9160_10 0 771 #define AR_SREV_REVISION_9160_11 1 772 #define AR_SREV_VERSION_9280 0x80 773 #define AR_SREV_REVISION_9280_10 0 774 #define AR_SREV_REVISION_9280_20 1 775 #define AR_SREV_REVISION_9280_21 2 776 #define AR_SREV_VERSION_9285 0xC0 777 #define AR_SREV_REVISION_9285_10 0 778 #define AR_SREV_REVISION_9285_11 1 779 #define AR_SREV_REVISION_9285_12 2 780 #define AR_SREV_VERSION_9287 0x180 781 #define AR_SREV_REVISION_9287_10 0 782 #define AR_SREV_REVISION_9287_11 1 783 #define AR_SREV_REVISION_9287_12 2 784 #define AR_SREV_REVISION_9287_13 3 785 #define AR_SREV_VERSION_9271 0x140 786 #define AR_SREV_REVISION_9271_10 0 787 #define AR_SREV_REVISION_9271_11 1 788 #define AR_SREV_VERSION_9300 0x1c0 789 #define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 790 #define AR_SREV_REVISION_9300_22 3 791 #define AR_SREV_VERSION_9330 0x200 792 #define AR_SREV_REVISION_9330_10 0 793 #define AR_SREV_REVISION_9330_11 1 794 #define AR_SREV_REVISION_9330_12 2 795 #define AR_SREV_VERSION_9485 0x240 796 #define AR_SREV_REVISION_9485_10 0 797 #define AR_SREV_REVISION_9485_11 1 798 #define AR_SREV_VERSION_9340 0x300 799 #define AR_SREV_REVISION_9340_10 0 800 #define AR_SREV_REVISION_9340_11 1 801 #define AR_SREV_REVISION_9340_12 2 802 #define AR_SREV_REVISION_9340_13 3 803 #define AR_SREV_VERSION_9580 0x1C0 804 #define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ 805 #define AR_SREV_VERSION_9462 0x280 806 #define AR_SREV_REVISION_9462_20 2 807 #define AR_SREV_REVISION_9462_21 3 808 #define AR_SREV_VERSION_9565 0x2C0 809 #define AR_SREV_REVISION_9565_10 0 810 #define AR_SREV_REVISION_9565_101 1 811 #define AR_SREV_REVISION_9565_11 2 812 #define AR_SREV_VERSION_9550 0x400 813 #define AR_SREV_VERSION_9531 0x500 814 #define AR_SREV_REVISION_9531_10 0 815 #define AR_SREV_REVISION_9531_11 1 816 #define AR_SREV_REVISION_9531_20 2 817 818 #define AR_SREV_5416(_ah) \ 819 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 820 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)) 821 #define AR_SREV_5416_22_OR_LATER(_ah) \ 822 (((AR_SREV_5416(_ah)) && \ 823 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \ 824 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 825 826 #define AR_SREV_9100(ah) \ 827 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) 828 #define AR_SREV_9100_OR_LATER(_ah) \ 829 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 830 831 #define AR_SREV_9160(_ah) \ 832 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) 833 #define AR_SREV_9160_10_OR_LATER(_ah) \ 834 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) 835 #define AR_SREV_9160_11(_ah) \ 836 (AR_SREV_9160(_ah) && \ 837 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) 838 #define AR_SREV_9280(_ah) \ 839 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 840 #define AR_SREV_9280_20_OR_LATER(_ah) \ 841 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) 842 #define AR_SREV_9280_20(_ah) \ 843 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 844 845 #define AR_SREV_9285(_ah) \ 846 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) 847 #define AR_SREV_9285_12_OR_LATER(_ah) \ 848 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) 849 850 #define AR_SREV_9287(_ah) \ 851 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) 852 #define AR_SREV_9287_11_OR_LATER(_ah) \ 853 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) 854 #define AR_SREV_9287_11(_ah) \ 855 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 856 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) 857 #define AR_SREV_9287_12(_ah) \ 858 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 859 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) 860 #define AR_SREV_9287_12_OR_LATER(_ah) \ 861 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 862 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 863 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12))) 864 #define AR_SREV_9287_13_OR_LATER(_ah) \ 865 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 866 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 867 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13))) 868 869 #define AR_SREV_9271(_ah) \ 870 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271) 871 #define AR_SREV_9271_10(_ah) \ 872 (AR_SREV_9271(_ah) && \ 873 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10)) 874 #define AR_SREV_9271_11(_ah) \ 875 (AR_SREV_9271(_ah) && \ 876 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) 877 878 #define AR_SREV_9300(_ah) \ 879 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300)) 880 #define AR_SREV_9300_20_OR_LATER(_ah) \ 881 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9300) 882 #define AR_SREV_9300_22(_ah) \ 883 (AR_SREV_9300(ah) && \ 884 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_22)) 885 886 #define AR_SREV_9330(_ah) \ 887 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9330)) 888 #define AR_SREV_9330_11(_ah) \ 889 (AR_SREV_9330((_ah)) && \ 890 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_11)) 891 #define AR_SREV_9330_12(_ah) \ 892 (AR_SREV_9330((_ah)) && \ 893 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9330_12)) 894 895 #define AR_SREV_9485(_ah) \ 896 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485)) 897 #define AR_SREV_9485_11_OR_LATER(_ah) \ 898 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485) && \ 899 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9485_11)) 900 #define AR_SREV_9485_OR_LATER(_ah) \ 901 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9485)) 902 903 #define AR_SREV_9340(_ah) \ 904 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340)) 905 906 #define AR_SREV_9340_13(_ah) \ 907 (AR_SREV_9340((_ah)) && \ 908 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9340_13)) 909 910 #define AR_SREV_9340_13_OR_LATER(_ah) \ 911 (AR_SREV_9340((_ah)) && \ 912 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13)) 913 914 #define AR_SREV_9285E_20(_ah) \ 915 (AR_SREV_9285_12_OR_LATER(_ah) && \ 916 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 917 918 #define AR_SREV_9462(_ah) \ 919 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462)) 920 #define AR_SREV_9462_20(_ah) \ 921 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 922 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_20)) 923 #define AR_SREV_9462_21(_ah) \ 924 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 925 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9462_21)) 926 #define AR_SREV_9462_20_OR_LATER(_ah) \ 927 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 928 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_20)) 929 #define AR_SREV_9462_21_OR_LATER(_ah) \ 930 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9462) && \ 931 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9462_21)) 932 933 #define AR_SREV_9565(_ah) \ 934 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565)) 935 #define AR_SREV_9565_10(_ah) \ 936 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ 937 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_10)) 938 #define AR_SREV_9565_101(_ah) \ 939 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ 940 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_101)) 941 #define AR_SREV_9565_11(_ah) \ 942 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ 943 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9565_11)) 944 #define AR_SREV_9565_11_OR_LATER(_ah) \ 945 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9565) && \ 946 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9565_11)) 947 948 #define AR_SREV_9550(_ah) \ 949 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9550)) 950 951 #define AR_SREV_9580(_ah) \ 952 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ 953 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9580_10)) 954 #define AR_SREV_9580_10(_ah) \ 955 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9580) && \ 956 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9580_10)) 957 958 #define AR_SREV_9531(_ah) \ 959 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531)) 960 #define AR_SREV_9531_10(_ah) \ 961 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ 962 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_10)) 963 #define AR_SREV_9531_11(_ah) \ 964 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ 965 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_11)) 966 #define AR_SREV_9531_20(_ah) \ 967 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \ 968 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_20)) 969 970 /* NOTE: When adding chips newer than Peacock, add chip check here */ 971 #define AR_SREV_9580_10_OR_LATER(_ah) \ 972 (AR_SREV_9580(_ah)) 973 974 enum ath_usb_dev { 975 AR9280_USB = 1, /* AR7010 + AR9280, UB94 */ 976 AR9287_USB = 2, /* AR7010 + AR9287, UB95 */ 977 STORAGE_DEVICE = 3, 978 }; 979 980 #define AR_DEVID_7010(_ah) \ 981 (((_ah)->hw_version.usbdev == AR9280_USB) || \ 982 ((_ah)->hw_version.usbdev == AR9287_USB)) 983 984 #define AR_RADIO_SREV_MAJOR 0xf0 985 #define AR_RAD5133_SREV_MAJOR 0xc0 986 #define AR_RAD2133_SREV_MAJOR 0xd0 987 #define AR_RAD5122_SREV_MAJOR 0xe0 988 #define AR_RAD2122_SREV_MAJOR 0xf0 989 990 #define AR_AHB_MODE 0x4024 991 #define AR_AHB_EXACT_WR_EN 0x00000000 992 #define AR_AHB_BUF_WR_EN 0x00000001 993 #define AR_AHB_EXACT_RD_EN 0x00000000 994 #define AR_AHB_CACHELINE_RD_EN 0x00000002 995 #define AR_AHB_PREFETCH_RD_EN 0x00000004 996 #define AR_AHB_PAGE_SIZE_1K 0x00000000 997 #define AR_AHB_PAGE_SIZE_2K 0x00000008 998 #define AR_AHB_PAGE_SIZE_4K 0x00000010 999 #define AR_AHB_CUSTOM_BURST_EN 0x000000C0 1000 #define AR_AHB_CUSTOM_BURST_EN_S 6 1001 #define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 1002 1003 #define AR_INTR_RTC_IRQ 0x00000001 1004 #define AR_INTR_MAC_IRQ 0x00000002 1005 #define AR_INTR_EEP_PROT_ACCESS 0x00000004 1006 #define AR_INTR_MAC_AWAKE 0x00020000 1007 #define AR_INTR_MAC_ASLEEP 0x00040000 1008 #define AR_INTR_SPURIOUS 0xFFFFFFFF 1009 1010 1011 #define AR_INTR_SYNC_CAUSE (AR_SREV_9340(ah) ? 0x4010 : 0x4028) 1012 #define AR_INTR_SYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4010 : 0x4028) 1013 1014 1015 #define AR_INTR_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4014 : 0x402c) 1016 #define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 1017 #define AR_INTR_SYNC_ENABLE_GPIO_S 18 1018 1019 enum { 1020 AR_INTR_SYNC_RTC_IRQ = 0x00000001, 1021 AR_INTR_SYNC_MAC_IRQ = 0x00000002, 1022 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 1023 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, 1024 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 1025 AR_INTR_SYNC_HOST1_FATAL = 0x00000020, 1026 AR_INTR_SYNC_HOST1_PERR = 0x00000040, 1027 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 1028 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, 1029 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 1030 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 1031 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 1032 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 1033 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 1034 AR_INTR_SYNC_PM_ACCESS = 0x00004000, 1035 AR_INTR_SYNC_MAC_AWAKE = 0x00008000, 1036 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, 1037 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 1038 AR_INTR_SYNC_ALL = 0x0003FFFF, 1039 1040 1041 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | 1042 AR_INTR_SYNC_HOST1_PERR | 1043 AR_INTR_SYNC_RADM_CPL_EP | 1044 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | 1045 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | 1046 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | 1047 AR_INTR_SYNC_RADM_CPL_TIMEOUT | 1048 AR_INTR_SYNC_LOCAL_TIMEOUT | 1049 AR_INTR_SYNC_MAC_SLEEP_ACCESS), 1050 1051 AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010, 1052 1053 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 1054 1055 }; 1056 1057 #define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030) 1058 #define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 1059 #define AR_INTR_ASYNC_MASK_GPIO_S 18 1060 #define AR_INTR_ASYNC_MASK_MCI 0x00000080 1061 #define AR_INTR_ASYNC_MASK_MCI_S 7 1062 1063 #define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034) 1064 #define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 1065 #define AR_INTR_SYNC_MASK_GPIO_S 18 1066 1067 #define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038) 1068 #define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038) 1069 #define AR_INTR_ASYNC_CAUSE_MCI 0x00000080 1070 #define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \ 1071 AR_INTR_ASYNC_CAUSE_MCI) 1072 1073 /* Asynchronous Interrupt Enable Register */ 1074 #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080 1075 #define AR_INTR_ASYNC_ENABLE_MCI_S 7 1076 1077 1078 #define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c) 1079 #define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 1080 #define AR_INTR_ASYNC_ENABLE_GPIO_S 18 1081 1082 #define AR_PCIE_SERDES 0x4040 1083 #define AR_PCIE_SERDES2 0x4044 1084 #define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014) 1085 #define AR_PCIE_PM_CTRL_ENA 0x00080000 1086 1087 #define AR_PCIE_PHY_REG3 0x18c08 1088 1089 #define AR_NUM_GPIO 14 1090 #define AR928X_NUM_GPIO 10 1091 #define AR9285_NUM_GPIO 12 1092 #define AR9287_NUM_GPIO 11 1093 #define AR9271_NUM_GPIO 16 1094 #define AR9300_NUM_GPIO 17 1095 #define AR7010_NUM_GPIO 16 1096 1097 #define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048) 1098 #define AR_GPIO_IN_VAL 0x0FFFC000 1099 #define AR_GPIO_IN_VAL_S 14 1100 #define AR928X_GPIO_IN_VAL 0x000FFC00 1101 #define AR928X_GPIO_IN_VAL_S 10 1102 #define AR9285_GPIO_IN_VAL 0x00FFF000 1103 #define AR9285_GPIO_IN_VAL_S 12 1104 #define AR9287_GPIO_IN_VAL 0x003FF800 1105 #define AR9287_GPIO_IN_VAL_S 11 1106 #define AR9271_GPIO_IN_VAL 0xFFFF0000 1107 #define AR9271_GPIO_IN_VAL_S 16 1108 #define AR7010_GPIO_IN_VAL 0x0000FFFF 1109 #define AR7010_GPIO_IN_VAL_S 0 1110 1111 #define AR_GPIO_IN (AR_SREV_9340(ah) ? 0x402c : 0x404c) 1112 #define AR9300_GPIO_IN_VAL 0x0001FFFF 1113 #define AR9300_GPIO_IN_VAL_S 0 1114 1115 #define AR_GPIO_OE_OUT (AR_SREV_9340(ah) ? 0x4030 : \ 1116 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c)) 1117 #define AR_GPIO_OE_OUT_DRV 0x3 1118 #define AR_GPIO_OE_OUT_DRV_NO 0x0 1119 #define AR_GPIO_OE_OUT_DRV_LOW 0x1 1120 #define AR_GPIO_OE_OUT_DRV_HI 0x2 1121 #define AR_GPIO_OE_OUT_DRV_ALL 0x3 1122 1123 #define AR7010_GPIO_OE 0x52000 1124 #define AR7010_GPIO_OE_MASK 0x1 1125 #define AR7010_GPIO_OE_AS_OUTPUT 0x0 1126 #define AR7010_GPIO_OE_AS_INPUT 0x1 1127 #define AR7010_GPIO_IN 0x52004 1128 #define AR7010_GPIO_OUT 0x52008 1129 #define AR7010_GPIO_SET 0x5200C 1130 #define AR7010_GPIO_CLEAR 0x52010 1131 #define AR7010_GPIO_INT 0x52014 1132 #define AR7010_GPIO_INT_TYPE 0x52018 1133 #define AR7010_GPIO_INT_POLARITY 0x5201C 1134 #define AR7010_GPIO_PENDING 0x52020 1135 #define AR7010_GPIO_INT_MASK 0x52024 1136 #define AR7010_GPIO_FUNCTION 0x52028 1137 1138 #define AR_GPIO_INTR_POL (AR_SREV_9340(ah) ? 0x4038 : \ 1139 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050)) 1140 #define AR_GPIO_INTR_POL_VAL 0x0001FFFF 1141 #define AR_GPIO_INTR_POL_VAL_S 0 1142 1143 #define AR_GPIO_INPUT_EN_VAL (AR_SREV_9340(ah) ? 0x403c : \ 1144 (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054)) 1145 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1146 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1147 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1148 #define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 1149 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 1150 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 1151 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 1152 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 1153 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 1154 #define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 1155 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 1156 #define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 1157 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 1158 #define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 1159 #define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1160 #define AR_GPIO_JTAG_DISABLE 0x00020000 1161 1162 #define AR_GPIO_INPUT_MUX1 (AR_SREV_9340(ah) ? 0x4040 : \ 1163 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058)) 1164 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1165 #define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1166 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1167 #define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1168 1169 #define AR_GPIO_INPUT_MUX2 (AR_SREV_9340(ah) ? 0x4044 : \ 1170 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c)) 1171 #define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1172 #define AR_GPIO_INPUT_MUX2_CLK25_S 0 1173 #define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1174 #define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 1175 #define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1176 #define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1177 1178 #define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9340(ah) ? 0x4048 : \ 1179 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060)) 1180 #define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9340(ah) ? 0x404c : \ 1181 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064)) 1182 #define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9340(ah) ? 0x4050 : \ 1183 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068)) 1184 1185 #define AR_INPUT_STATE (AR_SREV_9340(ah) ? 0x4054 : \ 1186 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c)) 1187 1188 #define AR_EEPROM_STATUS_DATA (AR_SREV_9340(ah) ? 0x40c8 : \ 1189 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c)) 1190 #define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1191 #define AR_EEPROM_STATUS_DATA_VAL_S 0 1192 #define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1193 #define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1194 #define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1195 #define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1196 1197 #define AR_OBS (AR_SREV_9340(ah) ? 0x405c : \ 1198 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080)) 1199 1200 #define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088) 1201 1202 #define AR_PCIE_MSI (AR_SREV_9340(ah) ? 0x40d8 : \ 1203 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094)) 1204 #define AR_PCIE_MSI_ENABLE 0x00000001 1205 1206 #define AR_INTR_PRIO_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4088 : 0x40c4) 1207 #define AR_INTR_PRIO_ASYNC_MASK (AR_SREV_9340(ah) ? 0x408c : 0x40c8) 1208 #define AR_INTR_PRIO_SYNC_MASK (AR_SREV_9340(ah) ? 0x4090 : 0x40cc) 1209 #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4) 1210 #define AR_ENT_OTP 0x40d8 1211 #define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000 1212 #define AR_ENT_OTP_49GHZ_DISABLE 0x00100000 1213 #define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000 1214 1215 #define AR_CH0_BB_DPLL1 0x16180 1216 #define AR_CH0_BB_DPLL1_REFDIV 0xF8000000 1217 #define AR_CH0_BB_DPLL1_REFDIV_S 27 1218 #define AR_CH0_BB_DPLL1_NINI 0x07FC0000 1219 #define AR_CH0_BB_DPLL1_NINI_S 18 1220 #define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF 1221 #define AR_CH0_BB_DPLL1_NFRAC_S 0 1222 1223 #define AR_CH0_BB_DPLL2 0x16184 1224 #define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000 1225 #define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30 1226 #define AR_CH0_DPLL2_KI 0x3C000000 1227 #define AR_CH0_DPLL2_KI_S 26 1228 #define AR_CH0_DPLL2_KD 0x03F80000 1229 #define AR_CH0_DPLL2_KD_S 19 1230 #define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000 1231 #define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18 1232 #define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000 1233 #define AR_CH0_BB_DPLL2_PLL_PWD_S 16 1234 #define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000 1235 #define AR_CH0_BB_DPLL2_OUTDIV_S 13 1236 1237 #define AR_CH0_BB_DPLL3 0x16188 1238 #define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000 1239 #define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23 1240 1241 #define AR_CH0_DDR_DPLL2 0x16244 1242 #define AR_CH0_DDR_DPLL3 0x16248 1243 #define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000 1244 #define AR_CH0_DPLL3_PHASE_SHIFT_S 23 1245 #define AR_PHY_CCA_NOM_VAL_2GHZ -118 1246 1247 #define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f 1248 #define AR_RTC_9300_SOC_PLL_DIV_INT_S 0 1249 #define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0 1250 #define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6 1251 #define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000 1252 #define AR_RTC_9300_SOC_PLL_REFDIV_S 20 1253 #define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000 1254 #define AR_RTC_9300_SOC_PLL_CLKSEL_S 25 1255 #define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000 1256 1257 #define AR_RTC_9300_PLL_DIV 0x000003ff 1258 #define AR_RTC_9300_PLL_DIV_S 0 1259 #define AR_RTC_9300_PLL_REFDIV 0x00003C00 1260 #define AR_RTC_9300_PLL_REFDIV_S 10 1261 #define AR_RTC_9300_PLL_CLKSEL 0x0000C000 1262 #define AR_RTC_9300_PLL_CLKSEL_S 14 1263 #define AR_RTC_9300_PLL_BYPASS 0x00010000 1264 1265 #define AR_RTC_9160_PLL_DIV 0x000003ff 1266 #define AR_RTC_9160_PLL_DIV_S 0 1267 #define AR_RTC_9160_PLL_REFDIV 0x00003C00 1268 #define AR_RTC_9160_PLL_REFDIV_S 10 1269 #define AR_RTC_9160_PLL_CLKSEL 0x0000C000 1270 #define AR_RTC_9160_PLL_CLKSEL_S 14 1271 1272 #define AR_RTC_BASE 0x00020000 1273 #define AR_RTC_RC \ 1274 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000) 1275 #define AR_RTC_RC_M 0x00000003 1276 #define AR_RTC_RC_MAC_WARM 0x00000001 1277 #define AR_RTC_RC_MAC_COLD 0x00000002 1278 #define AR_RTC_RC_COLD_RESET 0x00000004 1279 #define AR_RTC_RC_WARM_RESET 0x00000008 1280 1281 /* Crystal Control */ 1282 #define AR_RTC_XTAL_CONTROL 0x7004 1283 1284 /* Reg Control 0 */ 1285 #define AR_RTC_REG_CONTROL0 0x7008 1286 1287 /* Reg Control 1 */ 1288 #define AR_RTC_REG_CONTROL1 0x700c 1289 #define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 1290 1291 #define AR_RTC_PLL_CONTROL \ 1292 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1293 1294 #define AR_RTC_PLL_CONTROL2 0x703c 1295 1296 #define AR_RTC_PLL_DIV 0x0000001f 1297 #define AR_RTC_PLL_DIV_S 0 1298 #define AR_RTC_PLL_DIV2 0x00000020 1299 #define AR_RTC_PLL_REFDIV_5 0x000000c0 1300 #define AR_RTC_PLL_CLKSEL 0x00000300 1301 #define AR_RTC_PLL_CLKSEL_S 8 1302 #define AR_RTC_PLL_BYPASS 0x00010000 1303 #define AR_RTC_PLL_NOPWD 0x00040000 1304 #define AR_RTC_PLL_NOPWD_S 18 1305 1306 #define PLL3 0x16188 1307 #define PLL3_DO_MEAS_MASK 0x40000000 1308 #define PLL4 0x1618c 1309 #define PLL4_MEAS_DONE 0x8 1310 #define SQSUM_DVC_MASK 0x007ffff8 1311 1312 #define AR_RTC_RESET \ 1313 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1314 #define AR_RTC_RESET_EN (0x00000001) 1315 1316 #define AR_RTC_STATUS \ 1317 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) 1318 1319 #define AR_RTC_STATUS_M \ 1320 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) 1321 1322 #define AR_RTC_PM_STATUS_M 0x0000000f 1323 1324 #define AR_RTC_STATUS_SHUTDOWN 0x00000001 1325 #define AR_RTC_STATUS_ON 0x00000002 1326 #define AR_RTC_STATUS_SLEEP 0x00000004 1327 #define AR_RTC_STATUS_WAKEUP 0x00000008 1328 1329 #define AR_RTC_SLEEP_CLK \ 1330 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 1331 #define AR_RTC_FORCE_DERIVED_CLK 0x2 1332 #define AR_RTC_FORCE_SWREG_PRD 0x00000004 1333 1334 #define AR_RTC_FORCE_WAKE \ 1335 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 1336 #define AR_RTC_FORCE_WAKE_EN 0x00000001 1337 #define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 1338 1339 1340 #define AR_RTC_INTR_CAUSE \ 1341 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) 1342 1343 #define AR_RTC_INTR_ENABLE \ 1344 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) 1345 1346 #define AR_RTC_INTR_MASK \ 1347 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) 1348 1349 #define AR_RTC_KEEP_AWAKE 0x7034 1350 1351 /* RTC_DERIVED_* - only for AR9100 */ 1352 1353 #define AR_RTC_DERIVED_CLK \ 1354 (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038) 1355 #define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1356 #define AR_RTC_DERIVED_CLK_PERIOD_S 1 1357 1358 #define AR_SEQ_MASK 0x8060 1359 1360 #define AR_AN_RF2G1_CH0 0x7810 1361 #define AR_AN_RF2G1_CH0_OB 0x03800000 1362 #define AR_AN_RF2G1_CH0_OB_S 23 1363 #define AR_AN_RF2G1_CH0_DB 0x1C000000 1364 #define AR_AN_RF2G1_CH0_DB_S 26 1365 1366 #define AR_AN_RF5G1_CH0 0x7818 1367 #define AR_AN_RF5G1_CH0_OB5 0x00070000 1368 #define AR_AN_RF5G1_CH0_OB5_S 16 1369 #define AR_AN_RF5G1_CH0_DB5 0x00380000 1370 #define AR_AN_RF5G1_CH0_DB5_S 19 1371 1372 #define AR_AN_RF2G1_CH1 0x7834 1373 #define AR_AN_RF2G1_CH1_OB 0x03800000 1374 #define AR_AN_RF2G1_CH1_OB_S 23 1375 #define AR_AN_RF2G1_CH1_DB 0x1C000000 1376 #define AR_AN_RF2G1_CH1_DB_S 26 1377 1378 #define AR_AN_RF5G1_CH1 0x783C 1379 #define AR_AN_RF5G1_CH1_OB5 0x00070000 1380 #define AR_AN_RF5G1_CH1_OB5_S 16 1381 #define AR_AN_RF5G1_CH1_DB5 0x00380000 1382 #define AR_AN_RF5G1_CH1_DB5_S 19 1383 1384 #define AR_AN_TOP1 0x7890 1385 #define AR_AN_TOP1_DACIPMODE 0x00040000 1386 #define AR_AN_TOP1_DACIPMODE_S 18 1387 1388 #define AR_AN_TOP2 0x7894 1389 #define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1390 #define AR_AN_TOP2_XPABIAS_LVL_S 30 1391 #define AR_AN_TOP2_LOCALBIAS 0x00200000 1392 #define AR_AN_TOP2_LOCALBIAS_S 21 1393 #define AR_AN_TOP2_PWDCLKIND 0x00400000 1394 #define AR_AN_TOP2_PWDCLKIND_S 22 1395 1396 #define AR_AN_SYNTH9 0x7868 1397 #define AR_AN_SYNTH9_REFDIVA 0xf8000000 1398 #define AR_AN_SYNTH9_REFDIVA_S 27 1399 1400 #define AR9285_AN_RF2G1 0x7820 1401 #define AR9285_AN_RF2G1_ENPACAL 0x00000800 1402 #define AR9285_AN_RF2G1_ENPACAL_S 11 1403 #define AR9285_AN_RF2G1_PDPADRV1 0x02000000 1404 #define AR9285_AN_RF2G1_PDPADRV1_S 25 1405 #define AR9285_AN_RF2G1_PDPADRV2 0x01000000 1406 #define AR9285_AN_RF2G1_PDPADRV2_S 24 1407 #define AR9285_AN_RF2G1_PDPAOUT 0x00800000 1408 #define AR9285_AN_RF2G1_PDPAOUT_S 23 1409 1410 1411 #define AR9285_AN_RF2G2 0x7824 1412 #define AR9285_AN_RF2G2_OFFCAL 0x00001000 1413 #define AR9285_AN_RF2G2_OFFCAL_S 12 1414 1415 #define AR9285_AN_RF2G3 0x7828 1416 #define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 1417 #define AR9285_AN_RF2G3_PDVCCOMP_S 25 1418 #define AR9285_AN_RF2G3_OB_0 0x00E00000 1419 #define AR9285_AN_RF2G3_OB_0_S 21 1420 #define AR9285_AN_RF2G3_OB_1 0x001C0000 1421 #define AR9285_AN_RF2G3_OB_1_S 18 1422 #define AR9285_AN_RF2G3_OB_2 0x00038000 1423 #define AR9285_AN_RF2G3_OB_2_S 15 1424 #define AR9285_AN_RF2G3_OB_3 0x00007000 1425 #define AR9285_AN_RF2G3_OB_3_S 12 1426 #define AR9285_AN_RF2G3_OB_4 0x00000E00 1427 #define AR9285_AN_RF2G3_OB_4_S 9 1428 1429 #define AR9285_AN_RF2G3_DB1_0 0x000001C0 1430 #define AR9285_AN_RF2G3_DB1_0_S 6 1431 #define AR9285_AN_RF2G3_DB1_1 0x00000038 1432 #define AR9285_AN_RF2G3_DB1_1_S 3 1433 #define AR9285_AN_RF2G3_DB1_2 0x00000007 1434 #define AR9285_AN_RF2G3_DB1_2_S 0 1435 #define AR9285_AN_RF2G4 0x782C 1436 #define AR9285_AN_RF2G4_DB1_3 0xE0000000 1437 #define AR9285_AN_RF2G4_DB1_3_S 29 1438 #define AR9285_AN_RF2G4_DB1_4 0x1C000000 1439 #define AR9285_AN_RF2G4_DB1_4_S 26 1440 1441 #define AR9285_AN_RF2G4_DB2_0 0x03800000 1442 #define AR9285_AN_RF2G4_DB2_0_S 23 1443 #define AR9285_AN_RF2G4_DB2_1 0x00700000 1444 #define AR9285_AN_RF2G4_DB2_1_S 20 1445 #define AR9285_AN_RF2G4_DB2_2 0x000E0000 1446 #define AR9285_AN_RF2G4_DB2_2_S 17 1447 #define AR9285_AN_RF2G4_DB2_3 0x0001C000 1448 #define AR9285_AN_RF2G4_DB2_3_S 14 1449 #define AR9285_AN_RF2G4_DB2_4 0x00003800 1450 #define AR9285_AN_RF2G4_DB2_4_S 11 1451 1452 #define AR9285_RF2G5 0x7830 1453 #define AR9285_RF2G5_IC50TX 0xfffff8ff 1454 #define AR9285_RF2G5_IC50TX_SET 0x00000400 1455 #define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 1456 #define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 1457 #define AR9285_RF2G5_IC50TX_CLEAR_S 8 1458 1459 /* AR9271 : 0x7828, 0x782c different setting from AR9285 */ 1460 #define AR9271_AN_RF2G3_OB_cck 0x001C0000 1461 #define AR9271_AN_RF2G3_OB_cck_S 18 1462 #define AR9271_AN_RF2G3_OB_psk 0x00038000 1463 #define AR9271_AN_RF2G3_OB_psk_S 15 1464 #define AR9271_AN_RF2G3_OB_qam 0x00007000 1465 #define AR9271_AN_RF2G3_OB_qam_S 12 1466 1467 #define AR9271_AN_RF2G3_DB_1 0x00E00000 1468 #define AR9271_AN_RF2G3_DB_1_S 21 1469 1470 #define AR9271_AN_RF2G3_CCOMP 0xFFF 1471 #define AR9271_AN_RF2G3_CCOMP_S 0 1472 1473 #define AR9271_AN_RF2G4_DB_2 0xE0000000 1474 #define AR9271_AN_RF2G4_DB_2_S 29 1475 1476 #define AR9285_AN_RF2G6 0x7834 1477 #define AR9285_AN_RF2G6_CCOMP 0x00007800 1478 #define AR9285_AN_RF2G6_CCOMP_S 11 1479 #define AR9285_AN_RF2G6_OFFS 0x03f00000 1480 #define AR9285_AN_RF2G6_OFFS_S 20 1481 1482 #define AR9271_AN_RF2G6_OFFS 0x07f00000 1483 #define AR9271_AN_RF2G6_OFFS_S 20 1484 1485 #define AR9285_AN_RF2G7 0x7838 1486 #define AR9285_AN_RF2G7_PWDDB 0x00000002 1487 #define AR9285_AN_RF2G7_PWDDB_S 1 1488 #define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 1489 #define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 1490 1491 #define AR9285_AN_RF2G8 0x783C 1492 #define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 1493 #define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 1494 1495 1496 #define AR9285_AN_RF2G9 0x7840 1497 #define AR9285_AN_RXTXBB1 0x7854 1498 #define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 1499 #define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 1500 #define AR9285_AN_RXTXBB1_PDV2I 0x00000080 1501 #define AR9285_AN_RXTXBB1_PDV2I_S 7 1502 #define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 1503 #define AR9285_AN_RXTXBB1_PDDACIF_S 8 1504 #define AR9285_AN_RXTXBB1_SPARE9 0x00000001 1505 #define AR9285_AN_RXTXBB1_SPARE9_S 0 1506 1507 #define AR9285_AN_TOP2 0x7868 1508 1509 #define AR9285_AN_TOP3 0x786c 1510 #define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1511 #define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1512 #define AR9285_AN_TOP3_PWDDAC 0x00800000 1513 #define AR9285_AN_TOP3_PWDDAC_S 23 1514 1515 #define AR9285_AN_TOP4 0x7870 1516 #define AR9285_AN_TOP4_DEFAULT 0x10142c00 1517 1518 #define AR9287_AN_RF2G3_CH0 0x7808 1519 #define AR9287_AN_RF2G3_CH1 0x785c 1520 #define AR9287_AN_RF2G3_DB1 0xE0000000 1521 #define AR9287_AN_RF2G3_DB1_S 29 1522 #define AR9287_AN_RF2G3_DB2 0x1C000000 1523 #define AR9287_AN_RF2G3_DB2_S 26 1524 #define AR9287_AN_RF2G3_OB_CCK 0x03800000 1525 #define AR9287_AN_RF2G3_OB_CCK_S 23 1526 #define AR9287_AN_RF2G3_OB_PSK 0x00700000 1527 #define AR9287_AN_RF2G3_OB_PSK_S 20 1528 #define AR9287_AN_RF2G3_OB_QAM 0x000E0000 1529 #define AR9287_AN_RF2G3_OB_QAM_S 17 1530 #define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000 1531 #define AR9287_AN_RF2G3_OB_PAL_OFF_S 14 1532 1533 #define AR9287_AN_TXPC0 0x7898 1534 #define AR9287_AN_TXPC0_TXPCMODE 0x0000C000 1535 #define AR9287_AN_TXPC0_TXPCMODE_S 14 1536 #define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0 1537 #define AR9287_AN_TXPC0_TXPCMODE_TEST 1 1538 #define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2 1539 #define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3 1540 1541 #define AR9287_AN_TOP2 0x78b4 1542 #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 1543 #define AR9287_AN_TOP2_XPABIAS_LVL_S 30 1544 1545 /* AR9271 specific stuff */ 1546 #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 1547 #define AR9271_RADIO_RF_RST 0x20 1548 #define AR9271_GATE_MAC_CTL 0x4000 1549 1550 #define AR_STA_ID1_STA_AP 0x00010000 1551 #define AR_STA_ID1_ADHOC 0x00020000 1552 #define AR_STA_ID1_PWR_SAV 0x00040000 1553 #define AR_STA_ID1_KSRCHDIS 0x00080000 1554 #define AR_STA_ID1_PCF 0x00100000 1555 #define AR_STA_ID1_USE_DEFANT 0x00200000 1556 #define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1557 #define AR_STA_ID1_AR9100_BA_FIX 0x00400000 1558 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 1559 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 1560 #define AR_STA_ID1_BASE_RATE_11B 0x02000000 1561 #define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1562 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1563 #define AR_STA_ID1_KSRCH_MODE 0x10000000 1564 #define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1565 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1566 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 1567 1568 #define AR_BSS_ID0 0x8008 1569 #define AR_BSS_ID1 0x800C 1570 #define AR_BSS_ID1_U16 0x0000FFFF 1571 #define AR_BSS_ID1_AID 0x07FF0000 1572 #define AR_BSS_ID1_AID_S 16 1573 1574 #define AR_BCN_RSSI_AVE 0x8010 1575 #define AR_BCN_RSSI_AVE_MASK 0x00000FFF 1576 1577 #define AR_TIME_OUT 0x8014 1578 #define AR_TIME_OUT_ACK 0x00003FFF 1579 #define AR_TIME_OUT_ACK_S 0 1580 #define AR_TIME_OUT_CTS 0x3FFF0000 1581 #define AR_TIME_OUT_CTS_S 16 1582 1583 #define AR_RSSI_THR 0x8018 1584 #define AR_RSSI_THR_MASK 0x000000FF 1585 #define AR_RSSI_THR_BM_THR 0x0000FF00 1586 #define AR_RSSI_THR_BM_THR_S 8 1587 #define AR_RSSI_BCN_WEIGHT 0x1F000000 1588 #define AR_RSSI_BCN_WEIGHT_S 24 1589 #define AR_RSSI_BCN_RSSI_RST 0x20000000 1590 1591 #define AR_USEC 0x801c 1592 #define AR_USEC_USEC 0x0000007F 1593 #define AR_USEC_TX_LAT 0x007FC000 1594 #define AR_USEC_TX_LAT_S 14 1595 #define AR_USEC_RX_LAT 0x1F800000 1596 #define AR_USEC_RX_LAT_S 23 1597 #define AR_USEC_ASYNC_FIFO 0x12E00074 1598 1599 #define AR_RESET_TSF 0x8020 1600 #define AR_RESET_TSF_ONCE 0x01000000 1601 1602 #define AR_MAX_CFP_DUR 0x8038 1603 #define AR_CFP_VAL 0x0000FFFF 1604 1605 #define AR_RX_FILTER 0x803C 1606 1607 #define AR_MCAST_FIL0 0x8040 1608 #define AR_MCAST_FIL1 0x8044 1609 1610 /* 1611 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. 1612 * 1613 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with 1614 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down 1615 * receive. The force RX abort bit will kill any frame which is currently being 1616 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) 1617 * will prevent any new frames from getting started. 1618 */ 1619 #define AR_DIAG_SW 0x8048 1620 #define AR_DIAG_CACHE_ACK 0x00000001 1621 #define AR_DIAG_ACK_DIS 0x00000002 1622 #define AR_DIAG_CTS_DIS 0x00000004 1623 #define AR_DIAG_ENCRYPT_DIS 0x00000008 1624 #define AR_DIAG_DECRYPT_DIS 0x00000010 1625 #define AR_DIAG_RX_DIS 0x00000020 /* RX block */ 1626 #define AR_DIAG_LOOP_BACK 0x00000040 1627 #define AR_DIAG_CORR_FCS 0x00000080 1628 #define AR_DIAG_CHAN_INFO 0x00000100 1629 #define AR_DIAG_SCRAM_SEED 0x0001FE00 1630 #define AR_DIAG_SCRAM_SEED_S 8 1631 #define AR_DIAG_FRAME_NV0 0x00020000 1632 #define AR_DIAG_OBS_PT_SEL1 0x000C0000 1633 #define AR_DIAG_OBS_PT_SEL1_S 18 1634 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1635 #define AR_DIAG_OBS_PT_SEL2_S 27 1636 #define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ 1637 #define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1638 #define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1639 #define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1640 #define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1641 #define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ 1642 #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1643 #define AR_DIAG_OBS_PT_SEL2 0x08000000 1644 #define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1645 #define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1646 1647 #define AR_TSF_L32 0x804c 1648 #define AR_TSF_U32 0x8050 1649 1650 #define AR_TST_ADDAC 0x8054 1651 #define AR_DEF_ANTENNA 0x8058 1652 1653 #define AR_AES_MUTE_MASK0 0x805c 1654 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1655 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1656 #define AR_AES_MUTE_MASK0_QOS_S 16 1657 1658 #define AR_AES_MUTE_MASK1 0x8060 1659 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1660 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1661 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1662 1663 #define AR_GATED_CLKS 0x8064 1664 #define AR_GATED_CLKS_TX 0x00000002 1665 #define AR_GATED_CLKS_RX 0x00000004 1666 #define AR_GATED_CLKS_REG 0x00000008 1667 1668 #define AR_OBS_BUS_CTRL 0x8068 1669 #define AR_OBS_BUS_SEL_1 0x00040000 1670 #define AR_OBS_BUS_SEL_2 0x00080000 1671 #define AR_OBS_BUS_SEL_3 0x000C0000 1672 #define AR_OBS_BUS_SEL_4 0x08040000 1673 #define AR_OBS_BUS_SEL_5 0x08080000 1674 1675 #define AR_OBS_BUS_1 0x806c 1676 #define AR_OBS_BUS_1_PCU 0x00000001 1677 #define AR_OBS_BUS_1_RX_END 0x00000002 1678 #define AR_OBS_BUS_1_RX_WEP 0x00000004 1679 #define AR_OBS_BUS_1_RX_BEACON 0x00000008 1680 #define AR_OBS_BUS_1_RX_FILTER 0x00000010 1681 #define AR_OBS_BUS_1_TX_HCF 0x00000020 1682 #define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1683 #define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1684 #define AR_OBS_BUS_1_TX_HOLD 0x00000100 1685 #define AR_OBS_BUS_1_TX_FRAME 0x00000200 1686 #define AR_OBS_BUS_1_RX_FRAME 0x00000400 1687 #define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1688 #define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1689 #define AR_OBS_BUS_1_WEP_STATE_S 12 1690 #define AR_OBS_BUS_1_RX_STATE 0x01F00000 1691 #define AR_OBS_BUS_1_RX_STATE_S 20 1692 #define AR_OBS_BUS_1_TX_STATE 0x7E000000 1693 #define AR_OBS_BUS_1_TX_STATE_S 25 1694 1695 #define AR_LAST_TSTP 0x8080 1696 #define AR_NAV 0x8084 1697 #define AR_RTS_OK 0x8088 1698 #define AR_RTS_FAIL 0x808c 1699 #define AR_ACK_FAIL 0x8090 1700 #define AR_FCS_FAIL 0x8094 1701 #define AR_BEACON_CNT 0x8098 1702 1703 #define AR_SLEEP1 0x80d4 1704 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 1705 #define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 1706 #define AR_SLEEP1_CAB_TIMEOUT_S 21 1707 1708 #define AR_SLEEP2 0x80d8 1709 #define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1710 #define AR_SLEEP2_BEACON_TIMEOUT_S 21 1711 1712 #define AR_TPC 0x80e8 1713 #define AR_TPC_ACK 0x0000003f 1714 #define AR_TPC_ACK_S 0 1715 #define AR_TPC_CTS 0x00003f00 1716 #define AR_TPC_CTS_S 8 1717 #define AR_TPC_CHIRP 0x003f0000 1718 #define AR_TPC_CHIRP_S 16 1719 1720 #define AR_QUIET1 0x80fc 1721 #define AR_QUIET1_NEXT_QUIET_S 0 1722 #define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1723 #define AR_QUIET1_QUIET_ENABLE 0x00010000 1724 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1725 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1726 #define AR_QUIET2 0x8100 1727 #define AR_QUIET2_QUIET_PERIOD_S 0 1728 #define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1729 #define AR_QUIET2_QUIET_DUR_S 16 1730 #define AR_QUIET2_QUIET_DUR 0xffff0000 1731 1732 #define AR_TSF_PARM 0x8104 1733 #define AR_TSF_INCREMENT_M 0x000000ff 1734 #define AR_TSF_INCREMENT_S 0x00 1735 1736 #define AR_QOS_NO_ACK 0x8108 1737 #define AR_QOS_NO_ACK_TWO_BIT 0x0000000f 1738 #define AR_QOS_NO_ACK_TWO_BIT_S 0 1739 #define AR_QOS_NO_ACK_BIT_OFF 0x00000070 1740 #define AR_QOS_NO_ACK_BIT_OFF_S 4 1741 #define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 1742 #define AR_QOS_NO_ACK_BYTE_OFF_S 7 1743 1744 #define AR_PHY_ERR 0x810c 1745 1746 #define AR_PHY_ERR_DCHIRP 0x00000008 1747 #define AR_PHY_ERR_RADAR 0x00000020 1748 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 1749 #define AR_PHY_ERR_CCK_TIMING 0x02000000 1750 1751 #define AR_RXFIFO_CFG 0x8114 1752 1753 1754 #define AR_MIC_QOS_CONTROL 0x8118 1755 #define AR_MIC_QOS_SELECT 0x811c 1756 1757 #define AR_PCU_MISC 0x8120 1758 #define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1759 #define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1760 #define AR_PCU_TX_ADD_TSF 0x00000008 1761 #define AR_PCU_CCK_SIFS_MODE 0x00000010 1762 #define AR_PCU_RX_ANT_UPDT 0x00000800 1763 #define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1764 #define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1765 #define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1766 #define AR_PCU_FORCE_QUIET_COLL 0x00040000 1767 #define AR_PCU_TBTT_PROTECT 0x00200000 1768 #define AR_PCU_CLEAR_VMF 0x01000000 1769 #define AR_PCU_CLEAR_BA_VALID 0x04000000 1770 #define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000 1771 1772 #define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1773 #define AR_PCU_BT_ANT_PREVENT_RX_S 20 1774 1775 #define AR_FILT_OFDM 0x8124 1776 #define AR_FILT_OFDM_COUNT 0x00FFFFFF 1777 1778 #define AR_FILT_CCK 0x8128 1779 #define AR_FILT_CCK_COUNT 0x00FFFFFF 1780 1781 #define AR_PHY_ERR_1 0x812c 1782 #define AR_PHY_ERR_1_COUNT 0x00FFFFFF 1783 #define AR_PHY_ERR_MASK_1 0x8130 1784 1785 #define AR_PHY_ERR_2 0x8134 1786 #define AR_PHY_ERR_2_COUNT 0x00FFFFFF 1787 #define AR_PHY_ERR_MASK_2 0x8138 1788 1789 #define AR_PHY_COUNTMAX (3 << 22) 1790 #define AR_MIBCNT_INTRMASK (3 << 22) 1791 1792 #define AR_TSFOOR_THRESHOLD 0x813c 1793 #define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF 1794 1795 #define AR_PHY_ERR_EIFS_MASK 0x8144 1796 1797 #define AR_PHY_ERR_3 0x8168 1798 #define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1799 #define AR_PHY_ERR_MASK_3 0x816c 1800 1801 #define AR_BT_COEX_MODE 0x8170 1802 #define AR_BT_TIME_EXTEND 0x000000ff 1803 #define AR_BT_TIME_EXTEND_S 0 1804 #define AR_BT_TXSTATE_EXTEND 0x00000100 1805 #define AR_BT_TXSTATE_EXTEND_S 8 1806 #define AR_BT_TX_FRAME_EXTEND 0x00000200 1807 #define AR_BT_TX_FRAME_EXTEND_S 9 1808 #define AR_BT_MODE 0x00000c00 1809 #define AR_BT_MODE_S 10 1810 #define AR_BT_QUIET 0x00001000 1811 #define AR_BT_QUIET_S 12 1812 #define AR_BT_QCU_THRESH 0x0001e000 1813 #define AR_BT_QCU_THRESH_S 13 1814 #define AR_BT_RX_CLEAR_POLARITY 0x00020000 1815 #define AR_BT_RX_CLEAR_POLARITY_S 17 1816 #define AR_BT_PRIORITY_TIME 0x00fc0000 1817 #define AR_BT_PRIORITY_TIME_S 18 1818 #define AR_BT_FIRST_SLOT_TIME 0xff000000 1819 #define AR_BT_FIRST_SLOT_TIME_S 24 1820 1821 #define AR_BT_COEX_WEIGHT 0x8174 1822 #define AR_BT_COEX_WGHT 0xff55 1823 #define AR_STOMP_ALL_WLAN_WGHT 0xfcfc 1824 #define AR_STOMP_LOW_WLAN_WGHT 0xa8a8 1825 #define AR_STOMP_NONE_WLAN_WGHT 0x0000 1826 #define AR_BTCOEX_BT_WGHT 0x0000ffff 1827 #define AR_BTCOEX_BT_WGHT_S 0 1828 #define AR_BTCOEX_WL_WGHT 0xffff0000 1829 #define AR_BTCOEX_WL_WGHT_S 16 1830 1831 #define AR_BT_COEX_WL_WEIGHTS0 0x8174 1832 #define AR_BT_COEX_WL_WEIGHTS1 0x81c4 1833 #define AR_MCI_COEX_WL_WEIGHTS(_i) (0x18b0 + (_i << 2)) 1834 #define AR_BT_COEX_BT_WEIGHTS(_i) (0x83ac + (_i << 2)) 1835 1836 #define AR9300_BT_WGHT 0xcccc4444 1837 1838 #define AR_BT_COEX_MODE2 0x817c 1839 #define AR_BT_BCN_MISS_THRESH 0x000000ff 1840 #define AR_BT_BCN_MISS_THRESH_S 0 1841 #define AR_BT_BCN_MISS_CNT 0x0000ff00 1842 #define AR_BT_BCN_MISS_CNT_S 8 1843 #define AR_BT_HOLD_RX_CLEAR 0x00010000 1844 #define AR_BT_HOLD_RX_CLEAR_S 16 1845 #define AR_BT_DISABLE_BT_ANT 0x00100000 1846 #define AR_BT_DISABLE_BT_ANT_S 20 1847 1848 #define AR_TXSIFS 0x81d0 1849 #define AR_TXSIFS_TIME 0x000000FF 1850 #define AR_TXSIFS_TX_LATENCY 0x00000F00 1851 #define AR_TXSIFS_TX_LATENCY_S 8 1852 #define AR_TXSIFS_ACK_SHIFT 0x00007000 1853 #define AR_TXSIFS_ACK_SHIFT_S 12 1854 1855 #define AR_TXOP_X 0x81ec 1856 #define AR_TXOP_X_VAL 0x000000FF 1857 1858 1859 #define AR_TXOP_0_3 0x81f0 1860 #define AR_TXOP_4_7 0x81f4 1861 #define AR_TXOP_8_11 0x81f8 1862 #define AR_TXOP_12_15 0x81fc 1863 1864 #define AR_NEXT_NDP2_TIMER 0x8180 1865 #define AR_GEN_TIMER_BANK_1_LEN 8 1866 #define AR_FIRST_NDP_TIMER 7 1867 #define AR_NDP2_PERIOD 0x81a0 1868 #define AR_NDP2_TIMER_MODE 0x81c0 1869 1870 #define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) 1871 #define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1872 #define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) 1873 #define AR_NEXT_SWBA AR_GEN_TIMERS(2) 1874 #define AR_NEXT_CFP AR_GEN_TIMERS(2) 1875 #define AR_NEXT_HCF AR_GEN_TIMERS(3) 1876 #define AR_NEXT_TIM AR_GEN_TIMERS(4) 1877 #define AR_NEXT_DTIM AR_GEN_TIMERS(5) 1878 #define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) 1879 #define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) 1880 1881 #define AR_BEACON_PERIOD AR_GEN_TIMERS(8) 1882 #define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) 1883 #define AR_SWBA_PERIOD AR_GEN_TIMERS(10) 1884 #define AR_HCF_PERIOD AR_GEN_TIMERS(11) 1885 #define AR_TIM_PERIOD AR_GEN_TIMERS(12) 1886 #define AR_DTIM_PERIOD AR_GEN_TIMERS(13) 1887 #define AR_QUIET_PERIOD AR_GEN_TIMERS(14) 1888 #define AR_NDP_PERIOD AR_GEN_TIMERS(15) 1889 1890 #define AR_TIMER_MODE 0x8240 1891 #define AR_TBTT_TIMER_EN 0x00000001 1892 #define AR_DBA_TIMER_EN 0x00000002 1893 #define AR_SWBA_TIMER_EN 0x00000004 1894 #define AR_HCF_TIMER_EN 0x00000008 1895 #define AR_TIM_TIMER_EN 0x00000010 1896 #define AR_DTIM_TIMER_EN 0x00000020 1897 #define AR_QUIET_TIMER_EN 0x00000040 1898 #define AR_NDP_TIMER_EN 0x00000080 1899 #define AR_TIMER_OVERFLOW_INDEX 0x00000700 1900 #define AR_TIMER_OVERFLOW_INDEX_S 8 1901 #define AR_TIMER_THRESH 0xFFFFF000 1902 #define AR_TIMER_THRESH_S 12 1903 1904 #define AR_SLP32_MODE 0x8244 1905 #define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF 1906 #define AR_SLP32_ENA 0x00100000 1907 #define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1908 1909 #define AR_SLP32_WAKE 0x8248 1910 #define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF 1911 1912 #define AR_SLP32_INC 0x824c 1913 #define AR_SLP32_TST_INC 0x000FFFFF 1914 1915 #define AR_SLP_CNT 0x8250 1916 #define AR_SLP_CYCLE_CNT 0x8254 1917 1918 #define AR_SLP_MIB_CTRL 0x8258 1919 #define AR_SLP_MIB_CLEAR 0x00000001 1920 #define AR_SLP_MIB_PENDING 0x00000002 1921 1922 #define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 1923 #define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1924 1925 1926 #define AR_2040_MODE 0x8318 1927 #define AR_2040_JOINED_RX_CLEAR 0x00000001 1928 1929 1930 #define AR_EXTRCCNT 0x8328 1931 1932 #define AR_SELFGEN_MASK 0x832c 1933 1934 #define AR_PCU_TXBUF_CTRL 0x8340 1935 #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 1936 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 1937 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 1938 #define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE 0x500 1939 1940 #define AR_PCU_MISC_MODE2 0x8344 1941 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1942 #define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1943 1944 #define AR_PCU_MISC_MODE2_RESERVED 0x00000038 1945 #define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1946 #define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1947 #define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 1948 #define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1949 #define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 1950 #define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1951 #define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1952 #define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1953 #define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 1954 1955 #define AR_PCU_MISC_MODE3 0x83d0 1956 1957 #define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 1958 #define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1959 #define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1960 #define AR_MAC_PCU_GEN_TIMER_TSF_SEL 0x83d8 1961 1962 1963 #define AR_AES_MUTE_MASK0 0x805c 1964 #define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1965 #define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1966 #define AR_AES_MUTE_MASK0_QOS_S 16 1967 1968 #define AR_AES_MUTE_MASK1 0x8060 1969 #define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1970 #define AR_AES_MUTE_MASK1_SEQ_S 0 1971 #define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1972 #define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1973 1974 #define AR_RATE_DURATION_0 0x8700 1975 #define AR_RATE_DURATION_31 0x87CC 1976 #define AR_RATE_DURATION_32 0x8780 1977 #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1978 1979 /* WoW - Wake On Wireless */ 1980 1981 #define AR_PMCTRL_AUX_PWR_DET 0x10000000 /* Puts Chip in L2 state */ 1982 #define AR_PMCTRL_D3COLD_VAUX 0x00800000 1983 #define AR_PMCTRL_HOST_PME_EN 0x00400000 /* Send OOB WAKE_L on WoW 1984 event */ 1985 #define AR_PMCTRL_WOW_PME_CLR 0x00200000 /* Clear WoW event */ 1986 #define AR_PMCTRL_PWR_STATE_MASK 0x0f000000 /* Power State Mask */ 1987 #define AR_PMCTRL_PWR_STATE_D1D3 0x0f000000 /* Activate D1 and D3 */ 1988 #define AR_PMCTRL_PWR_STATE_D1D3_REAL 0x0f000000 /* Activate D1 and D3 */ 1989 #define AR_PMCTRL_PWR_STATE_D0 0x08000000 /* Activate D0 */ 1990 #define AR_PMCTRL_PWR_PM_CTRL_ENA 0x00008000 /* Enable power mgmt */ 1991 1992 #define AR_WOW_BEACON_TIMO_MAX 0xffffffff 1993 1994 /* 1995 * MAC WoW Registers 1996 */ 1997 1998 #define AR_WOW_PATTERN 0x825C 1999 #define AR_WOW_COUNT 0x8260 2000 #define AR_WOW_BCN_EN 0x8270 2001 #define AR_WOW_BCN_TIMO 0x8274 2002 #define AR_WOW_KEEP_ALIVE_TIMO 0x8278 2003 #define AR_WOW_KEEP_ALIVE 0x827c 2004 #define AR_WOW_US_SCALAR 0x8284 2005 #define AR_WOW_KEEP_ALIVE_DELAY 0x8288 2006 #define AR_WOW_PATTERN_MATCH 0x828c 2007 #define AR_WOW_PATTERN_OFF1 0x8290 /* pattern bytes 0 -> 3 */ 2008 #define AR_WOW_PATTERN_OFF2 0x8294 /* pattern bytes 4 -> 7 */ 2009 2010 /* for AR9285 or later version of chips */ 2011 #define AR_WOW_EXACT 0x829c 2012 #define AR_WOW_LENGTH1 0x8360 2013 #define AR_WOW_LENGTH2 0X8364 2014 /* register to enable match for less than 256 bytes packets */ 2015 #define AR_WOW_PATTERN_MATCH_LT_256B 0x8368 2016 2017 #define AR_SW_WOW_CONTROL 0x20018 2018 #define AR_SW_WOW_ENABLE 0x1 2019 #define AR_SWITCH_TO_REFCLK 0x2 2020 #define AR_RESET_CONTROL 0x4 2021 #define AR_RESET_VALUE_MASK 0x8 2022 #define AR_HW_WOW_DISABLE 0x10 2023 #define AR_CLR_MAC_INTERRUPT 0x20 2024 #define AR_CLR_KA_INTERRUPT 0x40 2025 2026 /* AR_WOW_PATTERN register values */ 2027 #define AR_WOW_BACK_OFF_SHIFT(x) ((x & 0xf) << 28) /* in usecs */ 2028 #define AR_WOW_MAC_INTR_EN 0x00040000 2029 #define AR_WOW_MAGIC_EN 0x00010000 2030 #define AR_WOW_PATTERN_EN(x) (x & 0xff) 2031 #define AR_WOW_PAT_FOUND_SHIFT 8 2032 #define AR_WOW_PATTERN_FOUND(x) (x & (0xff << AR_WOW_PAT_FOUND_SHIFT)) 2033 #define AR_WOW_PATTERN_FOUND_MASK ((0xff) << AR_WOW_PAT_FOUND_SHIFT) 2034 #define AR_WOW_MAGIC_PAT_FOUND 0x00020000 2035 #define AR_WOW_MAC_INTR 0x00080000 2036 #define AR_WOW_KEEP_ALIVE_FAIL 0x00100000 2037 #define AR_WOW_BEACON_FAIL 0x00200000 2038 2039 #define AR_WOW_STATUS(x) (x & (AR_WOW_PATTERN_FOUND_MASK | \ 2040 AR_WOW_MAGIC_PAT_FOUND | \ 2041 AR_WOW_KEEP_ALIVE_FAIL | \ 2042 AR_WOW_BEACON_FAIL)) 2043 #define AR_WOW_CLEAR_EVENTS(x) (x & ~(AR_WOW_PATTERN_EN(0xff) | \ 2044 AR_WOW_MAGIC_EN | \ 2045 AR_WOW_MAC_INTR_EN | \ 2046 AR_WOW_BEACON_FAIL | \ 2047 AR_WOW_KEEP_ALIVE_FAIL)) 2048 2049 /* AR_WOW_COUNT register values */ 2050 #define AR_WOW_AIFS_CNT(x) (x & 0xff) 2051 #define AR_WOW_SLOT_CNT(x) ((x & 0xff) << 8) 2052 #define AR_WOW_KEEP_ALIVE_CNT(x) ((x & 0xff) << 16) 2053 2054 /* AR_WOW_BCN_EN register */ 2055 #define AR_WOW_BEACON_FAIL_EN 0x00000001 2056 2057 /* AR_WOW_BCN_TIMO rgister */ 2058 #define AR_WOW_BEACON_TIMO 0x40000000 /* valid if BCN_EN is set */ 2059 2060 /* AR_WOW_KEEP_ALIVE_TIMO register */ 2061 #define AR_WOW_KEEP_ALIVE_TIMO_VALUE 2062 #define AR_WOW_KEEP_ALIVE_NEVER 0xffffffff 2063 2064 /* AR_WOW_KEEP_ALIVE register */ 2065 #define AR_WOW_KEEP_ALIVE_AUTO_DIS 0x00000001 2066 #define AR_WOW_KEEP_ALIVE_FAIL_DIS 0x00000002 2067 2068 /* AR_WOW_KEEP_ALIVE_DELAY register */ 2069 #define AR_WOW_KEEP_ALIVE_DELAY_VALUE 0x000003e8 /* 1 msec */ 2070 2071 2072 /* 2073 * keep it long for beacon workaround - ensure no false alarm 2074 */ 2075 #define AR_WOW_BMISSTHRESHOLD 0x20 2076 2077 /* AR_WOW_PATTERN_MATCH register */ 2078 #define AR_WOW_PAT_END_OF_PKT(x) (x & 0xf) 2079 #define AR_WOW_PAT_OFF_MATCH(x) ((x & 0xf) << 8) 2080 2081 /* 2082 * default values for Wow Configuration for backoff, aifs, slot, keep-alive 2083 * to be programmed into various registers. 2084 */ 2085 #define AR_WOW_PAT_BACKOFF 0x00000004 /* AR_WOW_PATTERN_REG */ 2086 #define AR_WOW_CNT_AIFS_CNT 0x00000022 /* AR_WOW_COUNT_REG */ 2087 #define AR_WOW_CNT_SLOT_CNT 0x00000009 /* AR_WOW_COUNT_REG */ 2088 /* 2089 * Keepalive count applicable for AR9280 2.0 and above. 2090 */ 2091 #define AR_WOW_CNT_KA_CNT 0x00000008 /* AR_WOW_COUNT register */ 2092 2093 /* WoW - Transmit buffer for keep alive frames */ 2094 #define AR_WOW_TRANSMIT_BUFFER 0xe000 /* E000 - EFFC */ 2095 2096 #define AR_WOW_TXBUF(i) (AR_WOW_TRANSMIT_BUFFER + ((i) << 2)) 2097 2098 #define AR_WOW_KA_DESC_WORD2 0xe000 2099 2100 #define AR_WOW_KA_DATA_WORD0 0xe030 2101 2102 /* WoW Transmit Buffer for patterns */ 2103 #define AR_WOW_TB_PATTERN(i) (0xe100 + (i << 8)) 2104 #define AR_WOW_TB_MASK(i) (0xec00 + (i << 5)) 2105 2106 /* Currently Pattern 0-7 are supported - so bit 0-7 are set */ 2107 #define AR_WOW_PATTERN_SUPPORTED 0xff 2108 #define AR_WOW_LENGTH_MAX 0xff 2109 #define AR_WOW_LEN1_SHIFT(_i) ((0x3 - ((_i) & 0x3)) << 0x3) 2110 #define AR_WOW_LENGTH1_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN1_SHIFT(_i)) 2111 #define AR_WOW_LEN2_SHIFT(_i) ((0x7 - ((_i) & 0x7)) << 0x3) 2112 #define AR_WOW_LENGTH2_MASK(_i) (AR_WOW_LENGTH_MAX << AR_WOW_LEN2_SHIFT(_i)) 2113 2114 #define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 2115 #define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 2116 2117 #define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */ 2118 #define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search 2119 * based on both MAC Address and Key ID. 2120 * If bit is 0, then Multicast search is 2121 * based on MAC address only. 2122 * For Merlin and above only. 2123 */ 2124 #define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, 2125 * when it is enable, AGG_WEP would takes 2126 * charge of the encryption interface of 2127 * pcu_txsm. 2128 */ 2129 2130 #define AR9300_SM_BASE 0xa200 2131 #define AR9002_PHY_AGC_CONTROL 0x9860 2132 #define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4 2133 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL) 2134 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 2135 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ 2136 #define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ 2137 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ 2138 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ 2139 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 2140 #define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 2141 #define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 2142 #define AR_PHY_AGC_CONTROL_PKDET_CAL 0x00100000 2143 #define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 2144 #define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 2145 2146 /* MCI Registers */ 2147 2148 #define AR_MCI_COMMAND0 0x1800 2149 #define AR_MCI_COMMAND0_HEADER 0xFF 2150 #define AR_MCI_COMMAND0_HEADER_S 0 2151 #define AR_MCI_COMMAND0_LEN 0x1f00 2152 #define AR_MCI_COMMAND0_LEN_S 8 2153 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP 0x2000 2154 #define AR_MCI_COMMAND0_DISABLE_TIMESTAMP_S 13 2155 2156 #define AR_MCI_COMMAND1 0x1804 2157 2158 #define AR_MCI_COMMAND2 0x1808 2159 #define AR_MCI_COMMAND2_RESET_TX 0x01 2160 #define AR_MCI_COMMAND2_RESET_TX_S 0 2161 #define AR_MCI_COMMAND2_RESET_RX 0x02 2162 #define AR_MCI_COMMAND2_RESET_RX_S 1 2163 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES 0x3FC 2164 #define AR_MCI_COMMAND2_RESET_RX_NUM_CYCLES_S 2 2165 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP 0x400 2166 #define AR_MCI_COMMAND2_RESET_REQ_WAKEUP_S 10 2167 2168 #define AR_MCI_RX_CTRL 0x180c 2169 2170 #define AR_MCI_TX_CTRL 0x1810 2171 /* 0 = no division, 1 = divide by 2, 2 = divide by 4, 3 = divide by 8 */ 2172 #define AR_MCI_TX_CTRL_CLK_DIV 0x03 2173 #define AR_MCI_TX_CTRL_CLK_DIV_S 0 2174 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE 0x04 2175 #define AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE_S 2 2176 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ 0xFFFFF8 2177 #define AR_MCI_TX_CTRL_GAIN_UPDATE_FREQ_S 3 2178 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM 0xF000000 2179 #define AR_MCI_TX_CTRL_GAIN_UPDATE_NUM_S 24 2180 2181 #define AR_MCI_MSG_ATTRIBUTES_TABLE 0x1814 2182 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM 0xFFFF 2183 #define AR_MCI_MSG_ATTRIBUTES_TABLE_CHECKSUM_S 0 2184 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR 0xFFFF0000 2185 #define AR_MCI_MSG_ATTRIBUTES_TABLE_INVALID_HDR_S 16 2186 2187 #define AR_MCI_SCHD_TABLE_0 0x1818 2188 #define AR_MCI_SCHD_TABLE_1 0x181c 2189 #define AR_MCI_GPM_0 0x1820 2190 #define AR_MCI_GPM_1 0x1824 2191 #define AR_MCI_GPM_WRITE_PTR 0xFFFF0000 2192 #define AR_MCI_GPM_WRITE_PTR_S 16 2193 #define AR_MCI_GPM_BUF_LEN 0x0000FFFF 2194 #define AR_MCI_GPM_BUF_LEN_S 0 2195 2196 #define AR_MCI_INTERRUPT_RAW 0x1828 2197 #define AR_MCI_INTERRUPT_EN 0x182c 2198 #define AR_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 2199 #define AR_MCI_INTERRUPT_SW_MSG_DONE_S 0 2200 #define AR_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 2201 #define AR_MCI_INTERRUPT_CPU_INT_MSG_S 1 2202 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL 0x00000004 2203 #define AR_MCI_INTERRUPT_RX_CKSUM_FAIL_S 2 2204 #define AR_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 2205 #define AR_MCI_INTERRUPT_RX_INVALID_HDR_S 3 2206 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 2207 #define AR_MCI_INTERRUPT_RX_HW_MSG_FAIL_S 4 2208 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 2209 #define AR_MCI_INTERRUPT_RX_SW_MSG_FAIL_S 5 2210 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 2211 #define AR_MCI_INTERRUPT_TX_HW_MSG_FAIL_S 7 2212 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 2213 #define AR_MCI_INTERRUPT_TX_SW_MSG_FAIL_S 8 2214 #define AR_MCI_INTERRUPT_RX_MSG 0x00000200 2215 #define AR_MCI_INTERRUPT_RX_MSG_S 9 2216 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 2217 #define AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE_S 10 2218 #define AR_MCI_INTERRUPT_BT_PRI 0x07fff800 2219 #define AR_MCI_INTERRUPT_BT_PRI_S 11 2220 #define AR_MCI_INTERRUPT_BT_PRI_THRESH 0x08000000 2221 #define AR_MCI_INTERRUPT_BT_PRI_THRESH_S 27 2222 #define AR_MCI_INTERRUPT_BT_FREQ 0x10000000 2223 #define AR_MCI_INTERRUPT_BT_FREQ_S 28 2224 #define AR_MCI_INTERRUPT_BT_STOMP 0x20000000 2225 #define AR_MCI_INTERRUPT_BT_STOMP_S 29 2226 #define AR_MCI_INTERRUPT_BB_AIC_IRQ 0x40000000 2227 #define AR_MCI_INTERRUPT_BB_AIC_IRQ_S 30 2228 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 2229 #define AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT_S 31 2230 2231 #define AR_MCI_INTERRUPT_DEFAULT (AR_MCI_INTERRUPT_SW_MSG_DONE | \ 2232 AR_MCI_INTERRUPT_RX_INVALID_HDR | \ 2233 AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2234 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2235 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2236 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL | \ 2237 AR_MCI_INTERRUPT_RX_MSG | \ 2238 AR_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE | \ 2239 AR_MCI_INTERRUPT_CONT_INFO_TIMEOUT) 2240 2241 #define AR_MCI_INTERRUPT_MSG_FAIL_MASK (AR_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 2242 AR_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 2243 AR_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 2244 AR_MCI_INTERRUPT_TX_SW_MSG_FAIL) 2245 2246 #define AR_MCI_REMOTE_CPU_INT 0x1830 2247 #define AR_MCI_REMOTE_CPU_INT_EN 0x1834 2248 #define AR_MCI_INTERRUPT_RX_MSG_RAW 0x1838 2249 #define AR_MCI_INTERRUPT_RX_MSG_EN 0x183c 2250 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 2251 #define AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET_S 0 2252 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 2253 #define AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL_S 1 2254 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 2255 #define AR_MCI_INTERRUPT_RX_MSG_CONT_NACK_S 2 2256 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 2257 #define AR_MCI_INTERRUPT_RX_MSG_CONT_INFO_S 3 2258 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 2259 #define AR_MCI_INTERRUPT_RX_MSG_CONT_RST_S 4 2260 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 2261 #define AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO_S 5 2262 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 2263 #define AR_MCI_INTERRUPT_RX_MSG_CPU_INT_S 6 2264 #define AR_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 2265 #define AR_MCI_INTERRUPT_RX_MSG_GPM_S 8 2266 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 2267 #define AR_MCI_INTERRUPT_RX_MSG_LNA_INFO_S 9 2268 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 2269 #define AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING_S 10 2270 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 2271 #define AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING_S 11 2272 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 2273 #define AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE_S 12 2274 #define AR_MCI_INTERRUPT_RX_HW_MSG_MASK (AR_MCI_INTERRUPT_RX_MSG_SCHD_INFO | \ 2275 AR_MCI_INTERRUPT_RX_MSG_LNA_CONTROL| \ 2276 AR_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 2277 AR_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 2278 AR_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 2279 AR_MCI_INTERRUPT_RX_MSG_CONT_RST) 2280 2281 #define AR_MCI_INTERRUPT_RX_MSG_DEFAULT (AR_MCI_INTERRUPT_RX_MSG_GPM | \ 2282 AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET| \ 2283 AR_MCI_INTERRUPT_RX_MSG_SYS_WAKING | \ 2284 AR_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING| \ 2285 AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE) 2286 2287 #define AR_MCI_CPU_INT 0x1840 2288 2289 #define AR_MCI_RX_STATUS 0x1844 2290 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX 0x00000F00 2291 #define AR_MCI_RX_LAST_SCHD_MSG_INDEX_S 8 2292 #define AR_MCI_RX_REMOTE_SLEEP 0x00001000 2293 #define AR_MCI_RX_REMOTE_SLEEP_S 12 2294 #define AR_MCI_RX_MCI_CLK_REQ 0x00002000 2295 #define AR_MCI_RX_MCI_CLK_REQ_S 13 2296 2297 #define AR_MCI_CONT_STATUS 0x1848 2298 #define AR_MCI_CONT_RSSI_POWER 0x000000FF 2299 #define AR_MCI_CONT_RSSI_POWER_S 0 2300 #define AR_MCI_CONT_PRIORITY 0x0000FF00 2301 #define AR_MCI_CONT_PRIORITY_S 8 2302 #define AR_MCI_CONT_TXRX 0x00010000 2303 #define AR_MCI_CONT_TXRX_S 16 2304 2305 #define AR_MCI_BT_PRI0 0x184c 2306 #define AR_MCI_BT_PRI1 0x1850 2307 #define AR_MCI_BT_PRI2 0x1854 2308 #define AR_MCI_BT_PRI3 0x1858 2309 #define AR_MCI_BT_PRI 0x185c 2310 #define AR_MCI_WL_FREQ0 0x1860 2311 #define AR_MCI_WL_FREQ1 0x1864 2312 #define AR_MCI_WL_FREQ2 0x1868 2313 #define AR_MCI_GAIN 0x186c 2314 #define AR_MCI_WBTIMER1 0x1870 2315 #define AR_MCI_WBTIMER2 0x1874 2316 #define AR_MCI_WBTIMER3 0x1878 2317 #define AR_MCI_WBTIMER4 0x187c 2318 #define AR_MCI_MAXGAIN 0x1880 2319 #define AR_MCI_HW_SCHD_TBL_CTL 0x1884 2320 #define AR_MCI_HW_SCHD_TBL_D0 0x1888 2321 #define AR_MCI_HW_SCHD_TBL_D1 0x188c 2322 #define AR_MCI_HW_SCHD_TBL_D2 0x1890 2323 #define AR_MCI_HW_SCHD_TBL_D3 0x1894 2324 #define AR_MCI_TX_PAYLOAD0 0x1898 2325 #define AR_MCI_TX_PAYLOAD1 0x189c 2326 #define AR_MCI_TX_PAYLOAD2 0x18a0 2327 #define AR_MCI_TX_PAYLOAD3 0x18a4 2328 #define AR_BTCOEX_WBTIMER 0x18a8 2329 2330 #define AR_BTCOEX_CTRL 0x18ac 2331 #define AR_BTCOEX_CTRL_AR9462_MODE 0x00000001 2332 #define AR_BTCOEX_CTRL_AR9462_MODE_S 0 2333 #define AR_BTCOEX_CTRL_WBTIMER_EN 0x00000002 2334 #define AR_BTCOEX_CTRL_WBTIMER_EN_S 1 2335 #define AR_BTCOEX_CTRL_MCI_MODE_EN 0x00000004 2336 #define AR_BTCOEX_CTRL_MCI_MODE_EN_S 2 2337 #define AR_BTCOEX_CTRL_LNA_SHARED 0x00000008 2338 #define AR_BTCOEX_CTRL_LNA_SHARED_S 3 2339 #define AR_BTCOEX_CTRL_PA_SHARED 0x00000010 2340 #define AR_BTCOEX_CTRL_PA_SHARED_S 4 2341 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN 0x00000020 2342 #define AR_BTCOEX_CTRL_ONE_STEP_LOOK_AHEAD_EN_S 5 2343 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN 0x00000040 2344 #define AR_BTCOEX_CTRL_TIME_TO_NEXT_BT_THRESH_EN_S 6 2345 #define AR_BTCOEX_CTRL_NUM_ANTENNAS 0x00000180 2346 #define AR_BTCOEX_CTRL_NUM_ANTENNAS_S 7 2347 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK 0x00000E00 2348 #define AR_BTCOEX_CTRL_RX_CHAIN_MASK_S 9 2349 #define AR_BTCOEX_CTRL_AGGR_THRESH 0x00007000 2350 #define AR_BTCOEX_CTRL_AGGR_THRESH_S 12 2351 #define AR_BTCOEX_CTRL_1_CHAIN_BCN 0x00080000 2352 #define AR_BTCOEX_CTRL_1_CHAIN_BCN_S 19 2353 #define AR_BTCOEX_CTRL_1_CHAIN_ACK 0x00100000 2354 #define AR_BTCOEX_CTRL_1_CHAIN_ACK_S 20 2355 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN 0x1FE00000 2356 #define AR_BTCOEX_CTRL_WAIT_BA_MARGIN_S 28 2357 #define AR_BTCOEX_CTRL_REDUCE_TXPWR 0x20000000 2358 #define AR_BTCOEX_CTRL_REDUCE_TXPWR_S 29 2359 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10 0x40000000 2360 #define AR_BTCOEX_CTRL_SPDT_ENABLE_10_S 30 2361 #define AR_BTCOEX_CTRL_SPDT_POLARITY 0x80000000 2362 #define AR_BTCOEX_CTRL_SPDT_POLARITY_S 31 2363 2364 #define AR_BTCOEX_MAX_TXPWR(_x) (0x18c0 + ((_x) << 2)) 2365 #define AR_BTCOEX_WL_LNA 0x1940 2366 #define AR_BTCOEX_RFGAIN_CTRL 0x1944 2367 #define AR_BTCOEX_WL_LNA_TIMEOUT 0x003FFFFF 2368 #define AR_BTCOEX_WL_LNA_TIMEOUT_S 0 2369 2370 #define AR_BTCOEX_CTRL2 0x1948 2371 #define AR_BTCOEX_CTRL2_TXPWR_THRESH 0x0007F800 2372 #define AR_BTCOEX_CTRL2_TXPWR_THRESH_S 11 2373 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK 0x00380000 2374 #define AR_BTCOEX_CTRL2_TX_CHAIN_MASK_S 19 2375 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT 0x00400000 2376 #define AR_BTCOEX_CTRL2_RX_DEWEIGHT_S 22 2377 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL 0x00800000 2378 #define AR_BTCOEX_CTRL2_GPIO_OBS_SEL_S 23 2379 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL 0x01000000 2380 #define AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL_S 24 2381 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE 0x02000000 2382 #define AR_BTCOEX_CTRL2_DESC_BASED_TXPWR_ENABLE_S 25 2383 2384 #define AR_BTCOEX_CTRL_SPDT_ENABLE 0x00000001 2385 #define AR_BTCOEX_CTRL_SPDT_ENABLE_S 0 2386 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL 0x00000002 2387 #define AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL_S 1 2388 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT 0x00000004 2389 #define AR_BTCOEX_CTRL_USE_LATCHED_BT_ANT_S 2 2390 #define AR_GLB_WLAN_UART_INTF_EN 0x00020000 2391 #define AR_GLB_WLAN_UART_INTF_EN_S 17 2392 #define AR_GLB_DS_JTAG_DISABLE 0x00040000 2393 #define AR_GLB_DS_JTAG_DISABLE_S 18 2394 2395 #define AR_BTCOEX_RC 0x194c 2396 #define AR_BTCOEX_MAX_RFGAIN(_x) (0x1950 + ((_x) << 2)) 2397 #define AR_BTCOEX_DBG 0x1a50 2398 #define AR_MCI_LAST_HW_MSG_HDR 0x1a54 2399 #define AR_MCI_LAST_HW_MSG_BDY 0x1a58 2400 2401 #define AR_MCI_SCHD_TABLE_2 0x1a5c 2402 #define AR_MCI_SCHD_TABLE_2_MEM_BASED 0x00000001 2403 #define AR_MCI_SCHD_TABLE_2_MEM_BASED_S 0 2404 #define AR_MCI_SCHD_TABLE_2_HW_BASED 0x00000002 2405 #define AR_MCI_SCHD_TABLE_2_HW_BASED_S 1 2406 2407 #define AR_BTCOEX_CTRL3 0x1a60 2408 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT 0x00000fff 2409 #define AR_BTCOEX_CTRL3_CONT_INFO_TIMEOUT_S 0 2410 2411 #define AR_GLB_SWREG_DISCONT_MODE 0x2002c 2412 #define AR_GLB_SWREG_DISCONT_EN_BT_WLAN 0x3 2413 2414 #define AR_MCI_MISC 0x1a74 2415 #define AR_MCI_MISC_HW_FIX_EN 0x00000001 2416 #define AR_MCI_MISC_HW_FIX_EN_S 0 2417 #define AR_MCI_DBG_CNT_CTRL 0x1a78 2418 #define AR_MCI_DBG_CNT_CTRL_ENABLE 0x00000001 2419 #define AR_MCI_DBG_CNT_CTRL_ENABLE_S 0 2420 2421 #endif 2422