1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "ath9k.h" 18 #include "ar9003_mac.h" 19 20 #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) 21 22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta, 23 int mindelta, int main_rssi_avg, 24 int alt_rssi_avg, int pkt_count) 25 { 26 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && 27 (alt_rssi_avg > main_rssi_avg + maxdelta)) || 28 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50); 29 } 30 31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) 32 { 33 return sc->ps_enabled && 34 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); 35 } 36 37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, 38 struct ieee80211_hdr *hdr) 39 { 40 struct ieee80211_hw *hw = sc->pri_wiphy->hw; 41 int i; 42 43 spin_lock_bh(&sc->wiphy_lock); 44 for (i = 0; i < sc->num_sec_wiphy; i++) { 45 struct ath_wiphy *aphy = sc->sec_wiphy[i]; 46 if (aphy == NULL) 47 continue; 48 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) 49 == 0) { 50 hw = aphy->hw; 51 break; 52 } 53 } 54 spin_unlock_bh(&sc->wiphy_lock); 55 return hw; 56 } 57 58 /* 59 * Setup and link descriptors. 60 * 61 * 11N: we can no longer afford to self link the last descriptor. 62 * MAC acknowledges BA status as long as it copies frames to host 63 * buffer (or rx fifo). This can incorrectly acknowledge packets 64 * to a sender if last desc is self-linked. 65 */ 66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) 67 { 68 struct ath_hw *ah = sc->sc_ah; 69 struct ath_common *common = ath9k_hw_common(ah); 70 struct ath_desc *ds; 71 struct sk_buff *skb; 72 73 ATH_RXBUF_RESET(bf); 74 75 ds = bf->bf_desc; 76 ds->ds_link = 0; /* link to null */ 77 ds->ds_data = bf->bf_buf_addr; 78 79 /* virtual addr of the beginning of the buffer. */ 80 skb = bf->bf_mpdu; 81 BUG_ON(skb == NULL); 82 ds->ds_vdata = skb->data; 83 84 /* 85 * setup rx descriptors. The rx_bufsize here tells the hardware 86 * how much data it can DMA to us and that we are prepared 87 * to process 88 */ 89 ath9k_hw_setuprxdesc(ah, ds, 90 common->rx_bufsize, 91 0); 92 93 if (sc->rx.rxlink == NULL) 94 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 95 else 96 *sc->rx.rxlink = bf->bf_daddr; 97 98 sc->rx.rxlink = &ds->ds_link; 99 ath9k_hw_rxena(ah); 100 } 101 102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) 103 { 104 /* XXX block beacon interrupts */ 105 ath9k_hw_setantenna(sc->sc_ah, antenna); 106 sc->rx.defant = antenna; 107 sc->rx.rxotherant = 0; 108 } 109 110 static void ath_opmode_init(struct ath_softc *sc) 111 { 112 struct ath_hw *ah = sc->sc_ah; 113 struct ath_common *common = ath9k_hw_common(ah); 114 115 u32 rfilt, mfilt[2]; 116 117 /* configure rx filter */ 118 rfilt = ath_calcrxfilter(sc); 119 ath9k_hw_setrxfilter(ah, rfilt); 120 121 /* configure bssid mask */ 122 ath_hw_setbssidmask(common); 123 124 /* configure operational mode */ 125 ath9k_hw_setopmode(ah); 126 127 /* calculate and install multicast filter */ 128 mfilt[0] = mfilt[1] = ~0; 129 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 130 } 131 132 static bool ath_rx_edma_buf_link(struct ath_softc *sc, 133 enum ath9k_rx_qtype qtype) 134 { 135 struct ath_hw *ah = sc->sc_ah; 136 struct ath_rx_edma *rx_edma; 137 struct sk_buff *skb; 138 struct ath_buf *bf; 139 140 rx_edma = &sc->rx.rx_edma[qtype]; 141 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) 142 return false; 143 144 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); 145 list_del_init(&bf->list); 146 147 skb = bf->bf_mpdu; 148 149 ATH_RXBUF_RESET(bf); 150 memset(skb->data, 0, ah->caps.rx_status_len); 151 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 152 ah->caps.rx_status_len, DMA_TO_DEVICE); 153 154 SKB_CB_ATHBUF(skb) = bf; 155 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); 156 skb_queue_tail(&rx_edma->rx_fifo, skb); 157 158 return true; 159 } 160 161 static void ath_rx_addbuffer_edma(struct ath_softc *sc, 162 enum ath9k_rx_qtype qtype, int size) 163 { 164 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 165 u32 nbuf = 0; 166 167 if (list_empty(&sc->rx.rxbuf)) { 168 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); 169 return; 170 } 171 172 while (!list_empty(&sc->rx.rxbuf)) { 173 nbuf++; 174 175 if (!ath_rx_edma_buf_link(sc, qtype)) 176 break; 177 178 if (nbuf >= size) 179 break; 180 } 181 } 182 183 static void ath_rx_remove_buffer(struct ath_softc *sc, 184 enum ath9k_rx_qtype qtype) 185 { 186 struct ath_buf *bf; 187 struct ath_rx_edma *rx_edma; 188 struct sk_buff *skb; 189 190 rx_edma = &sc->rx.rx_edma[qtype]; 191 192 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { 193 bf = SKB_CB_ATHBUF(skb); 194 BUG_ON(!bf); 195 list_add_tail(&bf->list, &sc->rx.rxbuf); 196 } 197 } 198 199 static void ath_rx_edma_cleanup(struct ath_softc *sc) 200 { 201 struct ath_buf *bf; 202 203 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 204 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 205 206 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 207 if (bf->bf_mpdu) 208 dev_kfree_skb_any(bf->bf_mpdu); 209 } 210 211 INIT_LIST_HEAD(&sc->rx.rxbuf); 212 213 kfree(sc->rx.rx_bufptr); 214 sc->rx.rx_bufptr = NULL; 215 } 216 217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) 218 { 219 skb_queue_head_init(&rx_edma->rx_fifo); 220 skb_queue_head_init(&rx_edma->rx_buffers); 221 rx_edma->rx_fifo_hwsize = size; 222 } 223 224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) 225 { 226 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 227 struct ath_hw *ah = sc->sc_ah; 228 struct sk_buff *skb; 229 struct ath_buf *bf; 230 int error = 0, i; 231 u32 size; 232 233 234 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN + 235 ah->caps.rx_status_len, 236 min(common->cachelsz, (u16)64)); 237 238 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 239 ah->caps.rx_status_len); 240 241 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], 242 ah->caps.rx_lp_qdepth); 243 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], 244 ah->caps.rx_hp_qdepth); 245 246 size = sizeof(struct ath_buf) * nbufs; 247 bf = kzalloc(size, GFP_KERNEL); 248 if (!bf) 249 return -ENOMEM; 250 251 INIT_LIST_HEAD(&sc->rx.rxbuf); 252 sc->rx.rx_bufptr = bf; 253 254 for (i = 0; i < nbufs; i++, bf++) { 255 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); 256 if (!skb) { 257 error = -ENOMEM; 258 goto rx_init_fail; 259 } 260 261 memset(skb->data, 0, common->rx_bufsize); 262 bf->bf_mpdu = skb; 263 264 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 265 common->rx_bufsize, 266 DMA_BIDIRECTIONAL); 267 if (unlikely(dma_mapping_error(sc->dev, 268 bf->bf_buf_addr))) { 269 dev_kfree_skb_any(skb); 270 bf->bf_mpdu = NULL; 271 bf->bf_buf_addr = 0; 272 ath_err(common, 273 "dma_mapping_error() on RX init\n"); 274 error = -ENOMEM; 275 goto rx_init_fail; 276 } 277 278 list_add_tail(&bf->list, &sc->rx.rxbuf); 279 } 280 281 return 0; 282 283 rx_init_fail: 284 ath_rx_edma_cleanup(sc); 285 return error; 286 } 287 288 static void ath_edma_start_recv(struct ath_softc *sc) 289 { 290 spin_lock_bh(&sc->rx.rxbuflock); 291 292 ath9k_hw_rxena(sc->sc_ah); 293 294 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, 295 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); 296 297 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, 298 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); 299 300 ath_opmode_init(sc); 301 302 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); 303 304 spin_unlock_bh(&sc->rx.rxbuflock); 305 } 306 307 static void ath_edma_stop_recv(struct ath_softc *sc) 308 { 309 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 310 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 311 } 312 313 int ath_rx_init(struct ath_softc *sc, int nbufs) 314 { 315 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 316 struct sk_buff *skb; 317 struct ath_buf *bf; 318 int error = 0; 319 320 spin_lock_init(&sc->sc_pcu_lock); 321 sc->sc_flags &= ~SC_OP_RXFLUSH; 322 spin_lock_init(&sc->rx.rxbuflock); 323 324 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 325 return ath_rx_edma_init(sc, nbufs); 326 } else { 327 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 328 min(common->cachelsz, (u16)64)); 329 330 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 331 common->cachelsz, common->rx_bufsize); 332 333 /* Initialize rx descriptors */ 334 335 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 336 "rx", nbufs, 1, 0); 337 if (error != 0) { 338 ath_err(common, 339 "failed to allocate rx descriptors: %d\n", 340 error); 341 goto err; 342 } 343 344 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 345 skb = ath_rxbuf_alloc(common, common->rx_bufsize, 346 GFP_KERNEL); 347 if (skb == NULL) { 348 error = -ENOMEM; 349 goto err; 350 } 351 352 bf->bf_mpdu = skb; 353 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 354 common->rx_bufsize, 355 DMA_FROM_DEVICE); 356 if (unlikely(dma_mapping_error(sc->dev, 357 bf->bf_buf_addr))) { 358 dev_kfree_skb_any(skb); 359 bf->bf_mpdu = NULL; 360 bf->bf_buf_addr = 0; 361 ath_err(common, 362 "dma_mapping_error() on RX init\n"); 363 error = -ENOMEM; 364 goto err; 365 } 366 } 367 sc->rx.rxlink = NULL; 368 } 369 370 err: 371 if (error) 372 ath_rx_cleanup(sc); 373 374 return error; 375 } 376 377 void ath_rx_cleanup(struct ath_softc *sc) 378 { 379 struct ath_hw *ah = sc->sc_ah; 380 struct ath_common *common = ath9k_hw_common(ah); 381 struct sk_buff *skb; 382 struct ath_buf *bf; 383 384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 385 ath_rx_edma_cleanup(sc); 386 return; 387 } else { 388 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 389 skb = bf->bf_mpdu; 390 if (skb) { 391 dma_unmap_single(sc->dev, bf->bf_buf_addr, 392 common->rx_bufsize, 393 DMA_FROM_DEVICE); 394 dev_kfree_skb(skb); 395 bf->bf_buf_addr = 0; 396 bf->bf_mpdu = NULL; 397 } 398 } 399 400 if (sc->rx.rxdma.dd_desc_len != 0) 401 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); 402 } 403 } 404 405 /* 406 * Calculate the receive filter according to the 407 * operating mode and state: 408 * 409 * o always accept unicast, broadcast, and multicast traffic 410 * o maintain current state of phy error reception (the hal 411 * may enable phy error frames for noise immunity work) 412 * o probe request frames are accepted only when operating in 413 * hostap, adhoc, or monitor modes 414 * o enable promiscuous mode according to the interface state 415 * o accept beacons: 416 * - when operating in adhoc mode so the 802.11 layer creates 417 * node table entries for peers, 418 * - when operating in station mode for collecting rssi data when 419 * the station is otherwise quiet, or 420 * - when operating as a repeater so we see repeater-sta beacons 421 * - when scanning 422 */ 423 424 u32 ath_calcrxfilter(struct ath_softc *sc) 425 { 426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) 427 428 u32 rfilt; 429 430 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) 431 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST 432 | ATH9K_RX_FILTER_MCAST; 433 434 if (sc->rx.rxfilter & FIF_PROBE_REQ) 435 rfilt |= ATH9K_RX_FILTER_PROBEREQ; 436 437 /* 438 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station 439 * mode interface or when in monitor mode. AP mode does not need this 440 * since it receives all in-BSS frames anyway. 441 */ 442 if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && 443 (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || 444 (sc->sc_ah->is_monitoring)) 445 rfilt |= ATH9K_RX_FILTER_PROM; 446 447 if (sc->rx.rxfilter & FIF_CONTROL) 448 rfilt |= ATH9K_RX_FILTER_CONTROL; 449 450 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 451 (sc->nvifs <= 1) && 452 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) 453 rfilt |= ATH9K_RX_FILTER_MYBEACON; 454 else 455 rfilt |= ATH9K_RX_FILTER_BEACON; 456 457 if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) || 458 AR_SREV_9285_12_OR_LATER(sc->sc_ah)) && 459 (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && 460 (sc->rx.rxfilter & FIF_PSPOLL)) 461 rfilt |= ATH9K_RX_FILTER_PSPOLL; 462 463 if (conf_is_ht(&sc->hw->conf)) 464 rfilt |= ATH9K_RX_FILTER_COMP_BAR; 465 466 if (sc->sec_wiphy || (sc->nvifs > 1) || 467 (sc->rx.rxfilter & FIF_OTHER_BSS)) { 468 /* The following may also be needed for other older chips */ 469 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) 470 rfilt |= ATH9K_RX_FILTER_PROM; 471 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; 472 } 473 474 return rfilt; 475 476 #undef RX_FILTER_PRESERVE 477 } 478 479 int ath_startrecv(struct ath_softc *sc) 480 { 481 struct ath_hw *ah = sc->sc_ah; 482 struct ath_buf *bf, *tbf; 483 484 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 485 ath_edma_start_recv(sc); 486 return 0; 487 } 488 489 spin_lock_bh(&sc->rx.rxbuflock); 490 if (list_empty(&sc->rx.rxbuf)) 491 goto start_recv; 492 493 sc->rx.rxlink = NULL; 494 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { 495 ath_rx_buf_link(sc, bf); 496 } 497 498 /* We could have deleted elements so the list may be empty now */ 499 if (list_empty(&sc->rx.rxbuf)) 500 goto start_recv; 501 502 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); 503 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 504 ath9k_hw_rxena(ah); 505 506 start_recv: 507 ath_opmode_init(sc); 508 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); 509 510 spin_unlock_bh(&sc->rx.rxbuflock); 511 512 return 0; 513 } 514 515 bool ath_stoprecv(struct ath_softc *sc) 516 { 517 struct ath_hw *ah = sc->sc_ah; 518 bool stopped; 519 520 spin_lock_bh(&sc->rx.rxbuflock); 521 ath9k_hw_abortpcurecv(ah); 522 ath9k_hw_setrxfilter(ah, 0); 523 stopped = ath9k_hw_stopdmarecv(ah); 524 525 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 526 ath_edma_stop_recv(sc); 527 else 528 sc->rx.rxlink = NULL; 529 spin_unlock_bh(&sc->rx.rxbuflock); 530 531 if (!(ah->ah_flags & AH_UNPLUGGED) && 532 unlikely(!stopped)) { 533 ath_err(ath9k_hw_common(sc->sc_ah), 534 "Could not stop RX, we could be " 535 "confusing the DMA engine when we start RX up\n"); 536 ATH_DBG_WARN_ON_ONCE(!stopped); 537 } 538 return stopped; 539 } 540 541 void ath_flushrecv(struct ath_softc *sc) 542 { 543 sc->sc_flags |= SC_OP_RXFLUSH; 544 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 545 ath_rx_tasklet(sc, 1, true); 546 ath_rx_tasklet(sc, 1, false); 547 sc->sc_flags &= ~SC_OP_RXFLUSH; 548 } 549 550 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) 551 { 552 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ 553 struct ieee80211_mgmt *mgmt; 554 u8 *pos, *end, id, elen; 555 struct ieee80211_tim_ie *tim; 556 557 mgmt = (struct ieee80211_mgmt *)skb->data; 558 pos = mgmt->u.beacon.variable; 559 end = skb->data + skb->len; 560 561 while (pos + 2 < end) { 562 id = *pos++; 563 elen = *pos++; 564 if (pos + elen > end) 565 break; 566 567 if (id == WLAN_EID_TIM) { 568 if (elen < sizeof(*tim)) 569 break; 570 tim = (struct ieee80211_tim_ie *) pos; 571 if (tim->dtim_count != 0) 572 break; 573 return tim->bitmap_ctrl & 0x01; 574 } 575 576 pos += elen; 577 } 578 579 return false; 580 } 581 582 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) 583 { 584 struct ieee80211_mgmt *mgmt; 585 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 586 587 if (skb->len < 24 + 8 + 2 + 2) 588 return; 589 590 mgmt = (struct ieee80211_mgmt *)skb->data; 591 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) 592 return; /* not from our current AP */ 593 594 sc->ps_flags &= ~PS_WAIT_FOR_BEACON; 595 596 if (sc->ps_flags & PS_BEACON_SYNC) { 597 sc->ps_flags &= ~PS_BEACON_SYNC; 598 ath_dbg(common, ATH_DBG_PS, 599 "Reconfigure Beacon timers based on timestamp from the AP\n"); 600 ath_beacon_config(sc, NULL); 601 } 602 603 if (ath_beacon_dtim_pending_cab(skb)) { 604 /* 605 * Remain awake waiting for buffered broadcast/multicast 606 * frames. If the last broadcast/multicast frame is not 607 * received properly, the next beacon frame will work as 608 * a backup trigger for returning into NETWORK SLEEP state, 609 * so we are waiting for it as well. 610 */ 611 ath_dbg(common, ATH_DBG_PS, 612 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); 613 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; 614 return; 615 } 616 617 if (sc->ps_flags & PS_WAIT_FOR_CAB) { 618 /* 619 * This can happen if a broadcast frame is dropped or the AP 620 * fails to send a frame indicating that all CAB frames have 621 * been delivered. 622 */ 623 sc->ps_flags &= ~PS_WAIT_FOR_CAB; 624 ath_dbg(common, ATH_DBG_PS, 625 "PS wait for CAB frames timed out\n"); 626 } 627 } 628 629 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) 630 { 631 struct ieee80211_hdr *hdr; 632 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 633 634 hdr = (struct ieee80211_hdr *)skb->data; 635 636 /* Process Beacon and CAB receive in PS state */ 637 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) 638 && ieee80211_is_beacon(hdr->frame_control)) 639 ath_rx_ps_beacon(sc, skb); 640 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && 641 (ieee80211_is_data(hdr->frame_control) || 642 ieee80211_is_action(hdr->frame_control)) && 643 is_multicast_ether_addr(hdr->addr1) && 644 !ieee80211_has_moredata(hdr->frame_control)) { 645 /* 646 * No more broadcast/multicast frames to be received at this 647 * point. 648 */ 649 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); 650 ath_dbg(common, ATH_DBG_PS, 651 "All PS CAB frames received, back to sleep\n"); 652 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && 653 !is_multicast_ether_addr(hdr->addr1) && 654 !ieee80211_has_morefrags(hdr->frame_control)) { 655 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; 656 ath_dbg(common, ATH_DBG_PS, 657 "Going back to sleep after having received PS-Poll data (0x%lx)\n", 658 sc->ps_flags & (PS_WAIT_FOR_BEACON | 659 PS_WAIT_FOR_CAB | 660 PS_WAIT_FOR_PSPOLL_DATA | 661 PS_WAIT_FOR_TX_ACK)); 662 } 663 } 664 665 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, 666 struct ath_softc *sc, struct sk_buff *skb) 667 { 668 struct ieee80211_hdr *hdr; 669 670 hdr = (struct ieee80211_hdr *)skb->data; 671 672 /* Send the frame to mac80211 */ 673 if (is_multicast_ether_addr(hdr->addr1)) { 674 int i; 675 /* 676 * Deliver broadcast/multicast frames to all suitable 677 * virtual wiphys. 678 */ 679 /* TODO: filter based on channel configuration */ 680 for (i = 0; i < sc->num_sec_wiphy; i++) { 681 struct ath_wiphy *aphy = sc->sec_wiphy[i]; 682 struct sk_buff *nskb; 683 if (aphy == NULL) 684 continue; 685 nskb = skb_copy(skb, GFP_ATOMIC); 686 if (!nskb) 687 continue; 688 ieee80211_rx(aphy->hw, nskb); 689 } 690 ieee80211_rx(sc->hw, skb); 691 } else 692 /* Deliver unicast frames based on receiver address */ 693 ieee80211_rx(hw, skb); 694 } 695 696 static bool ath_edma_get_buffers(struct ath_softc *sc, 697 enum ath9k_rx_qtype qtype) 698 { 699 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; 700 struct ath_hw *ah = sc->sc_ah; 701 struct ath_common *common = ath9k_hw_common(ah); 702 struct sk_buff *skb; 703 struct ath_buf *bf; 704 int ret; 705 706 skb = skb_peek(&rx_edma->rx_fifo); 707 if (!skb) 708 return false; 709 710 bf = SKB_CB_ATHBUF(skb); 711 BUG_ON(!bf); 712 713 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 714 common->rx_bufsize, DMA_FROM_DEVICE); 715 716 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data); 717 if (ret == -EINPROGRESS) { 718 /*let device gain the buffer again*/ 719 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 720 common->rx_bufsize, DMA_FROM_DEVICE); 721 return false; 722 } 723 724 __skb_unlink(skb, &rx_edma->rx_fifo); 725 if (ret == -EINVAL) { 726 /* corrupt descriptor, skip this one and the following one */ 727 list_add_tail(&bf->list, &sc->rx.rxbuf); 728 ath_rx_edma_buf_link(sc, qtype); 729 skb = skb_peek(&rx_edma->rx_fifo); 730 if (!skb) 731 return true; 732 733 bf = SKB_CB_ATHBUF(skb); 734 BUG_ON(!bf); 735 736 __skb_unlink(skb, &rx_edma->rx_fifo); 737 list_add_tail(&bf->list, &sc->rx.rxbuf); 738 ath_rx_edma_buf_link(sc, qtype); 739 return true; 740 } 741 skb_queue_tail(&rx_edma->rx_buffers, skb); 742 743 return true; 744 } 745 746 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, 747 struct ath_rx_status *rs, 748 enum ath9k_rx_qtype qtype) 749 { 750 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; 751 struct sk_buff *skb; 752 struct ath_buf *bf; 753 754 while (ath_edma_get_buffers(sc, qtype)); 755 skb = __skb_dequeue(&rx_edma->rx_buffers); 756 if (!skb) 757 return NULL; 758 759 bf = SKB_CB_ATHBUF(skb); 760 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data); 761 return bf; 762 } 763 764 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, 765 struct ath_rx_status *rs) 766 { 767 struct ath_hw *ah = sc->sc_ah; 768 struct ath_common *common = ath9k_hw_common(ah); 769 struct ath_desc *ds; 770 struct ath_buf *bf; 771 int ret; 772 773 if (list_empty(&sc->rx.rxbuf)) { 774 sc->rx.rxlink = NULL; 775 return NULL; 776 } 777 778 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); 779 ds = bf->bf_desc; 780 781 /* 782 * Must provide the virtual address of the current 783 * descriptor, the physical address, and the virtual 784 * address of the next descriptor in the h/w chain. 785 * This allows the HAL to look ahead to see if the 786 * hardware is done with a descriptor by checking the 787 * done bit in the following descriptor and the address 788 * of the current descriptor the DMA engine is working 789 * on. All this is necessary because of our use of 790 * a self-linked list to avoid rx overruns. 791 */ 792 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0); 793 if (ret == -EINPROGRESS) { 794 struct ath_rx_status trs; 795 struct ath_buf *tbf; 796 struct ath_desc *tds; 797 798 memset(&trs, 0, sizeof(trs)); 799 if (list_is_last(&bf->list, &sc->rx.rxbuf)) { 800 sc->rx.rxlink = NULL; 801 return NULL; 802 } 803 804 tbf = list_entry(bf->list.next, struct ath_buf, list); 805 806 /* 807 * On some hardware the descriptor status words could 808 * get corrupted, including the done bit. Because of 809 * this, check if the next descriptor's done bit is 810 * set or not. 811 * 812 * If the next descriptor's done bit is set, the current 813 * descriptor has been corrupted. Force s/w to discard 814 * this descriptor and continue... 815 */ 816 817 tds = tbf->bf_desc; 818 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0); 819 if (ret == -EINPROGRESS) 820 return NULL; 821 } 822 823 if (!bf->bf_mpdu) 824 return bf; 825 826 /* 827 * Synchronize the DMA transfer with CPU before 828 * 1. accessing the frame 829 * 2. requeueing the same buffer to h/w 830 */ 831 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 832 common->rx_bufsize, 833 DMA_FROM_DEVICE); 834 835 return bf; 836 } 837 838 /* Assumes you've already done the endian to CPU conversion */ 839 static bool ath9k_rx_accept(struct ath_common *common, 840 struct ieee80211_hdr *hdr, 841 struct ieee80211_rx_status *rxs, 842 struct ath_rx_status *rx_stats, 843 bool *decrypt_error) 844 { 845 #define is_mc_or_valid_tkip_keyix ((is_mc || \ 846 (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \ 847 test_bit(rx_stats->rs_keyix, common->tkip_keymap)))) 848 849 struct ath_hw *ah = common->ah; 850 __le16 fc; 851 u8 rx_status_len = ah->caps.rx_status_len; 852 853 fc = hdr->frame_control; 854 855 if (!rx_stats->rs_datalen) 856 return false; 857 /* 858 * rs_status follows rs_datalen so if rs_datalen is too large 859 * we can take a hint that hardware corrupted it, so ignore 860 * those frames. 861 */ 862 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) 863 return false; 864 865 /* 866 * rs_more indicates chained descriptors which can be used 867 * to link buffers together for a sort of scatter-gather 868 * operation. 869 * reject the frame, we don't support scatter-gather yet and 870 * the frame is probably corrupt anyway 871 */ 872 if (rx_stats->rs_more) 873 return false; 874 875 /* 876 * The rx_stats->rs_status will not be set until the end of the 877 * chained descriptors so it can be ignored if rs_more is set. The 878 * rs_more will be false at the last element of the chained 879 * descriptors. 880 */ 881 if (rx_stats->rs_status != 0) { 882 if (rx_stats->rs_status & ATH9K_RXERR_CRC) 883 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; 884 if (rx_stats->rs_status & ATH9K_RXERR_PHY) 885 return false; 886 887 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { 888 *decrypt_error = true; 889 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { 890 bool is_mc; 891 /* 892 * The MIC error bit is only valid if the frame 893 * is not a control frame or fragment, and it was 894 * decrypted using a valid TKIP key. 895 */ 896 is_mc = !!is_multicast_ether_addr(hdr->addr1); 897 898 if (!ieee80211_is_ctl(fc) && 899 !ieee80211_has_morefrags(fc) && 900 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && 901 is_mc_or_valid_tkip_keyix) 902 rxs->flag |= RX_FLAG_MMIC_ERROR; 903 else 904 rx_stats->rs_status &= ~ATH9K_RXERR_MIC; 905 } 906 /* 907 * Reject error frames with the exception of 908 * decryption and MIC failures. For monitor mode, 909 * we also ignore the CRC error. 910 */ 911 if (ah->is_monitoring) { 912 if (rx_stats->rs_status & 913 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | 914 ATH9K_RXERR_CRC)) 915 return false; 916 } else { 917 if (rx_stats->rs_status & 918 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { 919 return false; 920 } 921 } 922 } 923 return true; 924 } 925 926 static int ath9k_process_rate(struct ath_common *common, 927 struct ieee80211_hw *hw, 928 struct ath_rx_status *rx_stats, 929 struct ieee80211_rx_status *rxs) 930 { 931 struct ieee80211_supported_band *sband; 932 enum ieee80211_band band; 933 unsigned int i = 0; 934 935 band = hw->conf.channel->band; 936 sband = hw->wiphy->bands[band]; 937 938 if (rx_stats->rs_rate & 0x80) { 939 /* HT rate */ 940 rxs->flag |= RX_FLAG_HT; 941 if (rx_stats->rs_flags & ATH9K_RX_2040) 942 rxs->flag |= RX_FLAG_40MHZ; 943 if (rx_stats->rs_flags & ATH9K_RX_GI) 944 rxs->flag |= RX_FLAG_SHORT_GI; 945 rxs->rate_idx = rx_stats->rs_rate & 0x7f; 946 return 0; 947 } 948 949 for (i = 0; i < sband->n_bitrates; i++) { 950 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { 951 rxs->rate_idx = i; 952 return 0; 953 } 954 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { 955 rxs->flag |= RX_FLAG_SHORTPRE; 956 rxs->rate_idx = i; 957 return 0; 958 } 959 } 960 961 /* 962 * No valid hardware bitrate found -- we should not get here 963 * because hardware has already validated this frame as OK. 964 */ 965 ath_dbg(common, ATH_DBG_XMIT, 966 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", 967 rx_stats->rs_rate); 968 969 return -EINVAL; 970 } 971 972 static void ath9k_process_rssi(struct ath_common *common, 973 struct ieee80211_hw *hw, 974 struct ieee80211_hdr *hdr, 975 struct ath_rx_status *rx_stats) 976 { 977 struct ath_wiphy *aphy = hw->priv; 978 struct ath_hw *ah = common->ah; 979 int last_rssi; 980 __le16 fc; 981 982 if (ah->opmode != NL80211_IFTYPE_STATION) 983 return; 984 985 fc = hdr->frame_control; 986 if (!ieee80211_is_beacon(fc) || 987 compare_ether_addr(hdr->addr3, common->curbssid)) 988 return; 989 990 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) 991 ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi); 992 993 last_rssi = aphy->last_rssi; 994 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) 995 rx_stats->rs_rssi = ATH_EP_RND(last_rssi, 996 ATH_RSSI_EP_MULTIPLIER); 997 if (rx_stats->rs_rssi < 0) 998 rx_stats->rs_rssi = 0; 999 1000 /* Update Beacon RSSI, this is used by ANI. */ 1001 ah->stats.avgbrssi = rx_stats->rs_rssi; 1002 } 1003 1004 /* 1005 * For Decrypt or Demic errors, we only mark packet status here and always push 1006 * up the frame up to let mac80211 handle the actual error case, be it no 1007 * decryption key or real decryption error. This let us keep statistics there. 1008 */ 1009 static int ath9k_rx_skb_preprocess(struct ath_common *common, 1010 struct ieee80211_hw *hw, 1011 struct ieee80211_hdr *hdr, 1012 struct ath_rx_status *rx_stats, 1013 struct ieee80211_rx_status *rx_status, 1014 bool *decrypt_error) 1015 { 1016 memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); 1017 1018 /* 1019 * everything but the rate is checked here, the rate check is done 1020 * separately to avoid doing two lookups for a rate for each frame. 1021 */ 1022 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) 1023 return -EINVAL; 1024 1025 ath9k_process_rssi(common, hw, hdr, rx_stats); 1026 1027 if (ath9k_process_rate(common, hw, rx_stats, rx_status)) 1028 return -EINVAL; 1029 1030 rx_status->band = hw->conf.channel->band; 1031 rx_status->freq = hw->conf.channel->center_freq; 1032 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; 1033 rx_status->antenna = rx_stats->rs_antenna; 1034 rx_status->flag |= RX_FLAG_TSFT; 1035 1036 return 0; 1037 } 1038 1039 static void ath9k_rx_skb_postprocess(struct ath_common *common, 1040 struct sk_buff *skb, 1041 struct ath_rx_status *rx_stats, 1042 struct ieee80211_rx_status *rxs, 1043 bool decrypt_error) 1044 { 1045 struct ath_hw *ah = common->ah; 1046 struct ieee80211_hdr *hdr; 1047 int hdrlen, padpos, padsize; 1048 u8 keyix; 1049 __le16 fc; 1050 1051 /* see if any padding is done by the hw and remove it */ 1052 hdr = (struct ieee80211_hdr *) skb->data; 1053 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1054 fc = hdr->frame_control; 1055 padpos = ath9k_cmn_padpos(hdr->frame_control); 1056 1057 /* The MAC header is padded to have 32-bit boundary if the 1058 * packet payload is non-zero. The general calculation for 1059 * padsize would take into account odd header lengths: 1060 * padsize = (4 - padpos % 4) % 4; However, since only 1061 * even-length headers are used, padding can only be 0 or 2 1062 * bytes and we can optimize this a bit. In addition, we must 1063 * not try to remove padding from short control frames that do 1064 * not have payload. */ 1065 padsize = padpos & 3; 1066 if (padsize && skb->len>=padpos+padsize+FCS_LEN) { 1067 memmove(skb->data + padsize, skb->data, padpos); 1068 skb_pull(skb, padsize); 1069 } 1070 1071 keyix = rx_stats->rs_keyix; 1072 1073 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && 1074 ieee80211_has_protected(fc)) { 1075 rxs->flag |= RX_FLAG_DECRYPTED; 1076 } else if (ieee80211_has_protected(fc) 1077 && !decrypt_error && skb->len >= hdrlen + 4) { 1078 keyix = skb->data[hdrlen + 3] >> 6; 1079 1080 if (test_bit(keyix, common->keymap)) 1081 rxs->flag |= RX_FLAG_DECRYPTED; 1082 } 1083 if (ah->sw_mgmt_crypto && 1084 (rxs->flag & RX_FLAG_DECRYPTED) && 1085 ieee80211_is_mgmt(fc)) 1086 /* Use software decrypt for management frames. */ 1087 rxs->flag &= ~RX_FLAG_DECRYPTED; 1088 } 1089 1090 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb, 1091 struct ath_hw_antcomb_conf ant_conf, 1092 int main_rssi_avg) 1093 { 1094 antcomb->quick_scan_cnt = 0; 1095 1096 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2) 1097 antcomb->rssi_lna2 = main_rssi_avg; 1098 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1) 1099 antcomb->rssi_lna1 = main_rssi_avg; 1100 1101 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) { 1102 case (0x10): /* LNA2 A-B */ 1103 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1104 antcomb->first_quick_scan_conf = 1105 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1106 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; 1107 break; 1108 case (0x20): /* LNA1 A-B */ 1109 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1110 antcomb->first_quick_scan_conf = 1111 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1112 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; 1113 break; 1114 case (0x21): /* LNA1 LNA2 */ 1115 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2; 1116 antcomb->first_quick_scan_conf = 1117 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1118 antcomb->second_quick_scan_conf = 1119 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1120 break; 1121 case (0x12): /* LNA2 LNA1 */ 1122 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1; 1123 antcomb->first_quick_scan_conf = 1124 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1125 antcomb->second_quick_scan_conf = 1126 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1127 break; 1128 case (0x13): /* LNA2 A+B */ 1129 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1130 antcomb->first_quick_scan_conf = 1131 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1132 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; 1133 break; 1134 case (0x23): /* LNA1 A+B */ 1135 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1136 antcomb->first_quick_scan_conf = 1137 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1138 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; 1139 break; 1140 default: 1141 break; 1142 } 1143 } 1144 1145 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb, 1146 struct ath_hw_antcomb_conf *div_ant_conf, 1147 int main_rssi_avg, int alt_rssi_avg, 1148 int alt_ratio) 1149 { 1150 /* alt_good */ 1151 switch (antcomb->quick_scan_cnt) { 1152 case 0: 1153 /* set alt to main, and alt to first conf */ 1154 div_ant_conf->main_lna_conf = antcomb->main_conf; 1155 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf; 1156 break; 1157 case 1: 1158 /* set alt to main, and alt to first conf */ 1159 div_ant_conf->main_lna_conf = antcomb->main_conf; 1160 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf; 1161 antcomb->rssi_first = main_rssi_avg; 1162 antcomb->rssi_second = alt_rssi_avg; 1163 1164 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { 1165 /* main is LNA1 */ 1166 if (ath_is_alt_ant_ratio_better(alt_ratio, 1167 ATH_ANT_DIV_COMB_LNA1_DELTA_HI, 1168 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, 1169 main_rssi_avg, alt_rssi_avg, 1170 antcomb->total_pkt_count)) 1171 antcomb->first_ratio = true; 1172 else 1173 antcomb->first_ratio = false; 1174 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { 1175 if (ath_is_alt_ant_ratio_better(alt_ratio, 1176 ATH_ANT_DIV_COMB_LNA1_DELTA_MID, 1177 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, 1178 main_rssi_avg, alt_rssi_avg, 1179 antcomb->total_pkt_count)) 1180 antcomb->first_ratio = true; 1181 else 1182 antcomb->first_ratio = false; 1183 } else { 1184 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && 1185 (alt_rssi_avg > main_rssi_avg + 1186 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || 1187 (alt_rssi_avg > main_rssi_avg)) && 1188 (antcomb->total_pkt_count > 50)) 1189 antcomb->first_ratio = true; 1190 else 1191 antcomb->first_ratio = false; 1192 } 1193 break; 1194 case 2: 1195 antcomb->alt_good = false; 1196 antcomb->scan_not_start = false; 1197 antcomb->scan = false; 1198 antcomb->rssi_first = main_rssi_avg; 1199 antcomb->rssi_third = alt_rssi_avg; 1200 1201 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1) 1202 antcomb->rssi_lna1 = alt_rssi_avg; 1203 else if (antcomb->second_quick_scan_conf == 1204 ATH_ANT_DIV_COMB_LNA2) 1205 antcomb->rssi_lna2 = alt_rssi_avg; 1206 else if (antcomb->second_quick_scan_conf == 1207 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) { 1208 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) 1209 antcomb->rssi_lna2 = main_rssi_avg; 1210 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) 1211 antcomb->rssi_lna1 = main_rssi_avg; 1212 } 1213 1214 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 + 1215 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA) 1216 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2; 1217 else 1218 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1; 1219 1220 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { 1221 if (ath_is_alt_ant_ratio_better(alt_ratio, 1222 ATH_ANT_DIV_COMB_LNA1_DELTA_HI, 1223 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, 1224 main_rssi_avg, alt_rssi_avg, 1225 antcomb->total_pkt_count)) 1226 antcomb->second_ratio = true; 1227 else 1228 antcomb->second_ratio = false; 1229 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { 1230 if (ath_is_alt_ant_ratio_better(alt_ratio, 1231 ATH_ANT_DIV_COMB_LNA1_DELTA_MID, 1232 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, 1233 main_rssi_avg, alt_rssi_avg, 1234 antcomb->total_pkt_count)) 1235 antcomb->second_ratio = true; 1236 else 1237 antcomb->second_ratio = false; 1238 } else { 1239 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && 1240 (alt_rssi_avg > main_rssi_avg + 1241 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || 1242 (alt_rssi_avg > main_rssi_avg)) && 1243 (antcomb->total_pkt_count > 50)) 1244 antcomb->second_ratio = true; 1245 else 1246 antcomb->second_ratio = false; 1247 } 1248 1249 /* set alt to the conf with maximun ratio */ 1250 if (antcomb->first_ratio && antcomb->second_ratio) { 1251 if (antcomb->rssi_second > antcomb->rssi_third) { 1252 /* first alt*/ 1253 if ((antcomb->first_quick_scan_conf == 1254 ATH_ANT_DIV_COMB_LNA1) || 1255 (antcomb->first_quick_scan_conf == 1256 ATH_ANT_DIV_COMB_LNA2)) 1257 /* Set alt LNA1 or LNA2*/ 1258 if (div_ant_conf->main_lna_conf == 1259 ATH_ANT_DIV_COMB_LNA2) 1260 div_ant_conf->alt_lna_conf = 1261 ATH_ANT_DIV_COMB_LNA1; 1262 else 1263 div_ant_conf->alt_lna_conf = 1264 ATH_ANT_DIV_COMB_LNA2; 1265 else 1266 /* Set alt to A+B or A-B */ 1267 div_ant_conf->alt_lna_conf = 1268 antcomb->first_quick_scan_conf; 1269 } else if ((antcomb->second_quick_scan_conf == 1270 ATH_ANT_DIV_COMB_LNA1) || 1271 (antcomb->second_quick_scan_conf == 1272 ATH_ANT_DIV_COMB_LNA2)) { 1273 /* Set alt LNA1 or LNA2 */ 1274 if (div_ant_conf->main_lna_conf == 1275 ATH_ANT_DIV_COMB_LNA2) 1276 div_ant_conf->alt_lna_conf = 1277 ATH_ANT_DIV_COMB_LNA1; 1278 else 1279 div_ant_conf->alt_lna_conf = 1280 ATH_ANT_DIV_COMB_LNA2; 1281 } else { 1282 /* Set alt to A+B or A-B */ 1283 div_ant_conf->alt_lna_conf = 1284 antcomb->second_quick_scan_conf; 1285 } 1286 } else if (antcomb->first_ratio) { 1287 /* first alt */ 1288 if ((antcomb->first_quick_scan_conf == 1289 ATH_ANT_DIV_COMB_LNA1) || 1290 (antcomb->first_quick_scan_conf == 1291 ATH_ANT_DIV_COMB_LNA2)) 1292 /* Set alt LNA1 or LNA2 */ 1293 if (div_ant_conf->main_lna_conf == 1294 ATH_ANT_DIV_COMB_LNA2) 1295 div_ant_conf->alt_lna_conf = 1296 ATH_ANT_DIV_COMB_LNA1; 1297 else 1298 div_ant_conf->alt_lna_conf = 1299 ATH_ANT_DIV_COMB_LNA2; 1300 else 1301 /* Set alt to A+B or A-B */ 1302 div_ant_conf->alt_lna_conf = 1303 antcomb->first_quick_scan_conf; 1304 } else if (antcomb->second_ratio) { 1305 /* second alt */ 1306 if ((antcomb->second_quick_scan_conf == 1307 ATH_ANT_DIV_COMB_LNA1) || 1308 (antcomb->second_quick_scan_conf == 1309 ATH_ANT_DIV_COMB_LNA2)) 1310 /* Set alt LNA1 or LNA2 */ 1311 if (div_ant_conf->main_lna_conf == 1312 ATH_ANT_DIV_COMB_LNA2) 1313 div_ant_conf->alt_lna_conf = 1314 ATH_ANT_DIV_COMB_LNA1; 1315 else 1316 div_ant_conf->alt_lna_conf = 1317 ATH_ANT_DIV_COMB_LNA2; 1318 else 1319 /* Set alt to A+B or A-B */ 1320 div_ant_conf->alt_lna_conf = 1321 antcomb->second_quick_scan_conf; 1322 } else { 1323 /* main is largest */ 1324 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) || 1325 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)) 1326 /* Set alt LNA1 or LNA2 */ 1327 if (div_ant_conf->main_lna_conf == 1328 ATH_ANT_DIV_COMB_LNA2) 1329 div_ant_conf->alt_lna_conf = 1330 ATH_ANT_DIV_COMB_LNA1; 1331 else 1332 div_ant_conf->alt_lna_conf = 1333 ATH_ANT_DIV_COMB_LNA2; 1334 else 1335 /* Set alt to A+B or A-B */ 1336 div_ant_conf->alt_lna_conf = antcomb->main_conf; 1337 } 1338 break; 1339 default: 1340 break; 1341 } 1342 } 1343 1344 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf) 1345 { 1346 /* Adjust the fast_div_bias based on main and alt lna conf */ 1347 switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) { 1348 case (0x01): /* A-B LNA2 */ 1349 ant_conf->fast_div_bias = 0x3b; 1350 break; 1351 case (0x02): /* A-B LNA1 */ 1352 ant_conf->fast_div_bias = 0x3d; 1353 break; 1354 case (0x03): /* A-B A+B */ 1355 ant_conf->fast_div_bias = 0x1; 1356 break; 1357 case (0x10): /* LNA2 A-B */ 1358 ant_conf->fast_div_bias = 0x7; 1359 break; 1360 case (0x12): /* LNA2 LNA1 */ 1361 ant_conf->fast_div_bias = 0x2; 1362 break; 1363 case (0x13): /* LNA2 A+B */ 1364 ant_conf->fast_div_bias = 0x7; 1365 break; 1366 case (0x20): /* LNA1 A-B */ 1367 ant_conf->fast_div_bias = 0x6; 1368 break; 1369 case (0x21): /* LNA1 LNA2 */ 1370 ant_conf->fast_div_bias = 0x0; 1371 break; 1372 case (0x23): /* LNA1 A+B */ 1373 ant_conf->fast_div_bias = 0x6; 1374 break; 1375 case (0x30): /* A+B A-B */ 1376 ant_conf->fast_div_bias = 0x1; 1377 break; 1378 case (0x31): /* A+B LNA2 */ 1379 ant_conf->fast_div_bias = 0x3b; 1380 break; 1381 case (0x32): /* A+B LNA1 */ 1382 ant_conf->fast_div_bias = 0x3d; 1383 break; 1384 default: 1385 break; 1386 } 1387 } 1388 1389 /* Antenna diversity and combining */ 1390 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs) 1391 { 1392 struct ath_hw_antcomb_conf div_ant_conf; 1393 struct ath_ant_comb *antcomb = &sc->ant_comb; 1394 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set; 1395 int curr_main_set, curr_bias; 1396 int main_rssi = rs->rs_rssi_ctl0; 1397 int alt_rssi = rs->rs_rssi_ctl1; 1398 int rx_ant_conf, main_ant_conf; 1399 bool short_scan = false; 1400 1401 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) & 1402 ATH_ANT_RX_MASK; 1403 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) & 1404 ATH_ANT_RX_MASK; 1405 1406 /* Record packet only when alt_rssi is positive */ 1407 if (alt_rssi > 0) { 1408 antcomb->total_pkt_count++; 1409 antcomb->main_total_rssi += main_rssi; 1410 antcomb->alt_total_rssi += alt_rssi; 1411 if (main_ant_conf == rx_ant_conf) 1412 antcomb->main_recv_cnt++; 1413 else 1414 antcomb->alt_recv_cnt++; 1415 } 1416 1417 /* Short scan check */ 1418 if (antcomb->scan && antcomb->alt_good) { 1419 if (time_after(jiffies, antcomb->scan_start_time + 1420 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR))) 1421 short_scan = true; 1422 else 1423 if (antcomb->total_pkt_count == 1424 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) { 1425 alt_ratio = ((antcomb->alt_recv_cnt * 100) / 1426 antcomb->total_pkt_count); 1427 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO) 1428 short_scan = true; 1429 } 1430 } 1431 1432 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) || 1433 rs->rs_moreaggr) && !short_scan) 1434 return; 1435 1436 if (antcomb->total_pkt_count) { 1437 alt_ratio = ((antcomb->alt_recv_cnt * 100) / 1438 antcomb->total_pkt_count); 1439 main_rssi_avg = (antcomb->main_total_rssi / 1440 antcomb->total_pkt_count); 1441 alt_rssi_avg = (antcomb->alt_total_rssi / 1442 antcomb->total_pkt_count); 1443 } 1444 1445 1446 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf); 1447 curr_alt_set = div_ant_conf.alt_lna_conf; 1448 curr_main_set = div_ant_conf.main_lna_conf; 1449 curr_bias = div_ant_conf.fast_div_bias; 1450 1451 antcomb->count++; 1452 1453 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) { 1454 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { 1455 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf, 1456 main_rssi_avg); 1457 antcomb->alt_good = true; 1458 } else { 1459 antcomb->alt_good = false; 1460 } 1461 1462 antcomb->count = 0; 1463 antcomb->scan = true; 1464 antcomb->scan_not_start = true; 1465 } 1466 1467 if (!antcomb->scan) { 1468 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { 1469 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) { 1470 /* Switch main and alt LNA */ 1471 div_ant_conf.main_lna_conf = 1472 ATH_ANT_DIV_COMB_LNA2; 1473 div_ant_conf.alt_lna_conf = 1474 ATH_ANT_DIV_COMB_LNA1; 1475 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) { 1476 div_ant_conf.main_lna_conf = 1477 ATH_ANT_DIV_COMB_LNA1; 1478 div_ant_conf.alt_lna_conf = 1479 ATH_ANT_DIV_COMB_LNA2; 1480 } 1481 1482 goto div_comb_done; 1483 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) && 1484 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) { 1485 /* Set alt to another LNA */ 1486 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) 1487 div_ant_conf.alt_lna_conf = 1488 ATH_ANT_DIV_COMB_LNA1; 1489 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) 1490 div_ant_conf.alt_lna_conf = 1491 ATH_ANT_DIV_COMB_LNA2; 1492 1493 goto div_comb_done; 1494 } 1495 1496 if ((alt_rssi_avg < (main_rssi_avg + 1497 ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA))) 1498 goto div_comb_done; 1499 } 1500 1501 if (!antcomb->scan_not_start) { 1502 switch (curr_alt_set) { 1503 case ATH_ANT_DIV_COMB_LNA2: 1504 antcomb->rssi_lna2 = alt_rssi_avg; 1505 antcomb->rssi_lna1 = main_rssi_avg; 1506 antcomb->scan = true; 1507 /* set to A+B */ 1508 div_ant_conf.main_lna_conf = 1509 ATH_ANT_DIV_COMB_LNA1; 1510 div_ant_conf.alt_lna_conf = 1511 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1512 break; 1513 case ATH_ANT_DIV_COMB_LNA1: 1514 antcomb->rssi_lna1 = alt_rssi_avg; 1515 antcomb->rssi_lna2 = main_rssi_avg; 1516 antcomb->scan = true; 1517 /* set to A+B */ 1518 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2; 1519 div_ant_conf.alt_lna_conf = 1520 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1521 break; 1522 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2: 1523 antcomb->rssi_add = alt_rssi_avg; 1524 antcomb->scan = true; 1525 /* set to A-B */ 1526 div_ant_conf.alt_lna_conf = 1527 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1528 break; 1529 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2: 1530 antcomb->rssi_sub = alt_rssi_avg; 1531 antcomb->scan = false; 1532 if (antcomb->rssi_lna2 > 1533 (antcomb->rssi_lna1 + 1534 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) { 1535 /* use LNA2 as main LNA */ 1536 if ((antcomb->rssi_add > antcomb->rssi_lna1) && 1537 (antcomb->rssi_add > antcomb->rssi_sub)) { 1538 /* set to A+B */ 1539 div_ant_conf.main_lna_conf = 1540 ATH_ANT_DIV_COMB_LNA2; 1541 div_ant_conf.alt_lna_conf = 1542 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1543 } else if (antcomb->rssi_sub > 1544 antcomb->rssi_lna1) { 1545 /* set to A-B */ 1546 div_ant_conf.main_lna_conf = 1547 ATH_ANT_DIV_COMB_LNA2; 1548 div_ant_conf.alt_lna_conf = 1549 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1550 } else { 1551 /* set to LNA1 */ 1552 div_ant_conf.main_lna_conf = 1553 ATH_ANT_DIV_COMB_LNA2; 1554 div_ant_conf.alt_lna_conf = 1555 ATH_ANT_DIV_COMB_LNA1; 1556 } 1557 } else { 1558 /* use LNA1 as main LNA */ 1559 if ((antcomb->rssi_add > antcomb->rssi_lna2) && 1560 (antcomb->rssi_add > antcomb->rssi_sub)) { 1561 /* set to A+B */ 1562 div_ant_conf.main_lna_conf = 1563 ATH_ANT_DIV_COMB_LNA1; 1564 div_ant_conf.alt_lna_conf = 1565 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; 1566 } else if (antcomb->rssi_sub > 1567 antcomb->rssi_lna1) { 1568 /* set to A-B */ 1569 div_ant_conf.main_lna_conf = 1570 ATH_ANT_DIV_COMB_LNA1; 1571 div_ant_conf.alt_lna_conf = 1572 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; 1573 } else { 1574 /* set to LNA2 */ 1575 div_ant_conf.main_lna_conf = 1576 ATH_ANT_DIV_COMB_LNA1; 1577 div_ant_conf.alt_lna_conf = 1578 ATH_ANT_DIV_COMB_LNA2; 1579 } 1580 } 1581 break; 1582 default: 1583 break; 1584 } 1585 } else { 1586 if (!antcomb->alt_good) { 1587 antcomb->scan_not_start = false; 1588 /* Set alt to another LNA */ 1589 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) { 1590 div_ant_conf.main_lna_conf = 1591 ATH_ANT_DIV_COMB_LNA2; 1592 div_ant_conf.alt_lna_conf = 1593 ATH_ANT_DIV_COMB_LNA1; 1594 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) { 1595 div_ant_conf.main_lna_conf = 1596 ATH_ANT_DIV_COMB_LNA1; 1597 div_ant_conf.alt_lna_conf = 1598 ATH_ANT_DIV_COMB_LNA2; 1599 } 1600 goto div_comb_done; 1601 } 1602 } 1603 1604 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf, 1605 main_rssi_avg, alt_rssi_avg, 1606 alt_ratio); 1607 1608 antcomb->quick_scan_cnt++; 1609 1610 div_comb_done: 1611 ath_ant_div_conf_fast_divbias(&div_ant_conf); 1612 1613 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf); 1614 1615 antcomb->scan_start_time = jiffies; 1616 antcomb->total_pkt_count = 0; 1617 antcomb->main_total_rssi = 0; 1618 antcomb->alt_total_rssi = 0; 1619 antcomb->main_recv_cnt = 0; 1620 antcomb->alt_recv_cnt = 0; 1621 } 1622 1623 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) 1624 { 1625 struct ath_buf *bf; 1626 struct sk_buff *skb = NULL, *requeue_skb; 1627 struct ieee80211_rx_status *rxs; 1628 struct ath_hw *ah = sc->sc_ah; 1629 struct ath_common *common = ath9k_hw_common(ah); 1630 /* 1631 * The hw can technically differ from common->hw when using ath9k 1632 * virtual wiphy so to account for that we iterate over the active 1633 * wiphys and find the appropriate wiphy and therefore hw. 1634 */ 1635 struct ieee80211_hw *hw = NULL; 1636 struct ieee80211_hdr *hdr; 1637 int retval; 1638 bool decrypt_error = false; 1639 struct ath_rx_status rs; 1640 enum ath9k_rx_qtype qtype; 1641 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1642 int dma_type; 1643 u8 rx_status_len = ah->caps.rx_status_len; 1644 u64 tsf = 0; 1645 u32 tsf_lower = 0; 1646 unsigned long flags; 1647 1648 if (edma) 1649 dma_type = DMA_BIDIRECTIONAL; 1650 else 1651 dma_type = DMA_FROM_DEVICE; 1652 1653 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; 1654 spin_lock_bh(&sc->rx.rxbuflock); 1655 1656 tsf = ath9k_hw_gettsf64(ah); 1657 tsf_lower = tsf & 0xffffffff; 1658 1659 do { 1660 /* If handling rx interrupt and flush is in progress => exit */ 1661 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) 1662 break; 1663 1664 memset(&rs, 0, sizeof(rs)); 1665 if (edma) 1666 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); 1667 else 1668 bf = ath_get_next_rx_buf(sc, &rs); 1669 1670 if (!bf) 1671 break; 1672 1673 skb = bf->bf_mpdu; 1674 if (!skb) 1675 continue; 1676 1677 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len); 1678 rxs = IEEE80211_SKB_RXCB(skb); 1679 1680 hw = ath_get_virt_hw(sc, hdr); 1681 1682 ath_debug_stat_rx(sc, &rs); 1683 1684 /* 1685 * If we're asked to flush receive queue, directly 1686 * chain it back at the queue without processing it. 1687 */ 1688 if (flush) 1689 goto requeue; 1690 1691 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, 1692 rxs, &decrypt_error); 1693 if (retval) 1694 goto requeue; 1695 1696 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; 1697 if (rs.rs_tstamp > tsf_lower && 1698 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) 1699 rxs->mactime -= 0x100000000ULL; 1700 1701 if (rs.rs_tstamp < tsf_lower && 1702 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) 1703 rxs->mactime += 0x100000000ULL; 1704 1705 /* Ensure we always have an skb to requeue once we are done 1706 * processing the current buffer's skb */ 1707 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); 1708 1709 /* If there is no memory we ignore the current RX'd frame, 1710 * tell hardware it can give us a new frame using the old 1711 * skb and put it at the tail of the sc->rx.rxbuf list for 1712 * processing. */ 1713 if (!requeue_skb) 1714 goto requeue; 1715 1716 /* Unmap the frame */ 1717 dma_unmap_single(sc->dev, bf->bf_buf_addr, 1718 common->rx_bufsize, 1719 dma_type); 1720 1721 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); 1722 if (ah->caps.rx_status_len) 1723 skb_pull(skb, ah->caps.rx_status_len); 1724 1725 ath9k_rx_skb_postprocess(common, skb, &rs, 1726 rxs, decrypt_error); 1727 1728 /* We will now give hardware our shiny new allocated skb */ 1729 bf->bf_mpdu = requeue_skb; 1730 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 1731 common->rx_bufsize, 1732 dma_type); 1733 if (unlikely(dma_mapping_error(sc->dev, 1734 bf->bf_buf_addr))) { 1735 dev_kfree_skb_any(requeue_skb); 1736 bf->bf_mpdu = NULL; 1737 bf->bf_buf_addr = 0; 1738 ath_err(common, "dma_mapping_error() on RX\n"); 1739 ath_rx_send_to_mac80211(hw, sc, skb); 1740 break; 1741 } 1742 1743 /* 1744 * change the default rx antenna if rx diversity chooses the 1745 * other antenna 3 times in a row. 1746 */ 1747 if (sc->rx.defant != rs.rs_antenna) { 1748 if (++sc->rx.rxotherant >= 3) 1749 ath_setdefantenna(sc, rs.rs_antenna); 1750 } else { 1751 sc->rx.rxotherant = 0; 1752 } 1753 1754 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1755 1756 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | 1757 PS_WAIT_FOR_CAB | 1758 PS_WAIT_FOR_PSPOLL_DATA)) || 1759 unlikely(ath9k_check_auto_sleep(sc))) 1760 ath_rx_ps(sc, skb); 1761 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1762 1763 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) 1764 ath_ant_comb_scan(sc, &rs); 1765 1766 ath_rx_send_to_mac80211(hw, sc, skb); 1767 1768 requeue: 1769 if (edma) { 1770 list_add_tail(&bf->list, &sc->rx.rxbuf); 1771 ath_rx_edma_buf_link(sc, qtype); 1772 } else { 1773 list_move_tail(&bf->list, &sc->rx.rxbuf); 1774 ath_rx_buf_link(sc, bf); 1775 } 1776 } while (1); 1777 1778 spin_unlock_bh(&sc->rx.rxbuflock); 1779 1780 return 0; 1781 } 1782