1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb)) 22 23 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) 24 { 25 return sc->ps_enabled && 26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); 27 } 28 29 /* 30 * Setup and link descriptors. 31 * 32 * 11N: we can no longer afford to self link the last descriptor. 33 * MAC acknowledges BA status as long as it copies frames to host 34 * buffer (or rx fifo). This can incorrectly acknowledge packets 35 * to a sender if last desc is self-linked. 36 */ 37 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf, 38 bool flush) 39 { 40 struct ath_hw *ah = sc->sc_ah; 41 struct ath_common *common = ath9k_hw_common(ah); 42 struct ath_desc *ds; 43 struct sk_buff *skb; 44 45 ds = bf->bf_desc; 46 ds->ds_link = 0; /* link to null */ 47 ds->ds_data = bf->bf_buf_addr; 48 49 /* virtual addr of the beginning of the buffer. */ 50 skb = bf->bf_mpdu; 51 BUG_ON(skb == NULL); 52 ds->ds_vdata = skb->data; 53 54 /* 55 * setup rx descriptors. The rx_bufsize here tells the hardware 56 * how much data it can DMA to us and that we are prepared 57 * to process 58 */ 59 ath9k_hw_setuprxdesc(ah, ds, 60 common->rx_bufsize, 61 0); 62 63 if (sc->rx.rxlink) 64 *sc->rx.rxlink = bf->bf_daddr; 65 else if (!flush) 66 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 67 68 sc->rx.rxlink = &ds->ds_link; 69 } 70 71 static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf, 72 bool flush) 73 { 74 if (sc->rx.buf_hold) 75 ath_rx_buf_link(sc, sc->rx.buf_hold, flush); 76 77 sc->rx.buf_hold = bf; 78 } 79 80 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) 81 { 82 /* XXX block beacon interrupts */ 83 ath9k_hw_setantenna(sc->sc_ah, antenna); 84 sc->rx.defant = antenna; 85 sc->rx.rxotherant = 0; 86 } 87 88 static void ath_opmode_init(struct ath_softc *sc) 89 { 90 struct ath_hw *ah = sc->sc_ah; 91 struct ath_common *common = ath9k_hw_common(ah); 92 93 u32 rfilt, mfilt[2]; 94 95 /* configure rx filter */ 96 rfilt = ath_calcrxfilter(sc); 97 ath9k_hw_setrxfilter(ah, rfilt); 98 99 /* configure bssid mask */ 100 ath_hw_setbssidmask(common); 101 102 /* configure operational mode */ 103 ath9k_hw_setopmode(ah); 104 105 /* calculate and install multicast filter */ 106 mfilt[0] = mfilt[1] = ~0; 107 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 108 } 109 110 static bool ath_rx_edma_buf_link(struct ath_softc *sc, 111 enum ath9k_rx_qtype qtype) 112 { 113 struct ath_hw *ah = sc->sc_ah; 114 struct ath_rx_edma *rx_edma; 115 struct sk_buff *skb; 116 struct ath_rxbuf *bf; 117 118 rx_edma = &sc->rx.rx_edma[qtype]; 119 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) 120 return false; 121 122 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 123 list_del_init(&bf->list); 124 125 skb = bf->bf_mpdu; 126 127 memset(skb->data, 0, ah->caps.rx_status_len); 128 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 129 ah->caps.rx_status_len, DMA_TO_DEVICE); 130 131 SKB_CB_ATHBUF(skb) = bf; 132 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); 133 __skb_queue_tail(&rx_edma->rx_fifo, skb); 134 135 return true; 136 } 137 138 static void ath_rx_addbuffer_edma(struct ath_softc *sc, 139 enum ath9k_rx_qtype qtype) 140 { 141 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 142 struct ath_rxbuf *bf, *tbf; 143 144 if (list_empty(&sc->rx.rxbuf)) { 145 ath_dbg(common, QUEUE, "No free rx buf available\n"); 146 return; 147 } 148 149 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) 150 if (!ath_rx_edma_buf_link(sc, qtype)) 151 break; 152 153 } 154 155 static void ath_rx_remove_buffer(struct ath_softc *sc, 156 enum ath9k_rx_qtype qtype) 157 { 158 struct ath_rxbuf *bf; 159 struct ath_rx_edma *rx_edma; 160 struct sk_buff *skb; 161 162 rx_edma = &sc->rx.rx_edma[qtype]; 163 164 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) { 165 bf = SKB_CB_ATHBUF(skb); 166 BUG_ON(!bf); 167 list_add_tail(&bf->list, &sc->rx.rxbuf); 168 } 169 } 170 171 static void ath_rx_edma_cleanup(struct ath_softc *sc) 172 { 173 struct ath_hw *ah = sc->sc_ah; 174 struct ath_common *common = ath9k_hw_common(ah); 175 struct ath_rxbuf *bf; 176 177 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 178 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 179 180 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 181 if (bf->bf_mpdu) { 182 dma_unmap_single(sc->dev, bf->bf_buf_addr, 183 common->rx_bufsize, 184 DMA_BIDIRECTIONAL); 185 dev_kfree_skb_any(bf->bf_mpdu); 186 bf->bf_buf_addr = 0; 187 bf->bf_mpdu = NULL; 188 } 189 } 190 } 191 192 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) 193 { 194 __skb_queue_head_init(&rx_edma->rx_fifo); 195 rx_edma->rx_fifo_hwsize = size; 196 } 197 198 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) 199 { 200 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 201 struct ath_hw *ah = sc->sc_ah; 202 struct sk_buff *skb; 203 struct ath_rxbuf *bf; 204 int error = 0, i; 205 u32 size; 206 207 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - 208 ah->caps.rx_status_len); 209 210 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], 211 ah->caps.rx_lp_qdepth); 212 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], 213 ah->caps.rx_hp_qdepth); 214 215 size = sizeof(struct ath_rxbuf) * nbufs; 216 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL); 217 if (!bf) 218 return -ENOMEM; 219 220 INIT_LIST_HEAD(&sc->rx.rxbuf); 221 222 for (i = 0; i < nbufs; i++, bf++) { 223 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); 224 if (!skb) { 225 error = -ENOMEM; 226 goto rx_init_fail; 227 } 228 229 memset(skb->data, 0, common->rx_bufsize); 230 bf->bf_mpdu = skb; 231 232 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 233 common->rx_bufsize, 234 DMA_BIDIRECTIONAL); 235 if (unlikely(dma_mapping_error(sc->dev, 236 bf->bf_buf_addr))) { 237 dev_kfree_skb_any(skb); 238 bf->bf_mpdu = NULL; 239 bf->bf_buf_addr = 0; 240 ath_err(common, 241 "dma_mapping_error() on RX init\n"); 242 error = -ENOMEM; 243 goto rx_init_fail; 244 } 245 246 list_add_tail(&bf->list, &sc->rx.rxbuf); 247 } 248 249 return 0; 250 251 rx_init_fail: 252 ath_rx_edma_cleanup(sc); 253 return error; 254 } 255 256 static void ath_edma_start_recv(struct ath_softc *sc) 257 { 258 ath9k_hw_rxena(sc->sc_ah); 259 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP); 260 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP); 261 ath_opmode_init(sc); 262 ath9k_hw_startpcureceive(sc->sc_ah, sc->cur_chan->offchannel); 263 } 264 265 static void ath_edma_stop_recv(struct ath_softc *sc) 266 { 267 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); 268 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); 269 } 270 271 int ath_rx_init(struct ath_softc *sc, int nbufs) 272 { 273 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 274 struct sk_buff *skb; 275 struct ath_rxbuf *bf; 276 int error = 0; 277 278 spin_lock_init(&sc->sc_pcu_lock); 279 280 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + 281 sc->sc_ah->caps.rx_status_len; 282 283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 284 return ath_rx_edma_init(sc, nbufs); 285 286 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n", 287 common->cachelsz, common->rx_bufsize); 288 289 /* Initialize rx descriptors */ 290 291 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 292 "rx", nbufs, 1, 0); 293 if (error != 0) { 294 ath_err(common, 295 "failed to allocate rx descriptors: %d\n", 296 error); 297 goto err; 298 } 299 300 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 301 skb = ath_rxbuf_alloc(common, common->rx_bufsize, 302 GFP_KERNEL); 303 if (skb == NULL) { 304 error = -ENOMEM; 305 goto err; 306 } 307 308 bf->bf_mpdu = skb; 309 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 310 common->rx_bufsize, 311 DMA_FROM_DEVICE); 312 if (unlikely(dma_mapping_error(sc->dev, 313 bf->bf_buf_addr))) { 314 dev_kfree_skb_any(skb); 315 bf->bf_mpdu = NULL; 316 bf->bf_buf_addr = 0; 317 ath_err(common, 318 "dma_mapping_error() on RX init\n"); 319 error = -ENOMEM; 320 goto err; 321 } 322 } 323 sc->rx.rxlink = NULL; 324 err: 325 if (error) 326 ath_rx_cleanup(sc); 327 328 return error; 329 } 330 331 void ath_rx_cleanup(struct ath_softc *sc) 332 { 333 struct ath_hw *ah = sc->sc_ah; 334 struct ath_common *common = ath9k_hw_common(ah); 335 struct sk_buff *skb; 336 struct ath_rxbuf *bf; 337 338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 339 ath_rx_edma_cleanup(sc); 340 return; 341 } 342 343 list_for_each_entry(bf, &sc->rx.rxbuf, list) { 344 skb = bf->bf_mpdu; 345 if (skb) { 346 dma_unmap_single(sc->dev, bf->bf_buf_addr, 347 common->rx_bufsize, 348 DMA_FROM_DEVICE); 349 dev_kfree_skb(skb); 350 bf->bf_buf_addr = 0; 351 bf->bf_mpdu = NULL; 352 } 353 } 354 } 355 356 /* 357 * Calculate the receive filter according to the 358 * operating mode and state: 359 * 360 * o always accept unicast, broadcast, and multicast traffic 361 * o maintain current state of phy error reception (the hal 362 * may enable phy error frames for noise immunity work) 363 * o probe request frames are accepted only when operating in 364 * hostap, adhoc, or monitor modes 365 * o enable promiscuous mode according to the interface state 366 * o accept beacons: 367 * - when operating in adhoc mode so the 802.11 layer creates 368 * node table entries for peers, 369 * - when operating in station mode for collecting rssi data when 370 * the station is otherwise quiet, or 371 * - when operating as a repeater so we see repeater-sta beacons 372 * - when scanning 373 */ 374 375 u32 ath_calcrxfilter(struct ath_softc *sc) 376 { 377 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 378 u32 rfilt; 379 380 if (config_enabled(CONFIG_ATH9K_TX99)) 381 return 0; 382 383 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST 384 | ATH9K_RX_FILTER_MCAST; 385 386 /* if operating on a DFS channel, enable radar pulse detection */ 387 if (sc->hw->conf.radar_enabled) 388 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR; 389 390 spin_lock_bh(&sc->chan_lock); 391 392 if (sc->cur_chan->rxfilter & FIF_PROBE_REQ) 393 rfilt |= ATH9K_RX_FILTER_PROBEREQ; 394 395 if (sc->sc_ah->is_monitoring) 396 rfilt |= ATH9K_RX_FILTER_PROM; 397 398 if ((sc->cur_chan->rxfilter & FIF_CONTROL) || 399 sc->sc_ah->dynack.enabled) 400 rfilt |= ATH9K_RX_FILTER_CONTROL; 401 402 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && 403 (sc->cur_chan->nvifs <= 1) && 404 !(sc->cur_chan->rxfilter & FIF_BCN_PRBRESP_PROMISC)) 405 rfilt |= ATH9K_RX_FILTER_MYBEACON; 406 else 407 rfilt |= ATH9K_RX_FILTER_BEACON; 408 409 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || 410 (sc->cur_chan->rxfilter & FIF_PSPOLL)) 411 rfilt |= ATH9K_RX_FILTER_PSPOLL; 412 413 if (sc->cur_chandef.width != NL80211_CHAN_WIDTH_20_NOHT) 414 rfilt |= ATH9K_RX_FILTER_COMP_BAR; 415 416 if (sc->cur_chan->nvifs > 1 || (sc->cur_chan->rxfilter & FIF_OTHER_BSS)) { 417 /* This is needed for older chips */ 418 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160) 419 rfilt |= ATH9K_RX_FILTER_PROM; 420 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; 421 } 422 423 if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah) || 424 AR_SREV_9561(sc->sc_ah)) 425 rfilt |= ATH9K_RX_FILTER_4ADDRESS; 426 427 if (ath9k_is_chanctx_enabled() && 428 test_bit(ATH_OP_SCANNING, &common->op_flags)) 429 rfilt |= ATH9K_RX_FILTER_BEACON; 430 431 spin_unlock_bh(&sc->chan_lock); 432 433 return rfilt; 434 435 } 436 437 void ath_startrecv(struct ath_softc *sc) 438 { 439 struct ath_hw *ah = sc->sc_ah; 440 struct ath_rxbuf *bf, *tbf; 441 442 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 443 ath_edma_start_recv(sc); 444 return; 445 } 446 447 if (list_empty(&sc->rx.rxbuf)) 448 goto start_recv; 449 450 sc->rx.buf_hold = NULL; 451 sc->rx.rxlink = NULL; 452 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { 453 ath_rx_buf_link(sc, bf, false); 454 } 455 456 /* We could have deleted elements so the list may be empty now */ 457 if (list_empty(&sc->rx.rxbuf)) 458 goto start_recv; 459 460 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 461 ath9k_hw_putrxbuf(ah, bf->bf_daddr); 462 ath9k_hw_rxena(ah); 463 464 start_recv: 465 ath_opmode_init(sc); 466 ath9k_hw_startpcureceive(ah, sc->cur_chan->offchannel); 467 } 468 469 static void ath_flushrecv(struct ath_softc *sc) 470 { 471 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 472 ath_rx_tasklet(sc, 1, true); 473 ath_rx_tasklet(sc, 1, false); 474 } 475 476 bool ath_stoprecv(struct ath_softc *sc) 477 { 478 struct ath_hw *ah = sc->sc_ah; 479 bool stopped, reset = false; 480 481 ath9k_hw_abortpcurecv(ah); 482 ath9k_hw_setrxfilter(ah, 0); 483 stopped = ath9k_hw_stopdmarecv(ah, &reset); 484 485 ath_flushrecv(sc); 486 487 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 488 ath_edma_stop_recv(sc); 489 else 490 sc->rx.rxlink = NULL; 491 492 if (!(ah->ah_flags & AH_UNPLUGGED) && 493 unlikely(!stopped)) { 494 ath_err(ath9k_hw_common(sc->sc_ah), 495 "Could not stop RX, we could be " 496 "confusing the DMA engine when we start RX up\n"); 497 ATH_DBG_WARN_ON_ONCE(!stopped); 498 } 499 return stopped && !reset; 500 } 501 502 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) 503 { 504 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ 505 struct ieee80211_mgmt *mgmt; 506 u8 *pos, *end, id, elen; 507 struct ieee80211_tim_ie *tim; 508 509 mgmt = (struct ieee80211_mgmt *)skb->data; 510 pos = mgmt->u.beacon.variable; 511 end = skb->data + skb->len; 512 513 while (pos + 2 < end) { 514 id = *pos++; 515 elen = *pos++; 516 if (pos + elen > end) 517 break; 518 519 if (id == WLAN_EID_TIM) { 520 if (elen < sizeof(*tim)) 521 break; 522 tim = (struct ieee80211_tim_ie *) pos; 523 if (tim->dtim_count != 0) 524 break; 525 return tim->bitmap_ctrl & 0x01; 526 } 527 528 pos += elen; 529 } 530 531 return false; 532 } 533 534 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) 535 { 536 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 537 bool skip_beacon = false; 538 539 if (skb->len < 24 + 8 + 2 + 2) 540 return; 541 542 sc->ps_flags &= ~PS_WAIT_FOR_BEACON; 543 544 if (sc->ps_flags & PS_BEACON_SYNC) { 545 sc->ps_flags &= ~PS_BEACON_SYNC; 546 ath_dbg(common, PS, 547 "Reconfigure beacon timers based on synchronized timestamp\n"); 548 549 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT 550 if (ath9k_is_chanctx_enabled()) { 551 if (sc->cur_chan == &sc->offchannel.chan) 552 skip_beacon = true; 553 } 554 #endif 555 556 if (!skip_beacon && 557 !(WARN_ON_ONCE(sc->cur_chan->beacon.beacon_interval == 0))) 558 ath9k_set_beacon(sc); 559 560 ath9k_p2p_beacon_sync(sc); 561 } 562 563 if (ath_beacon_dtim_pending_cab(skb)) { 564 /* 565 * Remain awake waiting for buffered broadcast/multicast 566 * frames. If the last broadcast/multicast frame is not 567 * received properly, the next beacon frame will work as 568 * a backup trigger for returning into NETWORK SLEEP state, 569 * so we are waiting for it as well. 570 */ 571 ath_dbg(common, PS, 572 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); 573 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; 574 return; 575 } 576 577 if (sc->ps_flags & PS_WAIT_FOR_CAB) { 578 /* 579 * This can happen if a broadcast frame is dropped or the AP 580 * fails to send a frame indicating that all CAB frames have 581 * been delivered. 582 */ 583 sc->ps_flags &= ~PS_WAIT_FOR_CAB; 584 ath_dbg(common, PS, "PS wait for CAB frames timed out\n"); 585 } 586 } 587 588 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon) 589 { 590 struct ieee80211_hdr *hdr; 591 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 592 593 hdr = (struct ieee80211_hdr *)skb->data; 594 595 /* Process Beacon and CAB receive in PS state */ 596 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) 597 && mybeacon) { 598 ath_rx_ps_beacon(sc, skb); 599 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && 600 (ieee80211_is_data(hdr->frame_control) || 601 ieee80211_is_action(hdr->frame_control)) && 602 is_multicast_ether_addr(hdr->addr1) && 603 !ieee80211_has_moredata(hdr->frame_control)) { 604 /* 605 * No more broadcast/multicast frames to be received at this 606 * point. 607 */ 608 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); 609 ath_dbg(common, PS, 610 "All PS CAB frames received, back to sleep\n"); 611 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && 612 !is_multicast_ether_addr(hdr->addr1) && 613 !ieee80211_has_morefrags(hdr->frame_control)) { 614 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; 615 ath_dbg(common, PS, 616 "Going back to sleep after having received PS-Poll data (0x%lx)\n", 617 sc->ps_flags & (PS_WAIT_FOR_BEACON | 618 PS_WAIT_FOR_CAB | 619 PS_WAIT_FOR_PSPOLL_DATA | 620 PS_WAIT_FOR_TX_ACK)); 621 } 622 } 623 624 static bool ath_edma_get_buffers(struct ath_softc *sc, 625 enum ath9k_rx_qtype qtype, 626 struct ath_rx_status *rs, 627 struct ath_rxbuf **dest) 628 { 629 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; 630 struct ath_hw *ah = sc->sc_ah; 631 struct ath_common *common = ath9k_hw_common(ah); 632 struct sk_buff *skb; 633 struct ath_rxbuf *bf; 634 int ret; 635 636 skb = skb_peek(&rx_edma->rx_fifo); 637 if (!skb) 638 return false; 639 640 bf = SKB_CB_ATHBUF(skb); 641 BUG_ON(!bf); 642 643 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 644 common->rx_bufsize, DMA_FROM_DEVICE); 645 646 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data); 647 if (ret == -EINPROGRESS) { 648 /*let device gain the buffer again*/ 649 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 650 common->rx_bufsize, DMA_FROM_DEVICE); 651 return false; 652 } 653 654 __skb_unlink(skb, &rx_edma->rx_fifo); 655 if (ret == -EINVAL) { 656 /* corrupt descriptor, skip this one and the following one */ 657 list_add_tail(&bf->list, &sc->rx.rxbuf); 658 ath_rx_edma_buf_link(sc, qtype); 659 660 skb = skb_peek(&rx_edma->rx_fifo); 661 if (skb) { 662 bf = SKB_CB_ATHBUF(skb); 663 BUG_ON(!bf); 664 665 __skb_unlink(skb, &rx_edma->rx_fifo); 666 list_add_tail(&bf->list, &sc->rx.rxbuf); 667 ath_rx_edma_buf_link(sc, qtype); 668 } 669 670 bf = NULL; 671 } 672 673 *dest = bf; 674 return true; 675 } 676 677 static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc, 678 struct ath_rx_status *rs, 679 enum ath9k_rx_qtype qtype) 680 { 681 struct ath_rxbuf *bf = NULL; 682 683 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) { 684 if (!bf) 685 continue; 686 687 return bf; 688 } 689 return NULL; 690 } 691 692 static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc, 693 struct ath_rx_status *rs) 694 { 695 struct ath_hw *ah = sc->sc_ah; 696 struct ath_common *common = ath9k_hw_common(ah); 697 struct ath_desc *ds; 698 struct ath_rxbuf *bf; 699 int ret; 700 701 if (list_empty(&sc->rx.rxbuf)) { 702 sc->rx.rxlink = NULL; 703 return NULL; 704 } 705 706 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list); 707 if (bf == sc->rx.buf_hold) 708 return NULL; 709 710 ds = bf->bf_desc; 711 712 /* 713 * Must provide the virtual address of the current 714 * descriptor, the physical address, and the virtual 715 * address of the next descriptor in the h/w chain. 716 * This allows the HAL to look ahead to see if the 717 * hardware is done with a descriptor by checking the 718 * done bit in the following descriptor and the address 719 * of the current descriptor the DMA engine is working 720 * on. All this is necessary because of our use of 721 * a self-linked list to avoid rx overruns. 722 */ 723 ret = ath9k_hw_rxprocdesc(ah, ds, rs); 724 if (ret == -EINPROGRESS) { 725 struct ath_rx_status trs; 726 struct ath_rxbuf *tbf; 727 struct ath_desc *tds; 728 729 memset(&trs, 0, sizeof(trs)); 730 if (list_is_last(&bf->list, &sc->rx.rxbuf)) { 731 sc->rx.rxlink = NULL; 732 return NULL; 733 } 734 735 tbf = list_entry(bf->list.next, struct ath_rxbuf, list); 736 737 /* 738 * On some hardware the descriptor status words could 739 * get corrupted, including the done bit. Because of 740 * this, check if the next descriptor's done bit is 741 * set or not. 742 * 743 * If the next descriptor's done bit is set, the current 744 * descriptor has been corrupted. Force s/w to discard 745 * this descriptor and continue... 746 */ 747 748 tds = tbf->bf_desc; 749 ret = ath9k_hw_rxprocdesc(ah, tds, &trs); 750 if (ret == -EINPROGRESS) 751 return NULL; 752 753 /* 754 * Re-check previous descriptor, in case it has been filled 755 * in the mean time. 756 */ 757 ret = ath9k_hw_rxprocdesc(ah, ds, rs); 758 if (ret == -EINPROGRESS) { 759 /* 760 * mark descriptor as zero-length and set the 'more' 761 * flag to ensure that both buffers get discarded 762 */ 763 rs->rs_datalen = 0; 764 rs->rs_more = true; 765 } 766 } 767 768 list_del(&bf->list); 769 if (!bf->bf_mpdu) 770 return bf; 771 772 /* 773 * Synchronize the DMA transfer with CPU before 774 * 1. accessing the frame 775 * 2. requeueing the same buffer to h/w 776 */ 777 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, 778 common->rx_bufsize, 779 DMA_FROM_DEVICE); 780 781 return bf; 782 } 783 784 static void ath9k_process_tsf(struct ath_rx_status *rs, 785 struct ieee80211_rx_status *rxs, 786 u64 tsf) 787 { 788 u32 tsf_lower = tsf & 0xffffffff; 789 790 rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp; 791 if (rs->rs_tstamp > tsf_lower && 792 unlikely(rs->rs_tstamp - tsf_lower > 0x10000000)) 793 rxs->mactime -= 0x100000000ULL; 794 795 if (rs->rs_tstamp < tsf_lower && 796 unlikely(tsf_lower - rs->rs_tstamp > 0x10000000)) 797 rxs->mactime += 0x100000000ULL; 798 } 799 800 /* 801 * For Decrypt or Demic errors, we only mark packet status here and always push 802 * up the frame up to let mac80211 handle the actual error case, be it no 803 * decryption key or real decryption error. This let us keep statistics there. 804 */ 805 static int ath9k_rx_skb_preprocess(struct ath_softc *sc, 806 struct sk_buff *skb, 807 struct ath_rx_status *rx_stats, 808 struct ieee80211_rx_status *rx_status, 809 bool *decrypt_error, u64 tsf) 810 { 811 struct ieee80211_hw *hw = sc->hw; 812 struct ath_hw *ah = sc->sc_ah; 813 struct ath_common *common = ath9k_hw_common(ah); 814 struct ieee80211_hdr *hdr; 815 bool discard_current = sc->rx.discard_next; 816 817 /* 818 * Discard corrupt descriptors which are marked in 819 * ath_get_next_rx_buf(). 820 */ 821 if (discard_current) 822 goto corrupt; 823 824 sc->rx.discard_next = false; 825 826 /* 827 * Discard zero-length packets. 828 */ 829 if (!rx_stats->rs_datalen) { 830 RX_STAT_INC(rx_len_err); 831 goto corrupt; 832 } 833 834 /* 835 * rs_status follows rs_datalen so if rs_datalen is too large 836 * we can take a hint that hardware corrupted it, so ignore 837 * those frames. 838 */ 839 if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) { 840 RX_STAT_INC(rx_len_err); 841 goto corrupt; 842 } 843 844 /* Only use status info from the last fragment */ 845 if (rx_stats->rs_more) 846 return 0; 847 848 /* 849 * Return immediately if the RX descriptor has been marked 850 * as corrupt based on the various error bits. 851 * 852 * This is different from the other corrupt descriptor 853 * condition handled above. 854 */ 855 if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC) 856 goto corrupt; 857 858 hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len); 859 860 ath9k_process_tsf(rx_stats, rx_status, tsf); 861 ath_debug_stat_rx(sc, rx_stats); 862 863 /* 864 * Process PHY errors and return so that the packet 865 * can be dropped. 866 */ 867 if (rx_stats->rs_status & ATH9K_RXERR_PHY) { 868 ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime); 869 if (ath_cmn_process_fft(&sc->spec_priv, hdr, rx_stats, rx_status->mactime)) 870 RX_STAT_INC(rx_spectral); 871 872 return -EINVAL; 873 } 874 875 /* 876 * everything but the rate is checked here, the rate check is done 877 * separately to avoid doing two lookups for a rate for each frame. 878 */ 879 spin_lock_bh(&sc->chan_lock); 880 if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error, 881 sc->cur_chan->rxfilter)) { 882 spin_unlock_bh(&sc->chan_lock); 883 return -EINVAL; 884 } 885 spin_unlock_bh(&sc->chan_lock); 886 887 if (ath_is_mybeacon(common, hdr)) { 888 RX_STAT_INC(rx_beacons); 889 rx_stats->is_mybeacon = true; 890 } 891 892 /* 893 * This shouldn't happen, but have a safety check anyway. 894 */ 895 if (WARN_ON(!ah->curchan)) 896 return -EINVAL; 897 898 if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) { 899 /* 900 * No valid hardware bitrate found -- we should not get here 901 * because hardware has already validated this frame as OK. 902 */ 903 ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", 904 rx_stats->rs_rate); 905 RX_STAT_INC(rx_rate_err); 906 return -EINVAL; 907 } 908 909 if (ath9k_is_chanctx_enabled()) { 910 if (rx_stats->is_mybeacon) 911 ath_chanctx_beacon_recv_ev(sc, 912 ATH_CHANCTX_EVENT_BEACON_RECEIVED); 913 } 914 915 ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status); 916 917 rx_status->band = ah->curchan->chan->band; 918 rx_status->freq = ah->curchan->chan->center_freq; 919 rx_status->antenna = rx_stats->rs_antenna; 920 rx_status->flag |= RX_FLAG_MACTIME_END; 921 922 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT 923 if (ieee80211_is_data_present(hdr->frame_control) && 924 !ieee80211_is_qos_nullfunc(hdr->frame_control)) 925 sc->rx.num_pkts++; 926 #endif 927 928 return 0; 929 930 corrupt: 931 sc->rx.discard_next = rx_stats->rs_more; 932 return -EINVAL; 933 } 934 935 /* 936 * Run the LNA combining algorithm only in these cases: 937 * 938 * Standalone WLAN cards with both LNA/Antenna diversity 939 * enabled in the EEPROM. 940 * 941 * WLAN+BT cards which are in the supported card list 942 * in ath_pci_id_table and the user has loaded the 943 * driver with "bt_ant_diversity" set to true. 944 */ 945 static void ath9k_antenna_check(struct ath_softc *sc, 946 struct ath_rx_status *rs) 947 { 948 struct ath_hw *ah = sc->sc_ah; 949 struct ath9k_hw_capabilities *pCap = &ah->caps; 950 struct ath_common *common = ath9k_hw_common(ah); 951 952 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)) 953 return; 954 955 /* 956 * Change the default rx antenna if rx diversity 957 * chooses the other antenna 3 times in a row. 958 */ 959 if (sc->rx.defant != rs->rs_antenna) { 960 if (++sc->rx.rxotherant >= 3) 961 ath_setdefantenna(sc, rs->rs_antenna); 962 } else { 963 sc->rx.rxotherant = 0; 964 } 965 966 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) { 967 if (common->bt_ant_diversity) 968 ath_ant_comb_scan(sc, rs); 969 } else { 970 ath_ant_comb_scan(sc, rs); 971 } 972 } 973 974 static void ath9k_apply_ampdu_details(struct ath_softc *sc, 975 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs) 976 { 977 if (rs->rs_isaggr) { 978 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN; 979 980 rxs->ampdu_reference = sc->rx.ampdu_ref; 981 982 if (!rs->rs_moreaggr) { 983 rxs->flag |= RX_FLAG_AMPDU_IS_LAST; 984 sc->rx.ampdu_ref++; 985 } 986 987 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE) 988 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR; 989 } 990 } 991 992 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) 993 { 994 struct ath_rxbuf *bf; 995 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; 996 struct ieee80211_rx_status *rxs; 997 struct ath_hw *ah = sc->sc_ah; 998 struct ath_common *common = ath9k_hw_common(ah); 999 struct ieee80211_hw *hw = sc->hw; 1000 int retval; 1001 struct ath_rx_status rs; 1002 enum ath9k_rx_qtype qtype; 1003 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1004 int dma_type; 1005 u64 tsf = 0; 1006 unsigned long flags; 1007 dma_addr_t new_buf_addr; 1008 unsigned int budget = 512; 1009 struct ieee80211_hdr *hdr; 1010 1011 if (edma) 1012 dma_type = DMA_BIDIRECTIONAL; 1013 else 1014 dma_type = DMA_FROM_DEVICE; 1015 1016 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; 1017 1018 tsf = ath9k_hw_gettsf64(ah); 1019 1020 do { 1021 bool decrypt_error = false; 1022 1023 memset(&rs, 0, sizeof(rs)); 1024 if (edma) 1025 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); 1026 else 1027 bf = ath_get_next_rx_buf(sc, &rs); 1028 1029 if (!bf) 1030 break; 1031 1032 skb = bf->bf_mpdu; 1033 if (!skb) 1034 continue; 1035 1036 /* 1037 * Take frame header from the first fragment and RX status from 1038 * the last one. 1039 */ 1040 if (sc->rx.frag) 1041 hdr_skb = sc->rx.frag; 1042 else 1043 hdr_skb = skb; 1044 1045 rxs = IEEE80211_SKB_RXCB(hdr_skb); 1046 memset(rxs, 0, sizeof(struct ieee80211_rx_status)); 1047 1048 retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs, 1049 &decrypt_error, tsf); 1050 if (retval) 1051 goto requeue_drop_frag; 1052 1053 /* Ensure we always have an skb to requeue once we are done 1054 * processing the current buffer's skb */ 1055 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); 1056 1057 /* If there is no memory we ignore the current RX'd frame, 1058 * tell hardware it can give us a new frame using the old 1059 * skb and put it at the tail of the sc->rx.rxbuf list for 1060 * processing. */ 1061 if (!requeue_skb) { 1062 RX_STAT_INC(rx_oom_err); 1063 goto requeue_drop_frag; 1064 } 1065 1066 /* We will now give hardware our shiny new allocated skb */ 1067 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data, 1068 common->rx_bufsize, dma_type); 1069 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) { 1070 dev_kfree_skb_any(requeue_skb); 1071 goto requeue_drop_frag; 1072 } 1073 1074 /* Unmap the frame */ 1075 dma_unmap_single(sc->dev, bf->bf_buf_addr, 1076 common->rx_bufsize, dma_type); 1077 1078 bf->bf_mpdu = requeue_skb; 1079 bf->bf_buf_addr = new_buf_addr; 1080 1081 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); 1082 if (ah->caps.rx_status_len) 1083 skb_pull(skb, ah->caps.rx_status_len); 1084 1085 if (!rs.rs_more) 1086 ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs, 1087 rxs, decrypt_error); 1088 1089 if (rs.rs_more) { 1090 RX_STAT_INC(rx_frags); 1091 /* 1092 * rs_more indicates chained descriptors which can be 1093 * used to link buffers together for a sort of 1094 * scatter-gather operation. 1095 */ 1096 if (sc->rx.frag) { 1097 /* too many fragments - cannot handle frame */ 1098 dev_kfree_skb_any(sc->rx.frag); 1099 dev_kfree_skb_any(skb); 1100 RX_STAT_INC(rx_too_many_frags_err); 1101 skb = NULL; 1102 } 1103 sc->rx.frag = skb; 1104 goto requeue; 1105 } 1106 1107 if (sc->rx.frag) { 1108 int space = skb->len - skb_tailroom(hdr_skb); 1109 1110 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { 1111 dev_kfree_skb(skb); 1112 RX_STAT_INC(rx_oom_err); 1113 goto requeue_drop_frag; 1114 } 1115 1116 sc->rx.frag = NULL; 1117 1118 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), 1119 skb->len); 1120 dev_kfree_skb_any(skb); 1121 skb = hdr_skb; 1122 } 1123 1124 if (rxs->flag & RX_FLAG_MMIC_STRIPPED) 1125 skb_trim(skb, skb->len - 8); 1126 1127 spin_lock_irqsave(&sc->sc_pm_lock, flags); 1128 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | 1129 PS_WAIT_FOR_CAB | 1130 PS_WAIT_FOR_PSPOLL_DATA)) || 1131 ath9k_check_auto_sleep(sc)) 1132 ath_rx_ps(sc, skb, rs.is_mybeacon); 1133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 1134 1135 ath9k_antenna_check(sc, &rs); 1136 ath9k_apply_ampdu_details(sc, &rs, rxs); 1137 ath_debug_rate_stats(sc, &rs, skb); 1138 1139 hdr = (struct ieee80211_hdr *)skb->data; 1140 if (ieee80211_is_ack(hdr->frame_control)) 1141 ath_dynack_sample_ack_ts(sc->sc_ah, skb, rs.rs_tstamp); 1142 1143 ieee80211_rx(hw, skb); 1144 1145 requeue_drop_frag: 1146 if (sc->rx.frag) { 1147 dev_kfree_skb_any(sc->rx.frag); 1148 sc->rx.frag = NULL; 1149 } 1150 requeue: 1151 list_add_tail(&bf->list, &sc->rx.rxbuf); 1152 1153 if (!edma) { 1154 ath_rx_buf_relink(sc, bf, flush); 1155 if (!flush) 1156 ath9k_hw_rxena(ah); 1157 } else if (!flush) { 1158 ath_rx_edma_buf_link(sc, qtype); 1159 } 1160 1161 if (!budget--) 1162 break; 1163 } while (1); 1164 1165 if (!(ah->imask & ATH9K_INT_RXEOL)) { 1166 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN); 1167 ath9k_hw_set_interrupts(ah); 1168 } 1169 1170 return 0; 1171 } 1172