xref: /openbmc/linux/drivers/net/wireless/ath/ath9k/phy.h (revision f3539c12)
1 /*
2  * Copyright (c) 2008-2011 Atheros Communications Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef PHY_H
18 #define PHY_H
19 
20 #define CHANSEL_DIV		15
21 #define CHANSEL_2G(_freq)	(((_freq) * 0x10000) / CHANSEL_DIV)
22 #define CHANSEL_5G(_freq)	(((_freq) * 0x8000) / CHANSEL_DIV)
23 
24 #define AR_PHY_BASE     0x9800
25 #define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))
26 
27 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX   0x0007E000
28 #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
29 #define AR_PHY_TX_GAIN_CLC       0x0000001E
30 #define AR_PHY_TX_GAIN_CLC_S     1
31 #define AR_PHY_TX_GAIN           0x0007F000
32 #define AR_PHY_TX_GAIN_S         12
33 
34 #define AR_PHY_CLC_TBL1      0xa35c
35 #define AR_PHY_CLC_I0        0x07ff0000
36 #define AR_PHY_CLC_I0_S      16
37 #define AR_PHY_CLC_Q0        0x0000ffd0
38 #define AR_PHY_CLC_Q0_S      5
39 
40 #define ANTSWAP_AB 0x0001
41 #define REDUCE_CHAIN_0 0x00000050
42 #define REDUCE_CHAIN_1 0x00000051
43 #define AR_PHY_CHIP_ID 0x9818
44 
45 #define	AR_PHY_TIMING11_SPUR_FREQ_SD		0x3FF00000
46 #define	AR_PHY_TIMING11_SPUR_FREQ_SD_S		20
47 
48 #define AR_PHY_PLL_CONTROL 0x16180
49 #define AR_PHY_PLL_MODE 0x16184
50 
51 enum ath9k_ant_div_comb_lna_conf {
52 	ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
53 	ATH_ANT_DIV_COMB_LNA2,
54 	ATH_ANT_DIV_COMB_LNA1,
55 	ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
56 };
57 
58 #endif
59