1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef PHY_H 18 #define PHY_H 19 20 void ath9k_hw_ar9280_set_channel(struct ath_hw *ah, 21 struct ath9k_channel 22 *chan); 23 bool ath9k_hw_set_channel(struct ath_hw *ah, 24 struct ath9k_channel *chan); 25 void ath9k_hw_write_regs(struct ath_hw *ah, u32 modesIndex, 26 u32 freqIndex, int regWrites); 27 bool ath9k_hw_set_rf_regs(struct ath_hw *ah, 28 struct ath9k_channel *chan, 29 u16 modesIndex); 30 void ath9k_hw_decrease_chain_power(struct ath_hw *ah, 31 struct ath9k_channel *chan); 32 bool ath9k_hw_init_rf(struct ath_hw *ah, 33 int *status); 34 35 #define AR_PHY_BASE 0x9800 36 #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 37 38 #define AR_PHY_TEST 0x9800 39 #define PHY_AGC_CLR 0x10000000 40 #define RFSILENT_BB 0x00002000 41 42 #define AR_PHY_TURBO 0x9804 43 #define AR_PHY_FC_TURBO_MODE 0x00000001 44 #define AR_PHY_FC_TURBO_SHORT 0x00000002 45 #define AR_PHY_FC_DYN2040_EN 0x00000004 46 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008 47 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010 48 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020 49 #define AR_PHY_FC_HT_EN 0x00000040 50 #define AR_PHY_FC_SHORT_GI_40 0x00000080 51 #define AR_PHY_FC_WALSH 0x00000100 52 #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 53 #define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 54 55 #define AR_PHY_TEST2 0x9808 56 57 #define AR_PHY_TIMING2 0x9810 58 #define AR_PHY_TIMING3 0x9814 59 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000 60 #define AR_PHY_TIMING3_DSC_MAN_S 17 61 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000 62 #define AR_PHY_TIMING3_DSC_EXP_S 13 63 64 #define AR_PHY_CHIP_ID 0x9818 65 #define AR_PHY_CHIP_ID_REV_0 0x80 66 #define AR_PHY_CHIP_ID_REV_1 0x81 67 #define AR_PHY_CHIP_ID_9160_REV_0 0xb0 68 69 #define AR_PHY_ACTIVE 0x981C 70 #define AR_PHY_ACTIVE_EN 0x00000001 71 #define AR_PHY_ACTIVE_DIS 0x00000000 72 73 #define AR_PHY_RF_CTL2 0x9824 74 #define AR_PHY_TX_END_DATA_START 0x000000FF 75 #define AR_PHY_TX_END_DATA_START_S 0 76 #define AR_PHY_TX_END_PA_ON 0x0000FF00 77 #define AR_PHY_TX_END_PA_ON_S 8 78 79 #define AR_PHY_RF_CTL3 0x9828 80 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000 81 #define AR_PHY_TX_END_TO_A2_RX_ON_S 16 82 83 #define AR_PHY_ADC_CTL 0x982C 84 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003 85 #define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0 86 #define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000 87 #define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000 88 #define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000 89 #define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000 90 #define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16 91 92 #define AR_PHY_ADC_SERIAL_CTL 0x9830 93 #define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000 94 #define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001 95 96 #define AR_PHY_RF_CTL4 0x9834 97 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000 98 #define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24 99 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000 100 #define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16 101 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00 102 #define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8 103 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF 104 #define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0 105 106 #define AR_PHY_TSTDAC_CONST 0x983c 107 108 #define AR_PHY_SETTLING 0x9844 109 #define AR_PHY_SETTLING_SWITCH 0x00003F80 110 #define AR_PHY_SETTLING_SWITCH_S 7 111 112 #define AR_PHY_RXGAIN 0x9848 113 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000 114 #define AR_PHY_RXGAIN_TXRX_ATTEN_S 12 115 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000 116 #define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18 117 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 118 #define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 119 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 120 #define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 121 122 #define AR_PHY_DESIRED_SZ 0x9850 123 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF 124 #define AR_PHY_DESIRED_SZ_ADC_S 0 125 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00 126 #define AR_PHY_DESIRED_SZ_PGA_S 8 127 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000 128 #define AR_PHY_DESIRED_SZ_TOT_DES_S 20 129 130 #define AR_PHY_FIND_SIG 0x9858 131 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000 132 #define AR_PHY_FIND_SIG_FIRSTEP_S 12 133 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000 134 #define AR_PHY_FIND_SIG_FIRPWR_S 18 135 136 #define AR_PHY_AGC_CTL1 0x985C 137 #define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80 138 #define AR_PHY_AGC_CTL1_COARSE_LOW_S 7 139 #define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000 140 #define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15 141 142 #define AR_PHY_AGC_CONTROL 0x9860 143 #define AR_PHY_AGC_CONTROL_CAL 0x00000001 144 #define AR_PHY_AGC_CONTROL_NF 0x00000002 145 #define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 146 #define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 147 #define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 148 149 #define AR_PHY_CCA 0x9864 150 #define AR_PHY_MINCCA_PWR 0x0FF80000 151 #define AR_PHY_MINCCA_PWR_S 19 152 #define AR_PHY_CCA_THRESH62 0x0007F000 153 #define AR_PHY_CCA_THRESH62_S 12 154 #define AR9280_PHY_MINCCA_PWR 0x1FF00000 155 #define AR9280_PHY_MINCCA_PWR_S 20 156 #define AR9280_PHY_CCA_THRESH62 0x000FF000 157 #define AR9280_PHY_CCA_THRESH62_S 12 158 159 #define AR_PHY_SFCORR_LOW 0x986C 160 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001 161 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00 162 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8 163 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000 164 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14 165 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000 166 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21 167 168 #define AR_PHY_SFCORR 0x9868 169 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F 170 #define AR_PHY_SFCORR_M2COUNT_THR_S 0 171 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000 172 #define AR_PHY_SFCORR_M1_THRESH_S 17 173 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000 174 #define AR_PHY_SFCORR_M2_THRESH_S 24 175 176 #define AR_PHY_SLEEP_CTR_CONTROL 0x9870 177 #define AR_PHY_SLEEP_CTR_LIMIT 0x9874 178 #define AR_PHY_SYNTH_CONTROL 0x9874 179 #define AR_PHY_SLEEP_SCAL 0x9878 180 181 #define AR_PHY_PLL_CTL 0x987c 182 #define AR_PHY_PLL_CTL_40 0xaa 183 #define AR_PHY_PLL_CTL_40_5413 0x04 184 #define AR_PHY_PLL_CTL_44 0xab 185 #define AR_PHY_PLL_CTL_44_2133 0xeb 186 #define AR_PHY_PLL_CTL_40_2133 0xea 187 188 #define AR_PHY_SPECTRAL_SCAN 0x9912 189 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1 190 191 #define AR_PHY_RX_DELAY 0x9914 192 #define AR_PHY_SEARCH_START_DELAY 0x9918 193 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF 194 195 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) 196 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F 197 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0 198 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0 199 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 200 #define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800 201 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000 202 #define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 203 #define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000 204 205 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000 206 #define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000 207 #define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000 208 #define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000 209 210 #define AR_PHY_TIMING5 0x9924 211 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE 212 #define AR_PHY_TIMING5_CYCPWR_THR1_S 1 213 214 #define AR_PHY_POWER_TX_RATE1 0x9934 215 #define AR_PHY_POWER_TX_RATE2 0x9938 216 #define AR_PHY_POWER_TX_RATE_MAX 0x993c 217 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040 218 219 #define AR_PHY_FRAME_CTL 0x9944 220 #define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 221 #define AR_PHY_FRAME_CTL_TX_CLIP_S 3 222 223 #define AR_PHY_TXPWRADJ 0x994C 224 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0 225 #define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6 226 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000 227 #define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18 228 229 #define AR_PHY_RADAR_EXT 0x9940 230 #define AR_PHY_RADAR_EXT_ENA 0x00004000 231 232 #define AR_PHY_RADAR_0 0x9954 233 #define AR_PHY_RADAR_0_ENA 0x00000001 234 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000 235 #define AR_PHY_RADAR_0_INBAND 0x0000003e 236 #define AR_PHY_RADAR_0_INBAND_S 1 237 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 238 #define AR_PHY_RADAR_0_PRSSI_S 6 239 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 240 #define AR_PHY_RADAR_0_HEIGHT_S 12 241 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000 242 #define AR_PHY_RADAR_0_RRSSI_S 18 243 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000 244 #define AR_PHY_RADAR_0_FIRPWR_S 24 245 246 #define AR_PHY_RADAR_1 0x9958 247 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000 248 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000 249 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000 250 #define AR_PHY_RADAR_1_RELPWR_THRESH_S 16 251 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000 252 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000 253 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000 254 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00 255 #define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8 256 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF 257 #define AR_PHY_RADAR_1_MAXLEN_S 0 258 259 #define AR_PHY_SWITCH_CHAIN_0 0x9960 260 #define AR_PHY_SWITCH_COM 0x9964 261 262 #define AR_PHY_SIGMA_DELTA 0x996C 263 #define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 264 #define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0 265 #define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8 266 #define AR_PHY_SIGMA_DELTA_FILT2_S 3 267 #define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00 268 #define AR_PHY_SIGMA_DELTA_FILT1_S 8 269 #define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000 270 #define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13 271 272 #define AR_PHY_RESTART 0x9970 273 #define AR_PHY_RESTART_DIV_GC 0x001C0000 274 #define AR_PHY_RESTART_DIV_GC_S 18 275 276 #define AR_PHY_RFBUS_REQ 0x997C 277 #define AR_PHY_RFBUS_REQ_EN 0x00000001 278 279 #define AR_PHY_TIMING7 0x9980 280 #define AR_PHY_TIMING8 0x9984 281 #define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF 282 #define AR_PHY_TIMING8_PILOT_MASK_2_S 0 283 284 #define AR_PHY_BIN_MASK2_1 0x9988 285 #define AR_PHY_BIN_MASK2_2 0x998c 286 #define AR_PHY_BIN_MASK2_3 0x9990 287 #define AR_PHY_BIN_MASK2_4 0x9994 288 289 #define AR_PHY_BIN_MASK_1 0x9900 290 #define AR_PHY_BIN_MASK_2 0x9904 291 #define AR_PHY_BIN_MASK_3 0x9908 292 293 #define AR_PHY_MASK_CTL 0x990c 294 295 #define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF 296 #define AR_PHY_BIN_MASK2_4_MASK_4_S 0 297 298 #define AR_PHY_TIMING9 0x9998 299 #define AR_PHY_TIMING10 0x999c 300 #define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF 301 #define AR_PHY_TIMING10_PILOT_MASK_2_S 0 302 303 #define AR_PHY_TIMING11 0x99a0 304 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF 305 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0 306 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 307 #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 308 #define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000 309 #define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000 310 311 #define AR_PHY_RX_CHAINMASK 0x99a4 312 #define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12)) 313 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000 314 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000 315 316 #define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac 317 #define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000 318 #define AR_PHY_9285_ANT_DIV_CTL 0x01000000 319 #define AR_PHY_9285_ANT_DIV_CTL_S 24 320 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000 321 #define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25 322 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000 323 #define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27 324 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000 325 #define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29 326 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000 327 #define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30 328 #define AR_PHY_9285_ANT_DIV_LNA1 2 329 #define AR_PHY_9285_ANT_DIV_LNA2 1 330 #define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3 331 #define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0 332 #define AR_PHY_9285_ANT_DIV_GAINTB_0 0 333 #define AR_PHY_9285_ANT_DIV_GAINTB_1 1 334 335 #define AR_PHY_EXT_CCA0 0x99b8 336 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF 337 #define AR_PHY_EXT_CCA0_THRESH62_S 0 338 339 #define AR_PHY_EXT_CCA 0x99bc 340 #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 341 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 342 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000 343 #define AR_PHY_EXT_CCA_THRESH62_S 16 344 #define AR_PHY_EXT_MINCCA_PWR 0xFF800000 345 #define AR_PHY_EXT_MINCCA_PWR_S 23 346 #define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000 347 #define AR9280_PHY_EXT_MINCCA_PWR_S 16 348 349 #define AR_PHY_SFCORR_EXT 0x99c0 350 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F 351 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0 352 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80 353 #define AR_PHY_SFCORR_EXT_M2_THRESH_S 7 354 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000 355 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14 356 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000 357 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21 358 #define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28 359 360 #define AR_PHY_HALFGI 0x99D0 361 #define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0 362 #define AR_PHY_HALFGI_DSC_MAN_S 4 363 #define AR_PHY_HALFGI_DSC_EXP 0x0000000F 364 #define AR_PHY_HALFGI_DSC_EXP_S 0 365 366 #define AR_PHY_CHAN_INFO_MEMORY 0x99DC 367 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001 368 369 #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 370 371 #define AR_PHY_M_SLEEP 0x99f0 372 #define AR_PHY_REFCLKDLY 0x99f4 373 #define AR_PHY_REFCLKPD 0x99f8 374 375 #define AR_PHY_CALMODE 0x99f0 376 377 #define AR_PHY_CALMODE_IQ 0x00000000 378 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001 379 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002 380 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003 381 382 #define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12)) 383 #define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12)) 384 #define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12)) 385 #define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12)) 386 387 #define AR_PHY_CURRENT_RSSI 0x9c1c 388 #define AR9280_PHY_CURRENT_RSSI 0x9c3c 389 390 #define AR_PHY_RFBUS_GRANT 0x9C20 391 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 392 393 #define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4 394 #define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320 395 396 #define AR_PHY_CHAN_INFO_GAIN 0x9CFC 397 398 #define AR_PHY_MODE 0xA200 399 #define AR_PHY_MODE_ASYNCFIFO 0x80 400 #define AR_PHY_MODE_AR2133 0x08 401 #define AR_PHY_MODE_AR5111 0x00 402 #define AR_PHY_MODE_AR5112 0x08 403 #define AR_PHY_MODE_DYNAMIC 0x04 404 #define AR_PHY_MODE_RF2GHZ 0x02 405 #define AR_PHY_MODE_RF5GHZ 0x00 406 #define AR_PHY_MODE_CCK 0x01 407 #define AR_PHY_MODE_OFDM 0x00 408 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x100 409 410 #define AR_PHY_CCK_TX_CTRL 0xA204 411 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010 412 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C 413 #define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2 414 415 #define AR_PHY_CCK_DETECT 0xA208 416 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F 417 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 418 /* [12:6] settling time for antenna switch */ 419 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 420 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6 421 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000 422 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13 423 424 #define AR_PHY_GAIN_2GHZ 0xA20C 425 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000 426 #define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18 427 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00 428 #define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10 429 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F 430 #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 431 432 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 433 #define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 434 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 435 #define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 436 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 437 #define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 438 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F 439 #define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 440 441 #define AR_PHY_CCK_RXCTRL4 0xA21C 442 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000 443 #define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19 444 445 #define AR_PHY_DAG_CTRLCCK 0xA228 446 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200 447 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00 448 #define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10 449 450 #define AR_PHY_FORCE_CLKEN_CCK 0xA22C 451 #define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040 452 453 #define AR_PHY_POWER_TX_RATE3 0xA234 454 #define AR_PHY_POWER_TX_RATE4 0xA238 455 456 #define AR_PHY_SCRM_SEQ_XR 0xA23C 457 #define AR_PHY_HEADER_DETECT_XR 0xA240 458 #define AR_PHY_CHIRP_DETECTED_XR 0xA244 459 #define AR_PHY_BLUETOOTH 0xA254 460 461 #define AR_PHY_TPCRG1 0xA258 462 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000 463 #define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14 464 465 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000 466 #define AR_PHY_TPCRG1_PD_GAIN_1_S 16 467 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000 468 #define AR_PHY_TPCRG1_PD_GAIN_2_S 18 469 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000 470 #define AR_PHY_TPCRG1_PD_GAIN_3_S 20 471 472 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000 473 #define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22 474 475 #define AR_PHY_TX_PWRCTRL4 0xa264 476 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001 477 #define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0 478 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE 479 #define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1 480 481 #define AR_PHY_TX_PWRCTRL6_0 0xa270 482 #define AR_PHY_TX_PWRCTRL6_1 0xb270 483 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000 484 #define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24 485 486 #define AR_PHY_TX_PWRCTRL7 0xa274 487 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000 488 #define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19 489 490 #define AR_PHY_TX_PWRCTRL9 0xa27C 491 #define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00 492 #define AR_PHY_TX_DESIRED_SCALE_CCK_S 10 493 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000 494 #define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31 495 496 #define AR_PHY_TX_GAIN_TBL1 0xa300 497 #define AR_PHY_TX_GAIN 0x0007F000 498 #define AR_PHY_TX_GAIN_S 12 499 500 #define AR_PHY_CH0_TX_PWRCTRL11 0xa398 501 #define AR_PHY_CH1_TX_PWRCTRL11 0xb398 502 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00 503 #define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10 504 505 #define AR_PHY_VIT_MASK2_M_46_61 0xa3a0 506 #define AR_PHY_MASK2_M_31_45 0xa3a4 507 #define AR_PHY_MASK2_M_16_30 0xa3a8 508 #define AR_PHY_MASK2_M_00_15 0xa3ac 509 #define AR_PHY_MASK2_P_15_01 0xa3b8 510 #define AR_PHY_MASK2_P_30_16 0xa3bc 511 #define AR_PHY_MASK2_P_45_31 0xa3c0 512 #define AR_PHY_MASK2_P_61_45 0xa3c4 513 #define AR_PHY_SPUR_REG 0x994c 514 515 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18) 516 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18 517 518 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 519 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9) 520 #define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9 521 #define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100 522 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F 523 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0 524 525 #define AR_PHY_PILOT_MASK_01_30 0xa3b0 526 #define AR_PHY_PILOT_MASK_31_60 0xa3b4 527 528 #define AR_PHY_CHANNEL_MASK_01_30 0x99d4 529 #define AR_PHY_CHANNEL_MASK_31_60 0x99d8 530 531 #define AR_PHY_ANALOG_SWAP 0xa268 532 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040 533 534 #define AR_PHY_TPCRG5 0xA26C 535 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F 536 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0 537 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0 538 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4 539 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00 540 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10 541 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000 542 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16 543 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000 544 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22 545 546 /* Carrier leak calibration control, do it after AGC calibration */ 547 #define AR_PHY_CL_CAL_CTL 0xA358 548 #define AR_PHY_CL_CAL_ENABLE 0x00000002 549 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001 550 551 #define AR_PHY_POWER_TX_RATE5 0xA38C 552 #define AR_PHY_POWER_TX_RATE6 0xA390 553 554 #define AR_PHY_CAL_CHAINMASK 0xA39C 555 556 #define AR_PHY_POWER_TX_SUB 0xA3C8 557 #define AR_PHY_POWER_TX_RATE7 0xA3CC 558 #define AR_PHY_POWER_TX_RATE8 0xA3D0 559 #define AR_PHY_POWER_TX_RATE9 0xA3D4 560 561 #define AR_PHY_XPA_CFG 0xA3D8 562 #define AR_PHY_FORCE_XPA_CFG 0x000000001 563 #define AR_PHY_FORCE_XPA_CFG_S 0 564 565 #define AR_PHY_CH1_CCA 0xa864 566 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000 567 #define AR_PHY_CH1_MINCCA_PWR_S 19 568 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000 569 #define AR9280_PHY_CH1_MINCCA_PWR_S 20 570 571 #define AR_PHY_CH2_CCA 0xb864 572 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000 573 #define AR_PHY_CH2_MINCCA_PWR_S 19 574 575 #define AR_PHY_CH1_EXT_CCA 0xa9bc 576 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000 577 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23 578 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000 579 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16 580 581 #define AR_PHY_CH2_EXT_CCA 0xb9bc 582 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000 583 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23 584 585 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ 586 int r; \ 587 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 588 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ 589 DO_DELAY(regWr); \ 590 } \ 591 } while (0) 592 593 #define ATH9K_IS_MIC_ENABLED(ah) \ 594 ((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE) 595 596 #define ANTSWAP_AB 0x0001 597 #define REDUCE_CHAIN_0 0x00000050 598 #define REDUCE_CHAIN_1 0x00000051 599 600 #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ 601 int i; \ 602 for (i = 0; i < (_iniarray)->ia_rows; i++) \ 603 (_bank)[i] = INI_RA((_iniarray), i, _col);; \ 604 } while (0) 605 606 #endif 607