1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include "ath9k.h" 20 21 static struct pci_device_id ath_pci_id_table[] __devinitdata = { 22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 28 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 29 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 30 { 0 } 31 }; 32 33 /* return bus cachesize in 4B word units */ 34 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz) 35 { 36 u8 u8tmp; 37 38 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 39 *csz = (int)u8tmp; 40 41 /* 42 * This check was put in to avoid "unplesant" consequences if 43 * the bootrom has not fully initialized all PCI devices. 44 * Sometimes the cache line size register is not set 45 */ 46 47 if (*csz == 0) 48 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 49 } 50 51 static void ath_pci_cleanup(struct ath_softc *sc) 52 { 53 struct pci_dev *pdev = to_pci_dev(sc->dev); 54 55 pci_iounmap(pdev, sc->mem); 56 pci_disable_device(pdev); 57 pci_release_region(pdev, 0); 58 } 59 60 static bool ath_pci_eeprom_read(struct ath_hw *ah, u32 off, u16 *data) 61 { 62 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 63 64 if (!ath9k_hw_wait(ah, 65 AR_EEPROM_STATUS_DATA, 66 AR_EEPROM_STATUS_DATA_BUSY | 67 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 68 AH_WAIT_TIMEOUT)) { 69 return false; 70 } 71 72 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 73 AR_EEPROM_STATUS_DATA_VAL); 74 75 return true; 76 } 77 78 static struct ath_bus_ops ath_pci_bus_ops = { 79 .read_cachesize = ath_pci_read_cachesize, 80 .cleanup = ath_pci_cleanup, 81 .eeprom_read = ath_pci_eeprom_read, 82 }; 83 84 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 85 { 86 void __iomem *mem; 87 struct ath_wiphy *aphy; 88 struct ath_softc *sc; 89 struct ieee80211_hw *hw; 90 u8 csz; 91 u16 subsysid; 92 u32 val; 93 int ret = 0; 94 struct ath_hw *ah; 95 96 if (pci_enable_device(pdev)) 97 return -EIO; 98 99 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 100 101 if (ret) { 102 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 103 goto bad; 104 } 105 106 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 107 108 if (ret) { 109 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 110 "DMA enable failed\n"); 111 goto bad; 112 } 113 114 /* 115 * Cache line size is used to size and align various 116 * structures used to communicate with the hardware. 117 */ 118 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 119 if (csz == 0) { 120 /* 121 * Linux 2.4.18 (at least) writes the cache line size 122 * register as a 16-bit wide register which is wrong. 123 * We must have this setup properly for rx buffer 124 * DMA to work so force a reasonable value here if it 125 * comes up zero. 126 */ 127 csz = L1_CACHE_BYTES / sizeof(u32); 128 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 129 } 130 /* 131 * The default setting of latency timer yields poor results, 132 * set it to the value used by other systems. It may be worth 133 * tweaking this setting more. 134 */ 135 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 136 137 pci_set_master(pdev); 138 139 /* 140 * Disable the RETRY_TIMEOUT register (0x41) to keep 141 * PCI Tx retries from interfering with C3 CPU state. 142 */ 143 pci_read_config_dword(pdev, 0x40, &val); 144 if ((val & 0x0000ff00) != 0) 145 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 146 147 ret = pci_request_region(pdev, 0, "ath9k"); 148 if (ret) { 149 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 150 ret = -ENODEV; 151 goto bad; 152 } 153 154 mem = pci_iomap(pdev, 0, 0); 155 if (!mem) { 156 printk(KERN_ERR "PCI memory map error\n") ; 157 ret = -EIO; 158 goto bad1; 159 } 160 161 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) + 162 sizeof(struct ath_softc), &ath9k_ops); 163 if (!hw) { 164 dev_err(&pdev->dev, "no memory for ieee80211_hw\n"); 165 ret = -ENOMEM; 166 goto bad2; 167 } 168 169 SET_IEEE80211_DEV(hw, &pdev->dev); 170 pci_set_drvdata(pdev, hw); 171 172 aphy = hw->priv; 173 sc = (struct ath_softc *) (aphy + 1); 174 aphy->sc = sc; 175 aphy->hw = hw; 176 sc->pri_wiphy = aphy; 177 sc->hw = hw; 178 sc->dev = &pdev->dev; 179 sc->mem = mem; 180 sc->bus_ops = &ath_pci_bus_ops; 181 182 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); 183 ret = ath_init_device(id->device, sc, subsysid); 184 if (ret) { 185 dev_err(&pdev->dev, "failed to initialize device\n"); 186 goto bad3; 187 } 188 189 /* setup interrupt service routine */ 190 191 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 192 if (ret) { 193 dev_err(&pdev->dev, "request_irq failed\n"); 194 goto bad4; 195 } 196 197 sc->irq = pdev->irq; 198 199 ah = sc->sc_ah; 200 printk(KERN_INFO 201 "%s: Atheros AR%s MAC/BB Rev:%x " 202 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n", 203 wiphy_name(hw->wiphy), 204 ath_mac_bb_name(ah->hw_version.macVersion), 205 ah->hw_version.macRev, 206 ath_rf_name((ah->hw_version.analog5GhzRev & AR_RADIO_SREV_MAJOR)), 207 ah->hw_version.phyRev, 208 (unsigned long)mem, pdev->irq); 209 210 return 0; 211 bad4: 212 ath_detach(sc); 213 bad3: 214 ieee80211_free_hw(hw); 215 bad2: 216 pci_iounmap(pdev, mem); 217 bad1: 218 pci_release_region(pdev, 0); 219 bad: 220 pci_disable_device(pdev); 221 return ret; 222 } 223 224 static void ath_pci_remove(struct pci_dev *pdev) 225 { 226 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 227 struct ath_wiphy *aphy = hw->priv; 228 struct ath_softc *sc = aphy->sc; 229 230 ath_cleanup(sc); 231 } 232 233 #ifdef CONFIG_PM 234 235 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) 236 { 237 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 238 struct ath_wiphy *aphy = hw->priv; 239 struct ath_softc *sc = aphy->sc; 240 241 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 242 243 pci_save_state(pdev); 244 pci_disable_device(pdev); 245 pci_set_power_state(pdev, PCI_D3hot); 246 247 return 0; 248 } 249 250 static int ath_pci_resume(struct pci_dev *pdev) 251 { 252 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 253 struct ath_wiphy *aphy = hw->priv; 254 struct ath_softc *sc = aphy->sc; 255 u32 val; 256 int err; 257 258 pci_restore_state(pdev); 259 260 err = pci_enable_device(pdev); 261 if (err) 262 return err; 263 264 /* 265 * Suspend/Resume resets the PCI configuration space, so we have to 266 * re-disable the RETRY_TIMEOUT register (0x41) to keep 267 * PCI Tx retries from interfering with C3 CPU state 268 */ 269 pci_read_config_dword(pdev, 0x40, &val); 270 if ((val & 0x0000ff00) != 0) 271 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 272 273 /* Enable LED */ 274 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, 275 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 276 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 277 278 return 0; 279 } 280 281 #endif /* CONFIG_PM */ 282 283 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 284 285 static struct pci_driver ath_pci_driver = { 286 .name = "ath9k", 287 .id_table = ath_pci_id_table, 288 .probe = ath_pci_probe, 289 .remove = ath_pci_remove, 290 #ifdef CONFIG_PM 291 .suspend = ath_pci_suspend, 292 .resume = ath_pci_resume, 293 #endif /* CONFIG_PM */ 294 }; 295 296 int ath_pci_init(void) 297 { 298 return pci_register_driver(&ath_pci_driver); 299 } 300 301 void ath_pci_exit(void) 302 { 303 pci_unregister_driver(&ath_pci_driver); 304 } 305