1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/pci-aspm.h> 22 #include <linux/ath9k_platform.h> 23 #include <linux/module.h> 24 #include "ath9k.h" 25 26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 37 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 38 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 39 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 40 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 41 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ 42 { 0 } 43 }; 44 45 46 /* return bus cachesize in 4B word units */ 47 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 48 { 49 struct ath_softc *sc = (struct ath_softc *) common->priv; 50 u8 u8tmp; 51 52 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 53 *csz = (int)u8tmp; 54 55 /* 56 * This check was put in to avoid "unpleasant" consequences if 57 * the bootrom has not fully initialized all PCI devices. 58 * Sometimes the cache line size register is not set 59 */ 60 61 if (*csz == 0) 62 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 63 } 64 65 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 66 { 67 struct ath_softc *sc = (struct ath_softc *) common->priv; 68 struct ath9k_platform_data *pdata = sc->dev->platform_data; 69 70 if (pdata) { 71 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 72 ath_err(common, 73 "%s: eeprom read failed, offset %08x is out of range\n", 74 __func__, off); 75 } 76 77 *data = pdata->eeprom_data[off]; 78 } else { 79 struct ath_hw *ah = (struct ath_hw *) common->ah; 80 81 common->ops->read(ah, AR5416_EEPROM_OFFSET + 82 (off << AR5416_EEPROM_S)); 83 84 if (!ath9k_hw_wait(ah, 85 AR_EEPROM_STATUS_DATA, 86 AR_EEPROM_STATUS_DATA_BUSY | 87 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 88 AH_WAIT_TIMEOUT)) { 89 return false; 90 } 91 92 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 93 AR_EEPROM_STATUS_DATA_VAL); 94 } 95 96 return true; 97 } 98 99 /* Need to be called after we discover btcoex capabilities */ 100 static void ath_pci_aspm_init(struct ath_common *common) 101 { 102 struct ath_softc *sc = (struct ath_softc *) common->priv; 103 struct ath_hw *ah = sc->sc_ah; 104 struct pci_dev *pdev = to_pci_dev(sc->dev); 105 struct pci_dev *parent; 106 u16 aspm; 107 108 if (!ah->is_pciexpress) 109 return; 110 111 parent = pdev->bus->self; 112 if (!parent) 113 return; 114 115 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 116 (AR_SREV_9285(ah))) { 117 /* Bluetooth coexistence requires disabling ASPM. */ 118 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 119 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 120 121 /* 122 * Both upstream and downstream PCIe components should 123 * have the same ASPM settings. 124 */ 125 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 126 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 127 128 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 129 return; 130 } 131 132 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 133 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { 134 ah->aspm_enabled = true; 135 /* Initialize PCIe PM and SERDES registers. */ 136 ath9k_hw_configpcipowersave(ah, false); 137 ath_info(common, "ASPM enabled: 0x%x\n", aspm); 138 } 139 } 140 141 static const struct ath_bus_ops ath_pci_bus_ops = { 142 .ath_bus_type = ATH_PCI, 143 .read_cachesize = ath_pci_read_cachesize, 144 .eeprom_read = ath_pci_eeprom_read, 145 .aspm_init = ath_pci_aspm_init, 146 }; 147 148 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 149 { 150 void __iomem *mem; 151 struct ath_softc *sc; 152 struct ieee80211_hw *hw; 153 u8 csz; 154 u32 val; 155 int ret = 0; 156 char hw_name[64]; 157 158 if (pci_enable_device(pdev)) 159 return -EIO; 160 161 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 162 if (ret) { 163 pr_err("32-bit DMA not available\n"); 164 goto err_dma; 165 } 166 167 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 168 if (ret) { 169 pr_err("32-bit DMA consistent DMA enable failed\n"); 170 goto err_dma; 171 } 172 173 /* 174 * Cache line size is used to size and align various 175 * structures used to communicate with the hardware. 176 */ 177 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 178 if (csz == 0) { 179 /* 180 * Linux 2.4.18 (at least) writes the cache line size 181 * register as a 16-bit wide register which is wrong. 182 * We must have this setup properly for rx buffer 183 * DMA to work so force a reasonable value here if it 184 * comes up zero. 185 */ 186 csz = L1_CACHE_BYTES / sizeof(u32); 187 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 188 } 189 /* 190 * The default setting of latency timer yields poor results, 191 * set it to the value used by other systems. It may be worth 192 * tweaking this setting more. 193 */ 194 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 195 196 pci_set_master(pdev); 197 198 /* 199 * Disable the RETRY_TIMEOUT register (0x41) to keep 200 * PCI Tx retries from interfering with C3 CPU state. 201 */ 202 pci_read_config_dword(pdev, 0x40, &val); 203 if ((val & 0x0000ff00) != 0) 204 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 205 206 ret = pci_request_region(pdev, 0, "ath9k"); 207 if (ret) { 208 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 209 ret = -ENODEV; 210 goto err_region; 211 } 212 213 mem = pci_iomap(pdev, 0, 0); 214 if (!mem) { 215 pr_err("PCI memory map error\n") ; 216 ret = -EIO; 217 goto err_iomap; 218 } 219 220 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 221 if (!hw) { 222 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 223 ret = -ENOMEM; 224 goto err_alloc_hw; 225 } 226 227 SET_IEEE80211_DEV(hw, &pdev->dev); 228 pci_set_drvdata(pdev, hw); 229 230 sc = hw->priv; 231 sc->hw = hw; 232 sc->dev = &pdev->dev; 233 sc->mem = mem; 234 235 /* Will be cleared in ath9k_start() */ 236 set_bit(SC_OP_INVALID, &sc->sc_flags); 237 238 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 239 if (ret) { 240 dev_err(&pdev->dev, "request_irq failed\n"); 241 goto err_irq; 242 } 243 244 sc->irq = pdev->irq; 245 246 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 247 if (ret) { 248 dev_err(&pdev->dev, "Failed to initialize device\n"); 249 goto err_init; 250 } 251 252 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 253 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 254 hw_name, (unsigned long)mem, pdev->irq); 255 256 return 0; 257 258 err_init: 259 free_irq(sc->irq, sc); 260 err_irq: 261 ieee80211_free_hw(hw); 262 err_alloc_hw: 263 pci_iounmap(pdev, mem); 264 err_iomap: 265 pci_release_region(pdev, 0); 266 err_region: 267 /* Nothing */ 268 err_dma: 269 pci_disable_device(pdev); 270 return ret; 271 } 272 273 static void ath_pci_remove(struct pci_dev *pdev) 274 { 275 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 276 struct ath_softc *sc = hw->priv; 277 void __iomem *mem = sc->mem; 278 279 if (!is_ath9k_unloaded) 280 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 281 ath9k_deinit_device(sc); 282 free_irq(sc->irq, sc); 283 ieee80211_free_hw(sc->hw); 284 285 pci_iounmap(pdev, mem); 286 pci_disable_device(pdev); 287 pci_release_region(pdev, 0); 288 } 289 290 #ifdef CONFIG_PM_SLEEP 291 292 static int ath_pci_suspend(struct device *device) 293 { 294 struct pci_dev *pdev = to_pci_dev(device); 295 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 296 struct ath_softc *sc = hw->priv; 297 298 if (sc->wow_enabled) 299 return 0; 300 301 /* The device has to be moved to FULLSLEEP forcibly. 302 * Otherwise the chip never moved to full sleep, 303 * when no interface is up. 304 */ 305 ath9k_stop_btcoex(sc); 306 ath9k_hw_disable(sc->sc_ah); 307 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 308 309 return 0; 310 } 311 312 static int ath_pci_resume(struct device *device) 313 { 314 struct pci_dev *pdev = to_pci_dev(device); 315 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 316 struct ath_softc *sc = hw->priv; 317 struct ath_hw *ah = sc->sc_ah; 318 struct ath_common *common = ath9k_hw_common(ah); 319 u32 val; 320 321 /* 322 * Suspend/Resume resets the PCI configuration space, so we have to 323 * re-disable the RETRY_TIMEOUT register (0x41) to keep 324 * PCI Tx retries from interfering with C3 CPU state 325 */ 326 pci_read_config_dword(pdev, 0x40, &val); 327 if ((val & 0x0000ff00) != 0) 328 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 329 330 ath_pci_aspm_init(common); 331 ah->reset_power_on = false; 332 333 return 0; 334 } 335 336 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume); 337 338 #define ATH9K_PM_OPS (&ath9k_pm_ops) 339 340 #else /* !CONFIG_PM_SLEEP */ 341 342 #define ATH9K_PM_OPS NULL 343 344 #endif /* !CONFIG_PM_SLEEP */ 345 346 347 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 348 349 static struct pci_driver ath_pci_driver = { 350 .name = "ath9k", 351 .id_table = ath_pci_id_table, 352 .probe = ath_pci_probe, 353 .remove = ath_pci_remove, 354 .driver.pm = ATH9K_PM_OPS, 355 }; 356 357 int ath_pci_init(void) 358 { 359 return pci_register_driver(&ath_pci_driver); 360 } 361 362 void ath_pci_exit(void) 363 { 364 pci_unregister_driver(&ath_pci_driver); 365 } 366