1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include <linux/nl80211.h> 20 #include <linux/pci.h> 21 #include <linux/pci-aspm.h> 22 #include <linux/ath9k_platform.h> 23 #include <linux/module.h> 24 #include "ath9k.h" 25 26 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { 27 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 28 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 29 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 30 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 31 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 32 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 33 { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ 34 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 35 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 36 { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ 37 38 /* PCI-E CUS198 */ 39 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 40 0x0032, 41 PCI_VENDOR_ID_AZWAVE, 42 0x2086), 43 .driver_data = ATH9K_PCI_CUS198 }, 44 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 45 0x0032, 46 PCI_VENDOR_ID_AZWAVE, 47 0x1237), 48 .driver_data = ATH9K_PCI_CUS198 }, 49 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 50 0x0032, 51 PCI_VENDOR_ID_AZWAVE, 52 0x2126), 53 .driver_data = ATH9K_PCI_CUS198 }, 54 55 /* PCI-E CUS230 */ 56 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 57 0x0032, 58 PCI_VENDOR_ID_AZWAVE, 59 0x2152), 60 .driver_data = ATH9K_PCI_CUS230 }, 61 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 62 0x0032, 63 PCI_VENDOR_ID_FOXCONN, 64 0xE075), 65 .driver_data = ATH9K_PCI_CUS230 }, 66 67 { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ 68 { PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */ 69 70 /* PCI-E CUS217 */ 71 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 72 0x0034, 73 PCI_VENDOR_ID_AZWAVE, 74 0x2116), 75 .driver_data = ATH9K_PCI_CUS217 }, 76 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 77 0x0034, 78 0x11AD, /* LITEON */ 79 0x6661), 80 .driver_data = ATH9K_PCI_CUS217 }, 81 82 /* AR9462 with WoW support */ 83 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 84 0x0034, 85 PCI_VENDOR_ID_ATHEROS, 86 0x3117), 87 .driver_data = ATH9K_PCI_WOW }, 88 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 89 0x0034, 90 PCI_VENDOR_ID_LENOVO, 91 0x3214), 92 .driver_data = ATH9K_PCI_WOW }, 93 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 94 0x0034, 95 PCI_VENDOR_ID_ATTANSIC, 96 0x0091), 97 .driver_data = ATH9K_PCI_WOW }, 98 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 99 0x0034, 100 PCI_VENDOR_ID_AZWAVE, 101 0x2110), 102 .driver_data = ATH9K_PCI_WOW }, 103 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 104 0x0034, 105 PCI_VENDOR_ID_ASUSTEK, 106 0x850E), 107 .driver_data = ATH9K_PCI_WOW }, 108 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 109 0x0034, 110 0x11AD, /* LITEON */ 111 0x6631), 112 .driver_data = ATH9K_PCI_WOW }, 113 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 114 0x0034, 115 0x11AD, /* LITEON */ 116 0x6641), 117 .driver_data = ATH9K_PCI_WOW }, 118 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 119 0x0034, 120 PCI_VENDOR_ID_HP, 121 0x1864), 122 .driver_data = ATH9K_PCI_WOW }, 123 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 124 0x0034, 125 0x14CD, /* USI */ 126 0x0063), 127 .driver_data = ATH9K_PCI_WOW }, 128 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 129 0x0034, 130 0x14CD, /* USI */ 131 0x0064), 132 .driver_data = ATH9K_PCI_WOW }, 133 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS, 134 0x0034, 135 0x10CF, /* Fujitsu */ 136 0x1783), 137 .driver_data = ATH9K_PCI_WOW }, 138 139 { PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */ 140 { PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */ 141 { PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */ 142 { 0 } 143 }; 144 145 146 /* return bus cachesize in 4B word units */ 147 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 148 { 149 struct ath_softc *sc = (struct ath_softc *) common->priv; 150 u8 u8tmp; 151 152 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 153 *csz = (int)u8tmp; 154 155 /* 156 * This check was put in to avoid "unpleasant" consequences if 157 * the bootrom has not fully initialized all PCI devices. 158 * Sometimes the cache line size register is not set 159 */ 160 161 if (*csz == 0) 162 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 163 } 164 165 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 166 { 167 struct ath_softc *sc = (struct ath_softc *) common->priv; 168 struct ath9k_platform_data *pdata = sc->dev->platform_data; 169 170 if (pdata) { 171 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 172 ath_err(common, 173 "%s: eeprom read failed, offset %08x is out of range\n", 174 __func__, off); 175 } 176 177 *data = pdata->eeprom_data[off]; 178 } else { 179 struct ath_hw *ah = (struct ath_hw *) common->ah; 180 181 common->ops->read(ah, AR5416_EEPROM_OFFSET + 182 (off << AR5416_EEPROM_S)); 183 184 if (!ath9k_hw_wait(ah, 185 AR_EEPROM_STATUS_DATA, 186 AR_EEPROM_STATUS_DATA_BUSY | 187 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 188 AH_WAIT_TIMEOUT)) { 189 return false; 190 } 191 192 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 193 AR_EEPROM_STATUS_DATA_VAL); 194 } 195 196 return true; 197 } 198 199 /* Need to be called after we discover btcoex capabilities */ 200 static void ath_pci_aspm_init(struct ath_common *common) 201 { 202 struct ath_softc *sc = (struct ath_softc *) common->priv; 203 struct ath_hw *ah = sc->sc_ah; 204 struct pci_dev *pdev = to_pci_dev(sc->dev); 205 struct pci_dev *parent; 206 u16 aspm; 207 208 if (!ah->is_pciexpress) 209 return; 210 211 parent = pdev->bus->self; 212 if (!parent) 213 return; 214 215 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 216 (AR_SREV_9285(ah))) { 217 /* Bluetooth coexistence requires disabling ASPM. */ 218 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 219 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 220 221 /* 222 * Both upstream and downstream PCIe components should 223 * have the same ASPM settings. 224 */ 225 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 226 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1); 227 228 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 229 return; 230 } 231 232 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 233 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) { 234 ah->aspm_enabled = true; 235 /* Initialize PCIe PM and SERDES registers. */ 236 ath9k_hw_configpcipowersave(ah, false); 237 ath_info(common, "ASPM enabled: 0x%x\n", aspm); 238 } 239 } 240 241 static const struct ath_bus_ops ath_pci_bus_ops = { 242 .ath_bus_type = ATH_PCI, 243 .read_cachesize = ath_pci_read_cachesize, 244 .eeprom_read = ath_pci_eeprom_read, 245 .aspm_init = ath_pci_aspm_init, 246 }; 247 248 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 249 { 250 struct ath_softc *sc; 251 struct ieee80211_hw *hw; 252 u8 csz; 253 u32 val; 254 int ret = 0; 255 char hw_name[64]; 256 257 if (pcim_enable_device(pdev)) 258 return -EIO; 259 260 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 261 if (ret) { 262 pr_err("32-bit DMA not available\n"); 263 return ret; 264 } 265 266 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 267 if (ret) { 268 pr_err("32-bit DMA consistent DMA enable failed\n"); 269 return ret; 270 } 271 272 /* 273 * Cache line size is used to size and align various 274 * structures used to communicate with the hardware. 275 */ 276 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 277 if (csz == 0) { 278 /* 279 * Linux 2.4.18 (at least) writes the cache line size 280 * register as a 16-bit wide register which is wrong. 281 * We must have this setup properly for rx buffer 282 * DMA to work so force a reasonable value here if it 283 * comes up zero. 284 */ 285 csz = L1_CACHE_BYTES / sizeof(u32); 286 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 287 } 288 /* 289 * The default setting of latency timer yields poor results, 290 * set it to the value used by other systems. It may be worth 291 * tweaking this setting more. 292 */ 293 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 294 295 pci_set_master(pdev); 296 297 /* 298 * Disable the RETRY_TIMEOUT register (0x41) to keep 299 * PCI Tx retries from interfering with C3 CPU state. 300 */ 301 pci_read_config_dword(pdev, 0x40, &val); 302 if ((val & 0x0000ff00) != 0) 303 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 304 305 ret = pcim_iomap_regions(pdev, BIT(0), "ath9k"); 306 if (ret) { 307 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 308 return -ENODEV; 309 } 310 311 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); 312 if (!hw) { 313 dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); 314 return -ENOMEM; 315 } 316 317 SET_IEEE80211_DEV(hw, &pdev->dev); 318 pci_set_drvdata(pdev, hw); 319 320 sc = hw->priv; 321 sc->hw = hw; 322 sc->dev = &pdev->dev; 323 sc->mem = pcim_iomap_table(pdev)[0]; 324 sc->driver_data = id->driver_data; 325 326 /* Will be cleared in ath9k_start() */ 327 set_bit(SC_OP_INVALID, &sc->sc_flags); 328 329 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 330 if (ret) { 331 dev_err(&pdev->dev, "request_irq failed\n"); 332 goto err_irq; 333 } 334 335 sc->irq = pdev->irq; 336 337 ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops); 338 if (ret) { 339 dev_err(&pdev->dev, "Failed to initialize device\n"); 340 goto err_init; 341 } 342 343 ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); 344 wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", 345 hw_name, (unsigned long)sc->mem, pdev->irq); 346 347 return 0; 348 349 err_init: 350 free_irq(sc->irq, sc); 351 err_irq: 352 ieee80211_free_hw(hw); 353 return ret; 354 } 355 356 static void ath_pci_remove(struct pci_dev *pdev) 357 { 358 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 359 struct ath_softc *sc = hw->priv; 360 361 if (!is_ath9k_unloaded) 362 sc->sc_ah->ah_flags |= AH_UNPLUGGED; 363 ath9k_deinit_device(sc); 364 free_irq(sc->irq, sc); 365 ieee80211_free_hw(sc->hw); 366 } 367 368 #ifdef CONFIG_PM_SLEEP 369 370 static int ath_pci_suspend(struct device *device) 371 { 372 struct pci_dev *pdev = to_pci_dev(device); 373 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 374 struct ath_softc *sc = hw->priv; 375 376 if (sc->wow_enabled) 377 return 0; 378 379 /* The device has to be moved to FULLSLEEP forcibly. 380 * Otherwise the chip never moved to full sleep, 381 * when no interface is up. 382 */ 383 ath9k_stop_btcoex(sc); 384 ath9k_hw_disable(sc->sc_ah); 385 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); 386 387 return 0; 388 } 389 390 static int ath_pci_resume(struct device *device) 391 { 392 struct pci_dev *pdev = to_pci_dev(device); 393 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 394 struct ath_softc *sc = hw->priv; 395 struct ath_hw *ah = sc->sc_ah; 396 struct ath_common *common = ath9k_hw_common(ah); 397 u32 val; 398 399 /* 400 * Suspend/Resume resets the PCI configuration space, so we have to 401 * re-disable the RETRY_TIMEOUT register (0x41) to keep 402 * PCI Tx retries from interfering with C3 CPU state 403 */ 404 pci_read_config_dword(pdev, 0x40, &val); 405 if ((val & 0x0000ff00) != 0) 406 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 407 408 ath_pci_aspm_init(common); 409 ah->reset_power_on = false; 410 411 return 0; 412 } 413 414 static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume); 415 416 #define ATH9K_PM_OPS (&ath9k_pm_ops) 417 418 #else /* !CONFIG_PM_SLEEP */ 419 420 #define ATH9K_PM_OPS NULL 421 422 #endif /* !CONFIG_PM_SLEEP */ 423 424 425 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 426 427 static struct pci_driver ath_pci_driver = { 428 .name = "ath9k", 429 .id_table = ath_pci_id_table, 430 .probe = ath_pci_probe, 431 .remove = ath_pci_remove, 432 .driver.pm = ATH9K_PM_OPS, 433 }; 434 435 int ath_pci_init(void) 436 { 437 return pci_register_driver(&ath_pci_driver); 438 } 439 440 void ath_pci_exit(void) 441 { 442 pci_unregister_driver(&ath_pci_driver); 443 } 444