1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/nl80211.h> 18 #include <linux/pci.h> 19 #include "ath9k.h" 20 21 static struct pci_device_id ath_pci_id_table[] __devinitdata = { 22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 23 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ 24 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ 25 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ 26 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ 27 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ 28 { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ 29 { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ 30 { 0 } 31 }; 32 33 /* return bus cachesize in 4B word units */ 34 static void ath_pci_read_cachesize(struct ath_common *common, int *csz) 35 { 36 struct ath_softc *sc = (struct ath_softc *) common->priv; 37 u8 u8tmp; 38 39 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); 40 *csz = (int)u8tmp; 41 42 /* 43 * This check was put in to avoid "unplesant" consequences if 44 * the bootrom has not fully initialized all PCI devices. 45 * Sometimes the cache line size register is not set 46 */ 47 48 if (*csz == 0) 49 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ 50 } 51 52 static void ath_pci_cleanup(struct ath_common *common) 53 { 54 struct ath_softc *sc = (struct ath_softc *) common->priv; 55 struct pci_dev *pdev = to_pci_dev(sc->dev); 56 57 pci_iounmap(pdev, sc->mem); 58 pci_disable_device(pdev); 59 pci_release_region(pdev, 0); 60 } 61 62 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) 63 { 64 struct ath_hw *ah = (struct ath_hw *) common->ah; 65 66 common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 67 68 if (!ath9k_hw_wait(ah, 69 AR_EEPROM_STATUS_DATA, 70 AR_EEPROM_STATUS_DATA_BUSY | 71 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 72 AH_WAIT_TIMEOUT)) { 73 return false; 74 } 75 76 *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), 77 AR_EEPROM_STATUS_DATA_VAL); 78 79 return true; 80 } 81 82 /* 83 * Bluetooth coexistance requires disabling ASPM. 84 */ 85 static void ath_pci_bt_coex_prep(struct ath_common *common) 86 { 87 struct ath_softc *sc = (struct ath_softc *) common->priv; 88 struct pci_dev *pdev = to_pci_dev(sc->dev); 89 u8 aspm; 90 91 if (!pdev->is_pcie) 92 return; 93 94 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); 95 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1); 96 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); 97 } 98 99 static const struct ath_bus_ops ath_pci_bus_ops = { 100 .read_cachesize = ath_pci_read_cachesize, 101 .cleanup = ath_pci_cleanup, 102 .eeprom_read = ath_pci_eeprom_read, 103 .bt_coex_prep = ath_pci_bt_coex_prep, 104 }; 105 106 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 107 { 108 void __iomem *mem; 109 struct ath_wiphy *aphy; 110 struct ath_softc *sc; 111 struct ieee80211_hw *hw; 112 u8 csz; 113 u16 subsysid; 114 u32 val; 115 int ret = 0; 116 struct ath_hw *ah; 117 char hw_name[64]; 118 119 if (pci_enable_device(pdev)) 120 return -EIO; 121 122 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 123 124 if (ret) { 125 printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); 126 goto bad; 127 } 128 129 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 130 131 if (ret) { 132 printk(KERN_ERR "ath9k: 32-bit DMA consistent " 133 "DMA enable failed\n"); 134 goto bad; 135 } 136 137 /* 138 * Cache line size is used to size and align various 139 * structures used to communicate with the hardware. 140 */ 141 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); 142 if (csz == 0) { 143 /* 144 * Linux 2.4.18 (at least) writes the cache line size 145 * register as a 16-bit wide register which is wrong. 146 * We must have this setup properly for rx buffer 147 * DMA to work so force a reasonable value here if it 148 * comes up zero. 149 */ 150 csz = L1_CACHE_BYTES / sizeof(u32); 151 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); 152 } 153 /* 154 * The default setting of latency timer yields poor results, 155 * set it to the value used by other systems. It may be worth 156 * tweaking this setting more. 157 */ 158 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); 159 160 pci_set_master(pdev); 161 162 /* 163 * Disable the RETRY_TIMEOUT register (0x41) to keep 164 * PCI Tx retries from interfering with C3 CPU state. 165 */ 166 pci_read_config_dword(pdev, 0x40, &val); 167 if ((val & 0x0000ff00) != 0) 168 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 169 170 ret = pci_request_region(pdev, 0, "ath9k"); 171 if (ret) { 172 dev_err(&pdev->dev, "PCI memory region reserve error\n"); 173 ret = -ENODEV; 174 goto bad; 175 } 176 177 mem = pci_iomap(pdev, 0, 0); 178 if (!mem) { 179 printk(KERN_ERR "PCI memory map error\n") ; 180 ret = -EIO; 181 goto bad1; 182 } 183 184 hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) + 185 sizeof(struct ath_softc), &ath9k_ops); 186 if (!hw) { 187 dev_err(&pdev->dev, "no memory for ieee80211_hw\n"); 188 ret = -ENOMEM; 189 goto bad2; 190 } 191 192 SET_IEEE80211_DEV(hw, &pdev->dev); 193 pci_set_drvdata(pdev, hw); 194 195 aphy = hw->priv; 196 sc = (struct ath_softc *) (aphy + 1); 197 aphy->sc = sc; 198 aphy->hw = hw; 199 sc->pri_wiphy = aphy; 200 sc->hw = hw; 201 sc->dev = &pdev->dev; 202 sc->mem = mem; 203 204 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); 205 ret = ath_init_device(id->device, sc, subsysid, &ath_pci_bus_ops); 206 if (ret) { 207 dev_err(&pdev->dev, "failed to initialize device\n"); 208 goto bad3; 209 } 210 211 /* setup interrupt service routine */ 212 213 ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); 214 if (ret) { 215 dev_err(&pdev->dev, "request_irq failed\n"); 216 goto bad4; 217 } 218 219 sc->irq = pdev->irq; 220 221 ah = sc->sc_ah; 222 ath9k_hw_name(ah, hw_name, sizeof(hw_name)); 223 printk(KERN_INFO 224 "%s: %s mem=0x%lx, irq=%d\n", 225 wiphy_name(hw->wiphy), 226 hw_name, 227 (unsigned long)mem, pdev->irq); 228 229 return 0; 230 bad4: 231 ath_detach(sc); 232 bad3: 233 ieee80211_free_hw(hw); 234 bad2: 235 pci_iounmap(pdev, mem); 236 bad1: 237 pci_release_region(pdev, 0); 238 bad: 239 pci_disable_device(pdev); 240 return ret; 241 } 242 243 static void ath_pci_remove(struct pci_dev *pdev) 244 { 245 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 246 struct ath_wiphy *aphy = hw->priv; 247 struct ath_softc *sc = aphy->sc; 248 249 ath_cleanup(sc); 250 } 251 252 #ifdef CONFIG_PM 253 254 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) 255 { 256 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 257 struct ath_wiphy *aphy = hw->priv; 258 struct ath_softc *sc = aphy->sc; 259 260 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 261 262 pci_save_state(pdev); 263 pci_disable_device(pdev); 264 pci_set_power_state(pdev, PCI_D3hot); 265 266 return 0; 267 } 268 269 static int ath_pci_resume(struct pci_dev *pdev) 270 { 271 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 272 struct ath_wiphy *aphy = hw->priv; 273 struct ath_softc *sc = aphy->sc; 274 u32 val; 275 int err; 276 277 pci_restore_state(pdev); 278 279 err = pci_enable_device(pdev); 280 if (err) 281 return err; 282 283 /* 284 * Suspend/Resume resets the PCI configuration space, so we have to 285 * re-disable the RETRY_TIMEOUT register (0x41) to keep 286 * PCI Tx retries from interfering with C3 CPU state 287 */ 288 pci_read_config_dword(pdev, 0x40, &val); 289 if ((val & 0x0000ff00) != 0) 290 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); 291 292 /* Enable LED */ 293 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, 294 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 295 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); 296 297 return 0; 298 } 299 300 #endif /* CONFIG_PM */ 301 302 MODULE_DEVICE_TABLE(pci, ath_pci_id_table); 303 304 static struct pci_driver ath_pci_driver = { 305 .name = "ath9k", 306 .id_table = ath_pci_id_table, 307 .probe = ath_pci_probe, 308 .remove = ath_pci_remove, 309 #ifdef CONFIG_PM 310 .suspend = ath_pci_suspend, 311 .resume = ath_pci_resume, 312 #endif /* CONFIG_PM */ 313 }; 314 315 int ath_pci_init(void) 316 { 317 return pci_register_driver(&ath_pci_driver); 318 } 319 320 void ath_pci_exit(void) 321 { 322 pci_unregister_driver(&ath_pci_driver); 323 } 324